JP2017065955A - P-type silicon carbide single crystal substrate having low resistivity - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a p-type silicon carbide single crystal substrate hardly causing the occurrence of basal plane stacking faults fatally affecting device performance characteristics even in high temperature annealing and having a low resistivity required for a highly efficient power device.SOLUTION: The p-type silicon carbide single crystal substrate has a volume resistivity of more than 0.012 Ωcm and 0.080 Ωcm or less, and 90% or more of the entire surface obtained by totaling the front and rear surface of the substrate has a surface roughness (Ra) of 0.3 nm or less.SELECTED DRAWING: None

Description

  The present invention relates to a silicon carbide single crystal substrate, and more particularly to a p-type silicon carbide single crystal substrate having a low electrical resistivity, which is used when manufacturing a high-performance electronic device.

  Silicon carbide (SiC) is excellent in various mechanical properties including heat resistance and radiation resistance, and has superior semiconductor properties compared to conventional semiconductor materials such as silicon (Si) and gallium arsenide (GaAs). Therefore, it is used as a substrate material for various short-wavelength light-emitting devices and high-frequency / high-voltage power devices, and in recent years, the demand for SiC single crystal substrates is rapidly increasing. Technological development of single crystal manufacturing technology has also progressed, and an improved Rayleigh method (see Non-Patent Document 1) in which sublimation recrystallization growth is performed using an SiC single crystal as a seed crystal, or although technically synonymous with a sublimation method ( In the present invention, a 100 mm diameter substrate (4 inches) has become the mainstream in the market at present because of the simple abbreviated sublimation recrystallization method. In addition, further development of sublimation recrystallization method technology is underway, and a large-diameter, high-quality SiC single crystal substrate of 150 mm (6 inches) is being put on the market.

  Advances in SiC single crystal growth technology have greatly reduced the density of various crystal defects that affect device operating characteristics. In particular, the micropipe defect, which is a characteristic defect of SiC, is a defect that has fine voids in the dislocation core part, so it has a fatal effect on the withstand voltage characteristics of power devices, and technology development that eliminates it completely Has long been desired, and has reached a level that is said to have been successfully achieved. By using such a high quality SiC single crystal substrate, various devices such as a Schottky diode (SBD) and a field effect transistor (MOSFET) have been developed and put into practical use.

  The SBD and MOSFET devices described above are unipolar devices mainly manufactured from an n-type SiC single crystal substrate doped with nitrogen, and in recent years, high-voltage devices of 3.3 kV class are on the practical stage (non- (See Patent Document 2). In a unipolar device using an n-type SiC single crystal substrate, the current bearer is mainly electrons. In particular, in the above vertical power device in which a large current flows also to the substrate portion, the volume resistivity (hereinafter referred to as the volume resistivity) of the substrate. It is important to keep the resistivity as low as possible.

  Here, the resistivity of a commercially available n-type SiC single crystal substrate is generally in the range of about 0.015 to 0.020 Ωcm. In recent years, device design / manufacturing technology has advanced remarkably, and the resistance of the element portion has been reduced, which has been effective in suppressing power conversion loss of the device. On the other hand, regarding the resistance of the substrate, the resistivity of the material itself does not change for a long time from the above range. For this reason, the resistance value of the substrate cannot be ignored with respect to the resistance value of the element portion. In such a situation, the Joule loss due to the resistance value of the substrate portion during energization becomes a rule, and the power conversion loss of the entire device remains high, which hinders high device characteristics.

  Usually, it is possible to reduce the resistivity of the SiC single crystal substrate by increasing the doping amount of nitrogen which is an n-type dopant. However, if the substrate doped with an increased amount of nitrogen doping and reduced the resistivity of the n-type SiC single crystal substrate to 0.012 Ωcm or less is subjected to heat treatment at 1000 ° C. or more, a large number of base area layer defects are generated in the substrate. There is a known problem (see Patent Document 1).

  That is, when the SiC single crystal is excessively doped with nitrogen, which is an n-type dopant, more than usual, an n-type low resistivity SiC single crystal substrate having a resistivity of 0.012 Ωcm or less can be produced. However, this substrate is subjected to high-temperature annealing at 1000 ° C. or higher in an epitaxial film formation or device manufacturing process, for example, an epitaxial growth step (1500 to 1600 ° C., about 2 to 10 hours), a thermal oxide film formation step (1000 to 1300 ° C., When a recovery annealing step (1700 to 1800 ° C., about several minutes to 10 minutes) after ion implantation or the like is performed, a base area layer defect is generated. This base area layer defect is also referred to as a Double Shockley stacking fault due to its characteristic atomic stack structure (see Non-Patent Document 3), and when a large amount of base area layer defects occur, the substrate In the case of a vertical power device of a type in which current flows in the thickness direction, the electrical resistance during energization is greatly increased. For this reason, an increase in Joule loss during energization is caused. In particular, in an ultra-high voltage device that allows a large current to flow, power conversion loss increases, and a good power device cannot be manufactured.

  In order to deal with such a problem, as described in detail in Patent Document 1, the present inventors mainly generate nuclei of base area layer defects in a crystal damage layer in a surface damage layer introduced during substrate processing. It is clarified that a base area layer defect is generated by high-temperature annealing starting from this.

  Generally, when the roughness of the substrate surface is large in the polishing step, a surface damage layer is introduced near the substrate surface, and the crystal defect density increases. In a substrate with a large surface roughness, there are many base area layer defect nuclei in the surface damage layer near the surface, so that a large amount of base area layer defects are generated during the annealing process. . Therefore, in Patent Document 1, in order to suppress generation of base area layer defects, 90% or more of the entire surface of the substrate has a surface roughness Ra of 1 nm or less in a surface processing step such as a substrate polishing step. Thus, the nuclei of base area layer defects are removed as much as possible. That is, by making the surface roughness Ra a smooth surface of 1 nm or less, particularly in a SiC single crystal substrate having an n-type conductivity polarity, while having a very small resistivity of 0.012 Ωcm or less, a high level of base area layer defects is small. A quality SiC substrate can be realized.

  On the other hand, there is a strong application need for realizing an ultra-high withstand voltage device of 10.0 kV or more as a device characteristic region that makes the most of the characteristics of SiC single crystal. For such ultra-high voltage applications, bipolar devices such as PIN diodes and IGBTs (Insulated Gate Bipolar Transistors) that use both electron and hole carriers are practically advantageous for achieving stable breakdown characteristics. (See Non-Patent Document 4), and in order to achieve this, there is a strong demand for a p-type low-resistivity SiC single crystal substrate having a high quality with few crystal defects.

  However, in the case of a p-type SiC single crystal substrate manufactured by adding aluminum (Al) or boron (B), as in the case of n-type, the resistivity required for manufacturing a bipolar device is increased by the amount of doping. In order to cope with this, it is expected that a base area layer defect that has a fatal effect on the device operating characteristics will occur.

  On the other hand, when obtaining a p-type low resistivity SiC single crystal, it has been difficult to stably grow a 4H type polytype used in, for example, a power device. Therefore, an effective doping method of a p-type dopant for realizing a low resistivity required for a high-efficiency power device has not been established, and it is a fact that the practical use has been hindered until now.

  Here, in obtaining a p-type SiC single crystal, it is known that doping nitrogen into the single crystal simultaneously with the p-type dopant is effective in stabilizing the 4H polytype (Patent Document 2). Non-patent document 5). However, in these, there is no description regarding the p-type low resistivity SiC single crystal substrate considering the base area layer defect generated when annealing at a high temperature after crystal growth.

JP 2008-290898 A Japanese Patent Laid-Open No. 9-157091

Yu. M. Tairov and V. F. Tsvetkov, Journal of Crystal Growth. Vol.52 (1981) p.146. K. Wada, et al., Materials Science Forum. 821-823 (2015) p.592. T. A. Kuhr, et al., Journal of Applied Physics. Vol.92 (2002) p.5863. Fukuda, et al., SiC and related semiconductor research, 22nd Lecture Proceedings p.49. Eto, et al., Advanced Power Semiconductor Subcommittee Second Lecture Proceedings p.62.

  As a result of intensive studies on the above-mentioned problems, the present inventors have devised a p-type dopant doping method and then applied a polishing process in accordance with the characteristics of the low-resistance p-type SiC single crystal substrate, thereby improving device operation characteristics. The present inventors have found that a low resistivity necessary for a high-efficiency power device can be realized in a p-type SiC single crystal substrate by preventing the occurrence of fatal base layer defects, and the present invention has been completed.

  Accordingly, the present invention provides a high-quality p-type low resistivity SiC single crystal substrate with few occurrences of base area layer defects even during high-temperature annealing.

That is, the gist of the present invention is as follows.
(1) A p-type silicon carbide single crystal substrate having a volume resistivity of more than 0.012 Ωcm and not more than 0.080 Ωcm, and 90% or more of the total surface including the surface and the back surface of the substrate has a surface roughness (Ra) of 0.3 nm A p-type low resistivity silicon carbide single crystal substrate, characterized by:
(2) The p-type low resistivity silicon carbide single crystal substrate according to (1), wherein the polymorph of the silicon carbide single crystal substrate is a 4H type,
(3) A p-type dopant composed of one or both of Al and B is contained in a concentration range of 5 × 10 ¹⁹ / cm ³ or more and 1 × 10 ²¹ / cm ³ or less, and an n-type dopant composed of N 1 × 10 ¹⁸ pieces / cm ³ or more and 6 × 10 ²⁰ pieces / cm ³ or less, and contained at a lower concentration than the p-type dopant, described in (1) or (2) p-type low resistivity silicon carbide single crystal substrate,
(4) The p-type low resistivity silicon carbide single crystal substrate according to any one of (1) to (3), wherein the thickness is 0.05 mm or more and 0.9 mm or less,
(5) The p-type low resistivity silicon carbide single crystal substrate according to any one of (1) to (4), wherein an offset angle from the {0001} plane is 1 ° or more and 12 ° or less.
(6) The p-type low resistivity silicon carbide single crystal substrate according to any one of (1) to (5), wherein the diameter is 50 mm or more and 300 mm or less,
(7) When the high temperature annealing is performed at 1000 ° C. or more and 1800 ° C. or less, the base area layer defect density in the substrate after the high temperature annealing is 40 / cm or less, any one of (1) to (6) A p-type low resistivity silicon carbide single crystal substrate according to claim 1,
(8) The base area layer defect density in the substrate after the high-temperature annealing is 20 / cm or less when the high-temperature annealing is performed at 1000 ° C. or higher and 1800 ° C. or lower, any one of (1) to (6) A p-type low resistivity silicon carbide single crystal substrate according to claim 1,
(9) The p-type low resistivity silicon carbide single crystal substrate according to any one of (1) to (8), which is used for manufacturing a bipolar device,
It is.

  According to the present invention, in a p-type SiC single crystal substrate having a resistivity greater than 0.012 Ωcm and less than or equal to 0.080 Ωcm, generation of base area layer defects can be suppressed even when high-temperature annealing is performed at 1000 ° C. or more and 1800 ° C. or less, for example. . By using such a p-type low resistivity SiC single crystal substrate, it becomes possible to manufacture various high-frequency / high-voltage electronic devices, optical light-emitting elements, and the like, particularly power devices for ultra-high voltage applications. .

FIG. 1 is a schematic diagram for explaining a SiC single crystal growth apparatus for manufacturing a p-type low resistivity SiC single crystal substrate according to the present invention.

The present invention will be described in detail below.
The p-type low resistivity SiC single crystal substrate of the present invention has a surface roughness (Ra) of 0.3 nm or less at 90% or more of the total front and back surfaces, for example, an epitaxial growth process (1500 to 1600 ° C., 2-10 hours), thermal oxide film formation process (1000-1300 ° C, 1-4 hours), recovery annealing process after ion implantation (1700-1800 ° C, several minutes-10 minutes), etc. Even if it is exposed to high temperature annealing at 1000 ° C. or higher in the wafer process for the SiC single crystal substrate, almost no stacking faults occur, and it can be used for manufacturing a high-performance element.

  Here, as described above, when obtaining a p-type low resistivity SiC single crystal, it is difficult to stably grow a 4H type polytype used for a power device. An effective p-type dopant doping method for realizing the low resistivity required for high-efficiency power devices has not been established by the crystal method, and p-type low resistivity SiC single crystal substrates have been put into practical use so far. Has been blocked.

Among these, for example, as a method for doping Al, which is a typical p-type dopant, a method is known in which a predetermined amount of metal Al or aluminum carbide (Al ₄ C ₃ ) is mixed with raw material powder for sublimation recrystallization. (Japanese Unexamined Patent Publication No. 63-050399: Reference 1). However, in such a method, since the temperature of evaporation or sublimation decomposition of Al or Al ₄ C ₃ is lower than the SiC single crystal growth temperature, the single crystal ingot is uniformly doped over the entire growth time zone. Difficult to do. As another method, a separate graphite vessel connected to a SiC single crystal growth crucible is provided, and Al ₄ C ₃ is sublimated in a relatively low temperature region inside the crucible for single crystal growth. A method of guiding and doping into a container has been proposed (T. Kato, et al., Material Science Forum. Vol.778-780 (2014) p.47 .: Reference 2). However, the resistivity of the p-type SiC single crystal obtained by this method remains at 0.750 Ωcm. Further, the SiC raw material powder to be used and Al ₄ C ₃ are mixed and then fired in an argon atmosphere to prepare an Al-doped SiC raw material powder in advance, and the Al-doped SiC raw material powder is used as a sublimation recrystallization raw material. A method has been proposed (Japanese Patent Laid-Open No. H5-221796: Reference 3). However, the resistivity obtained even by this method is 0.100 Ωcm, and it cannot be said that the low resistivity necessary for the ultrahigh voltage power device is sufficiently obtained.

Under such circumstances, in order to solve these problems, the present inventors mixed not a SiC raw material but a high purity silicon powder and a high purity carbon powder, and further added a predetermined amount of Al ₄ C _3. , After mixing, by firing at a high temperature of 1800 ° C. or higher in argon under atmospheric pressure, SiC raw material powder doped with Al at a higher concentration than before can be synthesized relatively easily, By using this raw material powder as a raw material powder for sublimation recrystallization, it is possible to produce a high-concentration Al-doped p-type SiC single crystal that reaches 1 × 10 ²¹ / cm ³ , which is the solid solubility limit of Al in SiC. I found. For example, a SiC single crystal having an Al doping amount of 2 × 10 ²⁰ / cm ³ is obtained by this method, and the electrical resistivity is measured to obtain a result of about 0.015 Ωcm.

  Thus, as a result of producing a p-type low resistivity SiC single crystal by the above-described method and investigating the relationship between the surface roughness (Ra) and the occurrence of the base area layer defect, the p-type SiC single crystal is also an n-type single crystal. However, it has been clarified that p-type single crystals have specific technical difficulties that are not present in the case of n-type.

That is, nitrogen, which is an n-type dopant, forms a very shallow impurity level of about 0.04 to 0.11 eV immediately below the conduction band in a SiC single crystal, so that the resistance can be lowered even if the doping amount is small. Although it can be easily realized, Al (0.15-0.19 eV) and B (0.300-0.350 eV), which are p-type dopants, form a deep impurity level immediately above the valence band as compared with nitrogen. In order to realize the same resistivity as that of the n-type single crystal, it is necessary to dope excessively. For example, in order to realize a resistivity of 15 mΩcm, in the case of n-type, it can be realized by doping with nitrogen having an atom number density of about 1 × 10 ¹⁹ / cm ³ , but in the case of p-type, about 2 × 10 It is necessary to dope ²⁰ / cm ³ of Al (see Reference 2 above). Thus, the overdoping of the impurity element over one digit or more leads to an increase in strain of the SiC single crystal itself, and has a great influence on the mechanical properties. In other words, the mechanical properties of SiC as the original hard material deteriorates and becomes brittle, and therefore, there is a high possibility that the damage layer introduced during processing increases. In p-type low resistivity SiC single crystal, n-type SiC single crystal Compared to crystals, base area layer defects occur more frequently during annealing.

  As a method for solving such a material problem of the p-type low-resistance single crystal substrate, the present inventors removed the end portion (side surface) of the substrate by mechanochemical polishing (CMP) that is usually performed as the final step of substrate processing. Except for the area of 90% or more of the entire surface of the substrate comprising both the front and back surfaces of the substrate, the smoothness is further improved as compared with the case of the n-type SiC single crystal substrate, and the surface roughness Ra is 0.3 nm or less, preferably 0.2 nm or less. Furthermore, it has been found that by forming a smooth surface of 0.12 nm or less, the nuclei of base area layer defects can be substantially removed. When the surface roughness (Ra) exceeds 0.3 nm, the density of base area layer defect generation nuclei in the vicinity of the surface increases in the p-type low resistivity SiC single crystal substrate. It tends to occur.

  In addition, the mechanochemical polishing is typically performed using a polishing liquid obtained by mixing a highly alkaline liquid having an etching action with colloidal silica having a small particle diameter as an example of a SiC single crystal substrate. In order to increase the polishing rate, a method of adding an oxidation accelerator such as hydrogen peroxide to the colloidal silica slurry is generally employed. However, the method described here shows an example of mechanochemical polishing, and does not define the present invention. Other slurry exhibiting the same mechanochemical action and a polishing apparatus that effectively realizes the slurry are provided. May be used.

  Here, “surface roughness” refers to the arithmetic average surface roughness Ra (JIS B0601-2001) in a 10 μm square region on the substrate surface. In addition, the ratio of the smooth surface (the silicon carbide single crystal surface with Ra of 0.3 nm or less) to the total surface area of the substrate is 90% or more, preferably 95% or more. When the proportion of such a smooth surface is less than 90%, stacking faults generated near the surface other than the smooth surface adversely affect the characteristics of the device, which is not preferable. Further, by setting the ratio of the smooth surface to preferably 95% or more, it is possible to further reduce the influence of stacking faults generated near the surface other than the smooth surface adversely affecting the characteristics of the device. In the present invention, the area ratio is calculated only for the front and back surfaces, but a greater effect can be obtained by smoothing the side surface of the substrate.

  The resistivity of the p-type SiC single crystal substrate in the present invention is more than 0.012 Ωcm and 0.080 Ωcm or less, preferably more than 0.012 Ωcm and 0.050 Ωcm or less. If the resistivity exceeds 0.080 Ωcm, the resistance of the p-type SiC single crystal substrate is not negligible compared to the resistance of the element portion in the bipolar device, which is not preferable. By making the resistivity of the p-type SiC single crystal substrate more preferably more than 0.012 Ωcm and 0.025 Ωcm or less, the resistance of the substrate can be made sufficiently smaller than the element resistance. From the standpoint of device characteristics, the resistivity of the p-type SiC single crystal substrate is preferably as small as possible. However, the p-type impurity in the SiC single crystal has a solid solution limit, and about 0.012 Ωcm is substantially the lower limit of the resistivity. It becomes.

  Moreover, as for the thickness of the p-type SiC single crystal substrate, it is desirable that the lower limit is 0.05 mm or more and the upper limit is 0.9 mm or less, more preferably 0.6 mm or less. If the thickness of the p-type SiC single crystal substrate exceeds 0.9 mm, the substrate resistance is unnecessarily increased due to the thickness of the substrate, which is not preferable. From the viewpoint of device characteristics, the thinner the p-type SiC single crystal substrate, the better. However, considering the handling properties of the p-type SiC single crystal substrate for the purpose of preventing damage during the process, the substrate thickness In practice, the lower limit is about 0.05 mm.

  The polytype of the crystal of the p-type SiC single crystal substrate is not particularly limited, but when the SiC single crystal substrate of the present invention is applied to an electronic device such as a power device, crystal orientations of various semiconductor characteristics. It is preferable that it is 4H type | mold with little dependence.

  The effect of the present invention is considered to be manifested in a p-type SiC single crystal substrate having any crystal orientation. However, as a p-type SiC single crystal substrate used for manufacturing a power device or the like, from the {0001} plane, [11] -20] or [1-100] direction, it is desirable to have an offset angle of about 1 ° to 12 °. This is because when manufacturing a power device or the like, it is necessary to epitaxially grow SiC single crystal thin films having various conductivity on a p-type SiC single crystal substrate, but the offset angle from the {0001} plane is 1 °. If it is less than or more than 12 °, it is difficult to deposit a good-quality SiC epitaxial thin film.

The SiC single crystal substrate of the present invention is manufactured by cutting and polishing a low resistivity p-type SiC single crystal ingot manufactured by, for example, a sublimation recrystallization method. In general, in the sublimation recrystallization method, a SiC single crystal as a seed crystal and a SiC powder as a raw material are stored in a graphite crucible, and 2000 to 2400 ° C. in an inert gas atmosphere (133 to 13.3 kPa) such as argon. Heat to the extent. At this time, the temperature gradient is set so that the seed crystal has a slightly lower temperature than the raw material powder. The raw material is thermally decomposed when heated, and the generated sublimation gas is diffused and transported in the direction of the seed crystal, and recrystallized on the seed crystal set at a lower temperature than the raw material portion. At this time, the p-type dopant can be doped by crystal growth in a mixed gas obtained by adding a source gas containing an impurity element to an atmosphere gas made of an inert gas, or the impurity element in the SiC raw material powder. Alternatively, it is possible to mix the compounds, but from the viewpoint as described above, in the present invention, instead of the SiC raw material, high-purity silicon powder and high-purity carbon powder are mixed, and further Al ₄ C ₃ is added. After a fixed amount is added and mixed, raw material powder that has been baked at a high temperature of 1800 ° C. or higher in argon under atmospheric pressure is used. As the p-type dopant (impurity element), B can be used in addition to Al, or both of them may be used. When B is used, B ₄ C can also be used as the B compound to be mixed at the time of raw material powder synthesis in obtaining the above raw material powder.

Here, in obtaining the p-type SiC single crystal substrate in the present invention, preferably, a p-type dopant composed of either one or both of Al and B has a concentration of 5 × 10 ¹⁹ atoms / cm ³ or more and 1 × 10 ²¹ atoms / contained in cm ³ or less in the range, a range of n-type dopant of n of 1 × 10 ¹⁸ / cm ³ or more 6 × 10 ²⁰ atoms / cm ³ or less, and the content lower than the p-type dopant concentration Thus, a p-type SiC single crystal substrate is preferable. In this way, by simultaneously doping N, which is an n-type dopant, together with a p-type dopant, the occurrence frequency of base area layer defects due to high-temperature annealing treatment is suppressed, and 4H-type SiC necessary for an ultrahigh voltage power device, A p-type SiC single crystal substrate having a low resistivity can be suitably obtained.

  The p-type low resistivity SiC single crystal ingot manufactured by the sublimation recrystallization method as described above is processed into a single crystal substrate for device manufacturing by a substrate forming process mainly consisting of grinding, cutting and polishing. Each of these steps is performed by, for example, a surface grinder, a cylindrical grinder, a multi-wire saw, a double-side polishing apparatus, or the like, but is not limited thereto. Especially in the polishing process, it is usual to wrap using diamond slurry as abrasive grains, and while adjusting the substrate thickness, polishing is performed to gradually reduce the diamond particle diameter, and finally A polished surface having a surface roughness Ra of about 50 nm is formed. After the polishing process is completed, mechanochemical polishing is performed in order to obtain a higher flat surface (Ra: 0.3 nm or less). By performing mechanochemical polishing on both the front and back surfaces of the substrate except for the edge portion of the substrate, 90% or more of the total surface area of the substrate can be a smooth surface with Ra = 0.3 nm or less. Note that the method for realizing a smooth substrate surface is not limited to the above-described polishing method, and a surface treatment method using plasma or the like can be applied as long as a desired smoothness can be realized.

  The p-type SiC single crystal substrate of the present invention used for manufacturing a power device or the like has a diameter of the substrate of 50 mm or more, preferably 150 mm or more. If it is less than 50 mm, the device production efficiency decreases and the manufacturing cost increases. The upper limit of the substrate diameter is not particularly limited, but can be set to 300 mm from the viewpoint of avoiding an increase in manufacturing cost due to an increase in difficulty of the SiC single crystal manufacturing technology at the present time. That is, by making the diameter of the SiC single crystal substrate 50 mm or more and 300 mm or less, when manufacturing various power devices, a production line for conventional semiconductor (Si, GaAs, etc.) substrates established industrially is used. From the viewpoint of capital investment, it is convenient for mass production.

  For the p-type single crystal substrate of the present invention, even if high-temperature annealing is performed at a temperature range of 1000 ° C. to 1800 ° C., for example, the base area layer defect density after high-temperature annealing is 40 / cm or less, more preferably 20 / Since it can be kept below cm, it is particularly suitable for manufacturing high-current, high-power, ultra-high voltage and low-loss power devices.

  Moreover, it is possible to make an epitaxial wafer for power device manufacture by forming an epitaxial thin film having various conductivity on the p-type SiC single crystal substrate in the present invention. There are several methods for forming an epitaxial thin film on a p-type SiC single crystal substrate. Generally, a CVD (Chemical Vapor Deposition) method is usually employed. In the CVD method, a SiC single crystal thin film can be formed by supplying a raw material with a gas, decomposing the raw material gas with heat, and generating SiC by reaction.

  Examples of the present invention and comparative examples will be described below.

(Example 1)
FIG. 1 shows a SiC single crystal growth apparatus by a sublimation recrystallization method for manufacturing a p-type low resistivity SiC single crystal substrate of the present invention. However, FIG. 1 shows an example of the growth apparatus, and the present invention is not limited to this.
A seed crystal 1 made of SiC single crystal is attached to the upper surface inside the graphite crucible 3, and the lower part is filled with SiC powder 2 as a raw material. The graphite crucible 3 is installed inside the double quartz tube 4. A heat insulating material 5 is installed around the graphite crucible 3 and serves as a heat shield. The double quartz tube 4 can be highly evacuated (10 ⁻³ Pa or less) by the evacuation device 6, and the internal atmosphere can be pressure controlled by argon gas. If necessary, an appropriate amount of nitrogen gas can be mixed to dope the SiC single crystal for growing nitrogen. A work coil 7 is installed on the outer periphery of the double quartz tube 4 to heat the graphite crucible 3 by flowing a high-frequency current and to a predetermined temperature. The temperature is measured by providing an optical path with a diameter of about 2 to 4 mm in the center of the felt covering the upper part of the crucible (temperature measurement upper heat insulating material hole 10), taking out the light from the upper part of the crucible, The temperature during growth was measured by a color radiation thermometer.

Here, the raw material to be filled in the graphite crucible 3 was prepared by previously synthesizing SiC raw material powder containing Al. First, high-purity Si powder and high-purity carbon powder were mixed at a mass ratio of 1: 1. Furthermore, aluminum carbide (Al ₄ C ₃ ) powder was mixed and fired at 2000 ° C. for 30 minutes in an argon atmosphere. As for the mixing ratio at this time, the Al ₄ C ₃ powder is 0.0004 by mass ratio with respect to the mixed powder 1 of Si powder and carbon powder. The obtained fired product is crushed taking care not to mix impurities, and after removing unreacted raw materials, it is washed in fluorinated nitric acid to remove unnecessary metal impurities, and then dried to obtain a powdery raw material ( Al-added raw material powder).

  On the other hand, a 4H type SiC single crystal substrate having a {0001} plane having a diameter of 100 mm and a thickness of 1 mm as a main surface was prepared, and the growth surface was polished to obtain a seed crystal 1. After the inside of the double quartz tube 4 was evacuated, a current was passed through the work coil 7 and the temperature was raised until the surface temperature of the upper part of the crucible reached 2000 ° C. Thereafter, argon gas was introduced as an atmospheric gas, and the raw material temperature was raised to the target temperature of 2400 ° C. while maintaining the pressure in the quartz tube at about 80 kPa. At this time, the nitrogen gas mixing ratio was set to a constant value of 0.4 in terms of the argon gas flow ratio. Thereafter, the pressure was reduced to 1.3 kPa over about 30 minutes, and the growth was continued for about 70 hours. At this time, the crucible position with respect to the work coil was controlled to give a temperature gradient in the crucible. The obtained SiC single crystal had a diameter of 101.9 mm and a height of about 33 mm. The growth rate calculated from the crystal height is about 0.4 to 0.5 mm / hour.

When the SiC single crystal thus obtained was analyzed by Raman scattering spectroscopy, it was confirmed that a 4H type SiC single crystal was grown. Moreover, as a result of investigating the nitrogen (N) and Al concentration in the crystal by secondary ion mass spectrometry (SIMS), they were 9.1 × 10 ¹⁸ / cm ³ and 3.1 × 10 ²⁰ / cm ³ , respectively. there were. Further, the resistivity of the p-type SiC single crystal was measured by an eddy current method and found to be about 0.016 Ωcm.

  Then, a p-type SiC single crystal substrate (offset direction: [11-20] direction) is cut out from the grown SiC single crystal ingot with a 4 ° offset of {0001} plane having a diameter of 100.0 mm, and a diamond slurry having a particle size of 0.5 μm. Was polished. After the polishing, mechanochemical polishing using a highly alkaline colloidal silica slurry further containing an oxidation accelerator (hydrogen peroxide solution) was performed. At this time, the polishing amount calculated from the mass of the p-type SiC single crystal substrate before and after polishing is about 0.1 μm. The thickness of the p-type SiC single crystal substrate after polishing was approximately 0.35 mm. Mechanochemical polishing is performed on both the front and back surfaces of the p-type SiC single crystal substrate. As a result, 95% or more of the entire surface (front surface + back surface) of the p-type SiC single crystal substrate has a substantially constant surface roughness Ra. It was a smooth surface. As the surface roughness (Ra) of the smooth surface, when the mechanochemically polished surface was measured with an atomic force microscope, the surface roughness Ra was 0.15 nm. Here, the measurement with the atomic force microscope includes not only the center point of the substrate but also four points on the diameter that are orthogonal to each other and located 10 mm inside from the circumference (edge) to the center side. In addition, the measurement was performed at a total of five locations, and a 10 μm square region was measured at each measurement point. Further, the area ratio of the smooth surface was evaluated using an optical roughness measuring instrument and a Nomarski-type differential interference microscope in addition to the above atomic force microscope. Specifically, surface roughness is measured at several points in the plane with an atomic force microscope or an optical roughness measuring instrument, and then, using a Nomarski-type differential interference microscope, the same surface morphology as the measurement point is obtained. The area of the indicated area was estimated.

  The p-type SiC single crystal substrate thus produced was placed in a high-temperature annealing furnace and annealed at 1100 ° C. for 2 hours in an argon atmosphere. After annealing, the surface of the p-type SiC single crystal substrate taken out is etched with molten KOH at about 510 ° C., and observation of stacking faults by X-ray topography and measurement of etch pits corresponding to stacking faults by an optical microscope, When the average density of the base area layer defects in the p-type SiC single crystal substrate was determined, a value of 13.9 / cm was obtained. Thus, Ra of the p-type SiC single crystal substrate surface is smoothed to 0.14 nm by increasing the mechanochemical polishing amount to 0.1 μm or more, and such p-type SiC single crystal substrate is subjected to subsequent high-temperature annealing. There are few occurrences of base area layer defects. In addition, all the generated base area layer defects were confirmed to be double stacking faults by atomic stacking structure analysis using an electron microscope.

(Examples 2 to 5)
A p-type SiC single crystal substrate (offset direction: [11-20] direction) having a thickness of 0.25 mm with an 8 ° offset is cut out from the same ingot produced in Example 1, and a diamond slurry having a particle size of 0.5 μm is used. Polished. After the polishing, mechanochemical polishing using a highly alkaline colloidal silica slurry further containing an oxidation accelerator (hydrogen peroxide solution) was performed. Here, each p-type SiC single crystal substrate having 90% or more of a smooth surface having a surface roughness Ra shown in Table 1 was prepared by changing the time of mechanochemical polishing. The amount of polishing at this time is about 0.01 to 0.10 μm, and mechanochemical polishing is performed on both surfaces of the substrate in the same manner as in Example 1, and 90% or more of the entire surface (front surface + back surface) is approximately 90% or more. It was confirmed in the same manner as in Example 1 that the surface was smooth with a constant Ra.

  The p-type SiC single crystal substrates according to Examples 2 to 5 prepared above were simultaneously placed in a high-temperature annealing furnace and annealed at 1200 ° C. for 1 hour in an argon atmosphere. After annealing, each p-type SiC single crystal substrate is taken out and etched with about 510 ° C. molten KOH, and then the average density of base area layer defects in the p-type SiC single crystal substrate is determined in the same manner as in Example 1. did. Table 1 shows the relationship between the base area layer defect density and the surface roughness Ra.

  As can be seen from Table 1, on all p-type SiC single crystal substrates with Ra of 0.3 nm or less by mechanochemical polishing, the occurrence of base area layer defects occurring at high temperature annealing is as low as 40 / cm or less. there were. In addition, it was confirmed that when Ra is set to 0.2 nm or less, further 0.12 nm or less, an even greater effect of suppressing the occurrence of base area layer defects can be obtained.

(Examples 6 to 9)
A p-type SiC single crystal ingot according to Examples 6 to 9 was produced by a method substantially similar to that of Example 1. However, when synthesizing the SiC raw material powder, various Al-added raw material powders are produced by changing the Al ₃ C ₄ mixing amount and used as the raw material powder for the sublimation recrystallization method, so that the amount of Al to be doped in the ingot is reduced. Changed. Here, the nitrogen concentration in the atmospheric gas during single crystal growth was the same as in Example 1. The diameter of the obtained single crystal ingot was approximately 102.1 to 102.5 mm, and it was confirmed that all were made of only 4H type polytype.

  The ingot was ground, cut, and polished to produce a p-type SiC single crystal substrate having a diameter of 100 mm. The off angle and off direction of the p-type SiC single crystal substrate were the same as those in Example 1. The thickness of the p-type SiC single crystal substrate after polishing is 250 μm, and after polishing using diamond slurry, a highly alkaline colloid containing an oxidation accelerator (hydrogen peroxide solution) is used in the same manner as in Example 1. Mechanochemical polishing using silica slurry was performed. The polishing amount at this time is in the range of 0.4 to 0.5 μm. In addition, by practicing mechanochemical polishing on both surfaces of all p-type SiC single crystal substrates, the p-type SiC single crystal substrates of Examples 6 to 9 have almost 95% or more of the entire surface as shown in Table 2. It was covered with a smooth surface having a constant Ra.

After measuring the resistivity, Al concentration, and N concentration of the obtained p-type SiC single crystal substrates of Examples 6 to 9 in the same manner as in Example 1, annealing was performed in an argon atmosphere at 1000 ° C. for 4 hours. The average stacking fault density of each subsequent p-type SiC single crystal substrate was examined in the same manner as in Example 1. Table 2 summarizes the measurement results and the base area layer defect density. Note that. In all the samples, the N concentration was 8.2 × 10 ^{18 to} 9.8 × 10 ¹⁸ / cm ³ .

  As shown in Table 2, all of the p-type SiC single crystal substrates have a low resistivity of 0.080 Ωcm or less, but the p-type SiC has a smooth surface with a surface roughness Ra of 0.30 nm or less. By performing mechanochemical polishing so as to cover 95% or more of the surface of the single crystal substrate, it was confirmed that the base area layer defect density after annealing remained at a small value of 40 / cm or less.

(Comparative Examples 1-2)
Two p-type SiC single crystal substrates (offset direction: [11-20] direction) with an 8 ° offset and a thickness of 0.25 mm are cut out from the p-type SiC single crystal ingot produced in the same manner as in Example 1, and diamond slurry is obtained. The front and back sides were polished using At this time, the diamond abrasive grain size used in the final polishing step is two types of 1 μm and 0.5 μm, and the surface roughness Ra of the substrates according to Comparative Example 1 and Comparative Example 2 polished by these is 0.42 nm, It was 0.69 nm. The obtained SiC single crystal was examined in the same manner as in Example 1 for nitrogen (N), Al concentration, and resistivity in the crystal, and it was confirmed that substantially the same values were obtained.

  Thereafter, any p-type SiC single crystal substrate was not subjected to mechanochemical polishing at all, and immediately put into a high-temperature annealing furnace and annealed in an argon atmosphere at 1300 ° C. for 0.5 hour. After annealing, the p-type SiC single crystal substrate was taken out and etched with molten KOH at about 510 ° C., respectively, and the average density of base area layer defects in the p-type SiC single crystal substrate was determined in the same manner as in Example 1. . Table 3 shows the relationship between the base area layer defect density and the surface roughness Ra.

  As shown in Table 3, the base area layer defects increased greatly after annealing in all the substrates. Especially in the case of Comparative Example 2 having a surface roughness Ra of 0.69 nm, a large amount exceeding 2000 / cm. Base area layer defects have occurred.

1 seed crystal (SiC single crystal)
2 SiC crystal powder raw material
3 crucible
4 Double quartz tube (water cooling)
5 Insulation
6 Vacuum exhaust system
7 Work coil
8 Temperature measuring window
9 Two-color thermometer (radiation thermometer)
10 Upper insulation hole for temperature measurement

Claims (9)

  A p-type silicon carbide single crystal substrate having a volume resistivity of more than 0.012 Ωcm and not more than 0.080 Ωcm, and a surface roughness (Ra) of 0.3 nm or less is 90% or more of the total surface of the surface and the back surface of the substrate. A p-type low resistivity silicon carbide single crystal substrate characterized by the above.   2. The p-type low resistivity silicon carbide single crystal substrate according to claim 1, wherein a crystal polymorph (polytype) of the silicon carbide single crystal substrate is a 4H type. 3. A p-type dopant composed of one or both of Al and B is contained in a concentration range of 5 × 10 ¹⁹ atoms / cm ^{3 to} 1 × 10 ²¹ atoms / cm ³ , and an n-type dopant composed of N is 1 × 10 ^3. The p-type low resistivity according to claim 1, wherein the p-type low resistivity is within a range of ¹⁸ pieces / cm ³ or more and 6 × 10 ²⁰ pieces / cm ³ or less and at a lower concentration than the p-type dopant. Silicon carbide single crystal substrate.   The p-type low resistivity silicon carbide single crystal substrate according to any one of claims 1 to 3, wherein the thickness is 0.05 mm or more and 0.9 mm or less.   The p-type low resistivity silicon carbide single crystal substrate according to claim 1, wherein an offset angle from the {0001} plane is 1 ° or more and 12 ° or less.   The p-type low resistivity silicon carbide single crystal substrate according to any one of claims 1 to 5, wherein the diameter is 50 mm or more and 300 mm or less.   The p-type according to any one of claims 1 to 6, wherein when the high-temperature annealing is performed at 1000 ° C or higher and 1800 ° C or lower, the base area layer defect density in the substrate after the high-temperature annealing is 40 / cm or less. Low resistivity silicon carbide single crystal substrate.   The p-type according to any one of claims 1 to 6, wherein when the high-temperature annealing is performed at a temperature of 1000 ° C or higher and 1800 ° C or lower, the base area layer defect density in the substrate after the high-temperature annealing is 20 / cm or less. Low resistivity silicon carbide single crystal substrate.   The p-type low resistivity silicon carbide single crystal substrate according to any one of claims 1 to 8, which is used for production of a bipolar device.

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