JP2017059517A - Electronic apparatus, and printer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic apparatus that has fastness to a radiative radio frequency electromagnetic field with a simple structure, and reduces unnecessary radiation noise.SOLUTION: The present invention provides a printer 80 that is an electronic apparatus comprising a main substrate 10, a sub substrate 50, and an FFC 20 electrically connecting between the substrates, where a pair of differential signal lines 2,4 in the FFC 20 are disposed across a ground line 3.SELECTED DRAWING: Figure 2A

Description

  The present invention relates to an electronic device and a printer.

  For example, LVDS (Low Voltage Differential Signaling) and USB (Universal Serial Bus) are known as methods for transmitting digital signals at high speed between a plurality of circuit boards constituting an electronic device. Use line pairs. The differential signal line pair is transmitted on the circuit board by being configured to have a specific transmission line impedance by two signal line pairs and a ground pattern. On the other hand, for transmission between circuit boards, a pair of two signal lines is drawn out as a lead wire and transmitted as a twisted cable.

  The purpose of using this twisted structure cable is because it has a feature that noise emission from the differential signal line can be reduced. In order to enhance these functions, a so-called shielded cable structure in which the outer peripheral portion of a twisted line pair is covered with an electrode having a braided wire structure and used as a ground potential (ground electrode) is adopted. Furthermore, by adding a power supply line and other signal lines for connecting the circuit boards to the inside of the ground electrode, the flexibility of the cable is also utilized to electrically connect the boards in the electronic device. Traditionally used as a cable.

  In addition, as an inexpensive member for a cable connecting circuit boards, for example, an FFC (Flexible Flat Cable) having a structure in which a plurality of conductive lines are supported by an insulating material is used and disclosed in Patent Document 1 and Patent Document 2. As shown, a differential signal line pair is formed in the FFC as it is to transmit / receive differential signals.

JP 2010-143154 A JP 2013-4506 A

  However, when using a conventional shielded cable with a twisted differential signal line as described above, both ends of the shielded cable and male and female are used to electrically connect the cable and each circuit board. It is necessary to prepare a connector, which is an expensive member due to the product configuration of the electronic device to be manufactured.

  In addition to the twisted cable, the conventional shielded cable itself has a power cable and other signal lines that are necessary between the circuit boards. It was easy to become a part.

  Furthermore, by putting many lines in the shielded cable, the cable diameter becomes thick and the flexibility of the cable deteriorates. For this reason, in the narrow place in the electronic device to manufacture, especially in the place where the bending angle of a cable becomes an acute angle, storage in the electronic device to manufacture may become difficult. In the first place, a cable using a braided wire is not allowed to bend at an acute angle because the braided wire easily breaks against an acute angle bend.

  On the other hand, in the transmission of differential signals using FFC simply for the purpose of low cost, the lines of the differential signal line pair are arranged adjacent to each other via a space on the dielectric of the FFC, so that from the outside world It is vulnerable to interference caused by radiated radio frequency electromagnetic fields (80 MHz to 1000 MHz), and it is difficult to pass an immunity test (international standard: IEC61000-4-3, etc.) for products. In addition, noise radiation from the differential signal line on the FFC tends to increase, and it is difficult to satisfy the standards of unnecessary radiation such as VCCI Association (Voluntary Control Council for Information Technology Equipment). For this reason, the manufactured electronic equipment cannot satisfy the above-mentioned standard of EMC (Electro Magnetic Compatibility) and cannot be shipped as a product.

  The present invention has been made in view of such problems, and the object of the present invention is to have flexibility with a simple configuration, and to be bent, pasted, etc. and mounted in a casing of an electronic device. It is possible to ensure the transmission quality of differential signals between circuit boards in electronic equipment with an inexpensive flexible cable, while the flexible cable is robust against radiated radio frequency electromagnetic fields from the outside It is another object of the present invention to provide an electronic device with high EMC performance that can reduce unnecessary radiation noise.

[Application Example 1]
The electronic apparatus according to this application example includes a first circuit board, a second circuit board, and a conductive line that electrically connects the circuit on the first circuit board and the circuit on the second circuit board. Are arranged in parallel, and the flexible cable has a differential signal line pair for transmitting a differential signal by a first signal line and a second signal line, A ground line for supplying a ground potential to the first signal line and the second signal line is disposed between the signal line and the second signal line, and the first circuit board, the second circuit board, The power supply line for sharing the power supply is provided between the substrates.

  With this configuration, the differential signal line pair of the electronic device has robustness against the radiated radio frequency electromagnetic field from the outside, can reduce unnecessary radiation noise, and can provide an inexpensive electronic device.

[Application Example 2]
It is preferable that at least one of the ground lines also serves as a live line of the power supply line.

  With this configuration, the wiring for electrically connecting the circuit boards of the electronic devices can be connected at low cost with a flexible cable having flexibility.

[Application Example 3]
Preferably, the first signal line is grounded via a first capacitor, and the second signal line is grounded via a second capacitor.

  With this configuration, the differential signal line pair of the electronic device is further robust against the radiated radio frequency electromagnetic field from the outside, can reduce the radiation of unnecessary radiation noise, and can provide an inexpensive electronic device. .

[Application Example 4]
The flexible cable preferably has conductive lines arranged in parallel in the order of the ground line, the first signal line, the ground line, the second signal line, and the ground line.

  With this configuration, the differential signal line pair of the electronic device has robustness against the radiated radio frequency electromagnetic field from the outside, can reduce unnecessary radiation noise, and the signal quality transmitted through the differential signal line pair And the operation of the electronic device can be stabilized.

[Application Example 5]
The first signal line and the second signal line are electrically connected to each other via the first resistor on the first circuit board and the second resistor on the second circuit board, respectively. It is preferable to do.

  With this configuration, it is possible to maintain the quality of the signal waveform to be transmitted and reduce unnecessary radiation noise in the differential signal line of the electronic device.

[Application Example 6]
In the flexible cable, the width of each line is preferably 0.3 mm or more and 0.7 mm or less, and the width of the space between each line is preferably 0.2 mm or more and 0.3 mm or less.

  With this configuration, commercially available parts can be used, and EMC characteristics can be further enhanced.

[Application Example 7]
The first resistor and the second resistor are each preferably 200 ± 50Ω.

  With this configuration, impedance mismatch can be eliminated and the quality of the signal waveform to be transmitted can be stabilized and maintained.

[Application Example 8]
In the differential signal line pair, when the first circuit board side is the signal transmission side and the second circuit board side is the signal reception side, the differential output impedance of the differential signal output element on the first circuit board side With respect to the value (R1) and the second resistor (resistance value R2), it is preferable that R2 has a larger relationship than R1.

  With this configuration, the voltage amplitude of the differential signal on the receiving side can be increased, and communication between circuit boards is stabilized.

[Application Example 9]
The flexible cable has a third signal line and a fourth signal line, and the first signal line and the second signal line form a differential signal line pair for transmitting a clock signal, and a third signal line is formed. The signal line and the fourth signal line are arranged adjacent to each other to form a differential signal line pair for transmitting a data signal, and ground lines are arranged on both sides of the differential signal line pair for transmitting a data signal. It is preferable that

  With this configuration, it is possible to suppress an increase in the number of ground lines in the flexible cable, and thus it is possible to reduce the costs associated with the flexible cable and its connector members. Also, the connector mounted on the circuit board can be miniaturized, and the mounting area on the circuit board can be reduced.

[Application Example 10]
The electronic device is preferably a printer.

  By applying it to a printer, it is possible to ensure the robustness against radiated radio frequency electromagnetic fields and reduce unnecessary radiation noise at low cost.

1 is a schematic configuration diagram of a printer according to Embodiment 1. FIG. The block diagram of the differential signal line pair in FFC. The block diagram between the boards connected using FFC. The model figure for simulating the influence of a radiation | emission radio frequency electromagnetic field. The figure which showed the voltage change (interference voltage) of the IC input terminal of the receiving side LVDS. The figure which showed the voltage change (interference voltage) of the IC input terminal of the receiving side LVDS. The figure which showed the tendency of the unnecessary radiation about FFC. The model figure for simulating the influence by an ESD test. The figure which showed the waveform of the discharge current of an ESD test. The figure which showed the disturbance voltage by the ESD test of FFC. The figure which showed the disturbance voltage by the ESD test of FFC. FIG. 3 is a configuration diagram of a printer according to a second embodiment. The block diagram of FFC which concerns on the modification 2. FIG. FIG. 2 is a configuration diagram of a printer using FFC. The figure of the frequency distribution of the clock signal 32MHz of LVDS output. The figure of the frequency distribution of the data signal 64Mbps of LVDS output. The model figure of the printer which mounted FFC. The elements on larger scale which show the state of bending (folding) of FFC. The figure which shows the eye pattern of FCC. The figure which shows the eye pattern of the conventional FFC.

  Hereinafter, an electronic device of the present invention will be described with reference to the drawings, taking a preferred embodiment as an example. In the following drawings, the scale of each member is made different from the actual scale so that each member can be recognized.

(Embodiment 1)
<< Schematic configuration of electronic equipment >>
FIG. 1 shows the configuration of a printer as an example of the electronic apparatus according to the first embodiment of the present invention. A printer 80 as an electronic apparatus according to the present embodiment includes a main board 10 serving as a first circuit board, a sub board 50 serving as a second circuit board, and a sub board 60 serving as another third circuit board. have.

The main board 10 includes a circuit that realizes the function of the printer, a power supply circuit unit 13, and the like. The ground line 15 is fixed to the main substrate 10 and is electrically connected to a metal frame 40 that houses a printer head, a paper feeding device, and the like, which are main members for printing. As a general electrical configuration, the metal frame 40 is grounded outside the printer 80.
Next, the sub board 50 is a board on which a display body such as an LCD (Liquid Crystal Display) is mounted, and the sub board 60 is a board on which, for example, a slot for mounting an external memory medium is mounted. The sub-boards 50 and 60 are arranged at a position away from the main board 10 because they are arranged at an optimal location on the exterior of the printer so as to be a display unit and a memory mounting unit that are convenient for the user.

The main board 10 and the sub boards 50 and 60 are electrically connected by FFCs 20 and 30 (flexible cables), respectively. The power supply and ground supplied to the sub-boards 50 and 60 are connected to the power supply line 11 and the ground line 15 in the main board 10, respectively, and the power supply line 21, the ground line 25, the power supply line 31, and the ground in the FFCs 20 and 30 Electrical connection is made via line 35.
In an actual configuration, when the sub-boards 50 and 60 cannot be directly bonded to the metal frame 40, the power supply and the ground potential as a signal pair are connected via a line in the FFC.

  Further, regarding each signal transmission between boards, when importance is attached to high-speed data transmission, the main board 10 and the display function sub-board 50 are LVDS, and the main board 10 and the memory function sub-board 60 are USB. High-speed transmission lines using differential signals are used. The signal lines 22 and 32 in the FFCs 20 and 30 become differential signal transmission paths.

<Configuration of FFC>
Here, FIG. 2A shows the configuration of the differential signal line pair of the differential signal transmission path in the FFC according to the present embodiment. In FIG. 2A, the FFC 20 has a plurality of line-shaped electrodes 1 to 5 (conductive lines) supported by an insulating material 7 in parallel arrangement, the electrodes 1, 3, and 5 are ground lines, and the electrodes 2, 4 are It is a differential signal line (a first signal line and a second signal line forming a differential pair).

The conventional concept of differential lines is based on how to handle analog high-frequency signals, and differential signals by two conductors are treated like balanced signals at analog high frequencies. Since the handling of the balance signal is basically transmission by two conductors that do not depend on the ground potential, the two conductors have electromagnetic coupling such that high-frequency currents flow in opposite directions. Since it becomes important in transmission, it was necessary to make the design as close as possible even with FFC or the like.
On the other hand, the ground potential is more important for digital differential lines. For example, when a clock signal is transmitted as a differential pair, the two signal lines (signal lines) forming the differential pair each set the amplitude voltage of the clock signal (pulse wave) with respect to the ground potential between the two signal lines. The high side voltage and the low side voltage are sent in synchronization. Therefore, unlike an analog differential signal, the degree of electromagnetic coupling between two signal lines forming a differential pair is not so important, and two differential lines are formed as shown in FIG. 2A. Even if a ground electrode (electrodes 1, 3, 5) is disposed between the signal lines (electrodes 2, 4), a desired differential signal can be transmitted.

However, it is necessary that the impedance of the transmission line is equal to the ground electrode (potential) of the signal line between the two signal lines forming the differential pair. That is, as shown in FIG. 2A, the differential signal line (electrode) 2 is sandwiched between the ground lines (electrodes) 1 and 3, and the differential signal line (electrode) 4 is sandwiched between the ground lines (electrodes) 3 and 5. The differential signal lines 2 and 4 have substantially the same line width, and the space between the lines needs to be substantially the same. Thereby, the impedance of each transmission line of the differential signal lines 2 and 4 with respect to the ground lines 1, 3 and 5 can be equalized.
It is extremely important to make the impedances equal. If the impedances of the differential signal lines 2 and 4 are not equal, a voltage difference is generated between the signals transmitted in the differential signal lines 2 and 4, Since the in-phase component as a transmission component increases, it becomes a factor which increases the unnecessary radiation noise as an apparatus.

Furthermore, the structure at the time of connecting between board | substrates using FFC20 which concerns on this embodiment is shown to FIG. 2B. FIG. 2B is a detailed view of the main part centering on the FFC 20 in FIG. In FIG. 2B, the main board 10 that is the first circuit board and the sub board 50 that is the second circuit board are connected using the FFC 20. One end of the differential signal lines 2 and 4 of the FFC 20 is electrically connected to the differential signal output terminals 102 and 103 of the IC 110 serving as the differential signal transmission side on the main substrate 10 and grounded. Capacitors 112 and 113 (first capacitor and second capacitor) are also electrically connected. The capacitors 112 and 113 are capacitors having substantially the same capacitance value.
In addition, the other ends of the differential signal lines 2 and 4 are electrically connected to the differential signal input ends 202 and 203 of the IC 210, respectively, on the differential signal receiving side on the sub-board 50, and It is also electrically connected to capacitors 212 and 213 which are grounded via ground lines 1, 3 and 5. For the ICs 110 and 210, the transmission / reception relationship may be the reverse relationship described above, or each of the ICs 110 and 210 may be used for both transmission and reception.
The ground electrode 105 in the main substrate 10 is connected to an external ground potential. The ground electrodes in the sub-board 50 are connected by ground lines 1, 3, 5 in the FFC 20. Alternatively, a harness and a lead wire for electrically connecting the ground electrode of the main board 10 and the ground electrode of the sub board 50 using another connection line (not shown) other than the FFC 20 are added. Good.

<< Evaluation by simulation >>
Next, regarding the printer which is the electronic device according to the present embodiment, the influence received under the radiation radio frequency electromagnetic field was examined using electromagnetic field simulation. The details of the simulation will be described below with reference to FIG.
FIG. 3 is a diagram showing an outline of a simulation model when the printer 80 is exposed to a radiated radio frequency electromagnetic field. The printer 80 is a model in which a metal portion that has an electromagnetic influence is mainly extracted, and includes a metal frame 40, a main board 10, and a sub board 50 on which a display body such as an LCD is mounted. In order to perform high-speed data transmission between the main board 10 and the sub board 50, connection is made using LVDS, and the FFC 20 is used for this.

The FFC 20 has the configuration described in FIG. 2A (referred to as “GSSGSG configuration”), and was compared with the configuration illustrated in Patent Document 1 (referred to as “GSSG configuration”). Each electrode of the FFC 20 is made of copper, and with respect to the cross-sectional shape in the width direction of each line-shaped electrode, the thickness is 0.035 mm, and the width of the electrode and the space between the electrodes are simulated under the following condition settings. It was.
Condition [A] The electrode width is 0.7 mm, and the space between the electrodes is 0.3 mm.
Condition [B] The width of the electrode is 0.3 mm, and the space between the electrodes is 0.2 mm.
Accordingly, in the configuration of the condition [A], each line-shaped electrode is arranged in the FFC at a pitch of 1 mm, and in the configuration of the condition [B], each line-shaped electrode is arranged in the FFC at a pitch of 0.5 mm. From the viewpoint of component mounting, in the case of the configuration of the condition [B], there is an advantage that the length in the width direction of the FFC is substantially halved compared to the condition [A].
The insulating material that supports each line-shaped electrode of the FFC 20 has a relative dielectric constant of 3.5 and covers the line-shaped electrode by 0.05 mm in the thickness direction.

  The main board 10 has a general shape of 141 mm in the X direction, 64 mm in the Y direction, and 1.2 mm in the Z direction. Since it can be regarded electrically as one conductive plate, it is composed of copper alone for the sake of simplification of the model. The sub-board 50 has a general shape of 186 mm in the X direction, 55 mm in the Y direction, and 1.6 mm in the Z direction, and is composed of copper alone for the same reason as described above. The main board 10 is mounted on a metal frame 40 (general shape: 380 mm in the X direction, 74 mm in the Y direction, and 112 mm in the Z direction) made of a steel plate, and is electrically connected by screws 301, 302, and 303.

The length of the FFC 20 was set to 236 mm in this simulation. One end of the FFC 20 is connected by a connector portion 305 of the main board 10. Of the lines of the FFC 20, three ground lines are directly connected to the main board 10, and two differential signal lines are connected to the main board 10 through 50Ω resistors (not shown). The resistance of 50Ω replaces the impedance of the LVDS output buffer on the main board 10 side. On the other hand, the other end of the FFC 20 is connected to the sub board 50 by the connector portion 605. The three ground lines of the FFC 20 are directly connected to the sub board 50. On the other hand, the two differential signal lines of the FFC 20 are connected to each other via a 100Ω termination resistor (not shown) on the LVDS reception side, and both ends of the termination resistor are connected to the sub-board 50. Each is connected via a capacitance value of 3 pF. This capacity is the load capacity value at the input end of the LVDS receiving IC, and no capacitor is mounted.
The space 100 is a rectangular parallelepiped region to be calculated, and a radiation radio frequency electromagnetic field (electric field direction: Z direction) having an electric field strength of 6 V / m is incident from the positive side in the X direction of the YZ plane 801.

FIG. 4 is a graph showing a change in voltage at one terminal of the terminating resistance of the LVDS with respect to the ground potential of the sub-board 50 (that is, the input terminal of the LVDS IC on the receiving side) according to each incident radio frequency. is there. The horizontal axis represents the frequency of the incident radio frequency electromagnetic field (30 MHz to 1000 MHz), and the vertical axis represents the induced (interference) voltage (unit: V). Each graph of FIG. 4 shows the above condition [A] (electrode 1 mm pitch) (graph line A in the figure) when the pitch of the line electrode is 1 mm (graph E in the figure) in the conventional GSSG configuration. The voltage with respect to the above condition [B] (electrode 0.5 mm pitch) (graph line B in the figure) is shown.
In either condition, when a radiation radio frequency electromagnetic field of about 150 MHz is received, a disturbance voltage is generated at the IC input terminal on the receiving side of the LVDS. Specifically, the maximum value of the disturbing voltage exceeds 2V on the graph line E, while the graph lines A and B are both halved to about 1V. Also, the graph lines A and B are significantly lower than the graph line E in the frequency range before and after the peak (from 100 MHz to 250 MHz). It has been experimentally confirmed that there is a correlation between the tendency of the disturbing voltage and the tendency of malfunction of the display unit of the LCD connected to the LVDS (the display state of the LCD deteriorates when the disturbing voltage increases).
Therefore, by reducing this disturbing voltage, the occurrence of LCD display defects can be reduced. That is, FIG. 4 shows that the interference voltage can be reduced to half or less in the GSSGSG configuration of the present embodiment compared to the conventional GSSG configuration. Note that the simulation results in FIG. 4 are results in a state where the capacitors 112, 113, 212, and 213 in FIG. 2B are not mounted.

  In order to further reduce the interference voltage, as shown in FIG. 2B, one end of each differential signal line of the FFC 20 is connected to the other electrode of the capacitor with one electrode grounded on the main board 10, respectively. The other end of each differential signal line of the FFC 20 is connected to the other electrode of the capacitor with one electrode grounded on the sub-board 50. In addition, the simulation which performs the incidence | injection of a radiation | emission radio frequency electromagnetic field on the same conditions as the above was performed for the capacitance value of each capacitor | condenser as 10 pF.

  FIG. 5 shows the results at this time, and data (graph line E in the figure) for the conventional GSSG configuration shown in FIG. 4 is added for comparison. In FIG. 5, the horizontal axis and the vertical axis are the same as those in FIG. Here, the graph line C in FIG. 5 is the result of applying the FFC 20 under the condition [A] (electrode 1 mm pitch) and the graph line D is the condition [B] (electrode 0.5 mm pitch). Specifically, although the generation tendency of the disturbance voltage is not different from that in FIG. 4, the peak value of the disturbance voltage in the approximately 150 MHz band is reduced to 0.7 V or less for both the graph lines C and D. Therefore, it was shown that the interference voltage can be further reduced by adding the capacitor as compared with the result of FIG.

Here, when the immunity with respect to the radiation | emission radio frequency electromagnetic field of the printer 80 is put together, the following effects can be acquired about FFC20.
(1) The GSSG configuration which is the configuration of the present embodiment improves the immunity with respect to the radiated radio frequency electromagnetic field as compared with the conventional configuration.
(2) By narrowing the pitch of the line-shaped electrodes having the GSSG configuration which is the configuration of the present embodiment, immunity is further improved with respect to the radiated radio frequency electromagnetic field.
(3) By electrically connecting one electrode to the other electrode of the grounded capacitor at both ends of each differential signal line of the GSSGSG configuration which is the configuration of the present embodiment, the radiated radio frequency electromagnetic field is further increased. On the other hand, immunity is improved.
The above effect was shown by simulation, and this tendency was confirmed in the immunity test for the radiated radio frequency electromagnetic field of an actual printer.

In addition, a simulation was performed for the situation of unnecessary radiation according to the configuration of the present embodiment. The simulation model examined is the same as that in FIG. 3, but in the above simulation, a 50 Ω resistor grounded as an output resistor is connected to each differential signal line in the connector portion 305 with the FFC 20 on the main board 10. In this simulation, the 50Ω resistor is replaced with a signal source that is a noise source. The maximum value of the level of each frequency radiated from the printer 80 by each frequency input by the signal source is based on the conventional GSSG configuration (the interval between the line electrodes is 1 mm pitch), and the following conditions ([ A) to [D]) were simulated.
Condition [A] Regarding the FFC 20, the GSSG configuration (the interval between the line electrodes is 1 mm pitch) according to the present embodiment was adopted.
Condition [B] Regarding the FFC 20, the GSSG configuration according to the present embodiment (the interval between the line electrodes is 0.5 mm pitch) is used.
The conditions [A] and [B] are the same as those described above.
Condition [C] Electrically connected to the other electrode of the capacitor with one electrode grounded at both ends of each differential signal line of the GSSG configuration (the interval between the line electrodes is 1 mm pitch) according to the present embodiment with respect to the FFC 20 did.
Condition [D] Electrically connected to the other electrode of the capacitor with one electrode grounded at both ends of each differential signal line of the GSSG configuration (the interval between the line electrodes is 0.5 mm pitch) according to the present embodiment with respect to the FFC 20 Connected to.
From the above, the situation of improvement of unwanted radiation was analyzed by comparing the maximum values at each frequency for each configuration condition. The result is shown in FIG.

  In FIG. 6, the horizontal axis represents the frequency (unit: MHz) of the input signal source. The vertical axis represents the electric field intensity of unnecessary radiation in the conventional GSSG configuration subtracted from the electric field intensity (unit: dB μV / m) of unnecessary radiation radiated from the printer 80 due to the signal source. It is represented by a difference in electric field strength (unit: dB). That is, when the difference in electric field strength is lower than 0 dB (negative value), it indicates that the level of unnecessary radiation is improved (reduced). The alphabet in the graph corresponds to the condition alphabet. Specifically, regarding the conditions [A], [B], [C], and [D], the electric field strength difference shows a negative value at most frequencies. Further, the values of the graphs C and D that are the configurations connected to the capacitors show negative values at all the measurement frequencies, and the numerical values are lower than the values of the graphs A and B that are the configurations that do not apply the capacitors.

From FIG. 6, unnecessary radiation can be summarized as follows.
(4) The level of unnecessary radiation is improved by the GSSG configuration which is the configuration of the present embodiment, compared to the conventional GSSG configuration.
(5) By reducing the pitch of the line-shaped electrodes having the GSSG configuration which is the configuration of the present embodiment, a tendency to improve the level of unnecessary radiation can be further observed.
(6) Further improvement of the level of unnecessary radiation by electrically connecting to the other electrode of the capacitor grounded to one electrode at both ends of each differential signal line of the GSSG SG configuration which is the configuration of this embodiment. There is a trend.
The above effect was shown by simulation, and this tendency was confirmed in actual measurement of unnecessary printer radiation.
As described above, with the configuration of the FFC 20 according to the present embodiment, it is possible to provide an electronic device with high EMC performance that has robustness against a radiated radio frequency electromagnetic field and also reduces unnecessary radiation noise.

As a further effect, the configuration of the FFC 20 according to the present embodiment also functions as a measure against performance deterioration or malfunction of an electronic device due to ESD (Electrostatic Discharge).
FIG. 7 is a diagram showing an outline of a model for simulating an ESD test of the printer 80. The configuration is the same as the model of the printer 80 shown in FIG. 3, but an abutment portion of an ESD gun is added to the ESD application location 91 on the metal frame 40, and a ground 90 is added as a current flow destination by the applied ESD. Model.
FIG. 8 is a diagram for explaining the current waveform of ESD applied to the metal frame 40 by the ESD gun. According to the international standard IEC61000-4-2, the rise time is 0.7 ns, and the peak value of the output current is 18 A ±. 10%.
The voltage response at the IC input terminal on the LVDS reception side on the sub-board 50 when this ESD was applied was compared with the conventional configuration under the conditions [A] and [B] of the FFC 20. The results are shown in FIG.
In FIG. 9, the horizontal axis indicates the elapsed time after the current application of the ESD gun, and the vertical axis indicates the damped oscillation of the response voltage with respect to the applied current. The larger the amplitude, the greater the damage to the input part of the receiving LVDS IC, and the longer the large voltage oscillation lasts, the more likely the LCD display malfunctions. The conditions [A] (graph line A in the figure) and [B] (graph line B in the figure), which are the structures of the FFC 20 according to the present embodiment, are all the structures of the conventional FFC (graph lines in the figure) in FIG. Compared to E), the amplitude of the voltage is less than half and the decay time is also shortened.
Therefore, the following effect can be said by FIG.
(7) With the GSSG configuration that is the configuration of the present embodiment, the occurrence of defects in the ESD test is improved as compared with the conventional GSSG configuration.
(8) The occurrence of defects in the ESD test is further improved by narrowing the pitch of the line-shaped electrodes having the GSSG configuration which is the configuration of the present embodiment.
Furthermore, regarding the FFC 20, FIG. 10 shows the result of comparing the above conditions [C] and [D] with the conventional configuration. 10, the horizontal axis and the vertical axis are the same as those in FIG. 9, and the condition [C] corresponds to the graph line C, and the condition [D] corresponds to the graph line D. In FIG. 10, the voltage that responds clearly is smaller than that of the conventional configuration (graph line E in the figure), and the voltage amplitude after about 30 ns after ESD application is smaller than the graph lines A and B. It has been shown that the influence from ESD can be reduced quickly.
Therefore, the following effect can be said from FIG.
(9) By connecting one electrode to the other electrode of the grounded capacitor at both ends of each differential signal line of the GSSGSG configuration which is the configuration of the present embodiment, further occurrence of problems due to the ESD test Improve.
This tendency has also been confirmed in actual printer ESD tests.
In the present embodiment, LVDS using differential transmission has been described. However, the present invention can be applied as a harness for electrically connecting boards in other transmission systems using differential signals such as USB.

(Embodiment 2)
<Impedance-related>
FIG. 11 is a configuration diagram of a printer according to the second embodiment. First, before describing the specific configuration of the second embodiment, a problem due to impedance mismatch will be described.
As described in the first embodiment, in the FFC 20, the line widths of the differential signal lines 2 and 4 and the ground lines 1, 3 and 5 are preferably 0.3 mm or more and 0.7 mm or less, and more preferably. Is 0.3 mm or more and 0.5 mm or less, and the space between each line is preferably 0.2 mm or more and 0.3 mm or less. This is based on the simulation results of the inventors. By setting the width of each line and the space between each line in the above range, it is possible to use an FFC that is inexpensive and can be easily accommodated in the housing of the electronic device, and the immunity of the applied electronic device is increased. Can be improved. At this time, the single-ended impedance of each transmission path with respect to the ground lines of the differential signal lines 2 and 4 in the FFC 20 is about 100Ω due to the cross-sectional structure of the wiring, and the differential signals are transmitted through the differential signal lines 2 and 4. In this case, the differential impedance of the differential signal lines 2 and 4 is about 200Ω. In general LVDS, since the output impedance of a differential IC is 100Ω, there is a concern about a problem due to impedance mismatch.

However, the impedance matching between the signal source and the transmission line is rough in digital as compared with analog, and in particular, the repetitive frequency band of the rectangular wave signal to be handled is about 30 MHz or less, and the rise time of the rectangular wave signal is about 10 ns or more. In this case, even if there is a mismatch between the output impedance on the transmission side and the impedance of the transmission line, the impedance of the terminating resistor on the reception side is dominant for the output impedance in the harness wiring length (about 500 mm or less) in the electronic equipment. Therefore, the impedance of the transmission line can be ignored, and there is no problem in the operation in the actual circuit.
On the other hand, if the repetitive frequency band of the rectangular wave signal to be handled is 30 MHz or more and the rising time of the rectangular wave signal is about 10 ns or less, the high-frequency component included in the rectangular wave increases. The mismatch of impedance and termination resistance cannot be ignored, the quality of the signal waveform to be transmitted is deteriorated, ringing of the signal waveform or the like may cause trouble in circuit operation and increase unnecessary radiation noise from the device.

A method for solving this problem will be described with reference to FIG. In FIG. 11, the same reference numerals as those in FIG. 2B denote the same members. The difference is that a resistor 150 as a first resistor is added to the output portion of the IC 110 on the main board 10 which is the transmission side of the differential signal, and the IC which is the reception side of the differential signal on the sub-board 50. Is changed to an IC 210A configured so that a terminal resistor 250 as a second resistor can be externally attached. At this time, when the differential output impedance of the IC 110 on the differential signal transmission side is 100Ω, the differential signal output on the differential signal transmission side is set by setting the resistance 150 and the termination resistor 250 to 200Ω respectively. The impedance viewed from the output part of the IC 110 as an element is 100Ω, and the impedance mismatch described above can be eliminated.
That is, by adding the resistor 150 set to 200Ω, the differential impedance on the load side (sub-board 50 side) viewed from the connection with the FFC 20 at the differential signal output terminals 102 and 103 can be set to 200Ω. . On the other hand, in the FFC 20 according to the present embodiment, as described above, the differential impedance of the differential signal lines 2 and 4 is about 200Ω, so that connection in a substantially impedance matching state is possible. Further, by terminating the differential signal on the sub-board 50 with a termination resistor 250 set to 200Ω, the transmitted differential signal can be received in a substantially non-reflecting state.
As a result, a high-speed rectangular wave differential signal having a repetition frequency band of 30 MHz or more and a rise time of about 10 ns or less can be transmitted while maintaining the quality of the signal waveform in the FFC according to the present invention. is there.

The resistance values of the resistor 150 and the termination resistor 250 are appropriately determined by the output impedance of the IC 110 on the differential signal transmission side and the differential impedance of the FFC 20, but are preferably 150Ω or more and 250Ω or less, more preferably. Is 200Ω (one significant digit). Thereby, impedance mismatch can be reduced or eliminated in the line width and inter-line space of the FFC 20 of the present embodiment. In the above embodiment, the resistor 150 and the terminating resistor 250 have the same resistance value. It is possible to set different values for problems such as actual operating conditions and EMC, but it is preferable to set the same values from the viewpoint of parts procurement.
At this time, the resistance value (R2) of the termination resistor 250 always has a relationship of R2> R1 when compared with the output impedance value (R1) of the IC 110. Thereby, even if the resistor 150 is added, the voltage amplitude of the differential signal in the termination resistor 250 is not reduced, and the transmission quality by the differential signal between the circuit boards is stabilized.

  The present invention is not limited to the above-described embodiment, and various changes and improvements can be added to the above-described embodiment. A modification will be described below.

(Modification 1)
This will be described with reference to FIG. 2A. In the above embodiment, the pair of differential signal lines 2 and 4 are arranged in the FFC 20 of FIG. 2A, but a plurality of pairs of differential signal lines may be formed in a single FFC. That is, each signal line constituting the differential signal line pair only needs to be arranged between the ground lines, and a plurality of differential signal lines of the second, third, or more in a single FFC. A pair (differential line) may be arranged. Specifically, in the configuration of FIG. 2A, as a new second differential line outside the ground lines 1 or 5 on both sides, one differential signal line of the second differential line, the ground line, The other differential signal line and the ground line of the second differential line can be arranged. Further, the third and subsequent differential lines are preferably configured in a similar arrangement.

  Further, other signal lines that are not differential can be arranged outside the outermost ground line. Similarly, the power line can be arranged outside the ground line in the outermost row. Generally, the power line is a so-called bypass capacitor (one electrode is grounded) near the connector on the board to which the FFC is connected. The capacitor is connected to a capacitor having a relatively large capacity, and the impedance of the high frequency band is reduced. Therefore, for example, referring to FIG. 2A, it is possible to use at least one of the ground lines 1, 3, and 5 as a power supply line. Although it is possible to use one of the outermost ground lines 1 and 5 as a power supply line, considering the symmetry of the single-ended impedance of the signal lines 2 and 4, the ground line 3 is used as the power supply line. Alternatively, two ground lines 1 and 5 can be used as power supply lines. In addition, a plurality of ground lines 1, 3, and 5 are used as power lines when a component that requires a relatively large current is mounted on the circuit board side that is supplied with power through the FFC. More preferably, a plurality of power supplies can be supplied, the voltage drop due to the resistance of the FFC electrode can be reduced, and the operation of the electronic apparatus can be stabilized.

  Here, for example, when FFC is applied to LVDS, as an actual configuration, a pair of differential lines are used for clock signal transmission, and for a data signal, a pair of differential lines is used as one channel and a multi-channel is used. The transmission width (bandwidth) of data is set by transmitting with. Therefore, the configuration of the present invention is preferably such that the line-shaped electrodes are thin and the space between the line-shaped electrodes is narrow, that is, the so-called line-shaped electrode pitch is smaller. However, due to the practicality, durability, workability during assembly, and stability of the actual manufacturing method of the connector in which both ends of the FFC are inserted / removed, inevitably, it is necessary to supply a narrow pitch FFC stably and at low cost. However, the 0.5 mm pitch FFC shown in the embodiment is the most preferable configuration.

As described above, according to the present modification, in addition to the effects in the above embodiment, the following effects can be obtained.
By placing each differential signal line between ground lines, even if multiple differential signal line pairs are placed in a single FFC, they are robust against radiated radio frequency electromagnetic fields and reduce unwanted radiation noise. Electronic equipment can be provided. Further, by using the ground line as a power supply line, the number of FFC line electrodes used can be reduced. Furthermore, since each line electrode of FFC is formed with the same width, it can be used for purposes other than the purpose of a differential signal line harness, and can be used as a highly versatile harness. And can be obtained at low cost.

(Modification 2)
The configuration of the FFC according to this modification will be described with reference to FIG. FIG. 12 is a schematic diagram illustrating a configuration of an FFC differential signal line pair. In the present modification, the same reference numerals are used for the same components as those in the above embodiment, and duplicate descriptions are omitted.

  The FFC 120 shown in FIG. 12 includes a power supply (Vcc) line 121, a differential signal line pair 123 for clock signals, differential signal line pairs 124, 125, and 126 for data signals, and other control signal (Cont) lines. 122. The differential signal line pair 123 for the clock signal has a GSSG configuration in which ground lines (G) are arranged on both sides of the differential signal line (S) as in the above embodiment. On the other hand, the differential signal line pairs 124, 125, and 126 for data signals do not have a ground line between the differential signal lines as the third signal line and the fourth signal line, and thus the difference. The GSSG configuration is such that the motion signal lines are arranged next to each other in parallel. Here, the outer ground lines of the differential signal line pairs 123, 124, 125, and 126 are configured to be shared with the outer ground lines of other adjacent differential signal line pairs.

  Next, connection between substrates using the FFC of this modification will be described with reference to FIG. FIG. 13 is a configuration diagram of a printer using FFC. FIG. 13 corresponds to FIGS. 2B and 11.

  A printer 180 illustrated in FIG. 13 includes a main substrate 10, a sub substrate 50, and an FFC 120. An IC 110 (circuit) on the differential signal transmission side is mounted on the main substrate 10, and an IC 210 (circuit) on the differential signal reception side is mounted on the sub-substrate 50. The IC 110 and the IC 210 are electrically connected by the above-described FFC 120 in FIG.

  Two differential signal lines (S) of the differential signal line pair 123 for clock signals are connected to the clock terminal of the IC 110. The two differential signal lines extend to the sub-board 50 and are connected to the receiving-side IC 210. On the sub-board 50, a termination resistor 250 is connected between the two differential signal lines. A ground line (G) is disposed between and adjacent to the two differential signal lines. In other words, two differential signal lines are arranged between three ground lines, and five lines run in parallel to form a GSSG SG configuration.

  Next, the differential signal line pair 124, 125, 126 for data transmission will be described by taking the differential signal line pair 124 as an example. The two differential signal lines of the differential signal line pair 124 have one end connected to the data output terminal of the IC 110 and the other end connected to the input terminal of the IC 210. On the sub-board 50, a termination resistor 250 is connected between the two differential signal lines. A ground line is disposed on both sides of the pair of differential signal lines. In other words, with a pair of differential signal lines sandwiched between two ground lines, the four lines run in parallel to form a GSSG configuration. Here, the data 131 is transmitted from the output terminal of the IC 110 through the two differential signal lines.

  The differential signal line pairs 125 and 126 are the same as the differential signal line pair 124 described above except that the differential signal line pair 125 transmits data 132 and the differential signal line pair 126 transmits data 133. The GSSG configuration is used.

  As described above, the FFC 120 used in the printer 180 has a differential signal line pair for clock signals in a GSSG configuration and a differential signal line pair for data signals in a GSSG configuration. This is based on the simulation results of the inventors. Specifically, for the differential signal line pair for data signals, a simulation result has been obtained that the intended electromagnetic environment compatibility can be ensured even with the GSSG configuration. Hereinafter, data on the simulation result will be described.

  A typical LDVS has a configuration in which a pair of differential signal lines that transmit a clock signal and a plurality of differential signal line pairs that transmit a data signal are combined. Therefore, the FFC has a configuration in which a plurality of differential signal line pairs for data signals are formed and the number of ground lines is further increased compared to the configuration of FIG. 2A of the above embodiment. In this case, since an FFC and a connector to be mated with the FFC use an existing member, it is necessary to prepare a multi-pin FFC and a connector corresponding to the increase in one conductive line. The FFC and the connector having more pins than usual are more expensive as the member cost, and the mounting area by the connector is also increased on the circuit board side to be mounted.

  Therefore, the rectangular waveforms of the clock signal and the data signal were compared by simulation, and the characteristics of the GSSG configuration in the data signal differential signal line pairs 124, 125, 126 were verified.

  FIG. 14 is a diagram in which frequency components are extracted from the waveform of a 32 MHz differential clock signal of an IC. In FIG. 14, the horizontal axis represents frequency and the vertical axis represents power. For extraction, a circuit model of the IC's differential buffer is used, a rectangular wave with respect to the time axis is calculated by circuit simulation, and this is expanded on the frequency axis by Fourier transform to display the distribution of the frequency component (spectrum) of the signal. I am letting. As a characteristic of this spectrum, a sharp peak appears in the harmonic band of an odd multiple of 32 MHz, and a signal having these spectral components is transmitted through a differential signal line pair for a clock signal. In addition, the spectrum causes radiation noise.

  FIG. 15 is a diagram showing a distribution with respect to frequency components when a circuit model of a differential buffer of the same IC as described above is operated by simulation with a pseudo-random bit sequence of 64 Mbps. Similarly to FIG. 14, the horizontal axis represents frequency and the vertical axis represents power. That is, a signal having the spectral component shown in FIG. 15 is transmitted through the differential signal line pair for data signals. Specifically, in the data signal line, modulation (change to High or Low level as a rectangular wave) is performed such that a 1-bit signal is superimposed on 0.5 period of a 32 MHz rectangular wave signal that is a fundamental wave. Therefore, due to the irregularity (randomness) of bits serving as data, a spectrum distribution in which the sharp peak is suppressed by 10 dB or more compared to the spectrum of the clock signal of 32 MHz (FIG. 14). At this time, the used pseudorandom bit sequence of 64 Mbps used a pattern that returns to the original at the 511th generation bit as a simulation condition. However, since the randomness is actually extremely high, the spectrum distribution of the data signal is as shown in FIG. It is thought that the peak becomes lower than that.

  14 and FIG. 15, the differential signal line pair for the data signal has a radiated noise compared with the GSSG configuration of the differential signal line pair for the clock signal even in the GSSG configuration. It can be said that the occurrence is small. In addition, when a plurality of differential signal line pairs for data signals are arranged, for example, even if two differential signal line pairs for data signals are used, the level of radiation noise is increased by 3 dB, and if the number of differential signal line pairs is increased by four, the calculation is also performed. Is done. However, these increased 3 dB and 6 dB are situations where data signals of the same pattern continue to flow through the differential lines for the respective data signals, and are combinations of data signals that cannot actually occur. Therefore, it is considered that the actual increase in the radiation noise level is a value smaller than 3 dB and 6 dB.

  In addition, regarding the influence of electronic devices under the radiated radio frequency electromagnetic field, even if a part of the data signal is obstructed, if the clock signal is basically robust, the data can be recovered and reproduced by the clock signal. Can do. Therefore, the differential signal line pair for clock signals can have a GSSG configuration, and the differential signal line pair for data signals can have a GSSG configuration.

With this configuration, it is possible to suppress an increase in the ground line of the differential signal line pair for data signals. Thereby, a cheaper FFC and its connector can be selected. Moreover, it can contribute to the miniaturization design of the circuit board on which the connector is mounted. When there is a margin in the FFC design, it is more preferable to adopt the GSSGSG configuration for the differential signal line pair for data signals.
Note that, in the FFC 120 of this modification as well, it is possible to improve EMC characteristics and signal quality by connecting the resistor 150 and the termination resistor 250 as described in the second embodiment (FIG. 11).

(Modification 3)
Although the electronic device of the above embodiment has been described by taking a printer as an example, it may be any electronic device that has a plurality of circuit boards in a housing and transmits a differential signal between the boards. Therefore, for example, the FFC configuration of the above embodiment and the modified example is also applied to a wearable terminal such as a scanner, a projector, an HMD (Head Mounted Display), a mobile phone, a small information terminal, a game machine, an AV (Audio Visual) device, and a photographing device. Can be applied, and similar effects can be obtained.
As described above, according to the present modification, the effects of the respective embodiments, that is, a simple and inexpensive configuration, robustness against a radiated radio frequency electromagnetic field, and an effect of reducing unnecessary radiation noise are various. Electronic devices can be provided.

(Modification 4)
The FFC bending according to this modification will be described.
In the above-described embodiment (see FIG. 3), the FFC 20 that electrically connects the main board 10 and the sub board 50 has been described as being configured in a substantially straight line. However, the FFC 20 may have a bend or a curve. In this modification, the FFC 1000 having a bent portion will be described. The FFC 1000 has the same configuration as the FFC 20. In addition, about the component same as FIG. 3, the same number is attached | subjected and the overlapping description is abbreviate | omitted.

  FIG. 16 is a model diagram of the printer 1801 in which the FFC 1000 is mounted. In the printer 1801, the main board 10 and the sub board 50 are electrically connected by the FFC 1000. The printer 1801 has the same configuration as the printer 80 except that the FFC 1000 is used. Here, the XYZ directions defined in the printer 80 (FIG. 3) described above will be applied to the printer 1801 and will be described. That is, the main board 10 and the sub board 50 face each other in the Z direction, and the FFC 1000 is extended and mounted in the substantially Z direction therebetween.

  FIG. 17 is a model diagram showing a bent (folded) state of the FFC 1000, and an enlarged portion A near the center of the FFC 1000 in FIG. As shown in FIG. 17, the FFC 1000 has the same configuration as that in FIG. 2A (the same reference numerals are given, and overlapping descriptions are omitted), and the hand-shaped foldings 1010, 1020, 1030, and 1040 at four points are provided. (In order to make the structure of the wiring easier to understand, the portion of the insulating material 7 is omitted).

The bent state of the folds 1010, 1020, 1030, and 1040 will be described from the main board 10 toward the sub board 50. Here, in the X direction (the width direction of the printer 1801), the direction toward the outside of the printer 1801 is the right side, and the opposite direction is the left side.
First, a fold 1010 is provided in the approximate center of the FFC 1000. The fold 1010 has a bend of about 90 degrees to the left. By this folding 1010, the direction of the FFC 1000 is temporarily changed from the Z direction to the X direction (the direction toward the inside of the printer 1801).
Next, a fold 1020 is provided at a position advanced 60 mm from the fold 1010. The fold 1020 has a bend of about 90 degrees toward the sub-substrate 50 in the Z direction again. By this folding 1020, the FFC 1000 can change its direction from the X direction to the Z direction again.
Next, a fold 1030 is provided at a position advanced 87 mm from the fold 1020. The fold 1030 has a bend of about 90 degrees to the left. By this folding 1030, the extending direction of the FFC 1000 is changed from the Z direction to the X direction (the direction toward the inside of the printer 1801) again.
Next, a fold 1040 is provided at a position advanced 60 mm from the fold 1030. The fold 1040 has a bend of about 90 degrees toward the sub-substrate 50 in the Z direction again. By this folding 1040, the FFC 1000 is connected again by reaching the sub-board 50 by changing the extending direction from the X direction to the Z direction again. The FFC 1000 has a configuration in which a resistor 150 (resistance value 200Ω) and a termination resistor 250 (resistance value 200Ω) are connected as described in the second embodiment (FIG. 11), in addition to the folding 1010, 1020, 1030, and 1040. It is said.

  A signal waveform simulation for the FFC 1000 was performed using the circuit model configuration described above. As a signal to be handled, a differential signal having an amplitude of ± 0.35 V was transmitted at 500 Mbps from the IC 110 on the transmission side using FIG. 11 as a circuit model. The so-called eye pattern is shown in FIG. 18 as a result of overwriting the voltage waveform in the specific period at the differential signal input terminals 202 and 203 of the receiving side IC 210A at this time. The FFC 1000 has a GSSG SG configuration as described in the first embodiment. For comparison, as a conventional configuration, when the FFC1000 portion is an FFC having a conventional GSSG configuration and has the same four folds as the FFC1000, the difference when the resistance value at the receiving end is set to 100Ω. FIG. 19 shows an eye pattern of the differential voltage at the input end of the motion signal. Here, in FIGS. 18 and 19, the horizontal axis represents a specific period of 0 ns to 4 ns (unit: nanosecond), and the vertical axis represents a differential voltage (unit: V).

  In the verification with the eye pattern, it is possible to determine whether the signal quality is good or not by overlaying and displaying rectangular wave waveforms for various bit columns. That is, the overlapping degree of the rectangular waves is high, and the maximum (overshoot) and the minimum value (undershoot) of the rectangular waves are within the allowable input voltage at the receiving end, and the central area of the eye pattern widens (the eye Open state means that the signal quality to be transmitted is good. Conversely, the overlap of the rectangular waves is low, and the overshoot and undershoot of the rectangular waves are near or above the allowable input voltage at the receiving end. In other cases, the state where the central area of the eye pattern is narrow (the eye is closed) means that the quality of the transmitted signal is poor.

Comparing FIG. 18 and FIG. 19, the eye pattern (FIG. 18) of FCC1000 has an open eye of about ± 0.1V in voltage, and overshoot and undershoot are improved by 0.15V or more, and the input terminal A sufficient allowable range can be provided within the allowable input voltage of the side IC. In other words, regarding the FFC folding, it can be seen that the FFC configuration according to the present invention has less degradation in the quality of the transmitted signal waveform and can suppress the occurrence of overshoot and undershoot on the receiving side compared to the conventional configuration. .
As described above, according to the FFC 1000 according to the present modification, the following effects can be obtained in addition to the effects of the above embodiment.
A space in which the FFC is accommodated and installed is limited, and an electronic device that can maintain the quality of a signal waveform to be transmitted can be provided even when the FFC is bent or curved and mounted.

  DESCRIPTION OF SYMBOLS 1, 3, 5, 15, 25, 35 ... Ground line, 2, 4 ... Differential signal line, 7 ... Insulating material, 10 ... Main board | substrate, 11, 21, 31, 121 ... Power supply line, 13 ... Power supply circuit 20, 30, 120 ... FFC, 22, 32 ... signal line, 40 ... metal frame, 50, 60 ... sub-board, 80, 180 ... printer, 90 ... ground, 91 ... ESD application location, 100 ... space, 102 , 103 ... Differential signal output terminal, 105 ... Ground electrode, 110, 210, 210A ... IC, 112, 113, 212, 213 ... Capacitor, 123, 124, 125, 126 ... Differential signal line pair, 150 ... Resistance, 202, 203 ... differential signal input ends, 250 ... termination resistance, 301, 302, 303 ... screwing, 305, 605 ... connector, 801 ... YZ plane.

Claims (10)

A first circuit board;
A second circuit board;
A flexible cable in which a plurality of conductive lines are arranged in parallel to electrically connect the circuit on the first circuit board and the circuit on the second circuit board;
The flexible cable has a differential signal line pair for transmitting a differential signal by a first signal line and a second signal line,
A ground line for supplying a ground potential to the first signal line and the second signal line is disposed between the first signal line and the second signal line;
An electronic apparatus comprising a power line for sharing a power source between the first circuit board and the second circuit board.   The electronic apparatus according to claim 1, wherein at least one of the ground lines also serves as a live line of the power supply line. The first signal line is grounded via a first capacitor;
The electronic apparatus according to claim 1, wherein the second signal line is grounded through a second capacitor.   The flexible cable includes the conductive lines arranged in parallel in the order of the ground line, the first signal line, the ground line, the second signal line, and the ground line. The electronic device according to claim 3.   The first signal line and the second signal line are connected to each other via a first resistor on the first circuit board and a second resistor on the second circuit board, respectively. The electronic apparatus according to claim 1, wherein the electronic apparatus is electrically connected.   The width of each line of the flexible cable is 0.3 mm or more and 0.7 mm or less, and the width of the space between each line is 0.2 mm or more and 0.3 mm or less. The electronic device according to claim 5.   The electronic device according to claim 6, wherein the first resistor and the second resistor are each 200 ± 50Ω.   In the differential signal line pair, when the first circuit board side is the signal transmission side and the second circuit board side is the signal reception side, the differential signal output element of the first circuit board side 8. The electronic apparatus according to claim 1, wherein the differential output impedance value (R 1) and the second resistor (resistance value R 2) have a relation that R 2 is larger than R 1. . The flexible cable has a third signal line and a fourth signal line,
The first signal line and the second signal line form a differential signal line pair for transmitting a clock signal;
The third signal line and the fourth signal line are arranged next to each other in parallel to form a differential signal line pair for transmitting a data signal,
The electronic apparatus according to claim 1, wherein the ground line is disposed on both sides of the differential signal line pair that transmits the data signal.   The electronic device according to claim 1, wherein the electronic device is a printer.

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