JP2017059273A - Calculation processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a calculation processor capable of increasing processing speed by reducing cycle overhead.SOLUTION: A calculation processor 1 includes: a computing unit 15 that executes a calculation; a stream engine 2 that executes a series of stream processing; and an instruction issuing section 14 that issues instructions to the computing unit and the stream engine. The instruction issued by the instruction issuing section to the stream engine is a step instruction. Each pipeline stage of the stream engine executes a series of processing according to one step instruction.SELECTED DRAWING: Figure 3

Description

  The embodiments referred to in this specification relate to an arithmetic processing device.

  In recent years, higher-speed wireless communication schemes have attracted attention as the amount of communication of mobile terminals such as smartphones and tablet computers increases. As such a high-speed wireless communication system, for example, LTE (Long Term Evolution) has become widespread, and LTE advanced (LTE-Advanced) of a next-generation mobile communication system with higher performance has been standardized and put into practical use. Various proposals have been made.

  By the way, for example, when LTE Advanced is applied, enormous matrix calculation processing is performed as the wireless communication baseband processing. This is not limited to LTE Advanced, and the same applies to various wireless communication systems (standards) including WiMAX 2 (Worldwide Interoperability for Microwave Access 2) and currently used systems.

  In general, in wireless communication baseband processing, enormous matrix operations are performed in proportion to the improvement in communication speed. For example, in LTE Advanced described above, matrix operations occupy a large amount of the entire operation amount. Yes.

  In order to execute matrix calculation processing (one of stream processing) at high speed, a memory storing matrix data and an arithmetic unit are connected in series, matrix calculation is performed on the data read from the memory, and the calculation result A stream engine that writes to memory is suitable.

  Thus, for example, as an arithmetic processing device (arithmetic processing system) that performs LTE advanced wireless communication baseband processing, a combination of a base processor that is a general-purpose processor and a coprocessor having a stream engine has been proposed.

  By the way, various arithmetic processing systems combining a base processor and a coprocessor having a stream engine have been proposed.

JP 2011-197774 A Japanese Patent Application Laid-Open No. 08-069377

  As described above, a combination of a base processor and a coprocessor having a stream engine has been proposed as an arithmetic processing system that performs wireless communication baseband processing.

  In such an arithmetic processing system, for example, when executing a stream instruction that is a coprocessor instruction, the base processor performs coprocessor state monitoring, data transfer, execution control, and the like by handshaking, resulting in overhead. This overhead is called, for example, communication cycle overhead.

  Further, for example, when an interrupt occurs while the stream engine of the coprocessor is executing the stream processing, the interrupt processing is performed until the execution of the stream processing is completed.

  That is, if the coprocessor is busy when an interrupt occurs, the base proprocessor waits until the coprocessor becomes idle, further increasing the communication cycle overhead.

  According to one embodiment, an arithmetic processing device includes an arithmetic unit that executes an operation, a stream engine that executes stream processing, and an instruction issuing unit that issues an instruction to the arithmetic unit and the stream engine. An arithmetic processing device is provided. The instruction issued by the instruction issuing unit to the stream engine is a step instruction, and each pipeline stage of the stream engine executes one process according to one step instruction.

  The disclosed arithmetic processing device has an effect of reducing the cycle overhead and speeding up the processing.

FIG. 1 is a block diagram illustrating an example of an arithmetic processing device. FIG. 2 is a block diagram illustrating an example of an arithmetic processing device according to the present example. FIG. 3 is a diagram for explaining the operation in the arithmetic processing apparatus of this example. FIG. 4 is a diagram for explaining the stop operation of the stream engine in the arithmetic processing apparatus according to this embodiment. FIG. 5 is a diagram for explaining an example of the effect of the stop operation of the stream engine described with reference to FIG. FIG. 6 is a diagram for explaining an example of the operation of the readout circuit in the arithmetic processing unit of this embodiment. FIG. 7 is a diagram for explaining another example of the operation of the readout circuit in the arithmetic processing unit of this embodiment. FIG. 8 is a diagram for explaining an example of the operation of the execution circuit in the arithmetic processing apparatus according to the present embodiment. FIG. 9 is a diagram for explaining another example of the operation of the execution circuit in the arithmetic processing apparatus according to the present embodiment. FIG. 10 is a diagram for explaining an example of the operation of the write circuit in the arithmetic processing unit of the present embodiment. FIG. 11 is a diagram for explaining another example of the operation of the writing circuit in the arithmetic processing unit of the present embodiment. FIG. 12 is a diagram for explaining an example of parameter information in the arithmetic processing apparatus according to the present embodiment. FIG. 13 is a diagram (part 1) for explaining a step command in the arithmetic processing unit according to the present embodiment. FIG. 14 is a diagram (part 2) for explaining the step command in the arithmetic processing unit according to the present embodiment. FIG. 15 is a diagram for explaining a modification of the step command in the arithmetic processing unit according to the present embodiment. FIG. 16 is a diagram (part 1) for explaining the micro instruction in the arithmetic processing unit of the present embodiment. FIG. 17 is a diagram (part 2) for explaining the micro instruction in the arithmetic processing unit of the present embodiment. FIG. 18 is a diagram for explaining access control by microinstructions in the arithmetic processing unit of this embodiment. FIG. 19 is a diagram illustrating a state in which the micro instruction is embedded in the VLIW instruction in the arithmetic processing unit according to the present embodiment. FIG. 20 is a diagram for explaining the prologue processing of the VLIW instruction shown in FIG. FIG. 21 is a diagram for explaining the epilogue processing of the VLIW instruction shown in FIG.

  First, before describing in detail an embodiment of the arithmetic processing device, an example of the arithmetic processing device and its problems will be described with reference to FIG.

  FIG. 1 is a block diagram showing an example of an arithmetic processing device, and shows an arithmetic processing device (arithmetic processing system) in which a base processor, which is a general-purpose processor, and a coprocessor having a stream engine are combined.

  In FIG. 1, reference symbol IF indicates an instruction read stage, ID indicates an instruction decode stage, and RR / II indicates a register read and instruction issue stage.

  Reference numeral EX denotes an execution stage, MA denotes a memory access stage, and RW denotes a register write stage. The arithmetic processing system illustrated in FIG. 1 includes, for example, a base processor 100 that is a general-purpose processor and a coprocessor 300 that includes a stream engine 200.

  In the base processor 100, in the IF stage, the instruction reading unit 101 fetches (reads) an instruction from the instruction memory 108, and in the ID stage, the instruction interpretation unit 102 reads the instruction read by the instruction reading unit 101. Receive and decode (interpret).

  In the RR / II stage, the register reading unit 103 reads (reads) the register 110 and the instruction issuing unit 104 issues the instruction interpreted by the instruction interpreting unit 102 to the computing unit 105.

  In the EX stage, the arithmetic unit 105 executes an operation according to the instruction issued from the instruction issuing unit 104. In the MA stage, the memory access unit 106 loads (reads) or stores (stores) the memory (data memory) 109. Write) access.

  In the RW stage, the register writing unit 107 writes the calculation result by the calculator 105 or the data loaded from the data memory 109 into the register 110.

  Here, as indicated by the reference symbol P100 in FIG. 1, the base processor 100 is configured to execute pipeline-execution processing between a register and a memory or between a register and an arithmetic unit as one instruction.

  In the coprocessor 300, in the IF stage, the instruction reading unit 301 reads an instruction from the instruction memory 108, and in the ID stage, the instruction interpreting unit 302 receives and interprets the instruction read by the instruction reading unit 301.

  In the RR / II stage, the register reading unit 303 reads the register 310 and the instruction issuing unit 304 issues the instruction interpreted by the instruction interpreting unit 302 to the stream engine 200. Here, the stream engine 200 includes a computing unit 205 and a memory access unit 206 that performs load or store access to the data memory 400.

  As indicated by reference numeral P200 in FIG. 1, the instruction from the instruction issuing unit 304 to the stream engine 200 is a stream instruction. When one stream instruction is issued, one stream processing between the memory and the arithmetic unit is completed. Pipeline execution is up to.

  That is, in the EX and MA stages, the arithmetic unit 205 and the memory access unit 206 in the stream engine 200 perform processing until the stream processing is completed according to the stream instruction issued from the instruction issuing unit 304. In the RW stage, the register writing unit 307 writes the data (calculation result) stream-processed by the stream engine 200 to the register 310.

  Here, in FIG. 1, reference numeral P <b> 150 indicates processing of the coprocessor 300 by the base processor 100, for example, processing of handshaking with the coprocessor 300 by issuing a stream instruction of the coprocessor 300. That is, for example, the base processor 100 monitors the state of the coprocessor 300, performs execution control of the coprocessor 300, and controls data transfer to the coprocessor 300.

  The arithmetic processing system combining the base processor 100 described with reference to FIG. 1 and the coprocessor 300 having the stream engine 200 has a problem of cycle overhead when the stream processing is executed by the stream engine 200.

  That is, when executing a stream instruction that is a coprocessor instruction, the base processor 100 monitors the state of the coprocessor 300 by handshaking, performs data transfer with the coprocessor 300, and Control execution.

  Therefore, overhead (communication cycle overhead) occurs between the base processor 100 and the coprocessor 300. Further, for example, when an interrupt occurs while the stream engine 200 of the coprocessor 300 is executing the stream process, the process waits until the execution of the stream process is completed, and the communication cycle overhead further increases.

  Hereinafter, the arithmetic processing apparatus of the present embodiment will be described in detail with reference to the accompanying drawings. FIG. 2 is a block diagram illustrating an example of an arithmetic processing device according to the present example. As is clear from the comparison between FIG. 2 and FIG. 1 described above, the arithmetic processing unit (processor) 1 shown in FIG. 2 includes a configuration corresponding to the base processor 100 in FIG. Yes.

  That is, as shown in FIG. 2, the processor 1 includes a register 10, an instruction reading unit 11, an instruction interpreting unit 12, a register reading unit 13, an instruction issuing unit 14, an arithmetic unit 15, a memory access unit 16, and a register writing unit. 17, an instruction memory 18 and a data memory 19 are included. Here, the instruction issuing unit 14 not only issues an instruction to the computing unit 15 but also issues an instruction (for example, a step instruction) to the stream engine 2.

  The stream engine 2 includes a POP unit 21 that reads data from the data memory 4 and writes the data to the registers 221 and 222, and an EXEC unit 23 that performs stream processing on the data written to the registers 221 and 222 and writes the data to the register 24. . Further, the stream engine 2 includes a PUSH unit 25 that writes the data written in the register 24 to the data memory 4.

  In FIG. 2, reference numerals IF, ID, RR / II, EX, MA, and RW indicate stages similar to those described with reference to FIG.

  That is, in the IF stage, the instruction reading unit 11 fetches (reads) an instruction from the instruction memory 18, and in the ID stage, the instruction interpretation unit 102 receives and decodes (interprets) the instruction fetched by the instruction reading unit 101. )

  In the RR / II stage, the register reading unit 13 reads (reads) the register 10 and the instruction issuing unit 14 issues the instruction interpreted by the instruction interpreting unit 12 to the arithmetic unit 15 and the stream engine 2.

  In the EX stage, the arithmetic unit 15 executes an operation according to the instruction issued from the instruction issue unit 14, and the stream engine 2 executes a stream process according to the instruction issued from the instruction issue unit 14. Here, the command from the command issuing unit 14 to the stream engine 2 is a step command as described above.

  In the MA stage, the memory access unit 16 performs load or store access to the memory (data memory) 19. Further, in the MA stage, the stream engine 2 (POP unit 21 or PUSH unit 25) performs load (read) or store (write) access to the memory (data memory) 4.

  In the RW stage, the register writing unit 17 writes the calculation result by the calculator 15 or the data loaded from the data memory 19 to the register 10, and the register writing unit 17 stores the data stream-processed by the stream engine 2 in the register 10. Write to.

  FIG. 3 is a diagram for explaining the operation in the arithmetic processing apparatus of this example. As is clear from the comparison between the reference symbol P1 in FIG. 3 and the reference symbol P100 in FIG. 1 described above, at the corresponding portion of the base processor 100 in FIG. 1, processing between the register and the memory or between the register and the arithmetic unit is performed by one instruction. As a pipeline execution.

  Further, as indicated by reference numerals P21 to P23 in FIG. 3, the stream engine 2 built in the processor 1 executes processing for each step in accordance with the step command issued from the command issuing unit 14.

  Here, the process P 21 is a process in which the POP unit 21 of the stream engine 2 reads out data from the data memory 4 and writes it in the registers 221 and 222. Process P22 is a process in which the EXEC unit 23 performs a stream process on the data written in the registers 221 and 222 and writes the data in the register 24.

  Further, the process P23 is a process in which the push unit 25 writes the data written in the register 24 to the data memory 4. These processes P21 to P23 are pipeline-executed according to the step instruction issued from the instruction issuing unit 14.

  In this specification, the stream engine 2 shows an example in which the three processes P21 to P23 are processed by three step commands (one rotation by three step commands). However, this is merely an example, and it is needless to say that the stream process may be executed by repeating the process of one rotation many times with four or more processes.

  FIG. 4 is a diagram for explaining the stop operation of the stream engine in the arithmetic processing apparatus according to this embodiment. For example, when an interrupt occurs while the stream engine 2 built in the processor 1 is executing stream processing, the instruction issuing unit 14 stops issuing step instructions to the stream engine 2.

  Thus, when the command issuing unit 14 stops issuing step commands to the stream engine 2, all the processes P21 to P23 in the stream engine 2 are stopped. That is, the POP unit 21 stops the process P21 that reads data from the data memory 4 and writes the data in the registers 221 and 222.

  In addition, the EXEC unit 23 performs a stream process on the data written in the registers 221 and 222 and stops the process P22 to write in the register 24. Then, the PUSH unit 25 stops the process P23 for writing the data written in the register 24 into the data memory 19.

  As described above, since the arithmetic processing unit according to the present embodiment controls the operation of the stream engine 2 with fine granularity by the step command, if an interrupt occurs during the stream processing, the stream processing is immediately stopped. Interrupt processing can be performed.

  That is, according to the arithmetic processing unit of this embodiment, for example, the stream engine 2 can be stopped immediately by stopping the issuance of a step command when an interrupt occurs. In other words, according to the arithmetic processing unit of this embodiment, after the instruction issuance is stopped, each pipeline stage (processes P21 to P23) of the stream engine 2 can be stopped autonomously, thereby reducing cycle overhead. Speeding up the process.

  FIG. 5 is a diagram for explaining an example of the effect of the stop operation of the stream engine described with reference to FIG. 4, and FIG. 5 (a) shows the operation of the arithmetic processing system shown in FIG. FIG. 5B shows the operation of the arithmetic processing unit described with reference to FIG.

  Here, it is assumed that the number of cycles for one stream processing (number of clock cycles) is 200 cycles, the latency of the operation data path is 10 cycles, and the bit width of parameter information used for one stream processing is 320 bits.

  Further, it is assumed that data transfer between the external and the memory overlaps with the stream processing, and the data transfer cycle is concealed. 5A, the data path between the base processor 100 and the coprocessor 300 is 32 bits, and parameter information is transferred from the base processor 100 to the coprocessor 300 in 10 cycles.

  Accordingly, in FIG. 5A, the communication cycle overhead is, for example, 10 [cycle] (data transfer) +10 [cycle] (calculation data path) = 20 [cycle].

  In FIG. 5B, since the data paths are tightly coupled, the parameter information is transferred in one cycle. In the present specification, tight coupling does not mean that a plurality of processors coupled at a bus level access a common memory, but the common instruction issuing unit 14 is connected to the arithmetic unit 15 and the stream engine 2. This means issuing commands and controlling them.

  Accordingly, in FIG. 5B, the communication cycle overhead is, for example, 1 [cycle] (data transfer) +10 [cycle] (calculation data path) = 11 [cycle].

  First, as shown in FIG. 5A, in the arithmetic processing system shown in FIG. 1, for example, when an interrupt occurs at the 50th cycle in the third stream process (A2), the third stream process is performed. After all the processing is completed, another stream process (B0) is executed.

  Therefore, in the arithmetic processing system, it takes 200 + 20 + 200 + 20 + 50 + 150 + 20 + 200 = 860 [cycles] to complete another stream processing (B0).

  On the other hand, in the arithmetic processing unit (processor) 1 of the present embodiment described with reference to FIG. 4, for example, when an interrupt occurs in the 50th cycle in the third stream processing (A2), the third stream is immediately generated. The process is stopped and another stream process (B0) is executed.

  Therefore, in the processor 1 of the present embodiment, only 200 + 11 + 200 + 11 + 50 + 11 + 200 = 683 [cycles] are required to complete another stream process (B0).

  That is, according to the processor 1 of the present embodiment, it can be understood that the same processing can be performed at a speed of 177 [cycles] from 860 [cycles] to 683 [cycles].

  Note that FIG. 5 is merely an example of stream processing. For example, the higher the number of processing cycles by one stream instruction, or the higher the frequency of interrupt generation during stream processing, the higher the speed. Needless to say, the effect of conversion is increased.

  FIG. 6 is a diagram for explaining an example of the operation of the readout circuit in the arithmetic processing apparatus of this embodiment, and FIG. 7 explains another example of the operation of the readout circuit in the arithmetic processing apparatus of this embodiment. FIG.

  As shown in FIGS. 6 and 7, read circuit 210 includes POP unit 21 and registers 221 and 222, and data memory 4 includes memory units 41 and 42. The memory units 41 and 42 indicate, for example, banked memory areas at different addresses (start addresses) in the data memory 4 and need not have two memories.

  As shown in FIG. 6, in the reading circuit 210, the POP unit 21 reads the first data from the memory unit (first bank) 41 of the data memory 4 by specifying the start address and the stream length, and stores the first data in the register 221. To do.

  Further, in the reading circuit 210, the POP unit 21 reads the second data from the memory unit (second bank) 42 of the data memory 4 by specifying the head address and the stream length, and stores the second data in the register 222. The processing of the reading circuit 210 corresponds to, for example, the processing P21 in the arithmetic processing device of FIG.

  That is, the POP unit 21 reads stream data from the data memory 4 and inputs (stores) the data into registers (pipeline registers) 221 and 222 between the read stage (POP unit 21) and the execution stage (EXEC unit 23) of the stream processing. ) To execute pipeline processing.

  In this way, for example, by reading stream data from the data memory 4 banked in the first bank 41 and the second bank 42 by specifying the head address and stream length, the number of memory ports and cycle overhead are eliminated. can do.

  As shown in FIG. 7, for example, data read from the memory units (first and second banks) 41 and 42 by the DMA (Direct Memory Access) 5 is converted into a FIFO (First In First Out) buffer 61. , 62 can be supplied to the reading circuit 210. That is, it is possible to leave the data transfer from the data memory 4 to the DMA 5 and take out the read data from the FIFO buffers 61 and 62.

  FIG. 8 is a diagram for explaining an example of the operation of the execution circuit in the arithmetic processing apparatus according to the present embodiment. As shown in FIG. 8, the execution circuit 230 includes an EXEC unit 23 and a register 24.

  In the execution circuit 230, the EXEC unit 23 performs stream processing on the data written in the registers 221 and 222, and writes the calculation result in the register 24. The process of the execution circuit 230 corresponds to, for example, the process P22 in the arithmetic processing apparatus of FIG.

  That is, the EXEC unit 23 performs stream processing on the data input to the registers 221 and 222, and inputs the calculation result to the register (pipeline register) 24 between the EXEC unit 23 and the PUSH unit 25. Perform pipeline processing.

  FIG. 9 is a diagram for explaining another example of the operation of the execution circuit in the arithmetic processing unit according to the present embodiment, in which the execution circuit 230 includes multi-stage EXEC units 231 to 233 and registers 241 to 243. .

  At this time, the registers of the read circuit 210 are four registers 221a, 221b and 222a, 222b corresponding to the two EXEC sections 231 and 232 in the first stage.

  The registers of the execution circuit 230 are also three registers 241 to 243 in order to store the calculation results by the three EXEC units 231 to 233. Note that the execution circuit shown in FIG. 9 is merely an example, and it is needless to say that various configurations can be applied.

  As described above, the execution circuit 230 (arithmetic unit data path) may have a multi-stage configuration, and the operation result is input to the register (pipeline register) 243 between the EXEC unit 233 and the PUSH unit 25 every cycle to execute pipeline processing. can do.

  FIG. 10 is a diagram for explaining an example of the operation of the writing circuit in the arithmetic processing apparatus of the present embodiment, and FIG. 11 is another example of the operation of the writing circuit in the arithmetic processing apparatus of the present embodiment. It is a figure for demonstrating.

  As shown in FIG. 10, the writing circuit 250 includes the PUSH unit 25 and writes the operation result stored in the register 24 into the memory unit 43 of the data memory 4. That is, output data is extracted from the pipeline register 24 between the EXEC unit 23 and the PUSH unit 25, and is written in, for example, a memory area indicated by the head address and stream length.

  The processing of the writing circuit 250 corresponds to, for example, the processing P23 in the arithmetic processing device shown in FIG. Here, the memory unit 43 can be a memory area different from the memory units 41 and 42 in the data memory 4, for example.

  The write circuit 250 shown in FIG. 10 directly writes the operation result stored in the register 24 into the data memory unit 43. On the other hand, the write circuit 250 shown in FIG. 11 writes the calculation result stored in the register 24 into the FIFO buffer 7, and the DMA 8 transfers the data written in the FIFO buffer 7 to the memory unit 43.

  That is, the write circuit 250 shown in FIG. 11 sequentially writes the operation results stored in the register 24 into the FIFO buffer 7 and leaves the data transfer from the FIFO buffer 7 to the memory unit 43 (data memory 4) to the DMA 8. It has become.

  FIG. 12 is a diagram for explaining an example of parameter information in the arithmetic processing apparatus according to the present embodiment. The parameter information used for the stream processing is, for example, a single long-bit length instruction (ai), stream length (li), operation opcode (o), and operation mode (m) for each stream (i). Set command: set).

  This set instruction (parameter information) is read from the instruction memory 18 and substituted (set) into the parameter register 140 in a lump as indicated by reference symbol P10. Each pipeline stage (the POP unit 21, the EXEC unit 23, and the PUSH unit 25) executes the pipeline by referring to the parameter information from the parameter register 140, as indicated by the reference symbol P11.

  13 and 14 are diagrams for explaining step commands in the arithmetic processing unit of the present embodiment. As shown in FIGS. 13 and 14, the arithmetic processing unit (stream engine 2) of this embodiment can be controlled by a set instruction.

  That is, as indicated by the reference symbol P20, a step instruction is read from the instruction memory 18, and the processing P21 to P23 of each pipeline stage of the stream engine 2 can be controlled by executing the step instruction. As the step command, for example, one prepared in advance by a programmer is used.

  Here, step instructions step 1 to step N are sequentially read from the instruction memory 18 and issued from the instruction issuing unit 14 to the stream engine 2 to execute the respective pipeline processes P21 to P23.

  As shown in FIG. 13, the step command is issued from the command issuing unit 14 to the stream engine 2, and one step command causes the POP unit 21, EXEC unit 23, and PUSH unit 25 to perform one process (P 21, P 22, P23) is executed.

  That is, as shown in FIG. 14A, the process P21 is a process in which the POP unit 21 reads data from the data memory 4 and writes it in the registers 221 and 222. 14B, the process P22 is a process in which the EXEC unit 23 performs a stream process on the data written in the registers 221 and 222 and writes the data in the register 24.

  Further, as shown in FIG. 14C, the process P <b> 23 is a process in which the push unit 25 writes the data written in the register 24 into the data memory 19. These processes P21 to P23 are pipeline-executed according to the step instruction issued from the instruction issuing unit 14.

  FIG. 15 is a diagram for explaining a modification of the step command in the arithmetic processing unit according to the present embodiment. In FIG. 13 described above, the N step instructions step 1 to step N are read from the instruction memory 18 as they are and issued from the instruction issuing unit 14 to the stream engine 2.

  On the other hand, in the modification shown in FIG. 15, the set instruction is combined with an instruction dedicated to loop processing (zero overhead loop instruction) for efficiently executing continuous repetition processing (loop processing). .

  That is, N step instructions step 1 to step N can be set to zero overhead loop instructions (loop N step), so that the instruction sequence is not increased. Also in the zero overhead loop instruction, for example, when an interrupt occurs, the stream immediately stops processing at the step being executed.

  16 and 17 are diagrams for explaining microinstructions in the arithmetic processing unit of the present embodiment. As shown in FIG. 16, the instruction issued from the instruction issuing unit 14 to the stream engine 2 is a microinstruction.

  That is, as indicated by reference numeral P30 in FIG. 16, the microinstruction is read from the instruction memory 18, and the processes P21 to P23 of each pipeline stage of the stream engine 2 are controlled by executing the microinstruction. Yes.

  For example, a pop instruction is assigned to the process P21 shown in FIG. 17A, an exec instruction is assigned to the process P22 shown in FIG. 17B, and the process P23 shown in FIG. A push instruction is assigned and executed by each microinstruction. Thereby, the processes P21 to P23 of each pipeline stage can be individually controlled by the micro instruction.

  FIG. 18 is a diagram for explaining access control by microinstructions in the arithmetic processing unit of this embodiment.

  Here, FIG. 18A shows a case where all the pop, exec and push instructions are issued, FIG. 18B shows a case where the pop instruction is stopped, and FIG. 18C shows a push instruction. Indicates the case where the instruction is stopped. The arithmetic processing unit is provided with DMAs 5, 8 and FIFO buffers 61, 62, 7 as shown in FIGS.

  First, as shown in FIG. 18A, when all of the pop instruction, the exec instruction, and the push instruction are issued, the processes P21 to P23 of each pipeline stage are executed every cycle.

  Next, as shown in FIG. 18B, when the pop instruction is stopped, that is, when only the exec instruction and the push instruction are executed, the POP unit 21 stops reading data from the FIFO buffers 61 and 62.

  As a result, the FIFO buffers 61 and 62 become full when data is transferred by the DMA (input DMA) 5, and the DMA 5 detects the full state of the FIFO buffers 61 and 62 and automatically stops. In other words, the pipeline processing of the stream engine 2 can be stopped by stopping the pop instruction that is a microinstruction.

  Further, as shown in FIG. 18C, when the push instruction is stopped, that is, when only the pop instruction and the exec instruction are executed, the PUSH unit 25 reads data from the register 24 and stores it in the FIFO buffer 7. Stop.

  As a result, the FIFO buffer 7 becomes empty, and the DMA (output DMA) 8 detects the empty state of the FIFO buffer 7 and automatically stops. That is, the pipeline processing of the stream engine 2 can be stopped by stopping the push instruction that is a micro instruction.

  In this way, by using the micro instructions such as the pop instruction, the exec instruction, and the push instruction, for example, even when an interrupt occurs, the DMAs 5 and 8 can autonomously control the memory access. That is, the control of data transfer between the memory and the arithmetic unit can be simplified, and the amount of hardware for memory access control can be reduced.

  FIG. 19 is a diagram illustrating a state in which a micro instruction is embedded (packed) in a VLIW instruction in the arithmetic processing unit according to the present embodiment. As described with reference to FIGS. 16 to 18, when a microinstruction is used, for example, each process can be executed simultaneously by embedding it in a VLIW (Very Long Instruction Word) instruction. It is possible to reduce the number of execution cycles.

  That is, by embedding a plurality of microinstructions in the VLIW instruction, the number of loop processing instructions can be reduced, and the number of loop execution cycles can also be reduced. It is also possible to effectively utilize the instruction set architecture of the base processor (assuming a VLIW processor: arithmetic processing unit 1).

  FIG. 19 shows how M microinstructions are packed into N VLIW instructions. Here, prologue processing by VLIW 1 instruction to VLIW 3 instructions and VLIW N-2 instructions to VLIW N instructions are shown. The epilogue processing according to the above will be described with reference to FIGS. 20 and 21. FIG.

  20 is a diagram for explaining the prologue processing of the VLIW instruction shown in FIG. 19, FIG. 20 (a) shows the processing of the VLIW 1 instruction, FIG. 20 (b) shows the processing of the VLIW 2 instruction, FIG. 20C shows the processing of the VLIW 3 instruction.

  Here, as shown in FIG. 19, the prologue process is a process of starting the stopped stream engine 2, and VLIW 1 [pop], VLIW 2 [pop, exec] and VLIW 3 [pop, exec, push] This is achieved by executing the following three instructions.

  First, as shown in FIG. 20A, only the pop instruction by the VLIW 1 instruction is executed. That is, in response to the pop instruction, the POP unit 21 executes processing P21 for reading data from the data memory 4 and writing the data in the registers 221 and 222. As a result, the registers 221 and 222 are filled with data to be processed by the EXEC unit 23.

  Next, as shown in FIG. 20B, a pop instruction and an exec instruction by the VLIW 2 instruction are executed. That is, the above-described process P21 is executed by the pop instruction, and the EXEC part 23 executes the stream process on the data written in the registers 221 and 222 and executes the process P22 written in the register 24 by the exec instruction.

  As a result, the data to be executed by the EXEC unit 23 is input to the registers 221 and 222, and the operation result data to be written to the data memory 4 by the PUSH unit 25 is input to the register 24. .

  Then, as shown in FIG. 20 (c), the pop instruction, the exec instruction, and the PUSH instruction by the VLIW 3 instruction are executed. That is, the process P21 is executed by the pop instruction, the process P22 is executed by the exec instruction, and the process P23 in which the PUSH unit 25 writes the operation result data written in the register 24 to the data memory 4 by the PUSH instruction is executed. To do.

  From this epilogue processing to the epilogue processing described with reference to FIG. 21, the pipeline processing by the processing P21 to P23 is continuously executed by the same instruction as the VLIW 3 instruction (VLIW 4 instruction, VLIW 5 instruction,...). Is done.

  FIG. 21 is a diagram for explaining the epilogue processing of the VLIW instruction shown in FIG. 19, FIG. 21 (a) shows the processing of the VLIW N-2 instruction, and FIG. 21 (b) shows the processing of the VLIW N-1 instruction. The processing is shown, and FIG. 21 (c) shows the processing of the VLIW N instruction.

  Here, as shown in FIG. 19, the epilogue process is a process of stopping the operating stream engine 2 in reverse to the prologue process described with reference to FIG. 20. This epilogue processing is achieved by executing three instructions, VLIW N-2 [pop, exec, push], VLIW N-1 [exec, push] and VLIW N [push].

  First, as shown in FIG. 21 (a), a pop instruction, an exec instruction, and a push instruction by the VLIW N-2 instruction are performed. This VLIW N-2 instruction is the same as the VLIW 3 instruction described with reference to FIG. 20 (c), that is, the pipeline process continuously executed by the processes P21 to P23.

  Next, as shown in FIG. 21B, the exec instruction and the push instruction by the VLIW N-1 instruction are executed. That is, by removing the pop instruction, the POP unit 21 stops the process P21 of reading data from the data memory 4 and writing it to the registers 221 and 222. As a result, the registers 221 and 222 become empty.

  Then, as shown in FIG. 21 (c), only the PUSH instruction by the VLIW N instruction is executed. That is, by removing the pop instruction and the exec instruction, not only the registers 221 and 222 but also the register 24 becomes empty.

  It should be noted that controlling the stream engine 2 with three microinstructions such as a pop instruction, an exec instruction, and a push instruction is merely an example, and various changes such as adding additional microinstructions or applying different microinstructions are possible. It goes without saying that it is possible.

  In the above-described embodiment, an arithmetic processing apparatus that performs matrix arithmetic processing in LTE Advanced or the like has been described as an example. However, the present embodiment is not limited to the arithmetic processing apparatus applied to such a wireless communication device, and various The present invention can be widely applied to various arithmetic processing devices.

  Although the embodiment has been described above, all examples and conditions described herein are described for the purpose of helping understanding of the concept of the invention applied to the invention and the technology. It is not intended to limit the scope of the invention. Nor does such a description of the specification indicate an advantage or disadvantage of the invention. Although embodiments of the invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made without departing from the spirit and scope of the invention.

Regarding the embodiment including the above examples, the following supplementary notes are further disclosed.
(Appendix 1)
An arithmetic unit that executes an operation, and a stream engine that executes stream processing, wherein a data path of the arithmetic unit and a data path of the stream engine are tightly coupled;
An arithmetic processing apparatus characterized by that.

(Appendix 2)
further,
An instruction issuing unit for issuing instructions;
The instruction issuing unit issues an instruction for the arithmetic unit and also issues an instruction for the stream engine.
The arithmetic processing apparatus according to Supplementary Note 1, wherein:

(Appendix 3)
The stream engine
A readout circuit for reading data from the memory;
An execution circuit for performing stream processing on the read data;
A write circuit for writing the stream-processed operation result into the memory,
The arithmetic processing device according to attachment 2, wherein

(Appendix 4)
The readout circuit includes a POP unit and a first register,
The POP unit reads data from a first memory unit indicated by a head address and a stream length in the memory and stores the data in the first register.
The arithmetic processing apparatus according to attachment 3, wherein:

(Appendix 5)
The execution circuit includes an EXEC unit and a second register,
The EXEC unit performs a stream process on the data stored in the first register, and stores the stream-processed operation result in the second register.
The arithmetic processing device according to appendix 4, wherein

(Appendix 6)
The execution circuit includes a plurality of hierarchical EXEC sections and a plurality of third registers provided between the EXEC sections of each hierarchy.
The arithmetic processing apparatus according to appendix 5, characterized in that:

(Appendix 7)
The writing circuit includes a PUSH unit;
The PUSH unit writes the operation result stored in the second register to the second memory unit indicated by a head address and a stream length in the memory.
The arithmetic processing apparatus according to appendix 5 or appendix 6, characterized in that.

(Appendix 8)
The command issued by the command issuing unit to the stream engine is a step command,
Each pipeline stage of the stream engine executes one process according to one step instruction,
The arithmetic processing apparatus according to any one of appendix 2 to appendix 7, characterized in that:

(Appendix 9)
The parameter information used for the stream processing is expressed by a single and long bit length set instruction.
The arithmetic processing apparatus according to appendix 8, wherein

(Appendix 10)
The parameter information used for the stream processing includes the start address of each stream, the stream length, and the operation mode.
The arithmetic processing apparatus according to appendix 9, wherein

(Appendix 11)
further,
Including a parameter register that collectively sets parameter information used for the stream processing;
Each pipeline stage of the stream engine executes pipeline referring to parameter information from the parameter register.
The arithmetic processing apparatus according to appendix 8, wherein

(Appendix 12)
The instruction issued to the stream engine by the instruction issuing unit is a short bit-length microinstruction that controls the operation of each pipeline stage of the stream engine by disassembling a step instruction.
Each pipeline stage performs processing independently according to the corresponding microinstruction,
The arithmetic processing apparatus according to any one of appendix 2 to appendix 7, characterized in that:

(Appendix 13)
further,
A first FIFO buffer provided between the memory and the readout circuit;
The memory is DMA-controlled, and the first microinstruction that controls the processing of the read circuit that reads data from the memory is stopped, thereby filling the first FIFO buffer and stopping the pipeline processing of the stream engine.
The arithmetic processing apparatus according to appendix 12, wherein

(Appendix 14)
further,
A second FIFO buffer provided between the write circuit and the memory;
The memory is DMA-controlled, and by stopping the second microinstruction that controls the processing of the writing circuit that writes data to the memory, the second FIFO buffer is emptied, and the pipeline processing of the stream engine is stopped. ,
The arithmetic processing apparatus according to appendix 12, wherein

(Appendix 15)
When the arithmetic unit is controlled by a VLIW instruction,
Embed a micro instruction in the VLIW instruction that controls the operation of each pipeline stage of the stream engine.
The arithmetic processing device according to any one of appendix 12 to appendix 14, wherein

1 processor 2,200 stream engine 4,400 data memory 5,8 DMA
7, 61, 62 FIFO buffer 10, 110, 310 Register 11, 101, 301 Instruction reading unit 12, 102, 302 Instruction interpreting unit 13, 103, 303 Register reading unit 14, 104, 304 Instruction issuing unit 15, 105 16, 106 Memory access unit 17, 107 Register writing unit 18, 108 Instruction memory 19, 109 Data memory 21 POP unit 23 EXEC unit 24, 221, 222, 221a, 221b, 222a, 222b, 241 to 243 Register 25 PUSH unit 41 to 43 Memory unit 100 Base processor 140 Parameter register 210 Read circuit 230 Execution circuit 250 Write circuit 300 Coprocessor

Claims (4)

An arithmetic processing unit comprising:
An arithmetic unit for performing the operation;
A stream engine that performs stream processing;
An instruction issuing unit for issuing an instruction to the arithmetic unit and the stream engine,
The command issued by the command issuing unit to the stream engine is a step command,
Each pipeline stage of the stream engine executes one process according to one step instruction,
An arithmetic processing apparatus characterized by that. The parameter information used for the stream processing is expressed by a single and long bit length set instruction.
The arithmetic processing apparatus according to claim 1. The parameter information used for the stream processing includes the start address of each stream, the stream length, and the operation mode.
The arithmetic processing apparatus according to claim 2. further,
Including a parameter register that collectively sets parameter information used for the stream processing;
Each pipeline stage of the stream engine executes pipeline referring to parameter information from the parameter register.
The arithmetic processing apparatus according to claim 1.

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