JP2017055555A - Inverter device and control system for three-phase motor having the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inverter device and a control system that can reduce the number of circulation current suppressing cores to be used while maintaining the suppression effect of circulation current, thereby contributing to miniaturization of the inverter device.SOLUTION: An inverter device includes a main circuit element constituting an inverter, a driving substrate for driving the main circuit element, a gate wiring for applying a gate voltage of the driving substrate to a gate portion of the main circuit element, and a circulation current suppressing core for suppressing circulation current. An upper arm gate wiring for applying the gate voltage of the driving substrate to the gate portion of the main circuit element constituting an in-phase upper arm in the inverter, and a lower arm gate wiring for applying the gate voltage of the driving substrate to the gate portion of the main circuit element constituting an in-phase lower arm in the inverter are passed through one circulation current suppressing core.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an inverter device and a control system for a three-phase motor including the inverter device.

  2. Description of the Related Art Conventionally, an elevator control device is provided with a driving circuit board for driving the main circuit element together with the main circuit element. In this drive substrate, the main circuit element is driven by applying an on / off voltage to the gate portion of the main circuit element via the gate wiring (for example, Patent Document 1).

  By the way, the voltage output to the motor by changing the main circuit element on / off is changed between the positive side and the negative side of the main circuit DC voltage to control the output of an arbitrary voltage. As the speed increases, the potential change due to stray capacitance becomes steep. When a current path is formed by the presence of the stray capacitance between phases of the components mounted on the driving substrate, the gate wiring, and the stray capacitance due to the main circuit element, a high-frequency circulating current flows through the gate wiring.

JP 2008-271617 A

  When the circulating current flows in this way, the voltage of the gate portion of the drive substrate and the main circuit gate portion rises due to the impedance of the gate wiring, and the overvoltage protection diode in the drive substrate performs an unnecessary operation or the gate of the main circuit element. There is a possibility that a failure may occur due to application of an overvoltage to the part. For this reason, in a conventional elevator control device, it is conceivable to attempt to suppress the circulating current by inserting a circulating current suppressing core on the drive substrate or the gate wiring. However, for example, when trying to insert a circulating current suppression core in each gate wiring, a space for arranging the circulating current suppression core is required, which is an obstacle to downsizing the inverter device. .

  The present invention has been made in view of the above points, and an inverter device that contributes to downsizing of the inverter device by exhibiting a circulating current suppressing effect and often reducing the number of circulating current suppressing cores used. The present invention is intended to propose a control system for a three-phase motor.

  In order to solve this problem, in the present invention, a main circuit element constituting an inverter, a driving substrate for driving the main circuit element, and a gate for applying a gate voltage of the driving substrate to a gate portion of the main circuit element The present invention relates to an inverter device comprising a wiring and a circulating current suppression core that suppresses circulating current, and for an upper arm that applies a gate voltage of the drive substrate to a gate portion of the main circuit element constituting an upper arm of the same phase in the inverter And the gate wiring for the lower arm that applies the gate voltage of the drive substrate to the gate portion of the main circuit element that constitutes the lower arm of the same phase in the inverter are passed through the one circulating current suppression core. I try to do it.

  ADVANTAGE OF THE INVENTION According to this invention, it can contribute to size reduction of an inverter apparatus by reducing the number of use of the circulating current suppression core, exhibiting the suppression effect of circulating current.

It is a block diagram which shows the structural example of the control system of the three-phase motor which employ | adopted the inverter apparatus of this embodiment. FIG. 2 is a conceptual diagram specifically illustrating a configuration of a control system in FIG. 1. It is a perspective view which shows an example of a mode that each wiring penetrates into the hole of the ferrite core for each phase on a ring as a pair.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(1) Configuration Example of Control System for Three-Phase Motor Employing Inverter Device First, the configuration of the control system 100 for the three-phase motor 8 by the inverter device 2 in the present embodiment will be described.

  FIG. 1 shows an outline of a control system 100 for a three-phase motor 8 by the inverter device 2 according to the present embodiment. The control system 100 is supplied with electric power from a driving power source, and performs speed control by supplying driving electric power to the U phase, V phase, and W phase of the three-phase motor 8. Hereinafter, a more specific configuration of the control system 100 will be described.

  FIG. 2 specifically shows a specific example of the configuration of the control system 100 of the three-phase motor 8 of FIG. The control system 100 includes an inverter device 2 that is electrically connected to the U phase, the V phase, and the W phase of the three-phase motor 8, and a drive board 3 that drives the inverter device 2. The drive board 3 receives a control signal from a control device (not shown), and controls the speed of the three-phase motor 8 by driving the inverter device 2 based on the input control signal.

  The inverter device 2 has an arm including a switching element and a diode as a main circuit element constituting the inverter, and is configured to be electrically connected in series to the positive electrode side (P side) and the negative electrode side (N side), respectively. Groups (referred to as “legs”) are provided for three phases of U phase, V phase and W phase, respectively. In the main circuit element, the switching element and the diode are electrically connected in parallel so that the forward direction of the diode is opposite to the direction of the current flowing through the switching element. Hereinafter, for convenience of explanation, the U-phase, V-phase, and W-phase positive circuit side (P-side) main circuit elements are respectively referred to as the U-phase upper arm 1UP, the V-phase upper arm 1VP, and the W-phase upper arm 1WP. The U-phase, V-phase, and W-phase negative circuit side (N-side) main circuit elements are described as a U-phase lower arm 1UN, a V-phase lower arm 1VN, and a W-phase lower arm WN, respectively.

  In the present embodiment, an IGBT (abbreviation for Insulated Gate Bipolar Transistor) having high-speed switching performance is employed as the switching element. Hereinafter, for example, for the U-phase upper arm 1UP, the gate part of the IGBT that is the switching element is referred to as “gate part of the U-phase upper arm 1UP”, and the collector part of the IGBT that is the switching element is referred to as “the U-phase upper arm 1UP”. "The collector part of the arm 1UP" and the emitter part of the IGBT, which is a switching element, is described as "the emitter part of the U-phase upper arm 1UP", and the V-phase upper arm 1VP, the W-phase upper arm 1WP, the U-phase The same applies to the lower arm 1UN, the V-phase lower arm 1VN, and the W-phase lower arm WN.

  The U-phase upper arm 1UP and the U-phase lower arm 1UN are arranged in the inverter device 2 so as to be separated from each other by a predetermined distance in order to ensure electrical insulation. The emitter part of the U-phase upper arm 1UP is electrically connected to the collector part of the U-phase lower arm 1UN to form a U-phase arm group (U-phase leg). It is electrically connected to the U-phase wiring.

  The V-phase upper arm 1VP and the V-phase lower arm 1VN are arranged in the inverter device 2 so as to be separated from each other by a predetermined distance in order to ensure electrical insulation. The emitter portion of the V-phase upper arm 1VP is electrically connected to the collector portion of the V-phase lower arm 1VN to form a V-phase arm group (V-phase leg). It is electrically connected to the V-phase wiring.

  W-phase upper arm 1WP and W-phase lower arm 1WN are arranged in inverter device 2 so as to be separated from each other by a predetermined distance in order to ensure electrical insulation. The emitter portion of the W-phase upper arm 1WP is electrically connected to the collector portion of the W-phase lower arm 1WN to form a W-phase arm group (W-phase leg). It is electrically connected to the W-phase wiring.

  Note that the U-phase leg, the V-phase leg, and the W-phase leg are arranged in the inverter device 2 so as to be separated from each other by a predetermined distance in order to ensure electrical insulation.

  The drive substrate 3 includes a gate signal control IC 3UP for the U-phase upper arm that applies a gate voltage to the gate portion of the U-phase upper arm 1UP, and a V that applies a gate voltage to the gate portion of the V-phase upper arm 1VP. And a W-phase upper arm gate signal control IC 3WP that applies a gate voltage to the gate portion of the W-phase upper arm 1WP. The drive substrate 3 is overvoltaged with respect to the U-phase upper arm gate signal control IC 3UP, the V-phase upper arm gate signal control IC 3VP, and the W-phase upper arm gate signal control IC 3WP. Each is provided with an overvoltage protection diode that prevents failure due to application.

  The drive substrate 3 includes a gate signal control IC 3UN for the U-phase lower arm that applies a gate voltage to the gate portion of the U-phase lower arm 1UN, and a V that applies a gate voltage to the gate portion of the V-phase lower arm 1VN. A gate signal control IC 3VN for the lower arm of the phase and a gate signal control IC 3WN for the lower arm of the W phase that applies a gate voltage to the gate portion of the lower arm 1WN of the W phase. The drive substrate 3 has an overvoltage with respect to the U-phase lower arm gate signal control IC 3UN, the V-phase lower arm gate signal control IC 3VN, and the W-phase lower arm gate signal control IC 3WN. Each is provided with an overvoltage protection diode that prevents failure due to application.

  The drive substrate 3 corresponds to the U-phase upper arm gate signal control IC 3UP, the V-phase upper arm gate signal control IC 3VP, and the W-phase upper arm gate signal control IC 3WP. Three transformers are provided: an upper arm transformer 3TUP, a V-phase upper arm transformer 3TVP, and a W-phase upper arm transformer 3TWP. The primary side (input side) and secondary side (output side) of the U-phase upper arm transformer 3TUP, the V-phase upper arm transformer 3TVP, and the W-phase upper arm transformer 3TWP are electrically 1 circuit is formed on the secondary side of the U-phase upper arm transformer 3TUP, the V-phase upper arm transformer 3TVP, and the W-phase upper arm transformer 3TWP.

  The drive substrate 3 is common to each phase corresponding to the gate signal control IC 3UN for the lower arm of the U phase, the gate signal control IC 3VN for the lower arm of the V phase, and the gate signal control IC 3WN for the lower arm of the W phase. One transformer called N-side transformer 3TN is provided. The primary side (input side) and the secondary side (output side) of the transformer 3TN on the common N side of each phase are electrically separated and insulated, and three phases are arranged on the secondary side of the transformer 3TN on the common N side of each phase. Corresponding to (U phase, V phase and W phase), three circuits (U phase circuit, V phase circuit and W phase circuit) are formed.

  The primary side of the U-phase upper arm transformer 3TUP, the V-phase upper arm transformer 3TVP, and the W-phase upper arm transformer 3TWP is supplied with driving power from the power supply device, respectively. In the upper arm transformer 3TUP, the V-phase upper arm transformer 3TVP, and the W-phase upper arm transformer 3TWP, the voltage of the driving power supply is converted into a predetermined voltage. The converted predetermined voltage and ground are respectively supplied from the secondary side of the U-phase upper arm transformer 3TUP to the U-phase upper arm gate signal control IC 3UP, and for the V-phase upper arm. The V-phase upper arm gate signal control IC 3VP is supplied from the secondary side of the transformer 3TVP, and the W-phase upper arm gate signal control IC 3WP is supplied from the secondary side of the W-phase upper arm transformer 3TWP. Are supplied to each.

  The primary side of each phase-common N-side transformer 3TN used in common for the lower arms of the U-phase, V-phase, and W-phase is supplied with driving power from the power supply device, and in each phase-common N-side transformer 3TN The voltage of the driving power supply is converted to a predetermined voltage. The converted predetermined voltage and ground are respectively supplied from the U-phase circuit on the secondary side of the transformer 3TN on the N-phase common side to the gate signal control IC 3UN for the lower arm of the U-phase. The V-phase lower-arm gate signal control IC 3VN is supplied from the secondary-side V-phase circuit of the N-side transformer 3TN to the secondary-side W-phase circuit of the common-side N-side transformer 3TN. It is supplied to the gate signal control IC 3WN for the lower arm of the W phase.

  The output portion of the U-phase upper arm gate signal control IC 3UP is electrically connected to the gate portion of the U-phase upper arm 1UP included in the inverter device 2 via the U-phase upper arm gate wiring 4UP. ing. The emitter part of the U-phase upper arm 1UP is electrically connected to the collector part of the U-phase lower arm 1UN and the U-phase of the three-phase motor 8, and via the U-phase upper arm ground wiring 4UPG. Thus, it is electrically connected to the secondary grant of the U-phase upper arm transformer 3TUP. The U-phase upper arm gate signal control IC 3UP applies a gate voltage from its output to the gate of the U-phase upper arm 1UP based on a control signal from the control device.

  The output portion of the V-phase upper arm gate signal control IC 3VP is electrically connected to the gate portion of the V-phase upper arm 1VP included in the inverter device 2 via the V-phase upper arm gate wiring 4VP. ing. The emitter of the V-phase upper arm 1VP is electrically connected to the collector of the V-phase lower arm 1VN and the V-phase of the three-phase motor 8, and via the V-phase upper arm ground wiring 4VPG. The V-phase upper arm transformer 3TVP is electrically connected to the secondary side grant. The V-phase upper arm gate signal control IC 3VP applies a gate voltage from its output to the gate of the V-phase upper arm 1VP based on a control signal from the control device.

  The output portion of the W-phase upper arm gate signal control IC 3WP is electrically connected to the gate portion of the W-phase upper arm 1WP provided in the inverter device 2 via the W-phase upper arm gate wiring 4WP. ing. The emitter portion of the W-phase upper arm 1WP is electrically connected to the collector portion of the W-phase lower arm 1WN and the W-phase of the three-phase motor 8, and via the W-phase upper arm ground wiring 4WPG. Thus, it is electrically connected to the secondary grant of the W-phase upper arm transformer 3TWP. The W-phase upper arm gate signal control IC 3WP applies a gate voltage from its output to the gate of the W-phase upper arm 1WP based on a control signal from the control device.

  Motor drive power from the power supply device is supplied to the collector section of the U-phase upper arm 1UP, the collector section of the V-phase upper arm 1VP, and the collector section of the W-phase upper arm 1WP provided in the inverter device 2. ing.

  The output portion of the U-phase lower arm gate signal control IC 3UN is electrically connected to the gate portion of the U-phase lower arm 1UN included in the inverter device 2 via the U-phase lower arm gate wiring 4UN. ing. The emitter part of the U-phase lower arm 1UN is electrically connected to the emitter part of the V-phase lower arm 1VN and the emitter part of the W-phase lower arm 1WN, as well as the U-phase lower arm ground wiring 4UNG. Is electrically connected to the grant of the U-phase circuit on the secondary side of the transformer 3TN on the N-side common N side. The U-phase lower arm gate signal control IC 3UN applies a gate voltage from its output to the gate of the U-phase lower arm 1UN based on a control signal from the control device.

  The output part of the V-phase lower arm gate signal control IC 3VN is electrically connected to the gate part of the V-phase lower arm 1VN included in the inverter device 2 via the V-phase lower arm gate wiring 4VN. ing. The emitter of the V-phase lower arm 1VN is electrically connected to the emitter of the U-phase lower arm 1UN and the emitter of the W-phase lower arm 1WN, and the V-phase lower arm ground wiring 4VNG. Is electrically connected to the grant of the secondary-side V-phase circuit of the transformer 3TN on the N-side common N side. The V-phase lower arm gate signal control IC 3VN applies a gate voltage from its output to the gate of the V-phase lower arm 1VN based on the control signal from the control device.

  The output part of the W-phase lower arm gate signal control IC 3WN is electrically connected to the gate part of the W-phase lower arm 1WN included in the inverter device 2 via the W-phase lower arm gate wiring 4WN. ing. The emitter portion of the W-phase lower arm 1WN is electrically connected to the emitter portion of the U-phase lower arm 1UN and the emitter portion of the V-phase lower arm 1VN, as well as the W-phase lower arm ground wiring 4WNG. And is electrically connected to the grant of the W-phase circuit on the secondary side of the transformer 3TN on the N-side common N side. The W-phase lower arm gate signal control IC 3WN applies a gate voltage from its output to the gate of the W-phase lower arm 1WN based on a control signal from the control device.

(2) Wiring for electrically connecting the inverter device and the driving substrate according to the present embodiment Next, wiring for electrically connecting the inverter device 2 and the driving substrate 3 will be described.

  In the present embodiment, since the IGBT is used as the switching element, the potential change having the stray capacitance becomes steep with respect to the gate portion of the IGBT and its surroundings due to the high-speed switching by the IGBT. In such a situation, as the stray capacitance that becomes a common mode of noise, for example, the stray capacitance between the V-phase lower arm 1VN and the ground provided in the inverter device 2, the gate portion of the V-phase lower arm 1VN, and the drive substrate 3 Stray capacitance between the V-phase lower arm gate wiring 4VN and the ground, which electrically connects the output portion of the V-phase lower-arm gate signal control IC 3VN, and the V-phase lower arm gate signal control. The stray capacitance between the IC 3VN and the ground, and the inter-phase stray capacitance 5 between the U-phase circuit and the V-phase circuit on the secondary side of the transformer 3TN on each phase common N side provided in the drive substrate 3 (shown by a chain line in FIG. 2). ), A stray capacitance between the U-phase lower-arm gate signal control IC 3UN and the ground included in the driving substrate 3, the lower-arm gate signal control IC 3UN and the U included in the inverter device 2 Stray capacitance of the gate wiring 4UN and ground lower arm of U-phase for electrically connecting the gate of the lower arm 1UN of, there is a stray capacitance between the lower arm 1UN the ground of the U-phase.

  Through these paths, the V-phase lower arm 1VN provided in the inverter device 2, the V-phase lower arm gate wiring 4VN, the V-phase lower arm gate signal control IC 3VN provided in the drive substrate 3, and the common N for each phase The U-phase circuit for the secondary side of the transformer 3TN on the side, the V-phase circuit, the gate signal control IC 3UN for the U-phase lower arm included in the drive substrate 3, and the U-phase lower arm gate wiring 4UN A high-frequency leakage current flows toward the lower arm 1UN of the U-phase provided in the inverter device 2 so that the circulating current 6 flows (flows in the path in the direction of the broken arrow in FIG. 2).

  When the circulating current 6 flows to the V-phase lower arm gate signal control IC 3VN provided in the drive substrate 3 via the V-phase lower arm gate wiring 4VN, a voltage is generated by the impedance of the V-phase lower arm gate wiring 4VN. Since the voltage applied to the output part of the gate signal control IC 3VN for the V-phase lower arm and the gate part of the V-phase lower arm 1VN included in the inverter device 2 also rises. There is a possibility that the overvoltage protection diode provided in the drive substrate 3 may perform an unnecessary operation, or a failure due to overvoltage application may occur in the gate portion of the V-phase lower arm 1VN.

  Further, when the circulating current 6 flows to the U-phase lower arm gate signal control IC 3UN provided in the drive substrate 3 via the U-phase lower arm gate wiring 4UN, the impedance of the U-phase lower arm gate wiring 4UN is increased. As a result, the voltage increases, and the voltage applied to the output part of the U-phase lower arm gate signal control IC 3UN and the gate part of the U-phase lower arm 1UN provided in the inverter device 2 also increases. Then, there is a possibility that the overvoltage protection diode provided in the drive substrate 3 may operate unnecessarily, or a failure due to overvoltage application may occur in the gate portion of the U-phase lower arm 1UN.

  The following method can be considered as a method for solving the problems that appear due to the use of an IGBT that performs high-speed switching as such a switching element. That is, the U-phase upper arm gate wiring 4UP and the U-phase upper arm ground wiring 4UPG are passed through the holes of the ring-shaped ferrite core as a pair, and the U-phase lower arm gate wiring 4UN and the U-phase The arm ground wiring 4UNG is passed through the hole of the ring-shaped ferrite core as a pair, and the V-phase upper arm gate wiring 4VP and the V-phase upper arm ground wiring 4VPG are paired into the hole of the ring-shaped ferrite core. The V-phase lower arm gate wiring 4VN and the V-phase lower arm ground wiring 4VNG are paired into the holes of the ring-shaped ferrite core, respectively, and the W-phase upper arm gate wiring 4WP and W-phase are penetrated. The upper-arm ground wiring 4WPG is passed through the hole of the ring-shaped ferrite core as a pair, and the W-phase And a method that each penetrates into a hole of the ring-shaped ferrite core ground wiring 4WNG the lower arm of the gate wiring 4WN and W-phase arm as a pair. With such a ferrite core, the circulating current 6 can be suppressed by attenuating high frequency noise due to high frequency leakage current.

  However, in such a method, six ferrite cores are required, and it is necessary to secure a space for arranging the ferrite cores. Therefore, it is not possible to contribute to downsizing of the inverter device 2.

  Therefore, in the present embodiment, it is not controllable that the upper arm and the lower arm in the U phase, the V phase, and the W phase simultaneously output the gate voltage from the viewpoint of preventing the upper arm and the lower arm from being damaged. , And the upper and lower arms of the same phase were paired to penetrate the ferrite core. Even if a circulating current flows in the same phase, the influence on other phases can be made difficult to occur.

  Specifically, in this embodiment, as shown in FIG. 3A, the U-phase upper arm gate wiring 4UP, the U-phase upper arm ground wiring 4UPG, the U-phase lower arm gate wiring 4UN, and A method was adopted in which the U-phase lower arm ground wiring 4UNG was passed through the holes of the ring-shaped U-phase ferrite core 7U as a pair.

  As a result, the U-phase upper arm gate wiring 4UP and the U-phase upper arm ground wiring 4UPG are passed through the holes of the ring-shaped ferrite core as a pair, and the U-phase lower arm gate wiring 4UN and U-phase are respectively passed through. The U-phase ferrite core 7U has substantially the same effect that the circulating current can be suppressed to a negligible level by penetrating the lower arm ground wiring 4UNG as a pair into the hole of the ring-shaped ferrite core. This can be realized with one ferrite core.

  In this embodiment, as shown in FIG. 3B, the V-phase upper arm gate wiring 4VP, the V-phase upper arm ground wiring 4VPG, the V-phase lower arm gate wiring 4VN, and the V-phase lower arm A method of penetrating through the holes of the ring-shaped V-phase ferrite core 7V with the ground wiring 4VNG as a pair was adopted. In FIG. 2, the V-phase ferrite core 7V is conceptually represented. At first glance, it looks different from the configuration shown in FIG. There is no difference in how to use 7V.

  In this way, the V-phase upper arm gate wiring 4VP and the V-phase upper arm ground wiring 4VPG are passed through the holes of the ring-shaped ferrite core as a pair, and the V-phase lower arm gate wiring 4VN and V-phase The V-phase ferrite core 7V has almost the same effect that the circulating current can be suppressed to a negligible level by penetrating the lower arm ground wiring 4VNG as a pair into the hole of the ring-shaped ferrite core. This can be realized with one ferrite core.

  In this embodiment, as shown in FIG. 3C, the W-phase upper arm gate wiring 4WP, the W-phase upper arm ground wiring 4WPG, the W-phase lower arm gate wiring 4WN, and the W-phase lower arm A method of penetrating through the holes of the ring-shaped W-phase ferrite core 7W as a pair was used for the ground wiring 4WNG. In FIG. 2, the W-phase ferrite core 7W is conceptually represented. At first glance, it seems to be different from the configuration shown in FIG. There is no difference in how to use 7W.

  As a result, the W-phase upper arm gate wiring 4WP and the W-phase upper arm ground wiring 4WPG are passed through the holes of the ring-shaped ferrite core as a pair, and the W-phase lower arm gate wiring 4WN and W-phase are respectively passed through. By passing the lower arm ground wiring 4WNG as a pair through the holes in the ring-shaped ferrite core, the substantially same effect that the circulating current can be suppressed to a negligible level is obtained. This can be realized with one ferrite core.

(3) Effect As described above, the inverter device 2 according to the present embodiment has the U-phase upper arm gate wiring 4UP, the V-phase upper arm gate wiring 4VP, the W-phase upper arm gate wiring 4WP, and the U-phase The same effect as the method of penetrating the lower arm gate wiring 4UN, the V-phase lower arm gate wiring 4VN, and the W-phase lower arm gate wiring 4WN into the corresponding six ferrite cores (circulation current suppression cores). Can be realized by three ferrite cores (circulation current suppression cores), ie, a U-phase ferrite core 7U, a V-phase ferrite core 7V, and a W-phase ferrite core 7W.

  As described above, the number of circulating current suppression cores used can be reduced by half from six to three while maintaining the circulating current suppression effect, thereby reducing the space for arranging the circulating current suppression cores. Therefore, it is possible to contribute to the downsizing of the inverter device 2. Therefore, it is possible to reduce the number of the circulating current suppression cores used while maintaining the circulating current suppression effect, thereby contributing to downsizing of the inverter device 2.

  Further, in the inverter device 2 according to the present embodiment, the U-phase upper arm 1UP and the U-phase lower arm 1UN are arranged in the inverter device 2 so as to be separated from each other by a predetermined distance in order to ensure electrical insulation. The upper arm 1VP of the phase and the lower arm 1VN of the U phase are arranged in the inverter device 2 apart from each other by a predetermined distance in order to ensure electrical insulation, and the upper arm 1WP of the W phase and the W phase of the W phase Since the lower arm 1WN is arranged in the inverter device 2 with a predetermined distance to ensure electrical insulation, stray capacitance between the upper and lower arms of each phase is almost ignored. It can be made as small as possible, and can be prevented from being electrically interfered with or influenced by each other.

(4) Other Embodiments In the above-described embodiments, the IGBT is adopted as the switching element. However, any element that can perform high-speed switching may be configured by another element instead of the IGBT. Good. Even in such a configuration, the U-phase upper arm gate wiring 4UP and the U-phase upper arm ground wiring 4UPG, U are used to solve the problem that the circulating current generated by performing high-speed switching as the switching element flows. The lower arm gate wiring 4UN and the U phase lower arm ground wiring 4UNG are passed through the holes of the U phase ferrite core 7U as a pair, respectively, and the V phase upper arm gate wiring 4VP and the V phase upper arm A pair of the ground wiring 4VPG, the V-phase lower arm gate wiring 4VN, and the V-phase lower arm ground wiring 4VNG passes through the holes of the V-phase ferrite core 7V, respectively, and the W-phase upper arm gate wiring 4WP, W Phase upper arm ground wiring 4WPG, W phase lower arm gate wiring 4WN, and W phase lower arm ground wiring 4WNG By adopting a method of penetrating through the holes of the W-phase ferrite core 7W as a pair, the U-phase ferrite core 7U, the V-phase ferrite core 7V, and the W-phase ferrite core 7W are circulated using three ferrite cores. The current can be suppressed to a level that can be ignored.

  In the above-described embodiment, the U-phase ferrite core 7U, the V-phase ferrite core 7V, and the W-phase ferrite core 7W penetrate each wiring. The ferrite core 7W for 7V and W phase may be fixedly attached to the inverter device 2 side so as to penetrate each wiring.

  Further, in the above-described embodiment, the U-phase ferrite core 7U, the V-phase ferrite core 7V, and the W-phase ferrite core 7W employ ring-shaped ferrite cores (circulating current suppression cores). Alternatively, a clamp type in which the ferrite core is divided in half may be adopted. In such a clamp type, the wiring can be penetrated into the ferrite core by sandwiching the wiring with the ferrite core divided in half.

  1UP ... U phase upper arm, 1UN ... U phase lower arm, 1VP ... V phase upper arm, 1VN ... V phase lower arm, 1WP ... W phase upper arm, 1WN ... W phase lower arm, 2 ... Inverter device, 3 ... Drive substrate, 4UP ... U-phase upper arm gate wiring, 4UN ... U-phase lower arm gate wiring, 4VP ... V-phase upper arm gate wiring, 4VN ... V-phase lower arm gate wiring Wiring, 4WP: W-phase upper arm gate wiring, 4WN: W-phase lower arm gate wiring, 5 ... interphase stray capacitance, 6 ... circulating current, 7U ... U-phase ferrite core, 7V ... V-phase ferrite core , 7W: ferrite core for W phase, 8: three-phase motor, 100: control system.

Claims (6)

Main circuit elements constituting the inverter;
A driving substrate for driving the main circuit element;
A gate wiring for applying a gate voltage of a driving substrate to the gate portion of the main circuit element;
With a circulating current suppression core that suppresses the circulating current,
A gate wiring for an upper arm that applies a gate voltage of the driving substrate to a gate portion of the main circuit element that constitutes the upper arm of the inverter that is in phase with the inverter, and a main circuit element that constitutes the lower arm of the inverter with the same phase. An inverter device, characterized in that a gate wiring for a lower arm that applies a gate voltage of the driving substrate to a gate portion is penetrated by one circulating current suppressing core. The inverter device according to claim 1, wherein the upper arm and the lower arm having the same phase are spaced apart by a predetermined distance in order to ensure electrical insulation.   2. The inverter device according to claim 1, wherein a gate voltage is applied to the gate unit at different timings in the upper arm and the lower arm in phase. Main circuit elements constituting the inverter;
A driving substrate for driving the main circuit element;
A gate wiring for applying a gate voltage of a driving substrate to the gate portion of the main circuit element;
With a circulating current suppression core that suppresses the circulating current,
A gate wiring for an upper arm that applies a gate voltage of the driving substrate to a gate portion of the main circuit element that constitutes the upper arm of the inverter that is in phase with the inverter, and a main circuit element that constitutes the lower arm of the inverter with the same phase. A control system for a three-phase motor, comprising: an inverter device configured such that a gate wiring for a lower arm that applies a gate voltage of the driving substrate to a gate portion is penetrated by one of the circulating current suppression cores . The three-phase motor control system according to claim 4, wherein the upper arm and the lower arm in phase are spaced apart by a predetermined distance to ensure electrical insulation.   5. The three-phase motor control system according to claim 4, wherein a gate voltage is applied to the gate unit at different timings in the upper arm and the lower arm in phase.

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