JP2017055350A - Solid state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid state imaging device capable of improving image quality under various lighting environments.SOLUTION: In a low illuminance mode, a switching transistor TC is turned off and a capacitive element CAP is disconnected from a floating diffusion FD. In a high illuminance mode, the switching transistor TC is turned on and the capacitive element CAP is connected to the floating diffusion FD. In an HDR mode, pixels S1 and S2 are used as high sensitivity pixels and pixels S3 and S4 are used as low sensitivity pixels.SELECTED DRAWING: Figure 3

Description

  Embodiments described herein relate generally to a solid-state imaging device.

  In a solid-state imaging device, in order to improve a dynamic range (a range from the darkest part to the brightest part of a captured image), a single pixel may be configured by a plurality of pixels with different sensitivities that can be individually read.

JP 2014-168112 A

  An object of one embodiment of the present invention is to provide a solid-state imaging device capable of improving image quality under various illumination environments.

  According to one embodiment of the present invention, a cell that includes a first pixel and a second pixel that can be read independently of each other, and a first floating diffusion layer is shared by the first pixel and the second pixel. And a capacitor provided in the cell, and a transistor provided in the cell and provided between the capacitor and the first floating diffusion layer.

FIG. 1 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment. 2A is a plan view showing a configuration example of the pixel array section of FIG. 1, and FIG. 2B is a plan view showing a configuration example of four pixels of the pixel array section of FIG. 2A. . FIG. 3 is a circuit diagram illustrating a configuration example of one pixel of the pixel array unit of FIG. FIG. 4 is a plan view showing a layout example for four pixels of the pixel array section of FIG. FIG. 5 is a cross-sectional view illustrating a configuration example of the capacitive element of FIG. FIG. 6 is a cross-sectional view showing another configuration example of the capacitive element of FIG. 7A is a timing chart showing a pixel driving method in the low illuminance mode, FIG. 7B is a timing chart showing a pixel driving method in the high illuminance mode, and FIG. 7C is HDR. 3 is a timing chart illustrating a pixel driving method in a mode. FIG. 8 is a diagram illustrating an example of a mode determination method of the solid-state imaging device of FIG. FIG. 9 is a flowchart showing the operation of the solid-state imaging device of FIG. FIG. 10 is a block diagram illustrating a schematic configuration of the solid-state imaging apparatus according to the second embodiment. FIG. 11A is a plan view showing a configuration example of the pixel array section of FIG. 10, and FIG. 11B is a plan view showing a configuration example of four pixels of the pixel array section of FIG. 11A. . FIG. 12 is a circuit diagram illustrating a configuration example of one pixel of the pixel array unit of FIG. FIG. 13 is a plan view showing a layout example for four pixels in the pixel array section of FIG. FIG. 14 is a timing chart showing an example of setting the charge accumulation time of the solid-state imaging device of FIG. FIG. 15 is a circuit diagram illustrating a configuration example of one pixel of the solid-state imaging device according to the third embodiment. FIG. 16 is a block diagram illustrating a schematic configuration of a digital camera to which the solid-state imaging device according to the fourth embodiment is applied. FIG. 17 is a cross-sectional view illustrating a schematic configuration of a camera module to which the solid-state imaging device according to the fifth embodiment is applied.

  Hereinafter, a solid-state imaging device according to an embodiment will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment.
In FIG. 1, the solid-state imaging device includes a sensor unit B1 and an image processing unit B2. The sensor unit B1 includes a pixel array unit 1 provided with a plurality of cells, a vertical scanning circuit 2 that scans a pixel to be read out in a vertical direction, a signal component of each pixel is detected for each column by CDS, and AD A column ADC circuit 3 for conversion and output, a horizontal scanning circuit 4 for scanning pixels to be read out in the horizontal direction, and a timing control circuit 5 for controlling the timing of reading and accumulation of each pixel are provided. The horizontal scanning circuit 4 can use a horizontal register that transfers AD conversion values generated in parallel for each column by the column ADC circuit 3 in series in the horizontal direction. The pixel array unit 1 is provided with a vertical OB (Optical Black) unit 6. The vertical OB unit 6 is provided with OB pixels used for setting a black level reference at the time of imaging. At this time, the timing control circuit 5 can adjust the output value of the OB pixel so that the black level read from the OB pixel matches the target value.
The image processing unit B2 includes a digital clamp unit 21, a sensitivity adjustment unit 22, delay elements 23 and 25, a defect correction unit 24, an image cutout unit 26, a drive mode setting unit 27, an automatic exposure control unit 28, and an interface unit 29. It has been.
The digital clamp unit 21 clamps (fixes the level of) the image signal read from the pixel PX based on the black level read from the OB pixel. At this time, the digital clamp unit 21 can subtract the average value of the output values from the OB pixel from the image signal of the pixel PX and add a predetermined black level value.
The sensitivity adjustment unit 22 adjusts the digital gain of the output values of the pixels S1 to S4 so that the sensitivity ratios match between the pixels S1 to S4 when the sensitivity or accumulation time differs between the pixels S1 to S4. Since the sensitivity ratio is matched between the pixels S1 to S4, the reciprocal of the sensitivity ratio can be multiplied by the digital gain. The pixels S1 to S4 will be described later.
The delay elements 23 and 25 can be used for delay for matching the output timing of the image signal when determining the effective pixel. At this time, SRAMs can be used as the delay elements 23 and 25. The effective pixel referred to here is one or more pixels selected from the pixels S1 to S4. At this time, a pixel having an output value within a predetermined range among the pixels S1 to S4 can be set as an effective pixel.
The defect correction unit 24 corrects the pixel signal read from the cell so that the defect of the cell is repaired.
The image cutout unit 26 cuts out a predetermined area of the image (hereinafter sometimes referred to as digital crop).
The drive mode setting unit 27 sets the drive mode of the pixel PX based on the distribution of output values from the pixel PX. As the drive mode, a normal mode and an HDR (High Dynamic Range) mode can be set. In the normal mode, a low illumination mode (a mode activated when the subject is dark) and a high illumination mode (a mode activated when the subject is bright) can be set. At this time, in the normal mode, charges accumulated in the pixels S1 to S4 can be read together (reading charges from a plurality of pixels collectively may be referred to as charge addition binning). In the HDR mode, when the pixels S1 to S4 are divided into two or more groups, charges can be read out separately for each group. At this time, the sensitivity can be set to be different for each group.
The automatic exposure control unit 28 performs automatic exposure control based on the luminance value of the pixel PX. At this time, the automatic exposure control unit 28 can adjust the accumulation time or the analog gain so that the average value of the output values in a predetermined area of the image becomes a predetermined value.
The interface unit 29 outputs the pixel signal in a predetermined format. This format can conform to, for example, the CSI (Camera Serial Interface) 2 standard.

In the digital clamp unit 21, the black level of the pixel signal output via the horizontal scanning circuit 4 is corrected. In the HDR mode, the sensitivity adjustment unit 22 adjusts the digital gain of the output values of the pixels S1 to S4 so that the sensitivity ratio is matched between the groups of the pixels S1 to S4. On the other hand, in the normal mode, the processing of the sensitivity adjustment unit 22 is omitted.
After the defect correction unit 24 corrects the pixel signal, the image cutout unit 26 cuts out a predetermined area of the image.
The drive mode setting unit 27 sets the drive mode of the pixel PX, and the automatic exposure control unit 28 performs automatic exposure control. Here, when the drive mode is set in the drive mode setting unit 27, the sensitivity adjustment unit 22 and the timing control circuit 5 are notified.
In the timing control circuit 5, the readout timing of the pixels S1 to S4, the accumulation time of the pixels S1 to S4, and the analog gain of the pixels S1 to S4 are set according to the drive mode.

Next, the pixel array unit of the solid-state imaging device according to the first embodiment will be described with reference to FIG.
2A is a plan view showing a configuration example of the pixel array section of FIG. 1, and FIG. 2B is a plan view showing a configuration example of four pixels of the pixel array section of FIG. 2A. .
2A and 2B, in the pixel array section 1, cells are arranged in an array in the row direction RD and the column direction CD. In the first embodiment, the cell will be described as including four pixels S1 to S4. The cells P can have the same sensitivity in the same color pixels. Regarding the pixels S1 to S4, at least one of the pixels S1 to S4 can have a sensitivity different from that of the other pixels with respect to the same color pixel. The pixels S1 to S4 can be read independently of each other. In addition, the pixels S1 to S4 can set the accumulation time independently of each other. As a method of making at least one of the pixels S1 to S4 have different sensitivity from other pixels, the amount of light received on the photosensitive surface may be made different, or the accumulation time may be made different. As a method of varying the light receiving amount of the photosensitive surface of the pixels S1 to S4, a light shielding layer may be provided, the area of the light receiving surface may be varied, or the size of the microlens may be varied. It may be.
In the pixel array unit 1, a Bayer array HP having a set of four cells P1 to P4 can be used to colorize a captured image. In this Bayer array HP, two green pixels Gr and Gb are arranged in the first diagonal direction of the Bayer array HP, and one red pixel R and one pixel are arranged in the second diagonal direction of the Bayer array HP. A blue pixel B is arranged. Each pixel S1 to S4 has at least a photoelectric conversion unit. A readout circuit that reads a signal from the photoelectric conversion unit may be shared between the pixels S1 to S4, or may be provided separately for each of the pixels S1 to S4.
In addition, by setting the cell P to the configuration of the pixels S1 to S4, it is possible to obtain pixel signals having different sensitivities from the cell P while making it possible to apply the read timing control for the cell P to the pixels S1 to S4.

FIG. 3 is a circuit diagram illustrating a configuration example of one pixel of the pixel array unit of FIG.
In FIG. 3, one cell P includes pixels S1 to S4, a capacitive element CAP, a row selection transistor TD, an amplification transistor TA, a reset transistor TR, readout transistors TE1 to TE4, a switching transistor TC, and a floating diffusion layer as a floating diffusion layer. Includes FD. The pixels S1 to S4 include photodiodes PD1 to PD4, respectively. Here, the row selection transistor TD, the amplification transistor TA, the reset transistor TR, and the switching transistor TC are shared by the photodiodes PD1 to PD4. The read transistors TE1 to TE4 are provided for the photodiodes PD1 to PD4. In addition, a floating diffusion FD is formed as a detection node at a connection point between the amplification transistor TA, the reset transistor TR, the read transistors TE1 to TE4, and the switching transistor TC.

The source of the read transistor TE1 is connected to the photodiode PD1, the source of the read transistor TE2 is connected to the photodiode PD2, the source of the read transistor TE3 is connected to the photodiode PD3, and the source of the read transistor TE4 is connected to the photo diode It is connected to the diode PD4.
The source of the reset transistor TR is connected to the drains of the read transistors TE1 to TE4.
The drains of the reset transistor TR and the amplification transistor TA are connected to the power supply potential VDD. The gate of the amplification transistor TA is connected to the drains of the read transistors TE1 to TE4.
The source of the row selection transistor TD is connected to the vertical signal line Vlin, and the drain of the row selection transistor TD is connected to the source of the amplification transistor TA.
The drain of the switching transistor TC is connected to the floating diffusion FD, and the source of the switching transistor TC is connected to the capacitive element CAP.
Read signals READ1 to READ4 are input to the gates of the read transistors TE1 to TE4. A reset signal RESET is input to the gate of the reset transistor TR. A row selection signal ADR is input to the gate of the row selection transistor TD. A switching signal FDW is input to the gate of the switching transistor TC. The pixel signal Vsig read from each of the photodiodes PD1 to PD4 is transmitted in the column direction CD through the vertical signal line Vlin.

FIG. 4 is a plan view showing a layout example for four pixels of the pixel array section of FIG.
In FIG. 4, a Bayer array HP is configured by arranging cells P1 to P4 in a square shape over 2 rows and 2 columns. For example, in the cell P1, the photodiodes PD1 to PD4 are arranged in a square shape on the semiconductor substrate SB, so that the pixels S1 to S4 are configured. Note that the material of the semiconductor substrate SB can be selected from, for example, Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, InGaAsP, GaP, GaN, and ZnSe.
The conductivity type of the semiconductor substrate SB can be set to P type, and the conductivity types of the photodiodes PD1 to PD4 can be set to N type. Between the cells P1 to P4, a capacitive element CAP, a row selection transistor TD, an amplification transistor TA, a reset transistor TR, and a switching transistor TC are arranged. The row selection transistor TD and the amplification transistor TA are disposed adjacent to the row direction RD. The capacitive element CAP, the switching transistor TC, and the reset transistor TR are disposed adjacent to the column direction CD. A floating diffusion FD is arranged in the center of the square arrangement of the photodiodes PD1 to PD4. At this time, the distances from the photodiodes PD1 to PD4 to the floating diffusion FD can be made equal to each other. Read transistors TE1 to TE4 are arranged between the photodiodes PD1 to PD4 and the floating diffusion FD. The gate electrode of the amplification transistor TA and the floating diffusion FD are connected via the wiring H1, and the source of the reset transistor TR and the floating diffusion FD are connected via the wiring H2. The source of the row selection transistor TD is connected to the vertical signal line Vlin. Microlenses ML are separately provided on the photodiodes PD1 to PD4.

FIG. 5 is a cross-sectional view illustrating a configuration example of the capacitive element of FIG.
In FIG. 5, impurity diffusion layers HU1 and HU2 are separately formed on the semiconductor substrate SB. A gate insulating film 31 is formed on the impurity diffusion layers HU1 and HU2. A gate electrode 32 is formed on the channel layer between the impurity diffusion layers HU1 and HU2 via the gate insulating film 31. A capacitive electrode 33 is formed on the impurity diffusion layer HU2 with a gate insulating film 31 interposed therebetween. At this time, the impurity diffusion layer HU1 can be used as the source of the reset transistor TR. The impurity diffusion layer HU2 and the capacitor electrode 33 can be used as a capacitor electrode of the capacitor element CAP.

FIG. 6 is a cross-sectional view showing another configuration example of the capacitive element of FIG. In FIG. 6, a back-illuminated CMOS sensor is taken as an example. In FIG. 6, an MIM (Metal Insulator Metal) structure is shown as the capacitor.
In FIG. 6, photodiodes PD1 and PD2 and a floating diffusion FD are separately formed on the semiconductor substrate SB. A gate insulating film 40 is formed on the photodiodes PD1 and PD2 and the floating diffusion FD. A gate electrode 41 is formed on the channel layer between the photodiode PD1 and the floating diffusion FD via a gate insulating film 40. The gate electrode 41 can be used for the read transistor TE1. A gate electrode 42 is formed on the channel layer between the photodiode PD2 and the floating diffusion FD via a gate insulating film 40. The gate electrode 42 can be used for the read transistor TE2. An interlayer insulating film 43 is formed on the gate insulating film 40 so as to cover the gate electrodes 41 and 42. On the interlayer insulating film 43, a dielectric layer 45 sandwiched between capacitive electrodes 44 and 46 is formed. As the material of the capacitance electrodes 44 and 46, a metal such as Al or Cu can be used. As a material of the dielectric layer 45, an insulator such as SiO ₂ or SiN can be used. At this time, the capacitive electrodes 44 and 46 and the dielectric layer 45 can be used as the capacitive element CAP. A transparent spacer layer SP is formed on the semiconductor substrate SB. A color filter FL is disposed on the transparent spacer layer SP. A microlens ML is disposed on the color filter FL. As the material of the microlens ML, for example, a transparent resin such as acrylic or polycarbonate can be used.
In the configuration of FIG. 6, the area of the capacitive element CAP can be easily increased compared to the configuration of FIG. 5, and the capacitance of the capacitive element CAP can be increased.

Next, the operation of the solid-state imaging device according to the first embodiment will be described with reference to FIG.
7A is a timing chart showing a pixel driving method in the low illuminance mode, FIG. 7B is a timing chart showing a pixel driving method in the high illuminance mode, and FIG. 7C is HDR. 3 is a timing chart illustrating a pixel driving method in a mode.
In FIG. 7A, in the low illuminance mode, the reset transistor TR and the read transistors TE1 to TE4 are turned on when the reset signal RESET and the read signals READ1 to READ4 rise. At this time, charges accumulated in the photodiodes PD1 to PD4 are discharged. When the reset signal RESET and the read signals READ1 to READ4 fall, the reset transistor TR and the read transistors TE1 to TE4 are turned off, and charge accumulation in the photodiodes PD1 to PD4 is started (time t1).
Next, when the reset signal RESET rises, the reset transistor TR is turned on. At this time, the charge accumulated in the floating diffusion FD is discharged (time t2).
Next, when the read signals READ1 to READ4 rise, the read transistors TE1 to TE4 are turned on. At this time, the charges accumulated in the photodiodes PD1 to PD4 are transferred to the floating diffusion FD (time t3).
The amplification transistor TA performs a source follower operation according to the potential of the floating diffusion FD when the row selection transistor TD is turned on, so that the pixel signal Vsig corresponding to the potential of the floating diffusion FD is transmitted via the vertical signal line Vlin. Can be transmitted. At this time, the charge accumulation time HT1 of the photodiodes PD1 to PD4 is from time t1 to time t3. Further, the charge accumulation binning of the pixels S1 to S4 can be performed by simultaneously reading out the charges accumulated in the photodiodes PD1 to PD4 to the floating diffusion FD. In this charge addition binning, the charges accumulated in the pixels S1 to S4 are added and read out simultaneously. For this reason, it is possible to improve the sensitivity and improve the reading speed as compared with the case where the signals are read separately from the pixels S1 to S4.
Here, at time t2 and t3, the switching signal FDW can be set to a low level, and the switching transistor TC can be turned off. At this time, the capacitive element CAP is disconnected from the floating diffusion FD. For this reason, it is possible to eliminate the additional capacitance due to the capacitance element CAP of the floating diffusion FD (hereinafter, the additional capacitance due to the capacitance element CAP of the floating diffusion FD is simply referred to as additional capacitance), and the conversion efficiency when converting charges into voltage is improved. It is possible to raise. The conversion efficiency η can be given by η = q / CF · G. Where q is the amount of charge of electrons, G is the gain of the amplification transistor TA, and CF is the capacitance of the floating diffusion FD (when there is additional capacitance due to the capacitive element CAP, the addition of the capacitance of the floating diffusion FD and the capacitance of the capacitive element CAP Value). The capacitance of the floating diffusion FD mentioned here includes not only the diffusion capacitance but also the wiring capacitance of the wiring connected to the floating diffusion FD. Increasing the conversion efficiency makes it possible to obtain a larger voltage from a small amount of charge. As a result, the signal-to-noise ratio (signal-to-noise ratio) at the time of signal readout can be improved, and noise in the captured image at low illuminance can be reduced.

In FIG. 7B, in the high illuminance mode, the reset transistor TR and the read transistors TE1 to TE4 are turned on when the reset signal RESET and the read signals READ1 to READ4 rise. At this time, charges accumulated in the photodiodes PD1 to PD4 are discharged. When the reset signal RESET and the read signals READ1 to READ4 fall, the reset transistor TR and the read transistors TE1 to TE4 are turned off, and charge accumulation in the photodiodes PD1 to PD4 is started (time t4).
Next, when the reset signal RESET rises, the reset transistor TR is turned on. At this time, the electric charge accumulated in the floating diffusion FD is discharged (time t5).
Next, when the read signals READ1 to READ4 rise, the read transistors TE1 to TE4 are turned on. At this time, the charges accumulated in the photodiodes PD1 to PD4 are transferred to the floating diffusion FD (time t6).
The amplification transistor TA performs a source follower operation according to the potential of the floating diffusion FD when the row selection transistor TD is turned on, so that the pixel signal Vsig corresponding to the potential of the floating diffusion FD is transmitted via the vertical signal line Vlin. Can be transmitted. At this time, the period from time t4 to time t6 is defined as the charge accumulation time HT2 of the photodiodes PD1 to PD4. The charge accumulation time HT2 can be made shorter than the charge accumulation time HT1. By reducing the charge storage time HT2, it is possible to prevent the charge from overflowing from the photodiodes PD1 to PD4 at high illuminance, and to prevent the bright part of the image from being crushed. Further, the charge accumulation binning of the pixels S1 to S4 can be performed by simultaneously reading out the charges accumulated in the photodiodes PD1 to PD4 to the floating diffusion FD.
Here, at times t5 and t6, the switching signal FDW is set to the high level, and the switching transistor TC is turned on. At this time, the capacitive element CAP is connected to the floating diffusion FD. For this reason, it is possible to increase the additional capacity of the floating diffusion FD, and it is possible to prevent the charges transferred from the photodiodes PD1 to PD4 to the floating diffusion FD from overflowing from the floating diffusion FD. As a result, the saturation level of the charge of the floating diffusion FD can be improved, and the dynamic range of the captured image at high illuminance can be improved.

In FIG. 7C, in the HDR mode, the pixels S1 to S4 are divided into two or more groups. In the example of FIG. 7C, the pixels S1 to S4 are divided into two groups, a group including the pixels S1 and S2 is a high sensitivity pixel (a pixel having high sensitivity), and a group including the pixels S3 and S4 is a low sensitivity pixel. The case where it is used as (a pixel with low sensitivity) is shown.
As the reset signal RESET and the read signals READ1 and READ2 rise, the reset transistor TR and the read transistors TE1 and TE2 are turned on. At this time, charges accumulated in the photodiodes PD1 and PD2 are discharged.
When the reset signal RESET and the read signals READ1 and READ2 fall, the reset transistor TR and the read transistors TE1 and TE2 are turned off, and charge accumulation in the photodiodes PD1 and PD2 is started (time t11).
Next, when the reset signal RESET and the read signals READ3 and READ4 rise, the reset transistor TR and the read transistors TE3 and TE4 are turned on. At this time, the charges accumulated in the photodiodes PD3 and PD4 are discharged.
When the reset signal RESET and the read signals READ3 and READ4 fall, the reset transistor TR and the read transistors TE3 and TE4 are turned off, and charge accumulation in the photodiodes PD3 and PD4 is started (time t12).
Next, when the reset signal RESET rises, the reset transistor TR is turned on. At this time, the charges accumulated in the floating diffusion FD are discharged (time t13).

Next, when the read signals READ1 and READ2 rise, the read transistors TE1 and TE2 are turned on. At this time, the charges accumulated in the photodiodes PD1 and PD2 are transferred to the floating diffusion FD (time t14).
The amplification transistor TA performs a source follower operation according to the potential of the floating diffusion FD when the row selection transistor TD is turned on, so that the pixel signal Vsig corresponding to the potential of the floating diffusion FD is transmitted via the vertical signal line Vlin. Can be transmitted. At this time, the period from time t11 to time t14 is defined as the charge accumulation time HT3 of the photodiodes PD1 and PD2. Further, by simultaneously reading the charges accumulated in the photodiodes PD1 and PD2 to the floating diffusion FD, the charge addition binning of the pixels S1 and S2 can be performed. In the charge addition binning, the charges accumulated in the pixels S1 and S2 can be added, and the sensitivity can be improved.
Next, when the reset signal RESET rises, the reset transistor TR is turned on. At this time, the electric charge accumulated in the floating diffusion FD is discharged (time t15).
Next, when the read signals READ3 and READ4 rise, the read transistors TE3 and TE4 are turned on. At this time, the charges accumulated in the photodiodes PD3 and PD4 are transferred to the floating diffusion FD (time t16).
The amplification transistor TA performs a source follower operation according to the potential of the floating diffusion FD when the row selection transistor TD is turned on, so that the pixel signal Vsig corresponding to the potential of the floating diffusion FD is transmitted via the vertical signal line Vlin. Can be transmitted. At this time, the period from time t12 to time t16 is defined as the charge accumulation time HT4 of the photodiodes PD3 and PD4. Here, by making the charge accumulation time HT4 shorter than the charge accumulation time HT3, it is possible to increase the sensitivity of the pixels S1 and S2 and decrease the sensitivity of the pixels S3 and S4. In the high-sensitivity pixels S1 and S2, dark portions of the image can be prevented from being buried in noise. In the pixels S3 and S4 that have been reduced in sensitivity, it is possible to prevent saturation of bright portions of the image. Further, by simultaneously reading out the charges accumulated in the photodiodes PD3 and PD4 to the floating diffusion FD, the charge addition binning of the pixels S3 and S4 can be performed. In the charge addition binning, the charges accumulated in the pixels S3 and S4 can be added, and the sensitivity can be improved.

Here, at time t13 and t14, the switching signal FDW can be set to a high level, and the switching transistor TC can be turned on. At this time, the capacitive element CAP is connected to the floating diffusion FD. For this reason, it is possible to increase the additional capacitance of the floating diffusion FD, and it is possible to prevent the charges transferred from the photodiodes PD1 and PD2 to the floating diffusion FD from overflowing from the floating diffusion FD. As a result, the saturation level of the charge of the floating diffusion FD can be improved, and the dynamic range of the captured image in the highly sensitive pixels S1 and S2 can be improved.
At times t15 and t16, the switching signal FDW can be set to a low level, and the switching transistor TC can be turned off. At this time, the capacitive element CAP is disconnected from the floating diffusion FD. For this reason, it is possible to reduce the additional capacity of the floating diffusion FD, and it is possible to increase the conversion efficiency when converting charges into voltage. As a result, the signal-to-noise ratio at the time of signal readout can be improved, and noise in the captured image in the pixels S3 and S4 with reduced sensitivity can be reduced.

FIG. 8 is a diagram illustrating an example of a mode determination method of the solid-state imaging device of FIG.
In FIG. 8, the drive mode setting unit 27 in FIG. 1 can generate a histogram indicating the distribution of output values from the cell P in order to determine the mode. For the generation of this histogram, the output value of the first frame in the normal mode can be used. At this time, if the output value from the cell P is large, it indicates that the subject imaged by the pixel is bright. When the output value from the cell P is small, it indicates that the subject imaged by the pixel is dark. The frequency of the output value from the cell P indicates how many cells P indicating the output value are present.
For example, the low illumination mode can be selected when the histogram H1 is obtained, the high illumination mode can be selected when the histogram H2 is obtained, and the HDR mode can be selected when the histogram H3 is obtained. . The histogram H1 is a case where the maximum value is one and the maximum value of the output value from the pixel PX does not exceed the upper limit value Th. The histogram H2 is a case where the maximum value is one and the maximum value of the output value from the cell P exceeds the upper limit value Th. The histogram H3 is a case where there are a plurality of maximum values.

  The histogram H1 is when the subject is dark. For this reason, by selecting a low illumination mode, conversion efficiency can be improved and noise can be reduced. The histogram H2 is when the subject is bright. For this reason, by selecting the high illuminance mode, the saturation level can be improved and the dynamic range can be improved. The histogram H3 is when the subject has a wide luminance range. For this reason, by selecting the HDR mode, it is possible to improve the conversion efficiency in the dark part of the subject, improve the saturation level in the bright part of the subject, and improve the dynamic range. .

FIG. 9 is a flowchart showing the operation of the solid-state imaging device of FIG.
In FIG. 9, the normal mode is set as the initial setting (S0). Then, it is determined whether or not the automatic exposure control has converged (S1). If the automatic exposure control has not converged, the pixel PX is driven in the normal mode (S2), and black level correction is performed (S3). On the other hand, if it is determined in S1 that the automatic exposure control has converged, it is determined whether or not the HDR mode is set (S7). In the HDR mode, the pixel PX is driven in the HDR mode (S8), and black level correction is performed (S3). On the other hand, if it is determined in S7 that the mode is not the HDR mode, the pixel PX is driven in the normal mode (S2), and black level correction is performed (S3).
After the black level correction, it is determined whether or not the mode is the HDR mode (S4). If the mode is not HDR mode, scratch correction is performed (S5). On the other hand, if it is determined in S4 that the HDR mode is selected, after HDR synthesis is performed (S9), scratch correction is performed (S5).
After flaw correction, digital cropping is performed (S6). Next, automatic exposure control is performed (S10), the accumulation time or analog gain is adjusted according to the luminance of the subject (S11), and the process returns to S1.
Further, after digital cropping, a histogram of output values from the pixel PX is generated (S12). And mode setting is performed based on the histogram of the output value from the cell P (S13), and it returns to S1.

(Second Embodiment)
FIG. 10 is a block diagram illustrating a schematic configuration of the solid-state imaging apparatus according to the second embodiment.
In the configuration of FIG. 10, a sensor unit B1 ′ is provided instead of the sensor unit B1 of FIG. In the sensor unit B1 ′, a pixel array unit 1 ′ and a timing control circuit 5 ′ are provided instead of the pixel array unit 1 and the timing control circuit 5, and a column ADC circuit 3 ′ and a horizontal scanning circuit 4 ′ are added. . The column ADC circuit 3 ′ and the horizontal scanning circuit 4 ′ can be provided on the side opposite to the column ADC circuit 3 and the horizontal scanning circuit 4 with respect to the pixel array unit 1 ′.

FIG. 11A is a plan view showing a configuration example of the pixel array section of FIG. 10, and FIG. 11B is a plan view showing a configuration example of four pixels of the pixel array section of FIG. 11A. .
In FIG. 11A and FIG. 11B, in the pixel array portion 1 ′, cells P ′ for accumulating photoelectrically converted charges are arranged in an array in the row direction RD and the column direction CD. Each of the cells P1 ′ to P4 ′ included in the cell P ′ is composed of four pixels S1 to S3 and S4 ′. At this time, the area of the pixel S4 ′ can be made smaller than that of each of the pixels S1 to S3. The pixels S1 to S3 and S4 ′ can be read independently of each other. Further, the accumulation times of the pixels S1 to S3 and S4 ′ can be set independently of each other. Pixel signals of the pixels S1 to S3 can be detected by the column ADC circuit 3 and transferred to the timing control circuit 5 ′ via the horizontal scanning circuit 4. The pixel signal of the pixel S4 ′ can be detected by the column ADC circuit 3 ′ and transferred to the timing control circuit 5 ′ via the horizontal scanning circuit 4 ′.
In the drive mode setting unit 27, pixel signals from the pixels S1 to S3 can be used in the normal mode and the HDR mode. The pixel S4 ′ can be used as a blinking prevention pixel caused by intermittent light emission of the light source.

FIG. 12 is a circuit diagram illustrating a configuration example of one pixel of the pixel array unit of FIG.
In FIG. 12, one cell P ′ includes photodiodes PD1 to PD3 and PD4 ′, a capacitive element CAP, row selection transistors TD1 and TD2, amplification transistors TA1 and TA2, reset transistors TR1 and TR2, read transistors TE1 to TE3, TE4 ′ and a switching transistor TC are provided.
The pixels S1 to S3 and S4 ′ include photodiodes PD1 to PD3 and PD4 ′, respectively. Here, the row selection transistor TD1, the amplification transistor TA1, the reset transistor TR1, and the switching transistor TC are shared by the photodiodes PD1 to PD3.
The row selection transistor TD2, the amplification transistor TA2, and the reset transistor TR2 are uniquely provided in the photodiode PD4 ′.
The read transistors TE1 to TE3 and TE4 ′ are provided for each of the photodiodes PD1 to PD3 and PD′4. In addition, a floating diffusion FD1 is formed as a detection node at a connection point between the amplification transistor TA1, the reset transistor TR1, the read transistors TE1 to TE3, and the switching transistor TC. A floating diffusion FD2 is formed as a detection node at a connection point between the amplification transistor TA2, the reset transistor TR2, and the read transistor TE4 ′.

The source of the read transistor TE1 is connected to the photodiode PD1, the source of the read transistor TE2 is connected to the photodiode PD2, and the source of the read transistor TE3 is connected to the photodiode PD3. The source of the read transistor TE4 ′ is connected to the photodiode PD4 ′.
The source of the reset transistor TR1 is connected to the drains of the read transistors TE1 to TE3, and the drains of the reset transistor TR1 and the amplification transistor TA1 are connected to the power supply potential VDD.
The source of the reset transistor TR2 is connected to the drain of the read transistor TE4 ′, and the drains of the reset transistor TR2 and the amplification transistor TA2 are connected to the power supply potential VDD.
The source of the row selection transistor TD1 is connected to the vertical signal line Vlin1, and the source of the row selection transistor TD2 is connected to the vertical signal line Vlin2.
The gate of the amplification transistor TA1 is connected to the drains of the read transistors TE1 to TE3. The source of the amplification transistor TA1 is connected to the drain of the row selection transistor TD1.
The gate of the amplification transistor TA2 is connected to the drain of the read transistor TE4 ′. The source of the amplification transistor TA2 is connected to the drain of the row selection transistor TD2.
The drain of the switching transistor TC is connected to the floating diffusion FD1. The source of the switching transistor TC is connected to the capacitive element CAP.
Read signals READ1 to READ4 are applied to the gates of the read transistors TE1 to TE3 and TE4 ′. A reset signal RESET1 is applied to the gate of the reset transistor TR1, and a reset signal RESET2 is applied to the gate of the reset transistor TR2. A row selection signal ADR1 is applied to the gate of the row selection transistor TD1, and a row selection signal ADR2 is applied to the gate of the row selection transistor TD2. A switching signal FDW is applied to the gate of the switching transistor TC. The pixel signal Vsig1 read from each of the photodiodes PD1 to PD3 is transmitted in the column direction CD via the vertical signal line Vlin1, and the pixel signal Vsig2 read from the photodiode PD4 ′ is transmitted via the vertical signal line Vlin2. Transmitted in the column direction CD.

FIG. 13 is a plan view showing a layout example for four pixels in the pixel array section of FIG.
In FIG. 13, the Bayer array HP is configured by arranging cells P1 ′ to P4 ′ in a square shape over 2 rows and 2 columns. Here, the photodiodes PD1 to PD3, the capacitive element CAP, the row selection transistor TD, the amplification transistor TA, the reset transistor TR, the read transistors TE1 to TE3, and the switching transistor TC can have the same layout as that in FIG.
The photodiode PD4 ′ can be made smaller than the photodiode PD4 of FIG. 4 in order to make the sensitivity smaller than that of the photodiode PD4 of FIG. A floating diffusion FD2 is disposed separately from the photodiode PD4 ′, and a read transistor TE4 ′ is disposed between the photodiode PD4 ′ and the floating diffusion FD2. Further, the row selection transistor TD2, the amplification transistor TA2, and the reset transistor TR2 can be arranged in an empty space when the photodiode PD4 ′ is reduced.

FIG. 14 is a timing chart showing an example of setting the charge accumulation time of the solid-state imaging device of FIG.
In FIG. 14, light emitting diodes may be used for lighting such as roads and signs. In the illumination of the light emitting diode, intermittent light PL may be generated depending on the driving method of the light emitting diode, and flicker may occur. The intermittent light PL is light emitted discretely at a constant time interval. In order to prevent flickering of the picked-up image due to this flicker (flashing of light), it is equal to the light emission cycle SY of the intermittent light PL (the time from when the intermittent light PL is repeatedly turned on and off until it is turned on next time). Thus, the charge accumulation time TH5 of the pixel S4 ′ can be set for each of the frames F1 and F2. By setting the charge accumulation time TH5 in this manner, the imaging in the lighting state is always realized without taking off the emission timing of the intermittent light PL, regardless of the timing at which the charge accumulation of each frame F1, F2 is started. can do.
At this time, if the light emission period SY of the intermittent light PL is long, the charge accumulation time TH5 is also increased accordingly. As the charge accumulation time TH5 increases, the amount of charge accumulated in the pixel S4 ′ also increases. Here, by reducing the sensitivity of the pixel S4 ′, the charge accumulated in the pixel S4 ′ can be less likely to be saturated. For this reason, it can prevent that the image imaged by pixel S4 'under the illumination by intermittent light PL is crushed.
When the pixel S4 ′ is not used for the detection of the intermittent light PL, and the pixel S4 ′ is used for imaging under illumination such as sunlight like the pixels S1 to S3, the sensitivity adjustment unit 22 uses the pixels S1 to S1. The digital gain of the output value of the pixel S4 ′ can be adjusted so that the sensitivity ratio matches between S3 and the pixel S4 ′. And the sensitivity of each cell P1'-P4 'can be improved by adding the output value of pixel S1-S3, and the output value of pixel S4' digitally.

(Third embodiment)
FIG. 15 is a circuit diagram illustrating a configuration example of one pixel of the solid-state imaging device according to the third embodiment.
In the configuration of FIG. 15, a coupling transistor TP is added to the configuration of FIG. The coupling transistor TP is connected between the floating diffusions FD1 and FD2. A switching signal FDW ′ is applied to the gate of the coupling transistor TP.
When the pixel S4 ′ is used for detection of the intermittent light PL in FIG. 14, the coupling transistor TP can be turned off. Then, the pixel signals from the pixels S4 ′ are individually read out, so that imaging in the lighting state can always be realized.
On the other hand, when the pixel S4 ′ is not used for the detection of the intermittent light PL in FIG. 14, the coupling transistor TP can be turned on. By reading out the pixel signal through the vertical signal line Vlin1 by the charge addition binning of the pixels S1 to S3 and S4 ′, the sensitivity can be improved. At this time, the column ADC circuit 3 'and the horizontal scanning circuit 4' can be stopped, and power saving can be achieved.

(Fourth embodiment)
FIG. 16 is a block diagram illustrating a schematic configuration of a digital camera to which the solid-state imaging device according to the fourth embodiment is applied.
In FIG. 16, the digital camera 51 includes a camera module 52 and a post-processing unit 53. The camera module 52 includes an imaging optical system 54 and a solid-state imaging device 55. The post-processing unit 53 includes an image signal processor (ISP) 56, a storage unit 57, and a display unit 58. 1 can be provided in the image signal processor 56. Further, at least a part of the configuration of the ISP 56 may be integrated into one chip together with the solid-state imaging device 55. The solid-state imaging device 55 can use the configuration shown in FIG. 1 or FIG. In the configuration of FIG. 1 or FIG. 10, the image processing unit B <b> 2 may be provided in the ISP 56.

  The imaging optical system 54 takes in the incident light LI and forms a subject image. The solid-state imaging device 55 captures a subject image. The ISP 56 performs signal processing on an image signal obtained by imaging with the solid-state imaging device 55. The storage unit 57 stores an image that has undergone signal processing in the ISP 56. The storage unit 57 outputs an image signal to the display unit 58 in accordance with a user operation or the like. The display unit 58 displays an image according to an image signal input from the ISP 56 or the storage unit 57. The display unit 58 is, for example, a liquid crystal display. In addition to the digital camera 51, the camera module 52 may be applied to an electronic device such as a camera-equipped mobile terminal or a smartphone.

(Fifth embodiment)
FIG. 17 is a cross-sectional view illustrating a schematic configuration of a camera module to which the solid-state imaging device according to the fifth embodiment is applied.
In FIG. 17, the incident light LI collected by the lens 21 proceeds to the image sensor 107 through the main mirror 101, the sub mirror 102, and the mechanical shutter 106. The camera module 100 captures a subject image with the image sensor 107. The image sensor 107 can use the sensor portions B1 and B1 ′ of FIG. 1 or FIG.
The light reflected by the sub mirror 102 travels to the autofocus (AF) sensor 103. The camera module 100 performs focus adjustment using the detection result of the AF sensor 103. The light reflected by the main mirror 101 travels to the finder 108 through the lens 104 and the prism 105.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1 pixel array section, 2 vertical scanning circuit, 3 column ADC circuit, 4 horizontal scanning circuit, 5 timing control circuit, 6 vertical OB section, 21 digital clamp section, 22 sensitivity adjustment section, 23, 25 delay element, 24 defect correction section , 26 Image cutout unit, 27 Drive mode setting unit, 28 Automatic exposure control unit, 29 Interface unit, P1 to P4 cells, S1 to S4 pixels, HP Bayer array, Gr, Gb green pixels, R red pixels, B blue pixels

Claims (5)

A cell including a first pixel and a second pixel that can be read independently of each other, and the first floating diffusion layer is shared by the first pixel and the second pixel;
A capacitive element provided in the cell;
A solid-state imaging device including a transistor provided in the cell and provided between the capacitor and the first floating diffusion layer. The cell is
A third pixel that can be read independently of the first pixel and the second pixel;
A second floating diffusion layer provided for the third pixel,
The solid-state imaging device according to claim 1, wherein the third pixel is less sensitive than the first pixel and the second pixel.   When the sensitivity is different between the first pixel and the second pixel, the output value of the first pixel and the output value of the second pixel are set so that the sensitivity ratio between the first pixel and the second pixel matches. The solid-state imaging device according to claim 1, further comprising a sensitivity adjustment unit that adjusts the gain. A pixel array section provided with a plurality of the cells;
A timing control circuit capable of separately controlling an accumulation time in the first pixel and the second pixel;
A drive mode setting unit that sets the drive mode of the cell based on the distribution of output values from the cell,
In the driving mode, at least one of the output value of the first pixel and the output value of the second pixel is selected, or the accumulation time of the first pixel and the accumulation time of the second pixel are set. The solid-state imaging device according to claim 1, wherein the transistor is switched on and off.   The drive mode setting unit sets the accumulation time of the first pixel and the accumulation time of the second pixel to maximum values and turns on the transistor when the distribution of output values from the cell exceeds an upper limit value. The solid-state imaging device according to claim 4.