JP2017055345A - Level correction device and solid state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a level correction device and a solid state image pickup device capable of reducing the detection error of an incident light volume caused by a difference in the arrangement positions of pixels on an imaging surface.SOLUTION: A level correction part 27 detects the level difference between a pixel signal of a first pixel and that of a second pixel arranged at different positions of a sensor part 22, corrects the pixel signals on the basis of the level difference, and when the level difference between the pixel signal of the first pixel and that of the second pixel is less than a restriction value, sets a correction amount so as to reduce the level difference, thereby increase the correction amount from the center of the image of the sensor part 22 toward the periphery.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a level correction device and a solid-state imaging device.

  In the solid-state imaging device, the uniformity of the layout is lost as the pixels are miniaturized, and the inclination of the incident light to the peripheral pixels is increased as the camera module is reduced in height.

JP2013-118520A

  An object of one embodiment of the present invention is to provide a level correction device and a solid-state imaging device capable of reducing the detection error of the incident light amount due to the difference in the arrangement position of the pixels on the imaging surface.

  According to an embodiment of the present invention, the difference detection unit that is disposed adjacent to each other, detects the level difference of the pixel signal between the first pixel and the second pixel having the same sensitivity and the same color, An arithmetic processing unit that performs arithmetic processing on the pixel signal based on the level difference.

FIG. 1 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment. FIG. 2 is a block diagram illustrating a configuration example of the sensor unit and the AD conversion unit in FIG. 1. FIG. 3 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device of FIG. FIG. 4 is a plan view illustrating a layout example of pixels of the solid-state imaging device of FIG. FIG. 5 is a diagram illustrating pixels used for level correction of the solid-state imaging device according to the first embodiment. FIG. 6 is a block diagram illustrating a configuration example of the level correction unit in FIG. FIG. 7 is a diagram illustrating an example of input / output characteristics of the input restriction unit in FIG. 6. FIG. 8 is a diagram illustrating a setting example of a quadratic curve coefficient used for level correction of the solid-state imaging device according to the first embodiment. FIG. 9A is a diagram illustrating an example of a level difference between subjects, and FIG. 9B is a diagram illustrating an example of a level difference between pixels. FIG. 10 is a block diagram illustrating a schematic configuration of the solid-state imaging apparatus according to the second embodiment. FIG. 11 is a diagram illustrating an example of a shading coefficient used for level correction of the solid-state imaging device of FIG. FIG. 12 is a diagram illustrating a method of setting a quadratic curve coefficient used for level correction of the solid-state imaging device according to the third embodiment. FIG. 13 is a block diagram illustrating a schematic configuration of a digital camera to which the solid-state imaging device according to the fourth embodiment is applied. FIG. 14 is a cross-sectional view illustrating a schematic configuration of a camera module to which the solid-state imaging device according to the fifth embodiment is applied.

  Exemplary embodiments of a level correction apparatus and a solid-state imaging apparatus will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

(First embodiment)
FIG. 1 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the first embodiment.
In FIG. 1, the solid-state imaging device includes a sensor unit 22, an AD conversion unit 23, and an image processing unit 24. The image processing unit 24 includes a black level correction unit 25, a scratch correction unit 26, a level correction unit 27, a noise cancellation unit 28, a shading coefficient calculation unit 29, a digital gain unit 30, and a scaler digital crop processing unit 31. . A lens 21 is provided in front of the sensor unit 22. The image processing unit 24 performs signal processing on the pixel signal output from the AD conversion unit 23. The sensor unit 22 photoelectrically converts the subject for each pixel to generate a pixel signal. The AD conversion unit 23 converts the pixel signal output from the sensor unit 22 into a digital value. The black bell correction unit 25 corrects the offset value of the sensor output based on the output from the light shielding pixel provided in the sensor unit 22.
The defect correction unit 26 corrects the pixel signal read from the pixel so that the defect of the pixel is repaired.
The level correction unit 27 detects a level difference between the pixel signal of the first pixel and the pixel signal of the second pixel arranged at different positions of the sensor unit 22, and corrects the pixel signal based on the level difference. Can do. This level difference is sometimes called step noise. At this time, the level correction unit 27 may correct the pixel signal of the second pixel based on the calculated value of the level of the pixel signal of the first pixel when the first pixel is at the position of the second pixel. Good. As the calculated value of the pixel signal level of the first pixel, an average value of the pixel signals of the first pixels arranged evenly around the second pixel can be used.
The noise cancellation unit 28 reduces the noise of the pixel signal by filtering the pixel signal read from the pixel. Scratch correction and noise cancellation processing may be correction in a two-dimensional space using a line memory, or may be one-dimensional processing that does not use a line memory. In correction on a two-dimensional space, in order to correct a pixel signal of a certain pixel, not only a pixel signal of a pixel on the same line as the pixel but also a pixel signal of a pixel on a line different from the line is referred to. Can do. At this time, in the correction in the two-dimensional space, a memory can be used to store pixel signals of pixels on a line different from the line of the pixel to be corrected. In correction by one-dimensional processing, in order to correct a pixel signal of a certain pixel, a pixel signal of a pixel on the same line as that pixel can be referred to. At this time, in the one-dimensional processing, since it is not necessary to store pixel signals of pixels on a line different from the line of the pixel to be corrected, a line memory can be eliminated.
The digital gain unit 30 performs white balance adjustment, digital gain adjustment, and optical shading correction by multiplying the sensor output by a coefficient. In the optical shading correction, the attenuation of the peripheral light amount of the sensor unit 22 due to the optical characteristics of the lens 21 can be corrected.
The shading coefficient calculation unit 29 calculates a shading coefficient Ks used for optical shading correction. The shading coefficient Ks can be changed in a parabolic shape from the image center of the sensor unit 22 toward the periphery.
The scaler digital crop processing unit 31 can adjust the image size to a predetermined size or cut out a predetermined area of the image using a linear filter.

Imaging is performed when incident light LI enters the sensor unit 22 via the lens 21. The pixel signal read from the pixel is converted into a digital value by the AD conversion unit 23. Then, after the black level correction unit 25 corrects the black level of the pixel signal, the defect correction unit 26 corrects the defect of the pixel signal. In the level correction unit 27, the level difference between the pixel signal of the first pixel and the pixel signal of the second pixel arranged at different positions of the sensor unit 22 is detected, and the pixel signal is corrected based on the level difference. . At this time, when the level difference between the pixel signal of the first pixel and the pixel signal of the second pixel is less than the limit value, the level correction unit 27 can set the correction amount so that the level difference becomes small. Further, the level correction unit 27 can increase the correction amount from the center of the image of the sensor unit 22 toward the periphery. The center of the image of the sensor unit 22 can be, for example, the intersection of the straight lines when a straight line that bisects the image of the sensor unit 22 vertically and horizontally is drawn. It may be an intersection of diagonal lines of the image of the sensor unit 22.
After noise cancellation of the pixel signal is performed in the noise cancellation unit 28, white balance adjustment, digital gain adjustment, and optical shading correction are performed in the digital gain unit 30. Thereafter, the scaler digital crop processing unit 31 adjusts the image size to fit the display size of the output medium or cuts out the image.

FIG. 2 is a block diagram illustrating a configuration example of the sensor unit and the AD conversion unit in FIG. 1.
In FIG. 2, in the pixel array section 1, pixels PX that store photoelectrically converted charges are arranged in an array in the row direction RD and the column direction CD. Further, in the pixel array unit 1, a horizontal control line Hlin for performing readout control of the pixel PX is provided in the row direction RD, and a vertical signal line Vlin for transmitting a signal read from the pixel PX is provided in the column direction CD. Is provided.

  Further, in the solid-state imaging device, the source follower operation is performed between the vertical scanning circuit 2 that scans the pixel PX to be read in the vertical direction and the pixel PX, so that the vertical signal line Vlin from the pixel PX to each column. A load circuit 3 for reading signals, a column ADC circuit 4 for detecting signal components of each pixel PX for each column by means of CDS, AD-converting and outputting, and a horizontal scanning circuit 5 for scanning a pixel PX to be read in the horizontal direction A reference voltage generation circuit 6 that outputs a reference voltage VREF to the column ADC circuit 4 and a timing control circuit 7 that controls the reading and accumulation timing of each pixel PX are provided. Note that a ramp wave can be used as the reference voltage VREF. The horizontal scanning circuit 5 can use a horizontal register that serially transfers the AD conversion values generated in parallel by the column ADC circuit 4 in the horizontal direction.

  In the pixel array unit 1, a Bayer array HP in which a set of four pixels P1 to P4 is used can be used to colorize a captured image. In this Bayer array HP, two green pixels Gr and Gb are arranged in the first diagonal direction of the Bayer array HP, and one red pixel R and one pixel are arranged in the second diagonal direction of the Bayer array HP. A blue pixel B is arranged.

Then, the vertical scanning circuit 2 scans the pixel PX in the vertical direction, so that the pixel PX is selected in the row direction RD. The load circuit 3 performs a source follower operation with the pixel PX, whereby a signal read from the pixel PX is transmitted through the vertical signal line Vlin and sent to the column ADC circuit 4. In the reference voltage generation circuit 6, a ramp wave is set as the reference voltage VREF and sent to the column ADC circuit 4. Then, in the column ADC circuit 4, a clock counting operation is performed until the signal level read from the pixel PX and the reset level coincide with the ramp wave level, and the difference between the signal level and the reset level at that time is taken. Thus, the signal component of each pixel PX is detected by the CDS and output as the output signal Sout.
Here, the level correction unit 27 in FIG. 1 is arranged at a different position of the sensor unit 22, and as the first pixel and the second pixel used for detecting the level difference of the pixel signal, the green pixels Gr of each Bayer array HP. , Gb can be used. These green pixels Gr and Gb are arranged adjacent to each other, have the same sensitivity and the same color. The level correction unit 27 detects the level difference of the pixel signals between the green pixels Gr and Gb, and if the level difference is less than the limit value, the level correction unit 27 outputs the pixel signals of the green pixels Gr and Gb so that the level difference becomes small. Arithmetic processing can be performed.

FIG. 3 is a circuit diagram illustrating a configuration example of a pixel of the solid-state imaging device of FIG.
In FIG. 3, one pixel PX is provided with photodiodes PD1 to PD4, a row selection transistor TD, an amplification transistor TA, a reset transistor TR, and readout transistors TE1 to TE4. The photodiodes PD1 to PD4 are included in the pixels P1 to P4, respectively. Here, the row selection transistor TD, the amplification transistor TA, and the reset transistor TR are shared by the photodiodes PD1 to PD4. The read transistors TE1 to TE4 are provided for the photodiodes PD1 to PD4. In addition, a floating diffusion FD is formed as a detection node at a connection point between the amplification transistor TA, the reset transistor TR, and the read transistors TE1 to TE4.

The source of the read transistor TE1 is connected to the photodiode PD1, the source of the read transistor TE2 is connected to the photodiode PD2, the source of the read transistor TE3 is connected to the photodiode PD3, and the source of the read transistor TE4 is connected to the photo diode It is connected to the diode PD4.
The source of the reset transistor TR is connected to the drains of the read transistors TE1 to TE4, and the drains of the reset transistor TR and the amplification transistor TA are connected to the power supply potential VDD.
The source of the row selection transistor TD is connected to the vertical signal line Vlin, the gate of the amplification transistor TA is connected to the drains of the read transistors TE1 to TE4, and the drain of the row selection transistor TD is connected to the source of the amplification transistor TA. ing. Read signals READ1 to READ4 are applied to the gates of the read transistors TE1 to TE4. A reset signal RESET is applied to the gate of the reset transistor TR. A row selection signal ADR is applied to the gate of the row selection transistor TD. The read signals READ1 to READ4, the reset signal RESET, and the row selection signal ADR are transmitted in the row direction RD via the horizontal control line Hlin in FIG. The pixel signal Vsig read from each of the photodiodes PD1 to PD4 is transmitted in the column direction CD through the vertical signal line Vlin in FIG.

FIG. 4 is a plan view illustrating a layout example of pixels of the solid-state imaging device of FIG. FIG. 4 shows a layout example of four cells SE1 to SE4 forming the Bayer array HP.
In FIG. 4, the cells SE1 to SE4 are configured by arranging photodiodes PD1 to PD4 in a square shape on the semiconductor substrate SB.
A row selection transistor TD, an amplification transistor TA, and a reset transistor TR are arranged between the cells SE1 to SE4. The row selection transistor TD and the amplification transistor TA are disposed adjacent to the row direction RD. The reset transistor TR is arranged in the column direction CD. A floating diffusion FD is arranged in the center of the square arrangement of the photodiodes PD1 to PD4. Read transistors TE1 to TE4 are arranged between the photodiodes PD1 to PD4 and the floating diffusion FD. The gate electrode of the amplification transistor TA and the floating diffusion FD are connected via the wiring H1, and the source of the reset transistor TR and the floating diffusion FD are connected via the wiring H2. The source of the row selection transistor TD is connected to the vertical signal line Vlin.

FIG. 5 is a diagram illustrating pixels used for level correction of the solid-state imaging device according to the first embodiment. FIG. 5 shows a case where the pixels PX forming the Bayer array HP are extracted over 3 rows × 7 columns. At this time, the four green pixels Gb arranged on the line L1 in FIG. 5 are indicated by Gb1, Gb2, Gb3, and Gb4. Three green pixels Gr arranged on the line L2 in FIG. 5 are denoted by Gr1, Gr2, and Gr3. The four green pixels Gb arranged on the line L3 in FIG. 5 are indicated by Gb5, Gb6, Gb7, and Gb8.
In FIG. 5, it is assumed that the correction target pixel is the green pixel Gr2. At this time, in order to obtain the pixel signal of the green pixel Gb at the position of the green pixel Gr2, refer to the pixel signals Sb1 to Sb8 of the eight green pixels Gb1 to Gb8 that are evenly arranged around the green pixel Gr2. Can do.
At this time, the average value AGb of the pixel signals Sb1 to Sb8 of the green pixels Gb1 to Gb8 is
AGb = (Sb1 + Sb2 + Sb3 + Sb4 +++ Sb5 + Sb6 + Sb7 + Sb8) / 8.
For the green pixel Gr2, the weighted average value AGr of the pixel signals Sr1 to Sr3 of the green pixels Gr1 to Gr3 is referenced with reference to the pixel signals Sr1 and Sr3 of the green pixels Gr1 and Gr3 that are evenly arranged around the green pixel Gr2. Can be requested. At this time, the weighted average value AGr is
AGr = (Sr1 + 2 × Sr2 + Sr3) / 4
It can be given by the formula
In order to obtain the pixel signal of the green pixel Gb at the position of the green pixel Gr2, the pixel signals Sb1 to Sb8 of the green pixels Gb1 to Gb8 arranged over 3 rows × 7 columns were used. At this time, if there is a variation in pixel signals of pixels in an area of 3 rows × 7 columns, the variation is also reflected in the average value AGb. Therefore, the green pixel Gr2 is also calculated by calculating the weighted average value AGr for the pixel signals Sr1 to Sr3 of the green pixels Gr1, Gb2, and Gr3 arranged over 3 rows × 7 columns, thereby obtaining 3 rows × 7 columns. The variation in the pixel signal of the pixels in the area can be reflected in the weighted average value AGr. At this time, the pixel signal Sr2 of the green pixel Gb2 to be corrected can be given a higher weight than the pixel signals Sr1 and Sr3 of the surrounding green pixels Gr1 and Gr3.
The level difference between the pixel signal of the green pixel Gb at the position of the green pixel Gr2 and the pixel signal of the green pixel Gr at the position of the green pixel Gr2 can be given by the difference Sb between the average value AGb and the weighted average value AGr. The pixel signal of the green pixel Gr2 can be corrected based on the difference Sb between the average value AGb and the weighted average value AGr.
At this time, there is a difference in the amount of light incident on the green pixels Gr and Gb due to the arrangement positions of the green pixels Gr and Gb according to the layout of FIG. 4, or the incident light on the peripheral pixels as the height of the camera module is reduced. When the inclination of the pixel becomes large, a level difference occurs in the pixel signals of the green pixels Gr and Gb even when imaging a uniform surface. Here, by correcting these pixel signals based on the level difference of the pixel signals between the green pixels Gr and Gb, the level difference of the pixel signals between the green pixels Gr and Gb can be eliminated, and step noise Can be reduced.

In the example of FIG. 5, in order to obtain the pixel signal of the green pixel Gb at the position of the green pixel Gr2, refer to the pixel signals of the green pixels Gb1 to Gb8 in the area of 3 rows × 7 columns centering on the green pixel Gr2. However, the pixel signals of the green pixels Gb2, Gb3, Gb6, and Gb7 in the 3 × 3 area centered on the green pixel Gr2 may be referred to.
At this time, the average value AGb of the pixel signals Sb2, Sb3, Sb6, Sb7 of the green pixels Gb2, Gb3, Gb6, Gb7 is
AGb = (Sb2 + Sb3 + Sb6 + Sb7) / 4.
For the green pixel Gr2, since there is no green pixel Gb other than the green pixel Gr2 in the 3 × 3 area centered on the green pixel Gr2, the pixel signal Sr2 of the green pixel Gr2 is used to calculate the difference Sb. Can be used.

  In the example of FIG. 5, a method of using the difference Sb between the average value AGb of the pixel signals Sb1 to Sb8 and the weighted average value AGr of the pixel signals Sr1 to Sr3 as the level difference of the pixel signal between the green pixels Gr and Gb. As described above, the difference between the pixel signal of the green pixel Gb and the pixel signal of the green pixel Gr in each Bayer array HP may be used. For example, in order to eliminate the level difference between the green pixel Gr2 and the green pixel Gb7, a difference between the pixel signal of the green pixel Gr2 and the pixel signal of the green pixel Gb7 is obtained, and the green pixel Gr2 is set so that this difference approaches zero. , Gb7 pixel signals may be corrected.

FIG. 6 is a block diagram illustrating a configuration example of the level correction unit in FIG.
In FIG. 6, the level correction unit 27 includes 1H delay SRAMs 31 and 32, G pixel filters 33 and 34, a difference detection unit 35, an input limiting unit 36, a quadratic curve coefficient calculation circuit 37, a multiplier 38, and an adder 39. Is provided. The 1H delay SRAM 31 delays the output of the defect correction unit 26 by one horizontal period (hereinafter abbreviated as 1H). One horizontal period is a time required for scanning the pixel array unit 1 by one line in the row direction RD. The 1H delay SRAM 32 delays the output of the 1H delay SRAM 31 by 1H. The G pixel filter 33 obtains a weighted average value AGr of the pixel signals Sr1 to Sr3 of the green pixels Gr1 to Gr3. The G pixel filter 34 obtains an average value AGb of the pixel signals Sb1 to Sb8 of the green pixels Gb1 to Gb8. The difference detection unit 35 obtains a difference Sb between the average value AGb and the weighted average value AGr. When the difference Sb between the average value AGb and the weighted average value AGr is equal to or greater than the limit value lim, the input limiting unit 36 limits the correction amount Hs of the pixel signal Sr of the green pixel Gr. The quadratic curve coefficient calculation circuit 37 calculates a coefficient K × Pa used to derive the correction amount Hs of the correction target pixel based on the position of the correction target pixel from the image center of the pixel array unit 1. At this time, the count values of the horizontal synchronization signal SH and the vertical synchronization signal SV can be used to derive the position of the correction target pixel. The multiplier 38 multiplies the output Sm of the input limiting unit 36 by a coefficient K × Pa. The adder 39 adds the correction amount Hs to the pixel signal Sr.

  The pixel signal Sr delayed by 1H in the 1H delay SRAM 31 is input to the G pixel filter 33. The pixel signal Sb of the green pixel Gb and the pixel signal Sb delayed by 2H in the 1H delay SRAMs 31 and 32 are input to the G pixel filter 34. At this time, the G pixel filter 33 can receive the pixel signals Sr1 to Sr3 of the line L2 in FIG. 5, and the G pixel filter 34 can receive the pixel signals Sb1 to Sb8 of the lines L1 and L3 in FIG. Then, the G pixel filter 33 calculates a weighted average value AGr from the pixel signals Sr <b> 1 to Sr <b> 3 and outputs it to the difference detection unit 35 and the input restriction unit 36. In the G pixel filter 34, the average value AGb is calculated from the pixel signals Sb <b> 1 to Sb <b> 8 and output to the difference detection unit 35. Then, the difference detection unit 35 calculates a difference Sb between the average value AGb and the weighted average value AGr and outputs the difference Sb to the input restriction unit 36. Then, the input limiting unit 36 determines whether or not the condition −lim <Sb <lim is satisfied. When the condition −lim <Sb <lim is satisfied, the output Sm of the input limiting unit 36 is set to the weighted average value AGr. Is done. On the other hand, when the condition −lim <Sb <lim is not satisfied, the output Sm of the input restriction unit 36 is set so that the correction amount Hs is restricted.

FIG. 7 is a diagram illustrating an example of input / output characteristics of the input restriction unit in FIG. 6. In the example of FIG. 7, the method of setting the output Sm of the input limiting unit 36 by the triangular limiter method is shown.
In FIG. 7, if the condition −lim <Sb <lim is satisfied, the difference Sb is output as it is from the input restriction unit 36. On the other hand, when the condition of −lim <Sb <lim is not satisfied, a value obtained by reducing the difference Sb is output from the input restriction unit 36.
For example, when the difference Sb is positive, the output Sm of the input restriction unit 36 can be given by the following expression.
If Sb <lim, Sm = Sb
If Sb = lim, then Sm = lim
If Sb <2 × lim, Sm = 2 × lim−Sb
・ Sm = 0 otherwise
The limit value lim can be set according to the weighted average value AGr. For example, the limit value lim can be set to a value of about 2% of the weighted average value AGr. In the example of FIG. 7, the method of setting the output Sm of the input restriction unit 36 by the triangle limiter method has been described. However, the output Sm of the input restriction unit 36 may be set by the clip method.
On the other hand, the quadratic curve coefficient calculation circuit 37 calculates a coefficient K × Pa based on the position of the correction target pixel from the image center of the pixel array unit 1 and outputs the coefficient K × Pa to the multiplier 38.

FIG. 8 is a diagram illustrating a setting example of a quadratic curve coefficient used for level correction of the solid-state imaging device according to the first embodiment.
In FIG. 8, it is assumed that the horizontal position and the vertical position of the image center Sc of the pixel array unit 1 are given by (Ch, Cv). At this time, a quadratic curve equation Pa corresponding to the position of the correction target pixel from the image center Sc of the pixel array unit 1 can be given by the following equation.
Pa = (H−Ch) ² + (V−Cv) ²
However, H is the count value of the horizontal synchronizing signal SH, and V is the count value of the vertical synchronizing signal SV. The coefficient K × Pa can be calculated by multiplying the quadratic curve equation Pa by a constant K. The constant K can be set so that the maximum value of the quadratic curve equation Pa is 1 or less.

  Then, the multiplier 38 multiplies the output Sm of the input limiting unit 36 by the coefficient K × Pa, thereby calculating the correction amount Hs. Then, in the adder 39, the step noise is reduced by adding the correction amount Hs to the pixel signal Sr.

FIG. 9A is a diagram illustrating an example of a level difference between subjects, and FIG. 9B is a diagram illustrating an example of a level difference between pixels.
In FIG. 9A and FIG. 9B, generally, the luminance level difference LB of the subject is larger than the inter-pixel level difference LG caused by step noise. At this time, when the incident angle of the incident light LI increases from the image center Sc of the pixel array unit 1 toward the end, the level difference LG between the pixels due to the step noise increases.
Here, by providing the input restriction unit 36, it is possible to reduce the step noise while maintaining the luminance level difference LB of the subject. Also, by providing the quadratic curve coefficient calculation circuit 37, the correction amount Hs can be increased in accordance with the increase in the step noise caused by the position of the correction target pixel from the image center Sc of the pixel array unit 1. .

(Second Embodiment)
FIG. 10 is a block diagram illustrating a schematic configuration of the solid-state imaging apparatus according to the second embodiment.
In the configuration of FIG. 10, an image processing unit 24 ′ is provided instead of the image processing unit 24 of FIG. The image processing unit 24 ′ is provided with a level correction unit 27 ′ instead of the level correction unit 27 of FIG. In the level correction unit 27 ′, the quadratic curve coefficient calculation circuit 37 of FIG. 6 is deleted. Then, the shading coefficient Ks is input from the shading coefficient calculation unit 29 to the adder 39. Then, the multiplier 38 multiplies the output Sm of the input restriction unit 36 by the shading coefficient Ks to calculate the correction amount Hs.
Here, when the optical shading increases, the incident angle of the incident light LI increases at the end of the pixel array unit 1, and the step noise at the end of the pixel array unit 1 increases. At this time, by using the shading coefficient Ks for calculation of the correction amount Hs, the correction amount Hs can be calculated so as to compensate for the optical characteristics of the lens 21, and the correction accuracy can be improved.

FIG. 11 is a diagram illustrating an example of a shading coefficient used for level correction of the solid-state imaging device of FIG.
In FIG. 11, the shading coefficient Ks increases as the position Dk of the correction target pixel moves away from the image center Sc of the pixel array unit 1. For this reason, by using the shading coefficient Ks for calculation of the correction amount Hs, the correction amount Hs can be increased according to an increase in the step noise at the end of the pixel array unit 1.

(Third embodiment)
FIG. 12 is a diagram illustrating a method of setting a quadratic curve coefficient used for level correction of the solid-state imaging device according to the third embodiment.
In FIG. 12, when calculating the quadratic curve equation Pa in FIG. 6, the pixel array unit 1 is divided. In the example of FIG. 12, the pixel array unit 1 is divided into four areas EA to ED. At this time, the quadratic curve equation Pa can be given by the following equation.
Pa = A (H−Ch) ² + B (V−Cv) ²
However, the coefficients A and B can be set separately for each of the areas EA to ED. Here, by separately setting the coefficients A and B for each of the areas EA to ED, the consistency between the quadratic curve formula Pa and the optical characteristics of the lens 21 can be improved, and the correction accuracy can be improved. it can.

(Fourth embodiment)
FIG. 13 is a block diagram illustrating a schematic configuration of a digital camera to which the solid-state imaging device according to the fourth embodiment is applied.
In FIG. 13, the digital camera 51 includes a camera module 52 and a post-processing unit 53. The camera module 52 includes an imaging optical system 54 and a solid-state imaging device 55. The post-processing unit 53 includes an image signal processor (ISP) 56, a storage unit 57, and a display unit 58. 1 can be provided in the image signal processor 56. Further, at least a part of the configuration of the ISP 56 may be integrated into one chip together with the solid-state imaging device 55. The solid-state imaging device 55 can use the configuration shown in FIG.

  The imaging optical system 54 takes in the incident light LI and forms a subject image. The solid-state imaging device 55 captures a subject image. The ISP 56 performs signal processing on an image signal obtained by imaging with the solid-state imaging device 55. The storage unit 57 stores an image that has undergone signal processing in the ISP 56. The storage unit 57 outputs an image signal to the display unit 58 in accordance with a user operation or the like. The display unit 58 displays an image according to an image signal input from the ISP 56 or the storage unit 57. The display unit 58 is, for example, a liquid crystal display. In addition to the digital camera 51, the camera module 52 may be applied to an electronic device such as a camera-equipped mobile terminal or a smartphone.

(Fifth embodiment)
FIG. 14 is a cross-sectional view illustrating a schematic configuration of a camera module to which the solid-state imaging device according to the fifth embodiment is applied.
In FIG. 14, incident light LI collected by the lens 21 travels to the image sensor 107 through the main mirror 101, the sub mirror 102, and the mechanical shutter 106. The camera module 100 captures a subject image with the image sensor 107. The imaging element 107 can use the configuration shown in FIG.
The light reflected by the sub mirror 102 travels to the autofocus (AF) sensor 103. The camera module 100 performs focus adjustment using the detection result of the AF sensor 103. The light reflected by the main mirror 101 travels to the finder 108 through the lens 104 and the prism 105.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1 pixel array unit, 2 vertical scanning circuit, 3 load circuit, 4 column ADC circuit, 5 horizontal scanning circuit, 6 reference voltage generating circuit, 7 timing control circuit, Vlin vertical signal line, Hlin horizontal control line, PX, P1 to P4 Pixel, HP Bayer array, Gr, Gb Green pixel, R Red pixel, B Blue pixel

Claims (5)

A difference detection unit that is arranged adjacent to each other, detects the level difference of the pixel signals between the first pixel and the second pixel having the same sensitivity and the same color;
A level correction apparatus comprising: an arithmetic processing unit that performs arithmetic processing on the pixel signal so that the level difference is reduced when the level difference is less than a limit value.   2. The level correction apparatus according to claim 1, wherein the first pixel is a first green pixel in a Bayer array, and the second pixel is a second green pixel in the Bayer array. A pixel array unit in which pixels are arranged in a row direction and a column direction;
Based on the calculated value of the level of the pixel signal of the first pixel when the first pixel is located at the position of the second pixel in the first pixel and the second pixel arranged at different positions in the pixel array unit. And a level correction unit that corrects the pixel signal of the second pixel.   4. The solid-state imaging device according to claim 3, wherein the calculated value of the pixel signal level of the first pixel is an average value of the pixel signals of the first pixels arranged evenly around the second pixel. The level correction unit sets the correction amount of the pixel signal based on the level difference when the level difference between the pixel signal of the first pixel and the pixel signal of the second pixel is less than a limit value, When the level difference is greater than or equal to a limit value, an input limiter that limits the correction amount of the pixel signal;
5. The solid-state imaging device according to claim 3, further comprising: a coefficient calculation unit that calculates a coefficient used for deriving the correction amount based on a position of the first pixel from an image center of the pixel array unit.

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