JP2017055269A - Information processing apparatus and information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity of data after compression.SOLUTION: An information processing apparatus compressing input data comprises: a code generation part that changes a Hadamard code to generate a changed code; a conversion part that converts the input data on the basis of the changed code to generate first data; a calculation part that normalizes the first data and converts the first data into integers to generate second data; and coding part that encodes the second data to generate compressed data.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an information processing apparatus and an information processing system.

  2. Description of the Related Art Conventionally, a method for protecting analog data indicating multimedia information such as audio or moving images from being easily seen by others is known.

  For example, in analog data encoding, a method is known in which encoding can be realized with a simple configuration and high quality can be ensured by executing multidimensional orthogonal transform using a multidimensional orthogonal sequence. Specifically, first, a random number is generated, and an n-dimensional orthogonal sequence is generated using the generated random number. Next, a method for generating converted data by encrypting data by orthogonal transform using an n-dimensional orthogonal sequence is known (for example, Patent Document 1).

JP 2005-333386 A

  However, in the conventional method, in processing such as orthogonal transformation using an n-dimensional orthogonal sequence, the appearance density distribution of post-conversion data has a property that depends on the data before conversion, and thus data or processing that is overhead occurs. There are many cases. For example, in the process of constructing a Huffman tree for Huffman conversion by analyzing input data, data indicating a Huffman tree necessary for decompression is required as overhead. Therefore, the data capacity after compression may increase due to overhead or the like.

  One aspect of the present invention aims to reduce the data capacity after compression.

  In one aspect, an information processing apparatus that compresses input data includes: a code generation unit that changes a Hadamard code to generate a change code; and a conversion that converts the input data based on the change code to generate first data A calculation unit that generates the second data by normalizing and integerizing the first data, and an encoding unit that generates the compressed data by encoding the second data.

  Data capacity after compression can be reduced.

It is a block diagram explaining an example of the hardware constitutions of the embedded system which concerns on one Embodiment of this invention. It is a flowchart explaining an example of the process which performs the compression which concerns on one Embodiment of this invention. It is a schematic diagram which shows an example of the input data which concern on one Embodiment of this invention. It is a schematic diagram which shows the example of a change which rearranges the line which concerns on one Embodiment of this invention. It is a schematic diagram which shows the example of a change which rearranges the row | line | column which concerns on one Embodiment of this invention. It is a mimetic diagram showing an example of the 1st data concerning one embodiment of the present invention. It is a schematic diagram which shows an example of the 2nd data which concerns on one Embodiment of this invention. It is a schematic diagram which shows an example of the compressed data which concerns on one Embodiment of this invention. It is a table | surface which shows an example of the intensity | strength of encryption by the rearrangement which concerns on one Embodiment of this invention. It is a flowchart explaining an example of the process which performs the decompression | decompression which concerns on one Embodiment of this invention. It is a schematic diagram which shows an example of the normalization data which concern on one Embodiment of this invention. It is a mimetic diagram showing an example of the 3rd data concerning one embodiment of the present invention. It is a figure which shows an example of the relationship between the conversion based on the change code which concerns on one Embodiment of this invention, and the reverse conversion based on a change code. It is a schematic diagram which shows an example of the decoding data based on one Embodiment of this invention. It is a figure which shows an example of the probability density of the error which concerns on one Embodiment of this invention. It is a schematic diagram which shows an example of the interleaving which concerns on one Embodiment of this invention. It is a schematic diagram which shows the example which adds a guard bit in the coupling | bonding which concerns on one Embodiment of this invention. It is a schematic diagram which shows an example of the concatenation which concerns on one Embodiment of this invention. It is a schematic diagram which shows another example which adds a guard bit in the coupling | bonding which concerns on one Embodiment of this invention. It is a table | surface which shows an example of the conditions which narrow down the exact solution which concerns on one Embodiment of this invention. It is a schematic diagram which shows an example of the conditions based on the change of the guard bit which concerns on one Embodiment of this invention. It is a table | surface which shows an example of the conditions based on the change of the guard bit which concerns on one Embodiment of this invention. It is a functional block diagram which shows an example of a function structure of the information processing system which concerns on one Embodiment of this invention.

  The first information processing apparatus is, for example, an embedded system. The embedded system is a system for realizing a specific function that is built in an industrial device or a home appliance. The information processing apparatus may be a PC (Personal Computer) or the like. Hereinafter, an embodiment of the present invention will be described based on an example in which the first information processing apparatus is an embedded system, based on the drawings.

1. 1. Hardware configuration example of embedded system 2. Processing example of compression and decompression Functional configuration example of information processing system << 1. Example of hardware configuration of embedded system >>
FIG. 1 is a block diagram illustrating an example of a hardware configuration of an embedded system according to an embodiment of the present invention. As illustrated, the embedded system 1 includes an arithmetic device HW1, a storage device HW2, and an I / F (interface) HW3.

  The arithmetic device HW1 is a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). The arithmetic device HW1 is a control device that controls the hardware that the embedded system 1 has, and an arithmetic device that performs calculations and data processing for realizing all or part of the processing performed by the embedded system 1. Furthermore, the arithmetic unit HW1 incorporates a storage device such as a RAM (Random Access Memory) HW10 and a ROM (Read-Only Memory) HW11, as shown in the figure, and realizes a storage area.

  The RAM HW 10 is a storage device used for developing and storing programs, setting values, data, or the like used by the arithmetic device HW 1 or the like.

  The ROMHW11 is a storage device that stores programs, setting values, data, and the like used by the arithmetic device HW1 and the like.

  The storage device HW2 is a so-called memory or the like. The storage device HW2 is a storage device that stores programs, setting values, data, and the like used by the embedded system 1. Note that the storage device HW2 may include an auxiliary storage device or the like.

  The I / FHW 3 is an interface for inputting and outputting data and the like to the embedded system 1. The I / FHW 3 is realized by a bus, a connector, a cable, a driver, and the like.

  Note that the hardware configuration of the embedded system 1 is not limited to the illustrated configuration. For example, the embedded system 1 may not have the storage device HW2. The embedded system 1 may further include an auxiliary device such as an arithmetic device outside or inside.

<< 2. Example of compression and decompression processing >>
<< Compression example >>
FIG. 2 is a flowchart for explaining an example of processing for performing compression according to an embodiment of the present invention.

<< Input Example of Input Data (Step S0101) >>
In step S0101, the embedded system inputs data. The input data, that is, the data to be compressed is hereinafter referred to as “input data”.

FIG. 3 is a schematic diagram illustrating an example of input data according to an embodiment of the present invention. Hereinafter, a case where the input data a is the illustrated data will be described as an example. As shown in the figure, it is assumed that the input data a is composed of N pieces and ²ⁿ pieces of data. Further, it is assumed that data a _{0 to} a _N-1 (hereinafter sometimes referred to as “a _i ”) included in the input data a are x-bit data. That is, the input data a that is the data before compression can be expressed by the following equation (1).

According to the above equation (1), for example, if the input data a is 8-bit data, that is, x = 8, the data a _i included in the input data a is an integer up to “255”.

<< Example in which Hadamard Code is Changed to Generate Changed Code (Step S0102) >>
Returning to FIG. 2, in step S0102, the embedded system changes the Hadamard code to generate a changed code. Specifically, in step S0102, the embedded system rearranges the rows, columns, or both of the Hadamard matrix [H], which is an example of the Hadamard code, to generate a modified matrix [H] ′. The change matrix [H] ′ is an example of a change code.

  Hereinafter, the case where the Hadamard matrix [H] has the matrix and property shown in the following formula (2) will be described as an example.

As shown in the above equation (2), the Hadamard matrix [H] is composed of N rows and N columns, and each N × N component is “1” or “−1”. It is one of the matrices. That is, the Hadamard matrix [H] is a two-dimensional matrix or the like. The Hadamard code may have another dimension that is higher than two dimensions. Further, as shown in the above equation (2), the Hadamard matrix [H] is a matrix that is N times the unit matrix when multiplied by the transposed matrix [H] ^T.

  Further, the Hadamard matrix [H] can be expressed by, for example, the following equation (3) when expressed in the Sylvester form. The Hadamard matrix [H] may be an M-sequence type or the like.

  For example, the embedded system rearranges the rows and columns of the Hadamard matrix [H] shown in the above equation (2) to generate the modified matrix [H] ′.

FIG. 4 is a schematic diagram illustrating a modification example in which rows are rearranged according to an embodiment of the present invention. As shown, sorting line, and x _i-th row of the Hadamard matrix [H], a modification of rearranging the i-th row of the row.

FIG. 5 is a schematic diagram illustrating a modification example in which the columns are rearranged according to the embodiment of the present invention. As shown, sorting columns, and y _j-th column of the columns of the Hadamard matrix [H], a modified example of rearranging the columns in the j-th column.

  The relationship between the matrix before the change and the matrix after the change in which the changes in FIGS. 4 and 5 are performed, that is, the relationship between the Hadamard matrix [H] and the change matrix [H] ′ is expressed by the following equation (4): It can be shown as

  The change may be a process of multiplying the Hadamard code by a diagonal code such as a diagonal matrix. That is, the change code may be a diagonal matrix multiplied by a Hadamard matrix. Hereinafter, a diagonal matrix is a diagonal matrix, and a modification matrix that is an example of a modification code to be generated is referred to as a second modification matrix [H] ″. In this example, the relationship between the matrix before change and the matrix after change obtained by multiplying the matrix before change by a diagonal matrix, that is, Hadamard matrix [H] and second change matrix [H ] '' Can be expressed by the following equation (5).

  The embedded system may generate a change code that combines a change matrix obtained by rearranging a Hadamard code row or a Hadamard code column and a diagonal matrix multiplied by the Hadamard code. That is, the embedded system may perform the conversion by combining the rearranged change matrix and the multiplication by the diagonal matrix in the subsequent processing.

  Note that, for example, a parameter for generating a change code is generated from the serial number of each information processing apparatus, and the change code determines a row or a column to be rearranged based on the generated parameter. The value of each coefficient included in the diagonal matrix is determined or generated. Therefore, if this parameter is shared between the transmission side and the reception side, the change code can be specified, so the information processing system can perform the same process as the key sharing in the encryption.

<< Conversion Example Based on Change Code (Step S0103) >>
Returning to FIG. 2, in step S0103, the embedded system converts the input data based on the change code. Specifically, in step S0103, the input data a (see FIG. 3) input in step S0101 is converted based on the change code generated in step S0102, and the data (hereinafter referred to as “first data”) is converted by the conversion. .) Is generated.

FIG. 6 is a schematic diagram illustrating an example of first data according to an embodiment of the present invention. Hereinafter, the case where the first data b is the illustrated data will be described as an example. In this example, it is assumed that the data a _i included in the input data a is converted, and the first data b is composed of N pieces of data that have been converted based on the change code as illustrated.

  If the change code is a change matrix [H] ′, the conversion in step S0103, that is, the relationship between the input data a and the first data b indicating before and after the conversion, can be expressed as the following equation (6). .

  Further, the first data b can be expressed by the following equation (7).

Of the data b _{i included} in the first data b, b ₀ may have a range of possible values and a probability density different from those of other b _{i (i ≠ 0)} . Incidentally, _{b 0} is can show as follows (8).

As shown in the above equation (3), the first row of the Hadamard matrix [H] is “1”, so the coefficient related to b ₀ is used in the case of rearrangement or the like in which the first row is not subject to rearrangement. May all be positive. Therefore, b ₀ is different from other b _{i (i ≠ 0) in} the range of possible values and the probability density, and may not be collected in “0”. On the other hand, in order to match b ₀ with other b _{i (i ≠ 0)} , a calculation of subtracting N (2 ^x −1) may be performed on b ₀ . Since the value used for this calculation is an eigenvalue determined based on N, the embedded system can perform the calculation by inputting the eigenvalue in advance. Note that a calculation for addition may be performed during the inverse transformation. Alternatively, b _i may be a two's complement and the data a _{i included} in the input data a may be expressed by the following equation (9).

Further, the embedded system may compress the value corresponding to the first row of the Hadamard matrix [H], that is, the value based on the coefficient related to b ₀ by another compression method.

<< Normalization and Integer Example (Step S0104) >>
Returning to FIG. 2, in step S0104, the embedded system normalizes and integerizes the first data. Specifically, in step S0104, the first data b (see FIG. 6) generated in step S0103 is normalized and integerized, and the data (hereinafter referred to as “second data”) is obtained by normalization and integerization. Suppose that it is generated.

FIG. 7 is a schematic diagram showing an example of second data according to an embodiment of the present invention. Hereinafter, the case where the second data c is illustrated is described as an example. In this example, the data b _{i included in} the first data b shown in FIG. 6 is normalized and integerized, and the second data c is composed of N data normalized and integerized as shown in the figure. Suppose that

  Normalization and integerization are realized by, for example, calculation according to the following equation (10).

In the above equation (10), the embedded system can perform rounding by calculating “+0.5”. Further, in the above equation (10), the embedded system can remove the lower bits by calculating “2 ^w / N”.

Note that in the calculation by the expression (10), N> is preferably a ^{2 w.} For example, when N = ^2w , truncation due to normalization and integerization does not occur, and the portion where data is compressed decreases. On the other hand, if N> ^2w , the data can be compressed by normalization and integerization, so that the data can be further compressed, and the embedded system can make the data after compression smaller than the data before compression.

<< Encoding Example (Step S0105) >>
Returning to FIG. 2, in step S0105, the embedded system encodes the second data. Specifically, in step S0105, embedded systems, respectively encoded based data _{c i} second data c (see FIG. 7) has generated in step S0104 to the Huffman code (huffman coding) or the like, encoding To generate data (hereinafter referred to as “compressed data”).

FIG. 8 is a schematic diagram illustrating an example of compressed data according to an embodiment of the present invention. Hereinafter, a case where the compressed data d is the illustrated data will be described as an example. In this example, the data c _i with the second data c are respectively coded as shown in Figure 7, the compressed data d, as shown, and consists of N data encoded.

The probability density of the data c _{i included in} the second data c can be represented by a normal distribution whose mean and variance are determined by “w”, “x”, and “N” shown in the above formulas (1) and (10). Therefore, when “N” becomes a large value, the data c _i included in the second data c is collected at “0”. That is, the data c _i included in the second data c has a high probability of being “0”.

Therefore, the data c _i included in the second data c is gathered at “0”, that is, “0” increases. Therefore, when data based on the Huffman code is applied to data having many values, compression is performed at a high compression rate, so that the embedded system can reduce the data capacity to be transmitted.

  Further, since the normal distribution is determined by “w”, “x”, and “N”, if each value indicating “w”, “x”, and “N” is shared between the transmission side and the reception side, header data and the like are It becomes unnecessary, and the embedded system can reduce the data capacity to be transmitted.

  Furthermore, when data is converted based on a change code such as a change matrix, the data is obfuscated as in encryption. That is, if it is unclear what changes have been made, the data is not easily restored to the data before compression even if the data is decompressed. Therefore, by using the data related to the change code as a key, the embedded system can obfuscate the data to be transmitted by conversion based on the change code. In this way, the embedded system can improve the security of data to be transmitted. In other words, the embedded system can reduce the data capacity to be transmitted by compressing the data by the conversion based on the change code, and can improve the security of the data to be transmitted.

  In an N × N matrix, the sort type is N for row sorting! Similarly, the column rearrangement is N! Therefore, in the conversion based on the change code that combines these, the key length can be expressed for N as shown in the following equation (11).

  FIG. 9 is a table showing an example of encryption strength by rearrangement according to an embodiment of the present invention. Specifically, when N indicating the number of rows and columns of the matrix is as shown in FIG. 9, the encryption strength is as shown in the figure based on the above equation (11).

Also, assuming that the diagonal code as in the above equation (5) is used, there are 2 ^N combinations of diagonal codes. Therefore, in the conversion based on the diagonal code, the key length is N with respect to N. A bit.

  Furthermore, when the conversion is performed by combining rearrangement and multiplication using diagonal codes, the embedded system can perform stronger encryption on the data.

  Specifically, if “N = 16”, the encryption strength by rearrangement is “88.5 bits” from FIG. On the other hand, the strength of encryption by multiplication using diagonal codes is “16 bits”. Therefore, the encryption strength when these are combined is “88.5 bits + 16 bits = 104.5 bits”. When rearrangement and multiplication using diagonal codes are combined, the embedded system is more High strength encryption can be performed.

  If N is set to a large value such as “64”, the embedded system can reduce so-called key collision.

<< Example of thawing >>
FIG. 10 is a flowchart for explaining an example of processing for performing decompression according to an embodiment of the present invention. For example, the data compressed and generated by the process shown in FIG. 2 is the compressed data d shown in FIG. Hereinafter, an example where the decompression target is the compressed data d will be described.

<< Example of Input of Compressed Data (Step S0201) >>
In step S0201, the information processing apparatus inputs the compressed data d.

<< Decoding Example (Step S0202) >>
In step S0202, the information processing apparatus decrypts the compressed data d. That is, the decoding in step S0202 is, for example, an inverse transformation of the encoding in step S0105 shown in FIG. In this example, encoding and decoding based on the Huffman code is a reversible transformation. Therefore, when the second data c (see FIG. 7) is encoded by the Huffman code and the compressed data d is generated, when the compressed data d is decoded, the second data c is decoded. c can be generated.

  Since the transform and inverse transform based on the Huffman code are reversible transforms, the information processing apparatus can generate the second data c having no error from the compressed data d by decoding.

<< Normalization Example (Step S0203) >>
In step S0203, the information processing apparatus normalizes the second data. Specifically, in step S0203, the second data c (see FIG. 7) generated in step S0202 is normalized, and data (hereinafter referred to as “normalized data”) is generated by normalization.

FIG. 11 is a schematic diagram showing an example of normalized data according to an embodiment of the present invention. Hereinafter, the case where the normalized data b ′ is the illustrated data will be described as an example. In this example, the data c _i with the second data c shown in FIG. 7 is normalized respectively, each data constituting the normalized data b 'is generated. That is, it is assumed that the normalized data b ′ is composed of normalized N pieces of data as illustrated.

  Normalization is realized, for example, by calculation according to the following equation (12).

As shown in the above equation (12), in step S0203, the coefficient “2 ^w / N used in the equation (10) used in the processing shown in FIG. 2 is added to each data c _i of the second data c. Multiplication by the reciprocal number of “”, each data b ′ _i of the normalized data b ′ is calculated. Further, normalization, the respective data c _i with the second data c, may also perform the division by a factor of "2 ^{w /} N" used in the above (10).

<< Conversion Example Based on Change Code (Step S0204) >>
Returning to FIG. 10, in step S0204, the information processing apparatus converts the normalized data based on the change code. Specifically, in step S0204, the normalized data b ′ (see FIG. 11) generated in step S0203 is converted based on the change code shown in the above equation (4) or the above equation (5). To generate data (hereinafter referred to as “third data”).

FIG. 12 is a schematic diagram illustrating an example of third data according to an embodiment of the present invention. Hereinafter, the case where the third data a ′ is the illustrated data will be described as an example. In this example, when data b ′ _i included in the normalized data b ′ is converted based on the change code, each data constituting the third data a ′ is generated. That is, it is assumed that the third data a ′ is composed of N pieces of data that have been converted based on the change code, as illustrated.

  FIG. 13 is a diagram illustrating an example of a relationship between conversion based on a change code and inverse conversion based on the change code according to an embodiment of the present invention. That is, FIG. 13 shows the relationship between the conversion in step S0103 shown in FIG. 2 and the conversion in step S0204 shown in FIG. As shown in the drawing, the data converted in the compression can be returned to the data before the conversion when the inverse conversion is performed in the decompression.

<< Example of integerization (step S0205) >>
Returning to FIG. 10, in step S0205, the information processing apparatus converts the third data into an integer. Specifically, in step S0205, the information processing apparatus converts the third data a ′ generated in step S0204 to an integer by rounding off or the like, and generates data (hereinafter referred to as “decoded data”) by integerization.

  FIG. 14 is a schematic diagram showing an example of decoded data according to an embodiment of the present invention. Hereinafter, a case where the decoded data a ″ is the illustrated data will be described as an example. In this example, when the data included in the third data a ′ is normalized, each data constituting the decoded data a ″ is generated. That is, it is assumed that the decoded data a ″ is composed of N normalized data as illustrated.

  As described above, when the compressed data that is compressed and encrypted by the process shown in FIG. 2 is decompressed and decrypted by the process shown in FIG. 10, the receiver may use the plaintext data before compression and encryption. it can. Therefore, when data is transmitted and received, if the data is compressed on the transmission side and the data is decompressed on the reception side, the information processing apparatus may reduce the data capacity to transmit and receive and the data capacity to store the data. it can. In addition, the information processing apparatus can improve the security of data to be transmitted and received by encryption.

  Further, when the information processing apparatus realizes compression and decompression respectively by conversion based on the changed code obtained by changing the Hadamard code, compression or decompression can be realized by calculation such as shift operation, so that calculation such as division can be reduced. As a result, the information processing apparatus can reduce the load or the like related to the calculation in data compression or decompression.

  In an information processing system having a first information processing device such as an embedded system and a second information processing device such as a server, the information processing device that performs compression by the processing shown in FIG. It becomes a processing device. On the other hand, the information processing apparatus that performs decompression, that is, the reception side becomes the second information processing apparatus by the processing shown in FIG.

<< About error >>
In the following, each data related to compression is compared with each data related to decompression, and an error occurring in each processing of compression and decompression will be described.

  First, encoding based on the Huffman code (step S0105 shown in FIG. 2) and decoding based on the Huffman code (step S0202 shown in FIG. 10) will be described. In this case, the encoding based on the Huffman code and the decoding based on the Huffman code are a relationship between conversion and inverse conversion. In this relationship, since the encoding and decoding using the Huffman code is a reversible transformation, when the encoded data is decoded, the data generated by the decoding is encoded. Compared to the previous data, there is no error due to encoding and decoding.

  That is, in FIGS. 2 and 10, the second data c (see FIG. 7) before being encoded in step S0105 shown in FIG. 2 and the compressed data d (see FIG. 8) after being encoded are shown in FIG. There is no error in the second data c after being decoded in step S0202 shown in FIG. On the other hand, since the second data c converted from the first data b (see FIG. 6) includes an error due to normalization in compression, the error generated in the second data c after decoding is “− 0.5 "or more and less than" +0.5 "are included.

  Next, the first data b (see FIG. 6) before normalization and integerization (step S0104 shown in FIG. 2) in compression and the normalization after normalization (step S0203 shown in FIG. 10) in decompression The data b ′ (see FIG. 11) is compared. That is, the error between the first data b and the normalized data b ′ can be expressed by the following equation (13).

  Subsequently, the input data a (see FIG. 3) before conversion based on the change code in compression (step S0103 shown in FIG. 2) and the conversion based on the change code in decompression (step S0204 shown in FIG. 10). The third data a ′ (see FIG. 12) is compared. That is, the error between the input data a and the third data a ′ is generated from the normalized data b ′ including the error shown in the above equation (13) in the decompression, so that the following (14 ).

  Specifically, the error between the input data “a” and the third data “a ′” is calculated as shown in the following equation (15), considering the worst value.

  From the above equation (15), for example, in 8-bit data (x = 8), the worst value of error is “1.5” for 256 gradations. However, in the calculation, the worst value is the above equation (15), but in actuality, in the conversion based on the change code, the values of “+” and “−” are added to cancel out the error. Can often be made smaller than the worst value.

FIG. 15 is a diagram illustrating an example of error probability density according to an embodiment of the present invention. As shown in the figure, when the error between the input data a and the third data a ′ is a probability density function P (a ′), the probability density function P (a ′) can be represented by a normal distribution. This normal distribution is distributed in a range of “(N / 2 ^w ) −1” with “a _i ” as an average.

<< Examples of interleaving and concatenation >>
The compression ratio and the error are determined by “w” and “N”, and are expressed by the above equation (15). Therefore, when x becomes a large value, the influence of the error becomes relatively small. For example, in the case of 8-bit data (x = 8), considering the worst value, the influence of the error is “1.5 / 256”. On the other hand, in the case of 16-bit data (x = 16), the influence of the error is “1.5 / 65536”. Therefore, it can be said that the effect of error is smaller in the case of 16-bit data.

  Therefore, when there are a plurality of data to be compressed, it is desirable to combine the plurality of data to generate input data in which x is a large value. Specifically, it is desirable to combine a plurality of data by interleaving or the like to generate input data a (see FIG. 3).

  FIG. 16 is a schematic diagram illustrating an example of interleaving according to an embodiment of the present invention. Hereinafter, as illustrated, an example in which two 8-bit data (x = 8) is a plurality of data will be described, and in the description, the plurality of data are respectively referred to as first basic data s1 and second basic data s2. . That is, in the following description, an example in which the first basic data s1 and the second basic data s2 are interleaved will be described.

For example, as shown, first basic data s1 has _{"s 2i, 0"} through _{"s 2i, 7"} and the bit data of, or _{"s 2i + 1, 0"} included in the second basic data s2 _{"s 2i + 1 , 7} "are alternately combined with each other to generate 16-bit second input data a2. Since the second input data a2 is data obtained by combining two pieces of 8-bit data, it is 16-bit data. When the second input data a2 generated in this way is handled as input data, the input data changes from 8-bit data to 16-bit data. For this reason, since the input data has a large value, the embedded system can reduce the influence of the error by interleaving.

  Note that interleaving is not limited to combining two pieces of data or generating 16-bit data. For example, the interleaving may be a process of generating data having a larger value such as 32-bit data or 64-bit data. Further, interleaving may be a process of combining three or more data. Further, the interleaving may be a process of further interleaving the interleaved data to generate data having a larger value.

  Also, so-called guard bits may be added for interleaving or the like.

  FIG. 17 is a schematic diagram illustrating an example in which guard bits are added in the combination according to the embodiment of the present invention. Hereinafter, an example in which two guard bits GB are further added in the interleaving shown in FIG. 16 will be described. FIG. 17 is different from FIG. 16 in that a 2-bit guard bit GB is added and the generated third input data is 18 bits. Note that the guard bit GB is, for example, 2-bit data in which the upper side is “0” and the lower side is “1” as illustrated. Each data can be expressed by the following equation (16).

  Further, the position where the guard bit GB is added is set by “w” and “N”, for example. Specifically, as shown in the above equation (15), if (w, N) = (0, 8), the error is “± 3.5” in terms of the worst value. , An error of “−4 to 3” may occur. In this case, when the guard bit GB is added to the position shown in the figure, the guard bit absorbs the carry or carry by the error. Therefore, the error is higher on the upper side than the position where the guard bit GB is added. The influence of will disappear. In other words, when the guard bit GB is added, the embedded system can prevent an error occurring on the lower side from the position where the guard bit GB is added from affecting the upper side.

Since the error between the input data a and the third data a ′ is as in the above equation (14), if the guard bit GB is added at the position shown in the figure, it occurs in the third data a ′. It can be limited to the range of “a _{i, 2} ”, “a _{i, 1} ”, and “a _{i, 0} ” where the influence of the error is on the lower side. For example, in the range of “a _{i, 2} ”, “a _{i, 1} ” and “a _{i, 0} ”, even if a carry error, that is, an error of “+1” with respect to “111” occurs, When the guard bit GB is added, the guard bit GB “01” becomes “10”, and the embedded system can eliminate the effect of adding a carry error to “a _{i, 3} ”. .

Further, even if a carry error, that is, an error of “−1” with respect to “000” occurs in the range of “a _{i, 2} ”, “a _{i, 1} ”, and “a _{i, 0} ”. When the guard bit GB is added, the guard bit GB “01” becomes “00”, and the embedded system may eliminate the influence of a carry error being subtracted from “a _{i, 3} ”. it can.

  The guard bit GB is not limited to “01” as illustrated, and may be “10”, for example. Thus, the guard bit GB may be 3 bits or more, but is preferably 2 bits. If the guard bit GB is 2 bits such as “01” or “10”, an error due to a carry or carry can be prevented from being affected. Further, since the 2-bit guard bit GB has the smallest data capacity that can eliminate the influence of errors due to carry-down or carry-over, when the guard bit GB is 2 bits, the embedded system has a small data capacity. Can eliminate the influence of errors.

  Further, the combination is not limited to interleaving. For example, the bond may be a concatenation.

  FIG. 18 is a schematic diagram illustrating an example of concatenation according to an embodiment of the present invention. Hereinafter, an example in which the first basic data s1 and the second basic data s2, which are examples of two 8-bit data similar to those in FIG. 16, are concatenated will be described. For example, as shown in the figure, the concatenation uses the first basic data s1 as the higher-order 8-bit data, and the lower-order data is combined with the 8-bit data of the second basic data s2 as the fourth input. This is processing for generating data a4. The upper and lower levels to be combined may be reversed. The fourth input data a4 is 16-bit data because it is data obtained by combining two 8-bit data. When the fourth input data a4 generated in this way is handled as input data, the input data changes from 8-bit data to 16-bit data. For this reason, since the input data becomes a large value, the embedded system can reduce the influence of the error by concatenation.

  Similarly to interleaving, guard bits may be added in concatenation.

FIG. 19 is a schematic diagram showing another example of adding guard bits in the combination according to the embodiment of the present invention. For example, as shown in the figure, the guard bit GB may be added to the data generated by the concatenation shown in FIG. 18 similarly to FIG. 17, and the fifth input data a5 may be generated by the concatenation. . As shown in the drawing, the fifth input data a5 is 18-bit data because a 2-bit guard bit is added. As described above, when the guard bit GB is added in the concatenation as well as in the case of interleaving, the embedded system adds a carry or carry error to the upper bits from “a _{i, 3} ”. The influence of can be eliminated.

  Further, the concatenation may be a process of generating data having a larger value, such as 32-bit data or 64-bit data, or a process of combining three or more data, like interleaving. Further, the concatenation may be a process of further concatenating the concatenated data to generate data having a larger value.

<< Example of error correction >>
In embodiments, in order to reduce the influence of the generated error, the correction of the correction value e _i is applied may be performed. First, the error is the difference between the input data a (see FIG. 3) before the process shown in FIG. 2 and the third data a ′ (see FIG. 12) after the process shown in FIG. | A _i '−a _i | The correction value e _i for reducing this error is added to the normalized data b ′ (see FIG. 11) in the process shown in FIG. 10, for example. That is, when “b ′ + e _i ” is set, correction for reducing the error can be performed.

Correction value _{e i} is can show as follows (17).

Also, | a _i '-a _i |, which is an error, can be shown separately from | a _i ' -a _i | = _pi + q _i . In this case, it is assumed that the error is the integer part p _i and the decimal part q _i . The decimal part q _i is (−0.5 <q _i <0.5). Next, when the integer part p _i and the decimal part q _i are used, the error can be expressed by the following equation (18) from the above equation (17).

In many cases, it is mainly the fractional part q _i that makes it clear whether or not it is an error. This is because when the original data (data before compression) is an integer, if the data includes the decimal part q _i after decompression, it can be said that there is an error of at least the decimal part q _i. . In order to simplify the correction for the decimal part q _i , the correction value e _i is expressed by the following equation (19) based on the above equation (18).

  Next, conditions for narrowing down the exact solution will be described.

FIG. 20 is a table showing an example of conditions for narrowing down an exact solution according to an embodiment of the present invention. For example, when a combination of integer parts p _i satisfying the three conditions shown in the figure is searched, an exact solution can be obtained.

  In the illustrated (Condition 1), the search is preferably performed in order from the smallest absolute value. Since the error probability density is a normal distribution with an average of “0”, data is often collected at “0”. Therefore, when searching from a value having a small absolute value, that is, a value close to the average “0”, a candidate value can be searched quickly.

  The upper limit value and the lower limit value of the exact solution are determined so that (Condition 2) shown in the figure is satisfied.

Shown (condition 3) is a condition indicating a range of correction values e _i.

  When there are a plurality of candidates that satisfy the conditions shown in the drawing, the information processing system may treat the noise as a result of irreversible transformation. In addition, the information processing system may further narrow down candidates when there are a plurality of candidates that satisfy the illustrated conditions by using an error correction code such as a check sum.

For example, the range of the integer part p _i satisfying (Condition 1) shown in the figure can be expressed by the following equation (20).

As indicated by the above equation (20), the search range is determined by the value of the fractional part q _i . In this example, since the integer part p _i is about three or four, the combination of “(3-4) ⁴ = 81-256” can be applied to (condition 2) and (condition 3) shown in FIG. When a solution satisfying each is searched, an exact solution is obtained.

  The conditions are not limited to (Condition 1), (Condition 2) and (Condition 3) shown in FIG. For example, as shown in FIGS. 17 and 19, when guard bits are added, exact solutions may be narrowed down according to changes in guard bits. Hereinafter, a case where the added guard bit is “01” of 2 bits as in FIGS. 17 and 19 will be described as an example.

  FIG. 21 is a schematic diagram illustrating an example of conditions based on changes in guard bits according to an embodiment of the present invention. For example, as illustrated, an example will be described in which the guard bit GB “01” is added to the upper side of the three lower bits UB “XXX”, which is an example of lower data. In this example, an error occurs in the lower bit UB “XXX”, which is arbitrary data.

  FIG. 22 is a table showing an example of conditions based on changes in guard bits according to an embodiment of the present invention. As shown in the figure, it is possible to estimate what kind of error has occurred due to the change of the guard bit. First, when there is a change in the guard bit, it can be said that a carry or a carry has occurred in the lower bit UB, so it can be estimated whether or not an error has occurred depending on whether or not the guard bit has changed.

  Specifically, when the “guard bit after error occurrence” changes from “01” to “10”, the lower bit UB before error occurrence (see FIG. 21) is “111” and “+1”. It can be estimated that an error of. As shown in the figure, when “lower bit before error occurrence” is “111”, when “+1” is added to this, a carry occurs. That is, due to the carry, the guard bit GB (see FIG. 21) becomes “01 + 1 = 10”. Thus, if there is a change in the upper bits of the guard bit GB, it can be estimated that a positive value error such as “+1” has occurred in the lower bits UB.

  When the “guard bit after error occurrence” is changed from “01” to “00”, it is estimated that the lower bit UB before error occurrence is “000” and an error of “−1” has occurred. it can. As shown in the figure, when “-1” is added to “000” when “low order bit before error occurrence” is “000”, a carry occurs. That is, the guard bit GB becomes “01-1 = 00” due to the carry-down. Thus, if there is a change in the lower bits of the guard bit GB, it can be estimated that a negative value error such as “−1” has occurred in the lower bits UB.

  Therefore, when guard bits are included in the compressed data, a condition related to guard bits may be further added to the conditions shown in FIG. 20, and correction may be performed based on the conditions related to guard bits. Hereinafter, the condition relating to the guard bit is referred to as (condition 4). The added guard bit GB is “01”. In this case, (condition 4) is that when “the guard bit after occurrence of error” is “10”, the error is a positive value and “the guard bit after occurrence of error” is “00”. In some cases, the error is estimated to be a negative value, and so on.

  Note that (Condition 4) may be changed according to the added guard bit GB.

  As described above, when the condition relating to the guard bit is further added, the exact solution can be more easily narrowed down.

  The correction is preferably performed on the receiving side in the process shown in FIG. 10, that is, in the information processing system. The transmission side that transmits data, that is, the first information processing apparatus that performs compression in the process shown in FIG. 2 is often an embedded system or the like. On the other hand, the second information processing apparatus that becomes the receiving side and performs decompression by the processing shown in FIG. 10 is often a server or the like. As described above, the receiving side is often a device that has more CPU power, storage area, or the like than the transmitting side. Therefore, if the load related to the correction is borne on the receiving side, the influence of the load can be reduced as a whole system.

<< 3. Functional configuration example of information processing system >>
FIG. 23 is a functional block diagram illustrating an example of a functional configuration of an information processing system according to an embodiment of the present invention. As illustrated, the information processing system 10 includes an embedded system 1 and a server 2. In this example, the embedded system 1 compresses and transmits data to the server 2, and the server 2 receives the data and decompresses the data.

  Specifically, the information processing system 10 includes a code generation unit FN1, a first conversion unit FN2, a calculation unit FN3, an encoding unit FN4, a decoding unit FN5, a normalization unit FN6, and a second conversion. A part FN7 and an integerizing part FN8 are included.

  The code generation unit FN1 generates a change code by changing the Hadamard code based on the serial number or the like that the embedded system 1 has.

  The first conversion unit FN2 converts the input data a based on the change code to generate first data b.

  The calculation unit FN3 normalizes and integerizes the first data b to generate the second data c.

  The encoding unit FN4 encodes the second data c to generate compressed data d.

  The decryption unit FN5 decrypts the compressed data d to generate second data c.

  The normalizing unit FN6 normalizes the second data c to generate normalized data b ′.

  The second conversion unit FN7 converts the normalized data b 'based on the change code to generate the third data a'.

  The integer converting unit FN8 converts the third data a ′ into an integer to generate decoded data a ″.

  Each unit is realized by an arithmetic device such as a CPU included in the information processing apparatus, for example.

  The information processing system can compress and decompress data by conversion based on the change code and inverse conversion. In compression and decompression of data by conversion based on the change code and inverse conversion, since the code can be determined only by the conversion code, the data related to overhead is small compared to conversion using a multidimensional orthogonal sequence. Therefore, the information processing system can reduce the data capacity after compression by conversion based on the change code and inverse conversion.

  Further, since the conversion based on the change code and the inverse conversion involve many simple calculations, the information processing system can reduce the load related to the calculation in the compression or decompression of the data.

  Furthermore, since the data converted based on the change code is encrypted using the change code as an encryption key, that is, obfuscated, the information processing system performs conversion and reverse conversion based on the change code, The security of data to be transmitted / received can be improved.

  The input data is preferably sensor data indicating an image, sound, temperature, vibration, or the like. In other words, when the input data is compressed and then decompressed, it may include an error as compared to before compression. For this reason, it is desirable to use sensor data or the like in which errors are likely to be allowed after decompression.

  The embedded system may be applied to embedded devices in general, devices that communicate with other devices via the cloud, etc., each device used for IoT (Internet of Things), or an information processing system that combines these devices. .

  Further, the first information processing apparatus and the second information processing apparatus are not limited to the configuration realized by one information processing apparatus. That is, one or both of the first information processing apparatus and the second information processing apparatus may be two or more information processing apparatuses. In the information processing system, processing may be performed so that part or all of each processing is distributed, redundant, parallel, or a combination thereof.

  Note that the present invention may be realized by executing an information processing method. In this case, the present invention is not limited by the type of apparatus that executes the information processing method.

  In addition, the present invention may be realized by executing a part or all of the procedure according to the present invention by an information processing apparatus based on a program. That is, the present invention may be realized by a program or the like for executing information processing.

  As mentioned above, although the preferable Example of this invention was explained in full detail, this invention is not limited to the specific embodiment which concerns. That is, various modifications or changes can be made within the scope of the gist of the present invention described in the claims.

1 Embedded System 10 Information Processing System a Input Data b First Data c Second Data d Compressed Data b ′ Normalized Data a ′ Third Data a ″ Decoded Data GB Guard Bit

Claims (13)

An information processing apparatus for compressing input data,
A code generator that changes the Hadamard code to generate a change code;
A converter that converts the input data based on the change code to generate first data;
A calculation unit that normalizes and integerizes the first data to generate second data;
An information processing apparatus including an encoding unit that encodes the second data to generate compressed data.   The information processing apparatus according to claim 1, wherein the code generation unit generates the change code by rearranging rows of the Hadamard code or rearranging the Hadamard code column when the Hadamard code is a matrix.   The information processing apparatus according to claim 1, wherein the code generation unit generates the change code by multiplying the Hadamard code by a diagonal code when the Hadamard code is a matrix.   The code generator, when the Hadamard code is a matrix, rearranges the rows of the Hadamard code or rearranges the Hadamard code sequence, and multiplies the Hadamard code by a diagonal code to change the code. The information processing apparatus according to claim 1, which generates   5. The information processing apparatus according to claim 1, wherein when a plurality of pieces of data are input, the plurality of pieces of input data are combined to form the input data.   The information processing apparatus according to claim 5, wherein the combination is an interleaving of the plurality of data.   The information processing apparatus according to claim 5, wherein the combination is a concatenation of the plurality of data.   The information processing apparatus according to any one of claims 5 to 7, wherein the combining adds a guard bit to data on a lower bit side among the plurality of input data.   The information processing apparatus according to claim 8, wherein the guard bit is 2-bit data.   The information processing apparatus according to any one of claims 1 to 9, wherein the encoding is encoding based on a Huffman code.   The information processing apparatus according to any one of claims 1 to 10, wherein the information processing apparatus is an embedded system. An information processing apparatus for decompressing compressed data,
A decoding unit for decoding the compressed data to generate second data;
A normalization unit that normalizes the second data to generate normalized data;
A conversion unit that converts the normalized data based on a modified code obtained by changing a Hadamard code to generate third data;
An information processing apparatus comprising: an integerization unit that generates the decoded data by converting the third data into an integer. An information processing system comprising: a first information processing device that compresses input data; and a second information processing device that decompresses compressed data compressed by the first information processing device,
A code generator that changes the Hadamard code to generate a change code;
A first converter that converts the input data based on the change code to generate first data;
A calculation unit that normalizes and integerizes the first data to generate second data;
An encoding unit that encodes the second data to generate the compressed data;
A decoding unit for decoding the compressed data to generate the second data;
A normalization unit that normalizes the second data to generate normalized data;
A second converter that converts the normalized data based on the change code to generate third data;
An information processing system including an integerization unit that converts the third data into an integer and generates decoded data.

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