JP2017050619A - Timing adjustment circuit and inter-terminal synchronous circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing adjustment circuit and a master device, making coincident the transmission timing of a synchronous frame to accurately estimate synchronous frame transmission timing by the master device in cascade connection to a preceding stage.SOLUTION: A timing adjustment circuit (10), which can be loaded on a master device (12), adjusts the transmission timing of a synchronous frame to be transmitted to a slave device (18), relative to the master device, and another master device in cascade connection to a subsequent stage. The timing adjustment circuit includes: a calculation circuit (40) which obtains transmission timing (T2) in which the other master device connected to the preceding stage transmits a synchronous frame, on the basis of timing (T0), in which the master device (12) having the loaded adjustment circuit (10) receives the synchronous frame, and a predetermined value (T1); and a timing determination circuit (42) which determines timing (T2+T) to transmit a synchronous frame to the other master device connected to the subsequent stage, on the basis of the transmission timing (T2) and a transmission period (T).SELECTED DRAWING: Figure 2

Description

  The present invention relates to a timing adjustment circuit and an inter-terminal synchronization circuit, and more specifically, transmission of a synchronization frame transmitted simultaneously to a slave device connected to a master device and another master device cascade-connected to a subsequent stage. The present invention relates to a timing adjustment circuit for adjusting timing and an inter-terminal synchronization circuit.

  When a private branch exchange (PBX) is installed to use multiple telephones in various facilities, the time division control transmission (Time Compression Multiplexing: TCM) is generally used between the PBX and the telephone terminal. Connected in a manner. The time division control transmission method is a method adopted for wired or wireless digital communication of PBX or Integrated Services Digital Network (ISDN). These digital communication systems have a master device and a slave device, and the slave device synchronizes with the operation timing of the master device.

  In communication by ISDN or PBX, an exchange or PBX serves as a master device, and a terminating device (Digital Service Unit: DSU) or a telephone terminal connected to the exchange or PBX serves as a slave device. The master device has ports for inputting / outputting data to / from the slave device as many as the number of slave devices connectable to the master device. Normally, one slave device is connected to each port. The master device sends transmission data to the slave device called a frame to each port at the same timing.

  The frame transmitted from the master device is composed of data shorter than half of the transmission cycle. The remaining time in the transmission cycle is allocated to reception from the slave device. Timing information (clock) required in the communication system is embedded in the frame.

  The slave device that has received the frames sent from the master device at the same time extracts a necessary clock and synchronizes with the clock. Therefore, any of the plurality of slave devices connected to one master device can be synchronized with the master device.

  Each telephone terminal connected to the PBX is configured as a base unit of a cordless telephone, and a cordless telephone unit corresponding to each base unit using a digital cordless telephone wireless communication system called the DECT (Digital Enhanced Cordless Telecommunications) system. Can be connected to the machine. Here, in order to realize a plurality of communications in the same area using the DECT method, it is necessary to match the timing for transmitting one frame at a cycle of 10 msec. When a telephone terminal is used cordlessly, the private branch exchange embeds 10msec timing, that is, wireless synchronization timing, necessary for execution of wireless communication using the DECT method, and is connected to each port of the private branch exchange via a wired cable. Distribute frames to each phone terminal that has

JP 2009-182659 A

  However, the above-described configuration is based on a star-type connection form. In a large-scale system having a large number of PBXs, PBX devices are generally connected in a cascaded manner across multiple stages. The delay value when the cascade connection is used is affected by a delay caused by the apparatus and a delay caused by the cable length. Since these delays are not constant, it is difficult to control the delay values simultaneously in the entire system. More specifically, this is because the PBX device cannot accurately estimate the timing at which the PBX device connected in the previous stage sends out the synchronization frame, so the synchronization frame is sent to the PBX device connected in the subsequent stage. This means that it is difficult to match the transmission timing with the timing at which the preceding apparatus transmits the synchronization frame.

  With reference to FIG. 7, the delay timing of the synchronization frame at the time of normal cascade connection is shown. When the PBX devices are cascade-connected across three stages, the first-stage PBX apparatus sends the synchronization frame 902 to the terminals connected as slave apparatuses and the second-stage PBX apparatus at the same timing. The timing at which the synchronization frame 902 sent from the preceding PBX device is received by the second PBX device is delayed by time f due to the transmission delay caused by the cable connecting the PBX devices. Therefore, the second stage PBX device receives the synchronization frame 902 at a timing delayed by time f, that is, at a timing indicated as a synchronization frame 902a. The second-stage PBX device processes the received synchronization frame 902, and then sends the synchronization frame 904 to the terminals connected as slave devices and the third-stage PBX device at the same timing. Here, assuming that the processing delay time required for processing the synchronization frame received by the second-stage PBX device is time g, the timing at which the synchronization frame 904 is transmitted is the synchronization frame 902 transmitted by the first-stage PBX device. Is delayed by time f + g. This time f + g is a delay caused by cascade connection for each stage.

  For this reason, many systems that distribute synchronization timing using the cascade connection method employ a configuration in which only the clock is synchronized. Synchronizing only the clock means that the phases may be shifted, but the clocks are matched. By synchronizing each system with the same clock, it is possible to suppress the influence of the phase shift when the clock is asynchronous. However, since the phase is shifted, the wireless slot cannot be used effectively.

  FIG. 8a to FIG. 8b show time slot usage situations when the synchronization relationship between the terminal 906 and the terminal 908 is clock synchronous, asynchronous and frame synchronous, respectively. For convenience, it is assumed that one frame is divided into five time slots 1 to 5 in the figure, and the time slot used by the terminal 906 is the second one (time slot 2). First, in the case of clock synchronization, the delay h is constant for each frame. Since the phase between frames at each terminal shifts due to this delay h, the terminal 908 cannot use the time slot 1 in addition to the time slot 2 as shown in FIG. 8a. This is because the time slot 2 used by the terminal 906 overlaps in time. On the other hand, since the clock is synchronized, the time slot that cannot be used does not change over time.

  In the case of non-synchronization, since a delay i (t) occurs in the terminal 908 with respect to the terminal 906, as shown in FIG. 8b, the time slot 1 that overlaps with the time slot 2 used by the terminal 906 in time. The time slot 2 cannot be used on the terminal 908 side. However, the delay value i (t) varies with the passage of time t. Therefore, the unusable time slots can change with time. In FIG. 8b, the time slots 1 and 2 were originally unusable slots, but the unusable slots have changed to time slots 2 and 3 with the passage of time.

  In view of such a problem, the present invention, for example, even when the lengths of cables connecting master devices connected in cascade are different from each other, the transmission times of the synchronization frames are matched and cascade connection is performed in the previous stage. It is an object of the present invention to provide a timing adjustment circuit and an inter-terminal synchronization circuit that accurately estimate the timing at which a master device next sends out a synchronization frame.

  In order to solve the above-described problem, the present invention is configured to be mounted on a master device that is cascade-connected to another master device and performs frame communication with the other master device, and is connected to the master device. A timing adjustment circuit that adjusts the transmission timing of synchronization frames that are transmitted all at once to the device and other master devices cascade-connected to the subsequent stage, the timing at which the master device equipped with the timing adjustment circuit receives the synchronization frame, and Based on a predetermined time value determined in advance, an arithmetic circuit that calculates the timing at which another master device cascade-connected to the previous stage of the master device equipped with the timing adjustment circuit transmits a synchronization frame, and an arithmetic circuit Based on the calculated synchronization frame transmission timing and synchronization frame transmission cycle, And a timing decision circuit for the master device equipped with timing adjustment circuit toward the other master devices that are cascaded stages to determine the timing of transmitting the synchronization frame.

  In addition, the present invention is configured to be mountable on a master device that is cascade-connected to another master device and performs frame communication with the other master device, and ensures synchronization of frame transmission timing between the connected master devices. The inter-terminal synchronization circuit further includes a processing circuit that receives a synchronization frame from another master device cascade-connected to the preceding stage, a slave device connected to the master device, and a cascade connection to the subsequent stage. Connects to the previous stage of the processing circuit based on the timing at which the processing circuit receives the synchronization frame and a predetermined time value that is determined in advance, by adjusting the transmission timing of the synchronization frame that is transmitted all at once to other master devices Is calculated by the arithmetic circuit that calculates the timing at which the other master device transmits the synchronization frame, and the arithmetic circuit. And a timing determination circuit for determining a timing at which the inter-terminal synchronization circuit transmits the synchronization frame toward another master device cascade-connected to the subsequent stage based on the transmission timing of the synchronization frame and the transmission period of the synchronization frame When performing synchronization frame communication between the timing adjustment circuit and another master device connected to the latter stage, the timing adjustment circuit receives a timing for sending the synchronization frame determined by the timing adjustment circuit, and based on this timing, And an interface circuit for adjusting the transmission timing of a synchronization frame to be transmitted to another master device connected to the network.

  Further, the present invention is directed to a slave device connected to a master device and a master device cascaded to a subsequent stage when a computer is cascade-connected to the master device to execute frame communication with the master device. A timing adjustment program for functioning as a master device for adjusting the transmission timing of synchronization frames to be transmitted all at once, wherein the computer is based on at least a timing at which the computer receives a synchronization frame and a predetermined time value determined in advance. , Calculating means for calculating the timing at which the master device cascade-connected to the previous stage of the computer transmits the synchronization frame, and cascade connection to the subsequent stage based on the transmission timing of the synchronization frame and the transmission period of the synchronization frame calculated by the calculating means Master Computer to function as the timing determining means for determining a timing of transmitting the synchronization frame towards the location.

  According to the present invention, it is possible to match the transmission times of the synchronization frames regardless of the length of the cable connecting the master devices connected in cascade. In addition, it is possible to accurately estimate the timing at which the master device connected in the previous stage transmits the synchronization frame next time.

1 is a schematic diagram showing a private branch exchange system constructed using a private branch exchange that includes an embodiment of a timing adjustment circuit according to the present invention. FIG. It is a circuit block diagram which shows the schematic structure of the Example of the timing adjustment circuit which concerns on this invention. It is another figure which shows schematically the private branch exchange system of FIG. It is a figure which shows the timing chart when the delay adjustment of the frame output from a private branch exchange is performed using the Example of this invention. It is a figure which shows the phase of a time slot at the time of implement | achieving frame synchronization using the Example of this invention. It is the schematic which shows the structure which operates a computer as a private branch exchange including the Example of the timing adjustment circuit which concerns on this invention. It is a figure which shows the delay timing of the synchronous frame by the conventional private branch exchange system which connected the private branch exchange by cascade connection. It is a figure explaining the relationship between a clock synchronization and a phase shift. It is a figure explaining the relationship between asynchronous and phase shift.

  Embodiments of a timing adjustment circuit and a private branch exchange including the circuit according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, an embodiment of a timing adjustment circuit 10 according to the present invention is mounted in each private branch exchange (PBX) 12 serving as a master device in a DECT-type PBX digital communication network. This is a circuit that adjusts the frame transmission timing in consideration of a delay that may occur due to the cascade connection of the terminals.

  In the private branch exchange system 14 using the timing adjustment circuit 10, a plurality of PBXs 12 are connected in cascade. However, in FIG. 1 showing the private branch exchange system, the PBX 12a, the PBX 12b, and the PBX other than the PBX 12 are not shown for convenience. Further, in FIG. 1, only the PBX 12b connected to the second stage is shown without omitting the timing adjustment circuit 10 according to the embodiment of the present invention, but connected to the upper stage of the PBX 12b. The timing adjustment circuit 10 can also be mounted inside the PBX 12c connected to the lower stage of the PBX 12a and the PBX 12b.

  The private branch exchange (PBX) system 14 is essentially composed of the private branch exchanges (PBX) 12a to 12c that serve as a master device and have the timing adjustment circuit 10 and a plurality of telephone terminals 16 that serve as slave devices. . In the system 14 according to the present embodiment, a synchronization frame is transmitted from the upper PBX 14a to the PBX 14b via the wired cable 16a, and further, a synchronization frame is transmitted from the PBX 14b to the PBX 14c via the wired cable 16b. In the embodiment shown in the figure, it is assumed that three telephone terminals 18a to 18c corresponding to the slave devices are connected to the PBX 12b serving as the master device via wired cables 20a to 20c, respectively.

  With this configuration, the PBX 12b equipped with the timing adjustment circuit 10 transmits the synchronization frame whose transmission timing is adjusted to synchronize in units of frames to the telephone terminal 18 and the next-stage PBX 12c at the same time, and executes frame communication It becomes possible to do.

  The telephone terminal 18 is a base unit of a cordless telephone that does not require a wired connection with a handset used by a user for a call by a curl cord or the like. Each of the telephone terminals 18a to 18c is connected to a corresponding cordless telephone cordless handset 22a to 22c by radio 24a to 24c. The wireless connection method is the DECT method, and the private branch exchange 12 embeds 10 msec wireless synchronization timing in the frame and connects to the telephone terminal 18 connected via the wired cable 20 in order to realize multiple communications in the same area. Distribute frames with embedded wireless synchronization timing.

  An area in which a plurality of wireless communications using the DECT method by the telephone terminals 18 and their slaves 22 using the private branch exchange 12 as a master device is possible is represented as a DECT wireless area 26 in FIG.

  Following the overall description of the system 14 shown in FIG. 1, a more detailed description of the configuration of the private branch exchange 12 (12b) and the timing adjustment circuit 10 mounted thereon will be given with reference to FIG. In addition to the timing adjustment circuit 10, the private branch exchange 12 includes a time division control circuit 32 that is also an interface with the host device and an interface circuit 34 that is an interface with the lower device. In other words, the private branch exchange 12 includes these circuits 10, 32, and 34, and includes an inter-terminal synchronization circuit 35 that ensures synchronization of frame transmission timing as a process for performing normal communication between the terminals by the time division control method. Will be included. That is, it can be considered that a device equipped with the inter-terminal synchronization circuit 12 works as the private branch exchange 12. It should be noted that the configuration shown in this figure is limited only to components that are particularly relevant to adjustment of the synchronization frame transmission timing.

  The time division control circuit 32 is connected to the preceding PBX 12a via the cable 16a, and receives a signal such as a synchronization frame from the preceding PBX 12a. The time division control circuit 32 performs various processes necessary for performing communication using the time division control transmission method based on the received synchronization frame.

  The time division control circuit 32 is connected to the timing adjustment circuit 10 via the communication line 36. The timing adjustment circuit 10 may include a storage holding circuit 38 that holds predetermined information extracted from information related to the received synchronization frame. In particular, the memory holding circuit 38 holds the time when the time division control circuit 32 receives the synchronization frame from the preceding PBX 12a as the reception timing T0.

  In addition, the memory holding circuit 38, for example, a delay determined in advance in consideration of the transmission delay time that occurs when the synchronous frame is transmitted in the cascade-connected PBX paper from the PBX 12a to the PBX 12b via the cable 16a. The time value T1 can be stored. Alternatively, the maximum delay value TMAX may be stored as a maximum delay value TMAX as long as normal communication is ensured as a transmission delay time value between the PBX 12a and the PBX 12b.

  The memory holding circuit 38 may be a temporary storage circuit such as a DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) using, for example, an electrical storage method. Data can be read and written on. Further, when the memory holding circuit 38 is a temporary storage circuit using an electrical storage method, for example, a long-term storage device (not shown) such as a hard disk suitable for long-term storage is stored and held using a magnetic or other physical storage method. It may be connected to the circuit 38. Since the delay time T1 and the maximum delay value TMAX can be set in advance, the delay time T1 and the maximum delay value TMAX are first stored in a long-term storage device, and the time values T1 and TMAX are stored and retained as necessary. The data may be sent to the circuit 38 so that the data processing can be executed at a higher speed in the timing adjustment circuit 10.

  Note that the memory holding circuit 38 further holds the transmission period T of the synchronization frame. The transmission period T may be information extracted with the reception of the synchronization frame. In this case, the transmission period T is held in the storage holding circuit 38 together with the reception timing T0. If the transmission cycle T is known in advance and the long-term storage device is connected to the memory holding circuit 38, the transmission cycle T is stored in the long-term storage device prior to the operation of the PBX 12. It may be left.

  The timing adjustment circuit 10 further includes an arithmetic circuit 40 connected to the output 39 of the memory holding circuit 38. The arithmetic circuit 40 receives from the storage holding circuit 38 data related to the reception timing T0 when the time division control circuit 32 receives the synchronization frame and a predetermined delay time value T1. Instead of receiving the delay time value T1, when the memory holding circuit 38 stores the maximum delay value TMAX, the arithmetic circuit 40 may receive the maximum delay value TMAX from the memory holding circuit 38.

  The arithmetic circuit 40 uses the received data to calculate the timing at which the PBX connected in the previous stage actually sends out the synchronization frame. Specifically, the arithmetic circuit 40 subtracts the delay time value T1 from the reception timing T0, and calculates the timing T2 at which the preceding PBX 12a actually sends the synchronization frame to the PBX 12b.

  When the arithmetic circuit 40 receives the maximum delay value TMAX instead of the delay time value T1, the arithmetic circuit 40 subtracts the maximum delay value TMAX from the reception timing T0, and the preceding PBX 12a sends a synchronization frame to the PBX 12b. The calculated timing is calculated as the deemed transmission timing T2.

  The timing adjustment circuit 10 further includes a timing determination circuit 42 that is connected to the output 41 of the arithmetic circuit 40, receives the calculation result of the arithmetic circuit 40, and determines the timing for sending the synchronization frame to the subsequent PBX 12c. The timing determination circuit 42 is also connected to the output 43 of the memory holding circuit 38, and can receive information regarding the frame transmission period T.

  The timing determination circuit 42 adds the transmission cycle T received from the memory holding circuit 38 to the timing T2 received from the arithmetic circuit 40, and the timing T2 + when the PBX 12b transmits a synchronization frame to the telephone terminal 18 and the subsequent PBX 12c. Determine T.

  The output of the timing determination circuit 42 is connected to the input of the interface circuit 34 via the communication line 44. The interface circuit 34 is mounted in a private branch exchange (PBX) 12 that serves as a master device in a DECT PBX digital communication network, while the output of the interface circuit 34 is connected to each telephone terminal 18 that serves as a slave device. Connected. The interface circuits 34 are installed for each PBX 12 by the number of telephone terminals 18 that are slave devices of the PBX. The interface circuits 34a to 34c connect the PBX 12 and each telephone terminal 18 with such a configuration, and perform various control processes to enable communication between the two devices. In particular, the interface circuit 34 adjusts the transmission timing of transmission frames necessary for realizing communication by the time division control transmission method.

  The interface circuit 34 further functions as a synchronization circuit 46 for individually adjusting the transmission timing of a transmission frame transmitted to the telephone terminal 18 connected to the circuit 34 or the same kind of function in order to further improve the reliability of communication. It may have a circuit to do. In FIG. 2, the synchronization circuit 46 is clearly shown only in the interface circuit 34a, but it goes without saying that the synchronization circuit 46 may be included in the other circuits 34b and 34c. The synchronization circuit 46 is provided with, for example, a counter for measuring the amount of delay generated according to the length of each cable or a circuit similar thereto, so that the transmission frame can be received from the generation timing of the transmission frame in the PBX 12. Accordingly, a configuration may be adopted in which the interval until the reception timing for receiving the reception frame transmitted from the telephone terminal 18 side is measured. In addition, the delay amount between the PBX 12 and the telephone terminal 18 generated according to the length of each cable 44a to 44c is determined from this measured value, and transmitted from each circuit 34a to 34c toward each telephone terminal 18a to 18c. A circuit for adjusting the transmission timing of the frame to be individually delayed may be provided in the synchronization circuit 46.

  When the above-described synchronization circuit 46 or a circuit corresponding thereto is provided in the interface circuit 34, each telephone terminal can be used even when a different delay difference occurs in communication between the PBX 12 and each telephone terminal 18a to 18c. It is possible to make the reception timing of the synchronization frame supplied to 18 coincide with the timing of T2 + T.

  The output of the timing determination circuit 42 may be further connected to the input of the interface circuit 54 via the communication line 52. The output of the interface circuit 54 is connected via the cable 16b to the PBX 12c cascaded in the subsequent stage of the PBX 12b. The interface circuit 54 connects the PBX 12b and the PBX 12c with such a configuration, and performs necessary control processing so that the synchronization frame can be reliably and smoothly supplied from the PBX 12b to the PBX 12c. Note that the interface circuit 54 may include a circuit corresponding to the above-described synchronization circuit 46. With this configuration, when performing frame communication with the downstream PBX 12c, the transmission timing of the frame transmitted to the downstream PBX 12c can be adjusted. As a result, the timing necessary for realizing communication by the time division control transmission method is controlled.

  Subsequently, an operation related to adjustment of the transmission time of the synchronization frame executed by the timing adjustment circuit 10 according to the embodiment of the present invention will be described. The configuration of the private branch exchange system 10 shown in FIG. 3 is substantially the same as that shown in FIG. However, some of the components shown in the figure are changed so that the output timing of the synchronization frame sent from each device can be easily grasped. For example, telephone terminals 18d and 18e are connected via wired cables 20d and 20e as slave devices of the frontmost PBX 12a in the figure. FIG. 4 is a timing chart relating to delay adjustment executed in the embodiment of the timing adjustment circuit according to the present invention.

  First, the private branch exchange (PBX) 12a in the forefront in the figure transmits the synchronization frame 62 to the PBX 12b in the next stage in addition to the telephone terminals 18d and 18e which are wireless terminals at the same timing. Since the transmission of the synchronization frame 62 from the PBX 12a to the PBX 12b is performed via the cable 16a, a transmission delay corresponding to the length of the cable 16a occurs. Due to such a transmission delay, the PBX 12b receives the synchronization frame 62 at a delayed timing, that is, at the timing TO of the synchronization frame 62a shown in FIG.

  The memory holding circuit 38 of the timing adjustment circuit 10 of the PBX 12b that has received the synchronization frame 62a holds the timing TO received as the synchronization frame 62a. The memory holding circuit 38 also stores a delay time value T1 in advance.

  Subsequently, the arithmetic circuit 40 of the timing adjustment circuit 10 subtracts the delay time value T1 from the reception timing T0 held in the memory holding circuit 38, whereby the preceding PBX 12a actually sends the synchronization frame to the PBX 12b. Calculate T2.

  Even when the maximum delay value TMAX is stored in the memory holding circuit 38 instead of the delay time value T1, by subtracting the maximum delay value TMAX from the reception timing T0 as in the case of the delay time value T1, A presumed timing T2 at which the preceding PBX 12a estimates that a synchronization frame has been transmitted to the PBX 12b is calculated.

  The timing determination circuit 42 of the timing adjustment circuit 10 receives the timing T2 from the arithmetic circuit 40 and the frame transmission period T from the memory holding circuit 38, adds the transmission period T to the timing T2, and the PBX 12b receives the telephone terminals 18a and 18b. The timing T2 + T at which the synchronization frame 64 is transmitted to the subsequent PBX 12c is determined.

  From the point of view of PBX 12b, the value T2 that is the transmission timing of PBX 12a is the calculation result of T0-T1, and after delay processing is performed for the calculated value T0-T1 plus the transmission period T This means that the synchronization frame 64 is transmitted to the subsequent stage. For this reason, the processing delay time required for the processing of the synchronization frame 62a received by the PBX 12b in the present embodiment corresponds to the value of T0−T1 + T.

  Timing T2 corresponds to the timing at which the preceding PBX 12a transmits the synchronization frame 62, and the time T2 + T obtained by adding the transmission period T to this timing T2 is the transmission timing of the synchronization frame 64. Therefore, the transmission timing of the synchronization frame 64 Coincides with the transmission timing of the synchronization frame 62. Accordingly, the frame synchronization is realized with a delay of exactly one cycle (T), for example, from the telephone terminals 18d and 18e as slave devices of the PBX 12a and the telephone terminals 18a and 18b as slave devices of the PBX 12b, respectively. There is no phase shift in the emitted radio time slots.

  With reference to FIG. 5, a description will be given of time slots issued by telephone terminals connected from the respective PBXs when frame synchronization is established. In the description of the figure, as in the case of FIG. 8, for convenience, one frame is divided into five time slots 1 to 5, and the time slot used by a device such as the telephone terminal 18a is the second one. It is assumed that (time slot 2). If the synchronization frame 64 is frame-synchronized with the synchronization frame 62, the delay value j between frames is always 0 and constant, and no phase shift occurs. Therefore, as shown in FIG. 5, there is always only one time slot (time slot 2) that cannot be used on the other telephone terminal 18b side, and the radio slot can be used effectively.

  As described above, according to the embodiment of the present invention, all cascaded PBXs adjust the transmission time of the synchronization frame to the subsequent PBX based on the predetermined delay value, The transmission times can be matched regardless of the cable length. Also, by considering the delay value from the timing when the PBX received the synchronization frame, the timing at which the previous PBX actually sends the synchronization frame can be calculated, so the previous PBX sends the next synchronization frame. It is possible to accurately estimate the timing.

  By the way, the private branch exchange 14 including the timing adjustment circuit 10 and the circuit 10 according to the embodiment of the present invention can be realized by installing a program for executing the adjustment method described above in a computer. An embodiment in this case will be briefly described with reference to FIG. A program for causing the computer 82 to function as the private branch exchange 12 having the timing adjustment circuit 10 according to the embodiment of the present invention described above is stored in the storage medium 84. Here, the storage medium 84 includes any device or component capable of storing a program, such as an optical disk, a magnetic disk, or a flash memory.

  The computer 82 has a drive 86 that can read the storage contents of the storage medium 84. The drive 86 may be fixedly built in the computer 82, or may be an external device independent from the computer 82 and connectable to the computer 82. The computer 82 includes a central processing unit (CPU) 88 that performs information processing such as computation and control of the computer itself, and a storage device 90 that stores programs, data, and the like. For convenience, the storage device 90 shown in this figure includes both a device that temporarily stores data and a device that constantly stores data. The CPU 88 is connected to the drive 86 via the connection line 92 and is also connected to the storage device 90 via the connection line 94.

  The program stored in the storage medium 84 is read by the computer 82 via the drive 86, and the read program is stored in the storage device 90 of the computer 82 under the control of the CPU 88. The computer 82 in which the program is incorporated in this way can operate as the private branch exchange 12 equipped with the timing adjustment circuit 10 according to the above-described embodiment of the present invention by executing the program. This program also makes the CPU 88 in the computer 82, the storage device 90, and other various internal devices not shown work as the memory holding circuit 38, the arithmetic circuit 40, and the timing determination circuit 42 included in the timing adjustment circuit 10. I can say that. Further, the storage device 90 in the computer 82 may serve as a long-term storage device that stores data such as the delay time T1 and the maximum delay value TMAX in advance.

  Although several embodiments of the present invention have been described so far, specific methods for implementing the present invention are not limited to the above-described embodiments. As long as the present invention can be implemented, the design, operation procedure, and the like can be changed as appropriate. For example, circuits and other devices used for assisting the function of the components used in the present invention can be added and omitted as appropriate.

10 Timing adjustment circuit
12 Private branch exchange
14 Private branch exchange system
18 Telephone terminal
35 Inter-terminal synchronization circuit
40 Arithmetic circuit
42 Timing decision circuit
82 computers
84 Storage media

Claims (15)

It is configured to be mountable on a master device that is cascade-connected to another master device and performs frame communication with the other master device, and is connected to the master device and other devices that are cascade-connected to the subsequent stage. A timing adjustment circuit that adjusts the transmission timing of synchronization frames that are transmitted simultaneously to a master device, the timing adjustment circuit comprising:
Other masters cascade-connected to the preceding stage of the master device equipped with the timing adjustment circuit based on the timing at which the master device equipped with the timing adjustment circuit receives the synchronization frame and a predetermined time value determined in advance An arithmetic circuit for calculating the timing at which the device transmits the synchronization frame;
Based on the transmission timing of the synchronization frame calculated by the arithmetic circuit and the transmission cycle of the synchronization frame, a master device on which the timing adjustment circuit is mounted toward another master device cascade-connected to the subsequent stage transmits the synchronization frame. A timing adjustment circuit comprising: a timing determination circuit that determines a transmission timing.   2. The timing adjustment circuit according to claim 1, wherein the arithmetic circuit calculates a timing at which the synchronization frame is transmitted by subtracting the predetermined time value from a timing at which the synchronization frame is received. Adjustment circuit.   3. The timing adjustment circuit according to claim 1, wherein the timing determination circuit sends the synchronization frame by adding a transmission period of the synchronization frame to a transmission timing of the synchronization frame calculated by the arithmetic circuit. A timing adjustment circuit characterized by determining the timing.   4. The timing adjustment circuit according to claim 1, wherein the predetermined time value connects between a master device on which the timing adjustment circuit is mounted and a master device cascade-connected to a preceding stage of the master device. A timing adjustment circuit, wherein the timing adjustment circuit is determined based on a transmission delay time caused by a cable.   4. The timing adjustment circuit according to claim 1, wherein the predetermined time value connects between a master device on which the timing adjustment circuit is mounted and a master device cascade-connected to a preceding stage of the master device. A timing adjustment circuit characterized by being determined to be a maximum delay time value allowed as long as normal communication is ensured as a transmission delay time caused by a cable. Inter-terminal synchronization that is configured to be mounted on a master device that is cascade-connected to another master device and performs frame communication with the other master device, and ensures synchronization of frame transmission timing between the connected master devices. The inter-terminal synchronization circuit further comprises:
A processing circuit for receiving a synchronization frame from another master device cascaded in the previous stage;
It adjusts the transmission timing of the synchronization frame transmitted simultaneously to the slave device connected to the master device and other master devices cascade-connected in the subsequent stage, and determines in advance the timing at which the processing circuit receives the synchronization frame. An arithmetic circuit that calculates the timing at which another master device connected to the previous stage of the processing circuit transmits a synchronization frame based on the predetermined time value, and the transmission timing of the synchronization frame calculated by the arithmetic circuit A timing adjustment circuit including a timing determination circuit that determines a timing at which the inter-terminal synchronization circuit transmits a synchronization frame to another master device connected to the subsequent stage based on a transmission period of the synchronization frame;
When performing synchronization frame communication with another master device connected to the subsequent stage, the timing to send the synchronization frame determined by the timing adjustment circuit is received, and based on the timing, the synchronization frame is connected to the subsequent stage. And an interface circuit for adjusting a transmission timing of a synchronization frame to be transmitted to another master device.   7. The inter-terminal synchronization circuit according to claim 6, wherein the arithmetic circuit calculates the timing at which the synchronization frame is transmitted by subtracting the predetermined time value from the timing at which the synchronization frame is received. Inter-terminal synchronization circuit.   8. The inter-terminal synchronization circuit according to claim 6, wherein the timing determination circuit transmits the synchronization frame by adding a transmission period of the synchronization frame to the transmission timing of the synchronization frame calculated by the arithmetic circuit. An inter-terminal synchronization circuit characterized by determining timing.   9. The inter-terminal synchronization circuit according to claim 6, wherein the predetermined time value is caused by a cable connecting the master device and a master device cascade-connected to the previous stage of the master device. An inter-terminal synchronization circuit, which is determined based on a transmission delay time that occurs.   9. The inter-terminal synchronization circuit according to claim 6, wherein the predetermined time value is caused by a cable connecting the master device and a master device cascade-connected to the previous stage of the master device. A terminal-to-terminal synchronization circuit characterized in that a maximum delay time value that is allowed as long as normal communication is secured is determined as a transmission delay time that occurs. When the computer is cascade-connected to the master device and performs frame communication with the master device, the computer is simultaneously transmitted to the slave device connected to the master device and the master device cascade-connected to the subsequent stage. A timing adjustment program that functions as a master device for adjusting the transmission timing of a synchronization frame, the program comprising at least the computer,
Based on the timing at which the computer receives the synchronization frame and a predetermined time value determined in advance, a calculation means for calculating the timing at which the master device cascade-connected to the previous stage of the computer transmits the synchronization frame; and
Timing determination means for determining the timing at which the computer sends out the synchronization frame to the master device cascade-connected to the subsequent stage based on the transmission timing of the synchronization frame calculated by the calculation means and the transmission period of the synchronization frame A timing adjustment program characterized in that it functions as   12. The timing adjustment program according to claim 11, wherein the computer functioning as the calculation unit is configured to calculate the timing at which the synchronization frame is transmitted by subtracting the predetermined time value from the timing at which the synchronization frame is received. A featured timing adjustment program.   13. The timing adjustment program according to claim 11 or 12, wherein the synchronization frame is added to the computer serving as the timing determination unit by adding a transmission period of the synchronization frame to the transmission timing of the synchronization frame calculated by the calculation unit. A timing adjustment program for determining the timing of sending a message.   14. The timing adjustment program according to claim 11, wherein the predetermined time value is a transmission delay caused by a cable connecting the computer and a master device cascade-connected to a preceding stage of the computer. A timing adjustment program which is determined based on time. 14. The timing adjustment program according to claim 11, wherein the predetermined time value is a transmission delay caused by a cable connecting the computer and a master device cascade-connected to a preceding stage of the computer. A timing adjustment program characterized in that it is determined to be a maximum delay time value allowed as long as normal communication is ensured.

Images