JP2017050038A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress decrease in retention characteristics due to PVT variation.SOLUTION: A semiconductor memory 100 comprises: a memory cell array 100A composed of a plurality of SRAM cells 10 including an NMOS transistor and a PMOS transistor; and a bias circuit 100B connected to a ground GND1 or a power supply voltage VDD1 of the memory cell array 100A. The bias circuit 100B includes: NMOS transistors 121, 122, 133, 134 having the same channel length, the same channel width, and having the same dopant and dosage in a channel part, as those of the NMOS transistor in the SRAM cell 10; and PMOS transistors 111, 112 having the same channel length, the same channel width, and having the same dopant and dosage in a channel part, as those of the PMOS transistor in the SRAM cell 10. Diffusion regions of the NMOS transistor and the PMOS transistor are formed on the same semiconductor layer.SELECTED DRAWING: Figure 4

Description

  Embodiments described herein relate generally to a semiconductor memory.

  An SRAM (Static Random Access Memory) as a semiconductor memory device can store data without requiring a regular refresh operation like a DRAM (Dynamic Random Access Memory), and thus consumes very little power. Has the advantage.

  However, in an SRAM that does not perform a regular refresh operation, the retention characteristics may be degraded due to a leakage current during standby. Therefore, conventionally, the leakage current of the memory cell is suppressed by lowering the power supply voltage (VDD) in the cell array. However, with such a method, it is difficult to stabilize the lowered VDD against variations in process conditions, power supply voltage, and process temperature (hereinafter referred to as PVT (Process / Voltage / Temperature)). For this reason, there has been a case where the retention characteristic is lowered due to the PVT fluctuation.

US Pat. No. 8,406,039

  An object of the embodiment is to provide a semiconductor memory capable of reducing a decrease in retention characteristics due to PVT fluctuations.

  According to one embodiment, a semiconductor memory includes a memory cell array composed of a plurality of SRAM cells each including a first NMOS transistor and a first PMOS transistor, and a first ground line or power supply of the memory cell array. A bias circuit connected to a voltage line, wherein the bias circuit has the same channel length and the same channel width as the first NMOS transistor, and has the same dopant and dose in the channel portion. A second PMOS transistor having the same channel length and the same channel width as the first PMOS transistor and having the same dopant and dose in the channel portion, and the first and second NMOS transistors; The first and second PMOS transistors Are formed in the same semiconductor layer, and the bias circuit includes one or more cells, each cell including four transistors constituting two cross-connected inverters and a transfer for reading and writing. The NMOS transistor and the PMOS transistor are any of the four transistors constituting the two inverters and the two NMOS transistors constituting the transfer gate, respectively. It corresponds to one or more.

  According to another embodiment, a semiconductor memory includes a memory cell array including a plurality of SRAM cells, and a ring oscillator connected to a ground line of the memory cell array.

FIG. 1 is a diagram for explaining an example of leakage current generated in a general memory cell of an SRAM. FIG. 2 is a schematic diagram illustrating a schematic configuration example of the semiconductor memory according to the first embodiment. FIG. 3 is a schematic diagram illustrating a specific configuration example of the semiconductor memory according to the first embodiment. FIG. 4 is an enlarged view of the bias circuit shown in FIG. FIG. 5 is a schematic diagram illustrating a layout example of the cell according to the first embodiment. FIG. 6 is a schematic diagram illustrating a layout example of another cell according to the first embodiment. FIG. 7 is a schematic diagram illustrating a specific configuration example of the semiconductor memory according to the second embodiment. FIG. 8 is a diagram illustrating a simulation result of the potential fluctuation suppressing effect according to the first and second embodiments. FIG. 9 is a circuit diagram illustrating a schematic configuration example of the bias circuit according to the third embodiment. FIG. 10 is a schematic diagram illustrating a layout example of a cell according to the third embodiment. FIG. 11 is a schematic diagram illustrating a layout example of another cell according to the third embodiment. FIG. 12 is a schematic diagram illustrating a layout example of still another cell according to the third embodiment. FIG. 13 is a schematic diagram illustrating a layout example of still another cell according to the third embodiment. FIG. 14 is a schematic diagram illustrating a specific configuration example of the semiconductor memory according to the fourth embodiment. FIG. 15 is a circuit diagram illustrating a schematic configuration example of a substrate bias generation circuit for a PMOS transistor according to the fourth embodiment. FIG. 16 is a circuit diagram illustrating a schematic configuration example of a substrate bias generation circuit for an NMOS transistor according to the fourth embodiment.

  Exemplary embodiments of a semiconductor memory will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

Embodiment 1
In the first embodiment, first, an example of a leakage current generated in an SRAM memory cell (hereinafter referred to as an SRAM cell) will be described using a general SRAM cell structure. FIG. 1 is a diagram for explaining an example of a leakage current generated in a general SRAM cell. Note that FIG. 1 illustrates a case where GND is electrically floated to suppress leakage current during retention.

  As shown in FIG. 1, the SRAM cell 10 is composed of four transistors that constitute two inverters that are cross-connected and two transistors that constitute a transfer gate for reading and writing. Bits for SRAM cell 10 are stored in two inverters that are cross-connected.

  The leakage current of the SRAM cell 10 mainly includes a leakage current (1) of an NMOS (Metal-Oxide-Semiconductor) transistor constituting a transfer gate, an off-leakage current (2) of a PMOS transistor constituting an inverter, and an inverter. The off-leak current (3) of the NMOS transistor that constitutes. These leakage currents change the potential of GND in an electrically floating state. As a result, the bits stored in the two inverters may change and the retention characteristics of the SRAM cell 10 may deteriorate.

  Further, the leakage current generated in the SRAM cell 10 changes due to the variation of PVT. For this reason, in a method in which GND or VDD is simply floated electrically, it is difficult to stabilize the potential of GND or VDD with respect to fluctuations in PVT, and as a result, there is a possibility that the retention characteristics may deteriorate.

  Therefore, in the first embodiment, an example of a semiconductor memory capable of stabilizing the GND or VDD potential even when the PVT varies is given. FIG. 2 is a schematic diagram illustrating a schematic configuration example of the semiconductor memory according to the first embodiment.

  As shown in FIG. 2, the semiconductor memory 1 according to the first embodiment operates in a subthreshold region with respect to a memory cell array 10A composed of a plurality of two-dimensionally arranged SRAM cells, thereby causing leakage current (1). To (3) are provided with three types of transistors 11 to 13. The number of each of the transistors 11 to 13 is not limited to one, and may be appropriately set according to the scale of each leakage current (1) to (3) generated in the memory cell array 10A.

  The PMOS transistor 11 is a transistor for suppressing the off-leakage current (2) in the PMOS transistor constituting the inverter. The PMOS transistor 11 generates a GND potential with high accuracy by flowing a leak current equivalent to the leak current (2) generated in the entire memory cell array 10A.

  One of the NMOS transistors 12 and 13 (which will be referred to as the NMOS transistor 12) is a transistor for suppressing the leakage current (1) in the NMOS transistor constituting the transfer gate, and the other (this is referred to as the NMOS transistor 13). Is a transistor for suppressing off-leakage current (3) in the NMOS transistor constituting the inverter. These NMOS transistors 12 and 13 each generate a GND potential with high accuracy by flowing a leak current equivalent to the leak current (1) or (3) generated in the entire memory cell array 10A.

The total amount of leakage currents (1) to (3) generated in the memory cell array 10A can be expressed by the following equation (1). Therefore, in the first embodiment, the types (NMOS transistors or PMOS transistors) and sizes (gate width W and gate length L) of each of the three types of transistors 11 to 13 are compensated so that the amount of current represented by Expression (1) is compensated. ) Is adjusted. In Equation (1), Id is a leakage current amount, β is a gain coefficient, V _GS is a gate-source voltage, V _TH is a threshold voltage, and γ is a back of the threshold voltage V _TH . _BSB is a source-back gate voltage, η is a channel length modulation effect coefficient, and V _DS is a drain-source voltage.

  Subsequently, a more specific configuration example of the semiconductor memory according to the first embodiment will be described below. FIG. 3 is a schematic diagram illustrating a more specific configuration example of the semiconductor memory according to the first embodiment. As shown in FIG. 3, the semiconductor memory 100 according to the first embodiment is generated in a memory cell array 100A including a plurality of SRAM cells 10aa, 10ab,..., 10ba, 10bb,. And a bias circuit 100B that compensates for leakage current. In the following description, when the SRAM cells 10aa, 10ab,..., 10ba, 10bb,.

  The SRAM cell 10 may be a general SRAM cell, and may have a structure similar to that of the SRAM cell 10 illustrated in FIG. In that case, the leak currents (1) to (3) described with reference to FIG. 1 are generated in the memory cell array 100A. GND1 of the memory cell array 100A is connected to the bias circuit 100B as a virtual power supply voltage VDD2 (corresponding to the first ground).

  The bias circuit 100B will be described with reference to an enlarged view shown in FIG. As shown in FIG. 4, the bias circuit 100 </ b> B includes two types of cells 101 and 102 having a structure substantially similar to that of the SRAM cell 10. The number of each of the cells 101 and 102 is not limited to one, and is appropriately set according to the scale of the leak currents (1) to (3) generated in the memory cell array 100A. It is assumed that the magnitude of the leakage current generated in the memory cell array 100A is the amount of current given by the above equation (1).

  A cell 101 having substantially the same structure as the SRAM cell 10 includes two PMOS transistors 111 and 112 included in two cross-connected inverters, and two NMOS transistors 121 and 122 constituting a transfer gate. However, in the cell 101, the gates of the two NMOS transistors 121 and 122 constituting the transfer gate are connected to VDD2 instead of the word line via the wiring M121 or M122. In addition, nodes N1 and N2 in which three sources of the six transistors included in the cell 101 are gathered are connected to GND2 (second ground) via the wiring M111 or M112, respectively.

  Similarly, the cell 102 having a structure substantially similar to the SRAM cell 10 includes two NMOS transistors 133 and 134 included in two inverters that are cross-connected. However, in the cell 102, the gates of the two NMOS transistors constituting the transfer gate are connected to VDD2 instead of the word line via the wiring M131 or M132. Further, nodes N3 and N4, each of which gathers three sources of the six transistors constituting the cell 102, are connected to VDD2 via the wiring M133 or M134, respectively.

  The two PMOS transistors 111 and 112 in the cell 101 operate so as to pass an off-leak current (11) equivalent to the off-leak current (1) in the entire memory cell array 100A. Thereby, the off-leakage current (2) is compensated. Similarly, the two NMOS transistors 121 and 122 in the cell 101 operate so as to pass a leak current (12) equivalent to the leak current (2) in the entire memory cell array 100A.

  On the other hand, the two NMOS transistors 133 and 134 in the cell 102 operate so as to pass an off-leak current (13) equivalent to the off-leak current (3) in the entire memory cell array 100A.

  By connecting the bias circuit 100B having the above configuration to the GND 1 of the memory cell array 100A, leak currents (11) to (13) equivalent to the leak currents (1) to (3) in the entire memory cell array 100A are obtained. It is possible to flow. Thereby, the potential of GND1 can be stabilized.

  Further, the leak currents (1) to (3) in the entire memory cell array 100A change according to the change in PVT. In this case, the leak currents (11) to (13) in the bias circuit 100B also change in PVT. It changes similarly according to. That is, even when the total amount Id of the leakage currents (1) to (3) in the entire memory cell array 100A changes according to the variation of PVT, the leakage currents (11) to (13) of the equivalent current amount Id are biased. It is possible to flow through the circuit 100B. As a result, it becomes possible to stabilize the potential of GND1 against the variation of PVT.

  The cells 101 and 102 illustrated in FIG. 4 can be arranged adjacent to the memory cell array 100A in the column direction, for example, as shown in FIG. For the cells 101 and 102, a general SRAM cell layout as illustrated in FIG. 1 can be used. FIG. 5 is a schematic diagram illustrating a layout example of the cell 101. FIG. 6 is a schematic diagram illustrating a layout example of the cell 102.

  As shown in FIG. 5, the cell 101 forms two inverters that are cross-connected to diffusion regions 141 to 144 formed in the same semiconductor layer, similarly to the layout of a general SRAM cell (see, for example, FIG. 1). And four transistors constituting a transfer gate for reading and writing are formed. These six transistors can be formed in the same layer as the transistors constituting the SRAM cell 10. That is, the SRAM cell 10 and the cell 101 have the same underlayer. However, the gate MG121 of the NMOS transistor 121 and the gate MG122 of the NMOS transistor 122 are connected to the wiring M11 or M12 forming VDD2 via the wiring M121 or M122. In addition, the wirings M14 and M16 that become the nodes N1 and N2 where the sources of the three transistors constituting the two inverters of the cell 101 gather are connected to the wiring M13 or M15 forming the GND2 through the wiring M111 or M112. Is done. Further, the connection between the gate of the transfer gate (corresponding to MG121 and MG122) provided in the normal SRAM cell and the word line is deleted.

  On the other hand, as shown in FIG. 6, the cell 102 similarly has four transistors constituting two inverters cross-connected to the diffusion regions 151 to 154 formed in the same semiconductor layer, and transfer for reading and writing. It has a structure in which two transistors constituting a gate are formed. Similar to the cell 101, these six transistors can be formed in the same layer as the transistors constituting the SRAM cell 10. That is, the cell 102 also has the same underlayer as the SRAM cell 10. However, the gates MG131 and MG132 of the two NMOS transistors constituting the transfer gate are respectively connected to the wiring M21 or M22 forming VDD2 via the wiring M131 or M132. In addition, the wirings M24 and M26 serving as the nodes N3 and N4 where the sources of the three transistors constituting the two inverters of the cell 102 gather are connected to the wiring M23 or M25 forming VDD2 through the wiring M133 or M134. Has been. Further, the connection between the gate of the transfer gate (corresponding to MG131 and MG132) provided in the normal SRAM cell and the word line is deleted.

  In the above structure, the wirings M111, M112, M121, M122, and M131 to M134 may be metal wirings. Therefore, these metal wirings M111, M112, M121, M122, and M131 to M134 are formed in the same layer and in the same process as other metal wirings such as VDD2 and GND2 (for example, wirings M11 to M16, M21 to M26, etc.). Can do. That is, the semiconductor memory 100 according to the first embodiment can be easily manufactured by diverting the existing SRAM cell layout and manufacturing process. Therefore, it is possible to manufacture at low cost without requiring an increase in cost due to layout change or process addition.

  As described above, in the first embodiment, the leakage currents (11) to (13) equivalent to the leakage currents (1) to (3) generated in the entire memory cell array 100A can be passed through the bias circuit 100B. Therefore, the potential of GND1 can be stabilized. Further, when the leakage currents (1) to (3) change according to the PVT fluctuation, the leakage currents (11) to (13) in the bias circuit 100B also change according to the PVT fluctuation. In contrast, the potential of GND1 can be stabilized. Furthermore, since the semiconductor memory according to the first embodiment can be easily manufactured by using the layout and manufacturing process of the existing SRAM cell, it is not necessary to increase the cost due to the layout change or the process addition. It can be manufactured at low cost.

Embodiment 2
Next, the semiconductor memory according to the second embodiment will be described in detail with reference to the drawings. In the following description, the same configurations and operations as those of the first embodiment are denoted by the same reference numerals, and redundant description thereof is omitted.

  FIG. 7 is a schematic diagram illustrating a specific configuration example of the semiconductor memory according to the second embodiment. As illustrated in FIG. 7, the semiconductor memory 200 according to the second embodiment includes a memory cell array 100A, a ring oscillator 210, and a charge pump circuit 220. The memory cell array 100A may be the same as the memory cell array 100A illustrated in the first embodiment.

  Ring oscillator 210 is constituted by a plurality of inverters 211 to 215 connected in series, for example. This ring oscillator 210 can perform the same function as a switched capacitor connected to GND1. That is, the ring oscillator 210 outputs a periodic voltage signal when the potential generated at the GND 1 exceeds a certain value. As a result, the charge accumulated in GND1 is consumed and the potential of GND1 decreases. In this manner, the ring oscillator 210 acts to lower the potential of the GND1 when the potential of the GND1 exceeds a certain value, so that the potential of the GND1 can be stabilized. In FIG. 7, the number of stages of the ring oscillator 210 is five. However, the number of stages is not limited to this. For example, the number of ring oscillators 210 may be appropriately set according to the magnitude of the leak current generated in the memory cell array 100A.

  The voltage signal generated by the ring oscillator 210 may be boosted by the charge pump circuit 220 connected to the output stage of the ring oscillator 210 and supplied to the peripheral circuit. As a result, the consumption of the power supply voltage VDD by the peripheral circuit can be reduced.

  As described above, in the second embodiment, since the ring oscillator 210 that performs the same function as the switched capacitor is connected to the GND 1, the potential of the GND 1 can be stabilized as in the first embodiment. In addition, since the voltage signal generated by the ring oscillator 210 can be boosted by the charge pump circuit 220 and used as power for the peripheral circuit, consumption of the power supply voltage VDD by the peripheral circuit can also be reduced. Since other configurations, operations, and effects are the same as those of the first embodiment, detailed description thereof is omitted here. Note that ring oscillator 210 and / or charge pump circuit 220 may be provided on the same substrate as the semiconductor substrate on which memory cell array 100A is formed, or a substrate different from the semiconductor substrate on which memory cell array 100A is formed. May be provided.

  Here, the effect of suppressing the potential fluctuation according to the first and second embodiments will be described with reference to the simulation result shown in FIG. In FIG. 8, a one-dot broken line indicates a potential floating of GND1 when the bias circuit 100B according to the first embodiment is connected to GND1 (case 1), and a broken line connects the ring oscillator 210 according to the second embodiment to GND1. In this case (case 2), GND1 shows the potential lift, and the solid line simply shows the potential lift of GND1 when a diode composed of a transistor is connected to GND1 (case 3).

  As shown in FIG. 8, in the case 3 in which a diode composed simply of a transistor is connected to the GND 1, the potential floating of the GND 1 fluctuates relatively greatly with respect to the PVT fluctuation, whereas the case 1 of the first embodiment. Then, the potential lift of GND1 can be reduced to about 1/2 of that of Case 3. In addition, it can be seen that also in the case 2 of the second embodiment, the potential floating of the GND 1 can be reduced to about 1 / 1.7 of that in the case 3.

  As described above, according to the semiconductor memory according to the first and second embodiments, it is possible to suppress the potential fluctuation of the GND 1 with respect to the PVT fluctuation. Thereby, it is possible to reduce a decrease in retention characteristics due to PVT fluctuations.

Embodiment 3
Next, the semiconductor memory according to the third embodiment will be described in detail with reference to the drawings. In the following description, the same configurations and operations as those in the first or second embodiment are denoted by the same reference numerals, and redundant description thereof is omitted.

  In the third embodiment, another configuration example of the bias circuit according to the first embodiment will be described. FIG. 9 is a circuit diagram illustrating a schematic configuration example of the bias circuit according to the third embodiment. The schematic configuration of the semiconductor memory according to the third embodiment may be obtained by replacing the bias circuit 100B with the bias circuit 300 shown in FIG. 9 in the semiconductor memory 100 illustrated in FIG. 3, for example.

  As shown in FIG. 9, the bias circuit 300 includes four types of cells 310 to 340 each having a structure substantially similar to that of the SRAM cell 10. The number of cells 310 to 340 is not limited to one, and is appropriately set according to the scale of leakage currents (1) to (3) generated in a memory cell array (for example, memory cell array 10A shown in FIG. 2). It is assumed that the magnitude of the leakage current generated in the memory cell array is the amount of current given by the above equation (1).

  First, a schematic configuration example of the cell 310 will be described with reference to a circuit diagram shown in FIG. 9 and a cell layout example shown in FIG. As shown in FIGS. 9 and 10, the cell 310 includes two NMOS transistors 311 and 314 that form a transfer gate, two NMOS transistors 312 and 315 that form two inverters that are cross-connected, and a PMOS transistor 313. And 316. The gates of a total of four transistors 312, 313, 315 and 316 constituting two inverters are connected to each other by, for example, a metal wiring 317. A node to which the sources of the transistors 315 and 316 constituting one inverter and the source of the NMOS transistor 314 constituting the transfer gate are connected is connected to the GND 2 through a metal wiring 318. Further, the gate of the NMOS transistor 314 is connected to the GND 2 through the metal wiring 319.

  Next, a schematic configuration example of the cell 320 will be described with reference to a circuit diagram shown in FIG. 9 and a cell layout example shown in FIG. As shown in FIGS. 9 and 11, the cell 320 includes two NMOS transistors 321 and 324 constituting a transfer gate, two NMOS transistors 322 and 325 and two PMOS transistors 323 constituting two cross-connected inverters. And 326. The back gate of the PMOS transistor 323 is connected through a metal wiring 327 to a node to which the sources of the transistors 322 and 323 constituting the inverter and the source of the NMOS transistor 321 constituting the transfer gate are connected. Similarly, the back gate of the PMOS transistor 326 is connected through a metal wiring 328 to a node to which the sources of the transistors 325 and 326 constituting the inverter and the source of the NMOS transistor 324 constituting the transfer gate are connected. The gate of the NMOS transistor 324 is connected to VDD2 through the metal wiring 329.

  Next, a schematic configuration example of the cell 330 will be described with reference to a circuit diagram shown in FIG. 9 and a cell layout example shown in FIG. As shown in FIGS. 9 and 12, the cell 330 includes two NMOS transistors 331 and 334 constituting a transfer gate, two NMOS transistors 332 and 335 and two PMOS transistors 333 constituting two inverters cross-connected. And 336. The gate of the NMOS transistor 331 constituting the transfer gate is connected to VDD2 through the metal wiring 337. The back gate of the PMOS transistor 336 is connected via a metal wiring 338 to a node to which the sources of the transistors 335 and 336 constituting the inverter and the source of the NMOS transistor 334 constituting the transfer gate are connected. The gate of the NMOS transistor 334 is connected to the GND 2 through the metal wiring 339.

  Further, a schematic configuration example of the cell 340 will be described with reference to a circuit diagram shown in FIG. 9 and a cell layout example shown in FIG. As shown in FIGS. 9 and 13, the cell 340 includes two NMOS transistors 341 and 344 that form a transfer gate, two NMOS transistors 342 and 345 that form two inverters that are cross-connected, and a PMOS transistor 343. And 346. The gate of the NMOS transistor 341 constituting the transfer gate is connected to the GND 2 via the metal wiring 347. On the other hand, the gate of the NMOS transistor 344 constituting the transfer gate is connected to VDD2 via the metal wiring 349. The back gate of the PMOS transistor 343 is connected through a metal wiring 348 to a node where the sources of the transistors 342 and 343 constituting the inverter and the source of the NMOS transistor 341 constituting the transfer gate are connected.

  The bias circuit 300 having the above configuration operates so that a leak current (21) equivalent to the leak current (1) in the entire memory cell array 100A flows to the cells 330 and 340. Further, the operation is performed so that the leak current (22) equivalent to the leak current (2) in the entire memory cell array 100A flows to the cell 310. Further, the operation is performed so that the leak current (23) equivalent to the leak current (3) in the entire memory cell array 100A flows to the cell 320. Therefore, by connecting the bias circuit 300 having the above configuration to the GND 1 of the memory cell array 100A, the leakage currents (21) to (23) equivalent to the leakage currents (1) to (3) in the entire memory cell array 100A. ). Thereby, the potential of GND1 can be stabilized. Since other configurations, operations, and effects are the same as those of the above-described embodiment, detailed description thereof is omitted here.

Embodiment 4
Next, a semiconductor memory according to Embodiment 4 will be described in detail with reference to the drawings. In the second embodiment described above, the configuration in the case where the voltage signal generated from the potential generated in the GND 1 of the memory cell array 100A is supplied as the power of the peripheral circuit is exemplified. On the other hand, in the fourth embodiment, an example will be described in which a substrate bias voltage is generated from a potential generated at GND1 of the memory cell array 100A. Note that in the following description, the same configurations and operations as those in any of Embodiments 1 to 3 are denoted by the same reference numerals, and redundant description thereof is omitted.

  FIG. 14 is a schematic diagram illustrating a specific configuration example of the semiconductor memory according to the fourth embodiment. As illustrated in FIG. 14, the semiconductor memory 400 according to the fourth embodiment includes a memory cell array 100 </ b> A and a substrate bias generation circuit 401. The memory cell array 100A may be the same as the memory cell array 100A in the semiconductor memory 200 illustrated in FIG. 7, for example. Further, the substrate bias generation circuit 401 may be provided on the same substrate as the semiconductor substrate on which the memory cell array 100A is formed, or may be provided on a substrate different from the semiconductor substrate on which the memory cell array 100A is formed. Good.

  The substrate bias generation circuit 401 is connected to the GND 1 of the memory cell array 100A, and generates a substrate bias voltage from the potential generated at the GND 1. Here, the substrate bias generation circuit 401 illustrated in FIG. 14 is a substrate bias generation circuit for a PMOS transistor. Therefore, the output of the substrate bias generation circuit 401 is connected to the N well (N-WELL) of each PMOS transistor in the memory cell array 100A. FIG. 15 shows a schematic configuration example of a substrate bias generation circuit for a PMOS transistor.

  As shown in FIG. 15, the substrate bias generation circuit 401P for the PMOS transistor includes a ring oscillator 410 and a charge pump circuit 420.

  The ring oscillator 410 is composed of, for example, a plurality of inverters 411 to 415 connected in series as in the ring oscillator 210 in the second embodiment described above, and can perform the same function as the switched capacitor connected to the GND 1. Therefore, when the potential generated at GND1 exceeds a certain value, ring oscillator 410 oscillates and charges accumulated in GND1 are consumed. As a result, the potential of GND1 is lowered, so that the potential of GND1 is stabilized. It should be noted that the number of stages of ring oscillator 410 may be appropriately set according to, for example, the magnitude of leakage current generated in memory cell array 100A.

  The charge pump circuit 420 has a configuration in which a plurality (five in FIG. 15) of NMOS transistors Q21 to Q25, each having a gate-drain connection, are connected in series. Each of the NMOS transistors Q21 to Q25 constitutes an amplification stage. Each wiring for connecting the amplification stages in series is branched and connected to the wiring for connecting the inverters 411 to 415 in series via capacitors C21 to C24, respectively. Note that the number of stages of the charge pump circuit 420 may be appropriately set according to, for example, the size of the leak current generated in the memory cell array 100A and the necessary amplification factor.

  The GND1, that is, the virtual power supply voltage VDD2 connected to the memory cell array 100A is connected to each of the inverters 411 to 415 of the ring oscillator 410 and the gate and drain of the first stage NMOS transistor Q21 in the charge pump circuit 420, respectively. The Therefore, when the ring oscillator 410 oscillates when the potential generated at GND1 exceeds a certain value, the capacitors C21 to C24 of each stage are charged, whereby the potential of each wiring connecting the NMOS transistors Q21 to Q25 is changed. Boosted.

  On the other hand, the NMOS transistors Q21 to Q24 in each amplification stage in the charge pump circuit 420 amplify the potential of VDD2 or the wiring connected to the previous amplification stage and output it to the wiring connected to the subsequent amplification stage. As a result, the substrate bias voltage V_high boosted to a voltage value higher than the power supply voltage VDD1 is output from the NMOS transistor Q25 in the final amplification stage. This substrate bias voltage V_high is applied to the N well (N-WELL) of each PMOS transistor in the memory cell array 100A.

  Thus, by applying the substrate bias voltage V_high generated by the charge pump circuit 420 to the N well of each PMOS transistor in the memory cell array 100A, the potential of the N well of each PMOS transistor can be raised. Thereby, the leakage current at the time of retention can be further reduced.

  If the MOS transistor of the memory cell array 100A has a triple well structure, the substrate bias voltage V_high generated by the substrate bias generation circuit 401P can be applied to the N well of each NMOS transistor in the memory cell array 100A. Thereby, the leakage current at the time of retention can be further reduced.

  Further, instead of the substrate bias generation circuit 401P shown in FIG. 15 or together with the substrate bias generation circuit 401P, a substrate bias generation circuit for NMOS transistors can be mounted on the semiconductor memory 400 as the substrate bias generation circuit 401. It is. FIG. 16 shows a schematic configuration example of a substrate bias generation circuit for an NMOS transistor.

  As illustrated in FIG. 16, the substrate bias generation circuit 401N for the NMOS transistor includes a ring oscillator 430 and a charge pump circuit 440.

  The ring oscillator 430 is composed of, for example, a plurality of inverters 431 to 435 connected in series like the ring oscillator 410 in the substrate bias generation circuit 401P for the PMOS transistor, and performs the same function as the switched capacitor connected to GND1. obtain. Therefore, when the potential generated at GND1 exceeds a certain value, ring oscillator 430 oscillates and charges accumulated in GND1 are consumed. As a result, the potential of GND1 is lowered, so that the potential of GND1 is stabilized. It should be noted that the number of stages of ring oscillator 430 may be appropriately set according to, for example, the magnitude of leakage current generated in memory cell array 100A.

  The charge pump circuit 440 has a configuration in which a plurality (five in FIG. 16) of PMOS transistors Q41 to Q45, each having a gate-drain connection, are connected in series. However, the gate inputs of the PMOS transistors Q41 to Q45 are inverted. Each of the PMOS transistors Q41 to Q45 constitutes an amplification stage. The wiring for connecting the amplification stages in series is branched and connected to the wiring for connecting the inverters 431 to 435 in series via the capacitors C41 to C44, respectively. Note that the number of stages of the charge pump circuit 440 may be set as appropriate according to, for example, the magnitude of the leakage current generated in the memory cell array 100A, the necessary amplification factor, and the like, similar to the ring oscillator 430.

  The GND 1 connected to the memory cell array 100 A, that is, the virtual power supply voltage VDD 2 is connected to the inverters 431 to 435 of the ring oscillator 430. Therefore, when the ring oscillator 430 oscillates when the potential generated at GND1 exceeds a certain value, the capacitors C41 to C44 of each stage are charged, thereby boosting the potential of the wiring connecting the PMOS transistors Q41 to Q45. Is done.

  On the other hand, the PMOS transistors Q41 to Q44 of each amplification stage in the charge pump circuit 440 amplify the ground potential or the potential of the wiring connected to the previous amplification stage and output it to the wiring connected to the subsequent amplification stage. As a result, a negative substrate bias voltage V− is output from the PMOS transistor Q45 in the final amplification stage. The substrate bias voltage V− is applied to the semiconductor substrate on which the memory cell array 100A is formed.

  In this way, by applying the substrate bias voltage V− generated by the charge pump circuit 440 to the semiconductor substrate on which the memory cell array 100A is formed, the substantial threshold voltage of each NMOS transistor increases. It is possible to further reduce the leakage current.

  As described above, the configuration including the ring oscillator 410/430 and the charge pump circuit 420/440 generates the substrate bias voltage V_high and / or V− for further reducing the leakage current at the time of retention. The circuit 401 can also be used. Since the substrate bias generation circuit 401 configured in this manner automatically operates when the leakage current exceeds a certain value, in addition to stabilization of the potential of the GND 1 due to the oscillation of the ring oscillator 410/430, the effect It is also possible to achieve an effect that the leakage current can be reduced at a proper timing.

  Other configurations, operations, and effects are the same as those in the above-described embodiment, and thus redundant description is omitted here.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  10A, 100A ... memory cell array, 10 ... SRAM cell, 11-13 ... transistor, 1,100, 200, 400 ... semiconductor memory, 100B, 300 ... bias circuit, 101, 102, 310-340 ... cell, 111, 112, 313, 316, 323, 326, 333, 336, 343, 346 ... PMOS transistors, 121, 122, 133, 134, 311, 312, 314, 315, 321, 322, 324, 325, 331, 332, 334, 335 , 341, 342, 344, 345 ... NMOS transistors, 141-144, 151-154 ... diffusion regions, M11-M16, M21-M26, M111, M112, M121, M122, M131-M134 ... wiring, MG121, MG122, MG131 , MG132 ... , 317 to 319, 327 to 329, 337 to 339, 347 to 349 ... metal wiring, 210, 410, 430 ... ring oscillator, 220, 420, 440 ... charge pump circuit, 401, 401P, 401N ... substrate bias generation circuit

Claims (10)

A memory cell array composed of a plurality of SRAM cells each including a first NMOS transistor and a first PMOS transistor;
A bias circuit connected to a first ground line or a power supply voltage line of the memory cell array;
With
The bias circuit includes a second NMOS transistor having the same channel length and the same channel width as the first NMOS transistor and having the same dopant and dose in the channel portion, and the same channel length as the first PMOS transistor. And a second PMOS transistor having the same channel width and the same dopant and dose in the channel portion,
The diffusion regions of the first and second NMOS transistors and the first and second PMOS transistors are formed in the same semiconductor layer,
The bias circuit includes one or more cells;
Each cell includes four transistors constituting two cross-connected inverters and two transistors constituting a transfer gate for reading and writing,
The NMOS transistor and the PMOS transistor correspond to any one or more of the four transistors constituting the two inverters and the two transistors constituting the transfer gate, respectively. Semiconductor memory.   The semiconductor memory according to claim 1, wherein the bias circuit is arranged in a column direction with respect to the memory cell array. The bias circuit includes one or more cells;
The semiconductor memory according to claim 1, wherein the cell has a layout structure common to the SRAM cell. The one or more cells of the bias circuit include a first cell and a second cell;
The four transistors of the first cell are two first NMOS transistors and two first PMOS transistors constituting the two inverters,
The transfer gate of the first cell includes two second NMOS transistors;
The one or more transistors of the second cell are two third NMOS transistors and two second PMOS transistors constituting the two inverters;
The transfer gate of the second cell includes two fourth NMOS transistors;
The gate of the second NMOS transistor and the gate of the fourth NMOS transistor are respectively connected to the first ground line,
The source of the first NMOS transistor, the source of the first PMOS transistor, and the source of the second NMOS transistor are connected to a second ground line different from the first ground line,
The source of the third NMOS transistor, the source of the second PMOS transistor, and the source of the fourth NMOS transistor are connected to the second ground line,
2. The NMOS transistor and the PMOS transistor correspond to any one or more of the first to fourth NMOS transistors and the first and second PMOS transistors, respectively. The semiconductor memory described in 1. The one or more cells of the bias circuit include first to fourth cells;
The four transistors of the first cell are two first NMOS transistors and two first PMOS transistors constituting the two inverters,
The transfer gate of the first cell includes two second NMOS transistors;
The four transistors of the second cell are two third NMOS transistors and two second PMOS transistors constituting the two inverters,
The transfer gate of the second cell includes two fourth NMOS transistors;
The four transistors of the third cell are two fifth NMOS transistors and two third PMOS transistors constituting the two inverters,
The transfer gate of the third cell includes two sixth NMOS transistors;
The four transistors of the fourth cell are two seventh NMOS transistors and two fourth PMOS transistors constituting the two inverters,
The transfer gate of the fourth cell includes two eighth NMOS transistors;
In the first cell,
A gate of the first NMOS transistor and a gate of the first PMOS transistor are connected to each other;
A source of each of the first NMOS transistor and the first PMOS transistor constituting one of the two inverters and a source of the second NMOS transistor are different from the first ground line. Connected to the ground wire,
One gate of the two second NMOS transistors is connected to the second ground line,
In the second cell,
The back gate of each of the two second PMOS transistors is connected to the source of the second PMOS transistor,
One gate of the two fourth NMOS transistors is connected to the first ground line,
In the third cell,
The back gate of one of the two third PMOS transistors is connected to the source of the third PMOS transistor,
One gate of the two sixth NMOS transistors is connected to the first ground line, and the other gate is connected to the second ground line.
In the fourth cell,
One back gate of the two fourth PMOS transistors is connected to the source of the fourth PMOS transistor;
One gate of the two eighth NMOS transistors is connected to the first ground line, and the other gate is connected to the second ground line.
2. The NMOS transistor and the PMOS transistor correspond to any one or more of the first to eighth NMOS transistors and the first to fourth PMOS transistors, respectively. The semiconductor memory described in 1. The semiconductor memory according to claim 1, wherein the leakage current of the bias circuit is expressed by the following formula (1).

A memory cell array including a plurality of SRAM cells;
A ring oscillator connected to a ground line of the memory cell array;
A semiconductor memory comprising:   8. The semiconductor memory according to claim 7, further comprising a charge pump circuit connected to an output stage of the ring oscillator. A charge pump circuit for amplifying the voltage of the ground line based on the output voltage of each of the plurality of inverters constituting the ring oscillator;
A power supply voltage line of the ring oscillator is connected to the ground line of the memory cell array,
The semiconductor memory according to claim 7, wherein an output of the charge pump circuit is connected to a semiconductor substrate on which the memory cell array is formed. The memory cell array includes one or more PMOS transistors,
The semiconductor memory according to claim 9, wherein the output of the charge pump circuit is connected to a well of the one or more PMOS transistors in the semiconductor substrate.

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