JP2017049714A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for making it difficult to manufacture an illegal copy product of a semiconductor memory device.SOLUTION: In a memory controller 30, a read control unit 332 instructs a semiconductor memory 40 to read, on the basis of an address included in a received read command, data at the address which is included in the read command. A latency acquisition unit 32 obtains a fixed latency period 51 that is used for determining a transmission timing of the data included in the read command and is identical to a latency period that is held by a host device. A transmission control unit 333 transmits the data at the address included in the read command to the host device at a timing which is determined on the basis of the fixed latency period 51.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a memory controller that accesses a semiconductor memory in response to a request from a host device.

  The semiconductor memory device includes a memory controller and a semiconductor memory such as a NAND flash memory. When receiving a data read instruction or a data write instruction from the host device, the memory controller controls access to the semiconductor memory in accordance with the instruction from the host device.

  Conventionally, various measures such as authentication and data encryption have been taken in order to ensure the security of data such as contents stored in a semiconductor memory. In the case of using authentication, the host device and the memory controller read data stored in the semiconductor memory after confirming the validity of each other. When encryption is used, the memory controller encrypts data read from the semiconductor memory and transmits the encrypted data to the host device. Alternatively, the memory controller encrypts the data, writes it to the semiconductor memory, decrypts the encrypted data read from the semiconductor memory, and transmits it to the host device.

  Patent Document 1 discloses a semiconductor memory device that encrypts read data when the data read from the memory cell is output to the outside. When receiving a read command from the outside, the semiconductor memory device reads data at an address designated by the read command from the memory cell. The semiconductor memory device encrypts the read data by taking an exclusive OR of the read data and the address specified by the read command using a logic circuit mounted therein. The semiconductor memory device outputs the encrypted data as a response to the read command.

JP-A-7-219852

  When encryption is used as in the semiconductor memory device according to Patent Document 1, the encryption key may be stolen by a malicious third party. When the encryption key is stolen, the security of the data stored in the semiconductor memory device is invalidated. Even when security is ensured by authentication, the security of data stored in the semiconductor memory is invalidated by stealing a password or the like used for authentication.

  If a third party succeeds in stealing the encryption key or password used to access the semiconductor memory device, the third party can read all the data stored in the semiconductor memory. It is possible to easily create a copy of stored data. As a result, there is a problem that illegal copies of semiconductor memory devices are distributed in the market.

  An object of the present invention is to provide a technique that makes it difficult to manufacture an illegal duplicate of a semiconductor memory device.

  In order to solve the above problem, the invention according to claim 1 is a memory controller that accesses a semiconductor memory in response to a request from a host device, and based on an address included in a read command received from the host device, A read control unit that instructs the semiconductor memory to read data at the address, and a latency that is used to determine the transmission timing of the data at the address and acquires a fixed latency period that is the same as the latency period held by the host device An acquisition unit; and a transmission control unit that transmits the data of the address to the host device at a timing determined based on the fixed latency period.

  According to a second aspect of the present invention, in the memory controller according to the first aspect, the transmission control unit outputs data at an address included in the read command before the fixed latency period elapses from a predetermined timing. When it is notified from the semiconductor memory that the data can be transferred, the data at the address is transmitted at the timing when the fixed latency period has elapsed.

  A third aspect of the present invention is the memory controller according to the first or second aspect, wherein the transmission control unit conceals a busy signal transmitted before transmission of data at the address is started.

  The invention according to claim 4 is the memory controller according to claim 3, wherein the transmission control unit conceals at least one of a transmission period of the busy signal and a value of the busy signal.

  The invention according to claim 5 is the memory controller according to claim 4, further comprising a random number generator for generating a random number, wherein the transmission control unit uses a random number generated by the random number generator. Thus, at least one of the busy signal transmission period and the busy signal value is concealed.

  A sixth aspect of the present invention is the memory controller according to any one of the first to fifth aspects, wherein the latency acquisition unit updates the fixed latency period when a predetermined condition is satisfied.

  The invention according to claim 7 is the memory controller according to claim 6, wherein the latency acquisition unit updates the fixed latency period after the data of the address is transmitted by the transmission control unit.

  The invention according to claim 8 is the memory controller according to any one of claims 1 to 7, wherein the data of the address is further transmitted at a timing determined based on the fixed latency period, or A determination unit configured to determine whether to transmit data when the read control unit can read the data at the address;

  The invention according to claim 9 is the memory controller according to claim 1, wherein the latency acquisition unit is generated by the random number generator using a random number generator that generates a random number and a predetermined algorithm. A latency generation unit that generates the fixed latency period from a random number.

  A tenth aspect of the present invention is the memory controller according to the first aspect, wherein the latency acquisition unit acquires a fixed latency period generated by the host device.

  The invention according to claim 11 is a memory system, comprising: a host device; a semiconductor memory; and a memory controller that accesses the semiconductor memory in response to a request from the host device. Based on the address included in the read command received from the host device, the read control unit that instructs the semiconductor memory to read the data at the address, and the fixed latency period used to determine the transmission timing of the data at the address A latency acquisition unit that transmits the address data to the host device at a timing determined based on the fixed latency period, and the host device stores the fixed latency period. And determined based on the fixed latency period. Provided that the access control unit for receiving the data of the address from the memory controller at a timing, the.

  A twelfth aspect of the present invention is the memory system according to the eleventh aspect, wherein the access control unit receives the data at the address and passes the preset latency period until a predetermined period elapses. The transmission control unit updates the fixed latency period from the transmission of the address data until a preset period elapses.

  The invention according to claim 13 is the memory system according to claim 11 or 12, wherein the memory controller further includes a first random number generator for generating a first random number, and the host device is And a second random number generator for generating a second random number, wherein each of the latency acquisition unit and the access control unit uses the predetermined algorithm to fix the fixed number from the first random number and the second random number. Generate a latency period.

  The memory controller according to the present invention transmits the address data included in the read command at a timing determined based on the fixed latency period. As a result, it is possible to make it difficult to manufacture an illegal duplicate of the semiconductor memory device including the memory controller according to the present invention.

  In addition, the memory controller according to the present invention conceals the busy signal that is transmitted until transmission of data at the address included in the read command is started. As a result, when data at an address included in the read command is transmitted from the memory controller to the host device, it is difficult to specify this data by a third party.

It is a functional block diagram which shows the structure of the memory system which concerns on embodiment of this invention. It is a functional block diagram which shows the structure of the host apparatus shown in FIG. FIG. 2 is a functional block diagram showing a configuration of the semiconductor memory device shown in FIG. 1. FIG. 2 is a functional block diagram illustrating a configuration of the semiconductor memory illustrated in FIG. 1. FIG. 3 is a sequence diagram showing operations of a host device and a memory controller when determining a fixed latency period shown in FIG. 2. FIG. 3 is a sequence diagram showing operations of the host device and the memory controller when the host device shown in FIG. 1 transmits a read command including a normal address. FIG. 2 is a diagram illustrating a transmission timing of read data when the memory controller illustrated in FIG. 1 executes variable latency processing. FIG. 3 is a sequence diagram showing operations of the host device and the memory controller when the host device shown in FIG. 1 transmits a read command including a target address. FIG. 2 is a diagram illustrating a transmission timing of read data when the memory controller illustrated in FIG. 1 executes a fixed latency process. It is a figure which shows the timing which the memory controller of a duplicate product transmits read data. FIG. 8 is a diagram illustrating another example of read data transmission timing when the memory controller illustrated in FIG. 1 executes fixed latency processing.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

{1. Memory system configuration}
{1.1. overall structure}
FIG. 1 is a functional block diagram showing a configuration of a memory system 100 according to an embodiment of the present invention. As shown in FIG. 1, the memory system 100 includes a host device 10 and a semiconductor memory device 20. The semiconductor memory device 20 includes a memory controller 30 and a semiconductor memory 40.

  The memory controller 30 accesses the semiconductor memory 40 in response to a request from the host device 10.

  The semiconductor memory 40 is nonvolatile, for example, a NAND flash memory. The semiconductor memory 40 stores a program 41, content data 42, and target address data 43. The program 41 is a program for using the content data 42. The target address data 43 is used to determine whether the memory controller 30 executes a fixed latency process or a variable latency process. Details of the fixed latency processing and the variable latency processing will be described later.

{1.2. Configuration of Host Device 10}
FIG. 2 is a functional block diagram showing the configuration of the host device 10 shown in FIG. As shown in FIG. 2, the host device 10 includes a CPU (Central Processing Unit) 11, a RAM (Random Access Memory) 12, a random number generator 13, and a host-side controller 14. The CPU 11, RAM 12, random number generator 13, and host-side controller 14 are connected via a bus.

  The CPU 11 executes a program loaded on the RAM 12 and controls the operation of the host device 10. The RAM 12 is a main memory of the host device 10.

  The random number generator 13 generates random numbers 13A and 13B used for generating the fixed latency period 51. The random number generator 13 generates a true random number. The generation timings of the random numbers 13A and 13B are different from each other. Therefore, the random numbers 13A and 13B have different values. The fixed latency period 51 is used when executing the fixed latency process. The fixed latency period 51 is used for determining the timing at which the memory controller 30 transmits data at the address included in the read command. Details of the fixed latency period 51 will be described later.

  The host-side controller 14 controls access to the semiconductor memory device 20 by the host device 10 in accordance with instructions from the CPU 11. The host-side controller 14 includes an access control unit 141, a latency generation unit 142, and a storage unit 143.

  The access control unit 141 transmits a command based on an instruction from the CPU 11 to the memory controller 30 and receives a response to the transmitted command.

  The latency generation unit 142 generates a fixed latency period 51 from the random number 13A and the random number 34A stored in the storage unit 143. The random number 34A is generated by the memory controller 30 as will be described later.

  The storage unit 143 stores the random number 13A, the random number 34A, the target address data 43, and the fixed latency period 51. The target address data 43 is transmitted from the memory controller 30 when the host device 10 is activated.

{1.3. Configuration of Memory Controller 30}
FIG. 3 is a functional block diagram showing a configuration of the semiconductor memory device 20 shown in FIG. As shown in FIG. 3, the memory controller 30 includes a command decoder 31, a latency acquisition unit 32, an access control unit 33, and a random number generator 34.

  The memory controller 30 is connected to the host-side controller 14. In FIG. 3, the display of the interface circuit (host I / F) with the host device 10 and the interface circuit (memory I / F) with the semiconductor memory 40 in the memory controller 30 is omitted.

  The command decoder 31 acquires a command transmitted from the host-side controller 14 and decodes the acquired command. For example, when receiving a read command, the command decoder 31 extracts an address included in the read command, and outputs a read instruction and the extracted address to the access control unit 33. Hereinafter, an address included in the read command is referred to as a “read address”.

  The latency acquisition unit 32 acquires a fixed latency period 51. The latency acquisition unit 32 includes a register 321, a register 322, and a latency generation unit 323.

  The register 321 stores the random number 13A generated by the random number generator 13 (see FIG. 2). The register 322 stores the random number 34A generated by the random number generator 34. The latency generation unit 323 generates a fixed latency period 51 from the random number 13A stored in the register 321 and the random number 34A stored in the register 322. The fixed latency period 51 generated by the latency generator 323 is the same as the fixed latency period 51 generated by the latency generator 142 of the host device 10 shown in FIG.

  The access control unit 33 reads data from the semiconductor memory 40 in response to a read command from the host device 10 and transmits the read data to the host-side controller 14. The access control unit 33 includes a determination unit 331, a read control unit 332, and a transmission control unit 333.

  The determining unit 331 uses the target address data 43 to determine whether the read address is a target for fixed latency processing. In the target address data 43, the address of the semiconductor memory 40 that is the target of the fixed latency process is registered. When the read address matches the address registered in the target address data 43, the determination unit 331 determines to execute the fixed latency process. If the read address does not match the address registered in the target address data 43, the determination unit 331 determines to execute variable latency processing. The variable latency process is the same as the normal read process.

  The read control unit 332 controls reading of data from the semiconductor memory 40. The read control unit 332 transmits an access control signal including a read address, and instructs the semiconductor memory 40 to read data.

  The read control unit 332 outputs data read from the semiconductor memory 40 to the transmission control unit 333 according to the access control signal. Hereinafter, data read from the semiconductor memory 40 in response to the read command is referred to as “read data 52”. Further, the read control unit 332 reads the target address data 43 from the semiconductor memory 40 when the memory controller 30 is activated. The read target address data 43 is output to the determination unit 331 and the transmission control unit 333.

  The transmission control unit 333 executes either a fixed latency process or a variable latency process based on the determination result by the determination unit 331. In the variable latency process, the transmission control unit 333 starts transmission of the read data 52 to the host device 10 in accordance with the latency signal 54 output from the semiconductor memory 40. The latency signal 54 is a signal for notifying that data can be read from the semiconductor memory 40. In the variable latency process, the fixed latency period 51 is not used.

  On the other hand, in the fixed latency process, the transmission control unit 333 transmits the read data 52 after waiting until the fixed latency period 51 elapses after receiving the read command. The fixed latency period 51 is set to a period longer than the period from when the read control unit 332 instructs the semiconductor memory 40 to read the data at the read address until the data can be read from the semiconductor memory 40. . For example, when data at the address of page P-3 (see FIG. 4) is transmitted to the host device 10, the transmission timing of the data at the address of page P-3 is fixed latency processing than when variable latency processing is executed. Will be slower when running.

  The random number generator 34 generates random numbers 34A to 34C. The random numbers 34A and 34C are used to determine the fixed latency period 51. The random number 34B is used for transmission of a concealment signal to be described later. The generation timings of the random numbers 34A to 34C are different. Since the random number generator 34 generates a true random number, the random numbers 34A to 34C have different values.

{1.4. Configuration of Semiconductor Memory 40}
FIG. 4 is a functional block diagram showing a configuration of the semiconductor memory 40 shown in FIG. As shown in FIG. 4, the semiconductor memory 40 is composed of a single die. The die includes J blocks. The block includes N pages. J and N are both natural numbers of 1 or more. A block is a data erasing unit in the semiconductor memory 40. The page is a data reading unit and writing unit in the semiconductor memory 40.

  In the semiconductor memory 40, the block 40B is composed of pages P-1, P-2,. Target address data 43 is stored in page P-1. Programs 41A to 41C are stored in pages P-2 to P-4. The programs 41A to 41C constitute the program 41 shown in FIG. The programs 41A to 41C are generated by dividing the program 41 by the data size that can be stored in the page. Therefore, the programs 41A to 41C cannot be executed individually. Content data 42 is stored in page PN.

{2. Operation of memory system}
Hereinafter, determination of the fixed latency period 51, variable latency processing, fixed latency processing, and update of the fixed latency period 51 executed in the memory system 100 will be described. In the following description, a description of the logical address to physical address conversion process executed in the memory controller 30 is omitted.

{2.1. Determination of fixed latency period 51}
FIG. 5 is a sequence diagram showing operations of the host device 10 and the memory controller 30 when the fixed latency period 51 is determined.

  As an initial state, a reference time for determining the fixed latency period 51 is set in advance in the host device 10 and the memory controller 30. The reference time is the maximum time required for the memory controller 30 to receive the latency signal 54 output from the semiconductor memory 40 after instructing the semiconductor memory 40 to read data. That is, the reference time corresponds to the maximum time required for reading data from the semiconductor memory 40. The maximum time is obtained by measuring in advance the time from when the semiconductor memory 40 is instructed to read data to when the latency signal 54 is received. Alternatively, the maximum time may be determined according to the specifications of the semiconductor memory 40.

  The reference time may be recorded in a predetermined area of the semiconductor memory 40. In this case, the host device 10 acquires the reference time via the memory controller 30 at the time of activation.

  The sequence diagram shown in FIG. 5 is started when the host apparatus 10 is powered on. First, the operation of the host device 10 will be described. When the host device 10 is powered on, the CPU 11 instructs the random number generator 13 to generate the random number 13A. The random number generator 13 generates a random number 13A that is a true random number in response to an instruction from the CPU 11 (step S111). The generated random number 13A is output to the CPU 11 and the host-side controller 14.

  In the host-side controller 14, the access control unit 141 stores the random number 13A input from the random number generator 13 in the storage unit 143 (step S112).

  The CPU 11 generates a random number exchange command (step S113). The CPU 11 sets the random number 13A supplied from the random number generator 13 in the random number exchange command. The random number exchange command is a command for transmitting the random number 13A to the memory controller 30 and requesting transmission of the random number 34A and the target address data 43.

  The access control unit 141 acquires from the CPU 11 a random number exchange command in which the random number 13A is set. The host-side controller 14 transmits the acquired random number exchange command to the memory controller 30 (step S114). The access control unit 141 waits until a response to the random number exchange command is received.

  Next, the operation of the memory controller 30 will be described. The memory controller 30 is activated when the host device 10 is powered on. In the memory controller 30, the random number generator 34 generates a random number 34A (step S211). Similar to the random number generator 13, the random number generator 34 generates a true random number. Accordingly, the random numbers 13A and 34A generated immediately after the activation of the memory system 100 are different from each other.

  The random number generator 34 outputs the generated random number 34 </ b> A to the register 322 and the transmission control unit 333. The register 322 stores the output random number 34A (step S212).

  The memory controller 30 receives the random number exchange command transmitted from the host-side controller 14 in step S114. The memory controller 30 stores the random number 13A set in the received random number exchange command in the register 321 (step S213). Specifically, the command decoder 31 decodes the received random number exchange command, and determines that the host device 10 requests exchange of random numbers. The command decoder 31 extracts the random number 13A set in the random number exchange command and outputs it to the register 321. The register 321 stores the random number 13A output from the command decoder 31.

  The command decoder 31 notifies the read control unit 332 and the transmission control unit 333 that the random number exchange command has been received. In response to the notification from the command decoder 31, the read control unit 332 reads the target address data 43 from the semiconductor memory 40 (step S214).

  In response to the notification from the command decoder 31, the transmission control unit 333 acquires the target address data 43 from the read control unit 332, and acquires the random number 34 </ b> A from the random number generator 34. The transmission control unit 333 transmits the acquired random number 34A and the target address data 43 to the host device 10 as a response to the random number exchange command (step S215).

  The latency acquisition unit 32 generates a fixed latency period 51 (step S216). Specifically, the latency generation unit 323 calculates a fixed latency period 51 longer than the reference time from the random number 13A stored in the register 321 and the random number 34A stored in the register 322 using a preset algorithm. To do. The case where the fixed latency period 51 shorter than the reference time is calculated will be described later.

  The algorithm used for the calculation is not particularly limited. For example, a pseudo-random number generation algorithm, HMAC (Hash-based Message Authentication Code), or the like is used.

  When the fixed latency period 51 shorter than the reference time is calculated, the fixed latency period 51 may be generated again. In this case, the host device 10 transmits a random number exchange command including a new random number generated by the random number generator 13. When the memory controller 30 receives the random number exchange command, the memory controller 30 transmits the new random number generated by the random number generator 34 to the host device 10. The latency generation units 142 and 323 generate the fixed latency period 51 from the two new random numbers generated. Hereinafter, the host device 10 and the memory controller 30 may repeat the regeneration of the fixed latency period 51 until the fixed latency period 51 longer than the reference time is calculated.

  The latency generation unit 323 outputs the determined fixed latency period 51 to the transmission control unit 333. The transmission control unit 333 holds the fixed latency period 51 output from the latency generation unit 323. Thereby, the process at the time of starting of the memory controller 30 is completed.

  In the host device 10, the access control unit 141 receives the random number 34 </ b> A and the target address data 43 as a response to the random number exchange command. The access control unit 141 stores the received random number 34A and target address data 43 in the storage unit 143 (step S115).

  The latency generation unit 142 generates the fixed latency period 51 from the random numbers 13A and 34A stored in the storage unit 143 (Step S116). The algorithm used by the latency generation unit 142 to generate the fixed latency period 51 is the same as the algorithm used by the latency generation unit 323 of the memory controller 30. Therefore, the fixed latency period 51 generated by the latency generation unit 142 is the same as the fixed latency period 51 generated by the latency generation unit 323 of the memory controller 30.

{2.2. Variable latency processing}
When the memory controller 30 receives a read command including an address that is not registered in the target address data 43 from the host device 10, the memory controller 30 executes variable latency processing and transmits data at the address included in the read command.

  Hereinafter, an address registered in the target address data 43 is referred to as a “target address”, and an address that is not registered in the target address data 43 is referred to as a “normal address”.

  FIG. 6 is a sequence diagram illustrating operations of the host device 10 and the memory controller 30 when the host device 10 transmits a read command including a normal address as a read address.

  As illustrated in FIG. 6, the host device 10 executes Steps S311 to S314 and transmits a read command including a normal address to the memory controller 30. Specifically, the CPU 11 generates a read command and sets a read address in the generated read command. In the example shown in FIG. 6, the read address to be set is a normal address. Thereby, a read command including the normal address is generated (step S311).

  The CPU 11 outputs the generated read command to the access control unit 141. The access control unit 141 compares the read address included in the read command with the address registered in the target address data 43 (step S312).

  In the example shown in FIG. 6, the normal address is set as the read address in the read command, so the read address included in the read command does not match the address registered in the target address data 43. For this reason, when the access control unit 141 transmits a read command to the memory controller 30, the access control unit 141 determines that the memory controller 30 executes variable latency processing. The access control unit 141 determines to start access control for variable latency processing after transmission of the read command (step S313).

  The access control unit 141 transmits the read command generated in step S311 to the memory controller 30 (step S314). The access control unit 141 starts access control for variable latency processing by waiting until a ready signal is received from the memory controller 30.

  In the memory controller 30, the command decoder 31 receives the read command transmitted from the host device 10 in step S314. The command decoder 31 decodes the received read command. As a result, the command decoder 31 determines that reading has been instructed by the host device 10, and extracts a read address from the received read command (step S411).

  The command decoder 31 outputs the decoding result (read instruction and extracted read address) to the determination unit 331 and the read control unit 332. The determination unit 331 compares the read address acquired from the command decoder 31 with the address registered in the target address data 43 (step S412). In the example illustrated in FIG. 6, since the normal address is set as the read command in the read command, the acquired read address does not match the address registered in the target address data 43. For this reason, the determination unit 331 determines execution of variable latency processing (step S413).

  The transmission control unit 333 starts variable latency processing based on the determination by the determination unit 331. Specifically, the transmission control unit 333 starts transmission of a busy signal to the host device 10 (step S414). Transmission of the busy signal is continued until the transmission control unit 333 detects the latency signal 54 output from the semiconductor memory 40.

  The read control unit 332 outputs an access control signal including a read address to the semiconductor memory 40, and instructs to read data at the read address (step S415). After transmitting the access control signal, the read control unit 332 shifts to a waiting state for receiving the latency signal 54.

  The semiconductor memory 40 starts preparation for reading data at the read address based on the access control signal transmitted from the read control unit 332. When the read preparation is completed, the semiconductor memory 40 outputs the latency signal 54 to the read control unit 332 and the transmission control unit 333 to notify that the read address data can be output.

  The transmission control unit 333 detects the latency signal 54 transmitted from the semiconductor memory 40 (step S416). The transmission control unit 333 transmits a ready signal to the host device 10 based on the detected latency signal 54 (step S417).

  The semiconductor memory 40 starts outputting the read address data (read data 52) after outputting the latency signal 54. The transmission control unit 333 reads the read data 52 via the read control unit 332. The transmission control unit 333 transmits the read data 52 to the host device 10 following the ready signal (step S418).

  In the host device 10, the access control unit 141 determines that transmission of the read data 52 is started when a ready signal is detected. The access control unit 141 receives data transmitted after the ready signal as read data 52. The CPU 11 executes processing using the read data 52 received by the access control unit 141.

  FIG. 7 is a diagram illustrating the transmission timing of the read data 52 when the variable latency process is executed. As illustrated in FIG. 7, when the memory controller 30 determines that the read address does not match any of the addresses registered in the target address data 43, the memory controller 30 starts transmitting a busy signal immediately after receiving the read command. The transmission of the busy signal continues until the latency signal 54 from the semiconductor memory 40 is detected. When the latency signal 54 is detected, the memory controller 30 transmits a ready signal instead of the busy signal, and transmits read data 52 following the ready signal.

  The latency signal 54 is output when the read preparation in the semiconductor memory 40 is completed. However, since the time required for read preparation varies depending on the performance of the semiconductor memory 40, the read address, and the like, the busy signal transmission period Tb is not constant. For this reason, when the memory controller 30 executes the variable latency process, the host device 10 waits until a ready signal is received. The host device 10 receives the data transmitted following the ready signal as read data 52 using the ready signal as a trigger.

{2.3. Fixed latency processing}
When the read address matches the address registered in the target address data 43, the memory controller 30 executes fixed latency processing and transmits the read data 52. Unlike the variable latency process, in the fixed latency process, the transmission timing of the read data 52 is determined based on the fixed latency period 51.

  FIG. 8 is a sequence diagram illustrating operations of the host device 10 and the memory controller 30 when the host device 10 transmits a read command including a target address.

  The host device 10 executes steps S511 to S514 and transmits a read command including the target address to the memory controller 30. Specifically, the CPU 11 generates a read command and sets a read address in the generated read command. In the example shown in FIG. 8, the read address is the target address. As a result, a read command including the target address is generated (step S511).

  The CPU 11 outputs the generated read command to the access control unit 141. The access control unit 141 compares the read address included in the read command with the address registered in the target address data 43 (step S512).

  In the example shown in FIG. 8, the target address is set in the read command as the read address, so the read address matches any address registered in the target address data 43. Therefore, the access control unit 141 determines that the memory controller 30 executes the fixed latency process when the read command generated in step S511 is transmitted. The access control unit 141 determines to start the access control for fixed latency processing after the transmission of the read command (step S513).

  The access control unit 141 transmits the read command generated in step S511 to the memory controller 30 (step S514). The access control unit 141 waits until the fixed latency period 51 elapses after the read command is transmitted (step S515). The access control unit 141 receives a concealment signal from the memory controller 30 until the fixed latency period 51 elapses. As will be described later, since the concealment signal is random data, the access control unit 141 uses the fixed latency period 51 without using the concealment signal when specifying the reception timing of the read data 52.

  In the memory controller 30, the command decoder 31 receives the read command transmitted from the host device 10 in step S514. The command decoder 31 decodes the received read command. As a result, the command decoder 31 determines that reading has been instructed by the host device 10, and extracts a read address from the received read command (step S611).

  The command decoder 31 outputs the decoding result (read instruction and extracted read address) to the determination unit 331 and the read control unit 332. The determination unit 331 compares the read address acquired from the command decoder 31 with the address registered in the target address data 43 (step S612). In the example shown in FIG. 8, since the target address is set in the read command as the read address, the acquired read address matches any address registered in the target address data 43. For this reason, the determination unit 331 determines to execute the fixed latency process (step S613).

  The memory controller 30 executes steps S614 to S616 as fixed latency processing. The transmission control unit 333 starts transmission of the concealment signal instead of the busy signal (step S614). Specifically, the transmission control unit 333 continues to acquire the random number 34B from the random number generator 34 until the fixed latency period 51 elapses after receiving the read command, and transmits the acquired random number 34B as a concealment signal. That is, the concealment signal is continuously updated by the random number 34B generated by the random number generator 34 until the fixed latency period 51 elapses. Since the random number generator 34 generates the random number 34B at a timing different from the generation timing of the random number 34A, the random number 34B is different from the random number 34A. Transmission of the concealment signal is continued until the fixed latency period 51 elapses after the read command is received.

  The concealment signal has a random value. On the other hand, the patterns of the busy signal and the ready signal are set in advance. By transmitting the concealment signal instead of the busy signal and the ready signal, a third party cannot distinguish between the busy signal, the ready signal, and the read address data transmitted following the ready signal. That is, the transmission timing of the read data 52 is concealed by concealing the busy signal transmission period and the busy signal value by the random number 34B.

  Next, the read control unit 332 outputs an access control signal including the read address to the semiconductor memory 40, and instructs to read data at the read address (step S615). The semiconductor memory 40 starts preparation for reading data at the read address based on the access control signal output from the read control unit 332. When the read preparation is completed, the semiconductor memory 40 outputs a latency signal 54 to the transmission control unit 333 to notify that the read address data can be read.

  As described above, the fixed latency period 51 is longer than the reference time. The reference time is the maximum time taken from when the semiconductor memory 40 is instructed to read data to when the latency signal 54 is received from the semiconductor memory 40. Therefore, in the fixed latency process, the transmission control unit 333 detects the latency signal 54 during the standby period after the read command is received until the fixed latency period 51 elapses. However, even if the transmission control unit 333 detects the latency signal 54, the transmission control unit 333 does not start transmission of the read data 52 and continues to transmit the concealment signal.

  The transmission control unit 333 starts transmission of the read data 52 at the timing when the fixed latency period 51 elapses after the reception of the read command is completed (step S616). Specifically, the transmission control unit 333 stops the transmission of the concealment signal at the timing when the fixed latency period 51 elapses. The transmission control unit 333 reads the read data 52 from the semiconductor memory 40 via the read control unit 332. The transmission control unit 333 transmits the read data 52 to the host device 10 instead of the concealment signal.

  Here, the description returns to the host device 10. As described above, the access control unit 141 transmits a read command (step S514), and then waits until the fixed latency period 51 elapses (step S515). The access control unit 141 ignores the concealment signal received during standby. The access control unit 141 starts receiving the read data 52 at the timing when the fixed latency period 51 elapses (step S516). That is, the access control unit 141 receives data received after the timing when the fixed latency period 51 elapses as read data 52. Therefore, the host device 10 does not have to detect a ready signal when executing access control for fixed latency processing.

  FIG. 9 is a diagram illustrating the transmission timing of the read data 52 when the fixed latency process is executed. As illustrated in FIG. 9, the memory controller 30 receives a latency signal 54 indicating that the data at the read address can be read when the period Ts has elapsed after receiving the read command. However, the memory controller 30 ignores the latency signal 54 and waits until the fixed latency period 51 elapses. When the read address matches the address registered in the target address data 43, the memory controller 30 starts transmitting the concealment signal after receiving the read command. The concealment signal is a random number 34B generated by the random number generator 34. Therefore, even if a third party observes the signal transmitted from the memory controller 30, it cannot detect the busy signal and the ready signal. Since the memory controller 30 starts transmitting the read data 52 following the concealment signal when the fixed latency period 51 has elapsed, the third party cannot specify the transmission timing of the read data 52, and the read data 52 cannot be specified.

  The host device 10 and the memory controller 30 hold the same fixed latency period 51. Therefore, the host device 10 can specify the reception timing of the read data 52 based on the timing at which the transmission of the read command is completed and the fixed latency period 51. The memory controller 30 can specify the transmission timing of the read data 52 based on the timing when the reception of the read command is completed and the fixed latency period 51. Therefore, the host device 10 can specify the read data 52 transmitted from the memory controller 30 without using the busy signal and the ready signal.

  When the reference time used when generating the fixed latency period 51 is determined by measuring the latency signal 54, the memory controller 30 cannot detect the latency signal 54 before the fixed latency period 51 elapses. There is. In this case, the memory controller 30 cannot acquire the read data 52 and cannot transmit the read data 52 to the host device 10. The memory controller 30 transmits an error as a response to the read command at the timing when the fixed latency period 51 has elapsed. The host device 10 and the memory controller 30 execute update processing of the fixed latency period 51 described later. The updated fixed latency period 51 is preferably longer than the fixed latency period 51 before the update. Then, the host device 10 may transmit a read command to the memory controller 10 again.

  As described above, the memory controller 30 executes the fixed latency process when the read command including the target address is received. Since the fixed latency period 51 generated from the random numbers 13A and 34A is random, the third party cannot specify the fixed latency period 51. An illegally copied memory controller of a semiconductor memory device cannot reproduce the operation of the memory controller 30 that executes the fixed latency processing using the fixed latency period 51. Hereinafter, an illegally copied product of the semiconductor memory device 20 is simply referred to as a “replicated product”.

  For example, in FIG. 4, programs 41A to 41C are generated by simply dividing the program 41 based on the data size. When the address of the page P-3 is registered in the target address data 43, the memory controller 30 transmits the program 41B stored in the page P-3 by fixed latency processing. On the other hand, since the fixed latency period 51 is not specified by a third party, the copied memory controller cannot transmit the program 41B to the host device 10 by the fixed latency processing. When the duplicate product is connected to the host device 10, the host device 10 cannot reconfigure the program 41, and thus cannot use the program 41. In this way, a third party cannot manufacture a copy that can be used by the host device 10. Further, since the memory controller 30 conceals the busy signal and the ready signal using the random number 34B, a third party cannot specify the read data 52 transmitted to the host device 10 by the fixed latency process. Therefore, the third party cannot copy the data of the target address recorded in the semiconductor memory 40.

  Next, an address registered in the target address data 43 will be described. The addresses registered in the target address data 43 may be addresses of all pages of the semiconductor memory 40 or may be partial addresses. When some addresses are registered in the target address data 43, it is desirable that the registered addresses are addresses of data that is read at least once by the host device 10. For example, an address of an area where the host device 10 always accesses the semiconductor memory 40 such as an address of a page that stores the boot code of the host device 10 may be registered. Alternatively, an address of an area where the host device 10 is frequently accessed may be registered.

{2.4. Update of fixed latency period 51}
After the memory controller 30 transmits the read data 52 by the fixed latency process, the host device 10 and the memory controller 30 update the fixed latency period 51. The process of updating the fixed latency period 51 is the same as the flow for determining the fixed latency period 51 shown in FIG. However, when updating the fixed latency period 51, in the process shown in FIG. 5, the host device 10 generates a random number 13B different from the random number 13A and stores it in the storage unit 143 (steps S111 and S112). A random number exchange command in which the random number 13B is set is transmitted to the memory controller 30 (step S114). The memory controller 30 generates a random number 34C different from the random numbers 34A and 34B (step S211), and transmits the random number 34C as a response to the random number exchange command (step S215). As a result, the host device 10 and the memory controller 30 generate a fixed latency period 51 that is different from the fixed latency period 51 generated at startup. After the new fixed latency period 51 is generated (see step S116, FIG. 5), the host device 10 generates and transmits the next read command.

  For example, the update of the fixed latency period 51 is executed in the memory controller 30 after the data of the target address is transmitted until the next read command is received. In the host device 10, the update of the fixed latency period 51 is executed after the data of the target address is received until the next read command is generated. That is, the host device 10 and the memory controller 30 are updated within a preset period after the data reading process of the target address is completed. By aligning the timing for updating the fixed latency period 51, the host device 10 and the memory controller 30 can hold the same fixed latency period 51.

  Since the random number generators 13 and 34 generate genuine random numbers, the random numbers generated by the random number generators 13 and 34 are not reproducible. That is, the random numbers 13B and 34C used for updating the fixed latency period 51 are different from the random numbers 13A, 34A, and 34B, respectively. Since the fixed latency period 51 after the update is determined regardless of the fixed latency period 51 before the update, a third party cannot predict the fixed latency period after the update. Even if a third party can observe the concealment signal output from the memory controller 30 and specify the length of the concealment signal (fixed latency period 51), the fixed latency period 51 is updated. The specified fixed latency period 51 is not used when reading data of the next target address. Therefore, even if the third party can identify the fixed latency period 51, the third party cannot identify the updated fixed latency period 51. Therefore, the third party cannot specify the data of the next target address.

  Thus, in the memory system 100 according to the present embodiment, the host device 10 and the memory controller 30 each hold the same fixed latency period 51. When the memory controller 30 receives a read command including the target address from the host device 10, the memory controller 30 starts transmitting the data of the target address at a timing determined based on the fixed latency period 51. Reception of the data of the target address is started at a timing determined based on 51. Since the third party cannot specify the fixed latency period 51, the third party cannot reproduce the operation of the memory controller 30 that determines the transmission timing of the data of the target address based on the fixed latency period 51. Therefore, a third party cannot manufacture an illegal copy of the semiconductor memory device 20 that can be used by the host device 10.

  Further, since the fixed latency period 51 is concealed by the random number 34B, it becomes difficult for a third party to specify the read data 52, and tamper resistance can be improved. Further, by updating the fixed latency period 51, it becomes more difficult for a third party to specify the read data 52, so that tamper resistance can be further improved.

{Modification 1}
In the above-described embodiment, the host device 10 described an example of ignoring the concealment signal received in the fixed latency period 51 when executing access control for fixed latency processing, but is not limited thereto. The host device 10 may determine whether or not the semiconductor memory device 20 is an illegal duplicate by monitoring a signal received until the fixed latency period 51 elapses.

  FIG. 10 is a diagram illustrating the timing at which the replicated memory controller 30 transmits read data 52 when the host device 10 transmits a read command including a target address. When the host device 10 transmits a read command including the target address, the host device 10 can specify the reception timing of the ready signal in advance. Specifically, the host device 10 determines that the ready signal reception timing is immediately before the end of the fixed latency period 51.

  A replicated memory controller cannot perform fixed latency processing. Therefore, when a read command including a target address is received from the host device 10, the replicated memory controller transmits the read data 52 not by fixed latency processing but by normal read processing (variable latency processing). For example, when the memory controller of the duplicate product detects the latency signal 54 at time Td1, it transmits a ready signal at time Td1 before the fixed latency period 51 elapses. Alternatively, when the replica memory controller detects a ready signal after the fixed latency period 51 has elapsed, it transmits the ready signal after the fixed latency period 51 has elapsed.

  As a result, since the host device 10 receives the ready signal from the replica memory controller at a timing different from the reception timing specified in advance, it can be determined that the semiconductor memory device 20 that transmits the ready signal is a replica. .

{Modification 2}
In the above embodiment, the example in which the memory controller 30 determines whether the read address matches the target address with reference to the target address data 43 is not limited to this.

  The host device 10 may generate a read command including an instruction flag that instructs one of the variable latency processing and the fixed latency processing to be executed. In the read command, an instruction flag is added after the read address. For example, a flag for instructing variable latency processing is set to “00”, and a flag for instructing fixed latency processing is set to “01”. The memory controller 30 determines execution of variable latency processing or fixed latency processing according to the value of the instruction flag. In this case, the memory controller 30 does not have to execute the process of comparing the read address with the address registered in the target address data 43 (steps S412 and S612).

  Further, the host device 10 and the memory controller 30 may determine whether to execute the fixed latency process based on the length of the fixed latency period 51. In this case, threshold values used for comparison with the fixed latency period 51 are set in the host device 10 and the memory controller 30.

  When the host device 10 and the memory controller 30 generate the fixed latency period 51 by the processing shown in FIG. 5, the host apparatus 10 and the memory controller 30 compare the fixed latency period 51 with a threshold value. When the fixed latency period 51 is longer than the threshold value, the host device 10 executes access control for fixed latency processing, and the memory controller 30 executes fixed latency processing. After the host device 10 receives the read data 52, the fixed latency period 51 is updated in the host device 10 and the memory controller 30 and again compared with the threshold value.

  On the other hand, when the generated fixed latency period 51 is equal to or less than the threshold value, the host device 10 executes access control for variable latency processing, and the memory controller 30 executes variable latency processing. After the host device 10 receives the read data 52, the fixed latency period 51 is updated in the host device 10 and the memory controller 30 and again compared with the threshold value.

{Modification 3}
In the above-described embodiment, when the fixed latency process is executed, the memory controller 30 waits for the transmission of the read data 52 until the fixed latency period 51 elapses after receiving the read command. Not limited.

  The memory controller 30 may wait for transmission of the read data 52 from the detection of the latency signal 54 until the fixed latency period 51 elapses. FIG. 11 is a diagram illustrating another example of the transmission timing of the read data 52.

  As shown in FIG. 11, after receiving the read command, the memory controller 30 starts transmitting a busy signal instead of a concealment signal. The reason for this will be described later. When the memory controller 30 detects the latency signal 54, the memory controller 30 transmits a ready signal instead of the busy signal. Then, the memory controller 30 starts transmitting the concealment signal after the ready signal.

  The host device 10 determines that the ready signal is the start time of the fixed latency period 51 and waits until the fixed latency period 51 elapses after receiving the ready signal. The memory controller 30 starts transmitting read data 52 after a fixed latency period 51 has elapsed since the ready signal was transmitted. That is, the memory controller 30 uses the busy signal and the ready signal to notify the start time of the fixed latency period 51. Even in this case, the transmission timing of the read data 52 can be concealed.

{Other variations}
In the above embodiment, the example in which the memory controller 30 transmits the concealment signal after receiving the read command until the fixed latency period 51 elapses has been described, but the present invention is not limited to this. The memory controller 30 may transmit a busy signal and a ready signal instead of the concealment signal until the fixed latency period 51 elapses after reception of the read command is completed. Even in this case, the transmission timing of the data of the target address is determined based on the fixed latency period 51. Since the third party cannot specify the fixed latency period 51, the controller of the duplicate product cannot transmit the ready signal at a timing determined based on the fixed latency period 51. In this way, it is possible to make it difficult to produce a duplicate product without using a concealment signal.

  In the above embodiment, the example in which the host device 10 and the memory controller 30 each generate the fixed latency period 51 has been described. However, the present invention is not limited to this. It is only necessary that the host device 10 and the memory controller 30 hold the same fixed latency period 51.

  For example, only the host device 10 may generate the fixed latency period 51. In this case, the fixed latency period 51 is generated only from the random number 13A. The host device 10 may transmit the generated fixed latency period 51 to the memory controller 50 instead of the random number exchange command. Conversely, only the memory controller 30 may generate the fixed latency period 51 and transmit the generated fixed latency period 51 to the host device 10.

  The initial value of the fixed latency period 51 may be set in advance in the host device 10 and the memory controller. Alternatively, the initial value of the fixed latency period 51 may be set in advance only for the host device 10. In this case, the host device 10 may transmit the fixed latency period 51 to the memory controller 30 at the time of activation.

  In the above embodiment, the host device 10 and the memory controller 30 have exchanged random numbers when generating the fixed latency period 51. However, the present invention is not limited to this. When the random number generators 13 and 34 are pseudo random number generators using the same algorithm, the exchange of random numbers can be omitted. Specifically, both of the random number generators 13 and 34 generate the same pseudo-random number by updating the random number generated at a preset timing. Thereby, since the host apparatus 10 and the memory controller 30 do not need to exchange random numbers, the confidentiality of the fixed latency period 51 can be improved. The timing for updating the random number may be, for example, when a read process based on the read command is performed a predetermined number of times, or when the host device 10 transmits a command instructing to update the random number.

  In this way, by preventing transmission and reception of the fixed latency period 51 or the random number used to generate the fixed latency period 51 between the host device 10 and the memory controller 30, a third party can fix the fixed latency period 51 or Since it becomes more difficult to specify the data related to the fixed latency period 51, it is possible to make it more difficult to manufacture a duplicate product.

  Note that the use of the above pseudo-random numbers does not limit the exchange of random numbers. For example, the random number generators 13 and 34 may generate pseudo-random numbers using different algorithms. In this case, the pseudo random numbers generated by the random number generators 13 and 34 are exchanged.

  In the above embodiment, the fixed latency period 51 is updated every time the fixed latency process is executed. However, the host device 10 and the memory controller 30 do not update the fixed latency period 51. Also good.

  In addition, part or all of the memory controller 30 described in the above embodiments may be realized as an integrated circuit (for example, an LSI, a system LSI, or the like).

  In addition, a part or all of each processing in the above embodiment may be realized by hardware, or may be realized by software (including a case where it is realized together with an OS (operating system), middleware, or a predetermined library). It may be realized. Further, it may be realized by mixed processing of software and hardware.

  While the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and can be implemented by appropriately modifying the above-described embodiment without departing from the spirit thereof.

100 memory system 10 host device 11 CPU
12 RAM
13, 34 Random number generator 14 Host-side controller 20 Semiconductor memory device 30 Memory controller 31 Command decoder 32 Latency acquisition unit 321, 322 Register 33 Access control unit 40 Semiconductor memory 43 Target address data 51 Fixed latency period 52 Read data 331 Determination unit 332 Read control unit 333 Transmission control unit 141 Access control unit 142 Latency generation unit 143 Storage unit

Claims (13)

A memory controller that accesses a semiconductor memory in response to a request from a host device,
A read control unit that instructs the semiconductor memory to read data of the address based on an address included in a read command received from the host device;
A latency acquisition unit that is used to determine the transmission timing of the data at the address and acquires a fixed latency period that is the same as the latency period held by the host device;
A transmission control unit that transmits the data of the address to the host device at a timing determined based on the fixed latency period;
A memory controller. The memory controller of claim 1,
When the transmission control unit is notified from the semiconductor memory that output of data at an address included in the read command is possible before a fixed latency period elapses from a predetermined timing, the fixed latency period A memory controller that transmits the data of the address at a timing after elapse of time. The memory controller according to claim 1 or 2,
The transmission control unit is a memory controller that conceals a busy signal transmitted before transmission of data at the address is started. The memory controller according to claim 3,
The transmission control unit is a memory controller that hides at least one of a transmission period of the busy signal and a value of the busy signal. 5. The memory controller of claim 4, further comprising:
A random number generator to generate random numbers,
With
The transmission control unit is a memory controller that conceals at least one of a transmission period of the busy signal and a value of the busy signal using a random number generated by the random number generator. A memory controller according to any one of claims 1 to 5,
The latency acquisition unit is a memory controller that updates the fixed latency period when a predetermined condition is satisfied. The memory controller according to claim 6, comprising:
The latency acquisition unit is a memory controller that updates the fixed latency period after the data of the address is transmitted by the transmission control unit. The memory controller according to claim 1, further comprising:
A determination unit that determines whether to transmit the data of the address at a timing determined based on the fixed latency period, or to transmit when the read control unit can read the data of the address;
A memory controller. The memory controller of claim 1,
The latency acquisition unit
A random number generator for generating random numbers;
A latency generation unit that generates the fixed latency period from the random number generated by the random number generator using a predetermined algorithm;
Including memory controller. The memory controller of claim 1,
The latency acquisition unit is a memory controller that acquires a fixed latency period generated by the host device. A host device;
Semiconductor memory,
A memory controller that accesses the semiconductor memory in response to a request from the host device;
With
The memory controller is
A read control unit that instructs the semiconductor memory to read data of the address based on an address included in a read command received from the host device;
A latency acquisition unit that acquires a fixed latency period used to determine the transmission timing of the data at the address;
A transmission control unit that transmits the data of the address to the host device at a timing determined based on the fixed latency period;
With
The host device is
A storage unit for storing the fixed latency period;
An access control unit that receives data of the address from the memory controller at a timing determined based on the fixed latency period;
A memory system comprising: 12. The memory system according to claim 11, wherein
The access control unit updates the fixed latency period from when the address data is received until a preset period elapses,
The transmission control unit is a memory system in which the fixed latency period is updated until a predetermined period elapses after the data of the address is transmitted. The memory system according to claim 11 or 12,
The memory controller further includes:
A first random number generator for generating a first random number;
With
The host device further includes:
A second random number generator for generating a second random number;
With
Each of the latency acquisition unit and the access control unit generates the fixed latency period from the first random number and the second random number using a predetermined algorithm.

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