JP2017046438A - Drive circuit of power semiconductor element, power conversion unit and power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit of a power semiconductor element capable of improving not only current unbalance during a switching operation but also current unbalance during a steady operation.SOLUTION: The drive circuit of the power semiconductor element is a drive circuit provided corresponding to each of a plurality of power semiconductor elements connected in parallel to drive the power semiconductor element. The drive circuit of the power semiconductor element includes a storage part for storing characteristic information of the power semiconductor element, and a gate drive control part for controlling a gate drive condition of the power semiconductor element on the basis of the characteristic information stored in the storage part.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a power semiconductor element drive circuit, a power conversion unit, and a power conversion apparatus.

  As power converters, there are inverter devices that convert DC power into AC power, and converter devices that convert AC power into DC power. In these power conversion devices, power conversion is performed by a switching operation of the power semiconductor elements. For the purpose of increasing the conversion power capacity, a plurality of power semiconductor elements are connected in parallel, and the plurality of power semiconductors are connected. The elements are driven to be switched simultaneously.

  When driving a plurality of power semiconductor elements connected in parallel as described above, individual power semiconductor elements have variations in characteristics inherent to the elements such as threshold voltage and on-voltage. There is a problem that the value of the current flowing through the power semiconductor element is unbalanced. In consideration of this current value imbalance (hereinafter referred to as current imbalance), conventionally, when power semiconductor elements are connected in parallel, the power semiconductor elements are designed with current values smaller than their rated currents. It was necessary to make sure that it was not destroyed by abnormal voltage or current. Therefore, the performance of the power semiconductor element cannot be maximized.

  In addition, although the above-mentioned problems can be solved by selecting power semiconductor elements and combining power semiconductor elements having similar characteristics, the problem is an increase in cost and a limitation on the number of parallelism when selecting characteristics. . As a technique for solving these problems, a power conversion device described in Patent Document 1 has been proposed.

  Patent Document 1 states that “a plurality of variable gate resistance circuits that change the gate resistance of the IGBT and each variable gate resistance circuit according to the time lag of the current pulse that flows through the IGBT, And a control circuit that changes each gate resistance at the start of turn-off control.

JP 2014-230307 A

  According to the prior art described in Patent Document 1, current does not concentrate on a specific IGBT when the IGBT is turned on / off, that is, during a switching operation. However, the related art is a technique for improving the current imbalance during the switching operation of the IGBT, and does not consider the current imbalance during the steady operation. Therefore, current imbalance caused by individual differences in characteristics such as threshold voltage and on-voltage of the power semiconductor element cannot be reliably improved.

  The present invention relates to a power semiconductor element drive circuit capable of improving not only current imbalance during switching operation but also current imbalance during steady operation, a power conversion unit equipped with the drive circuit, and power provided with the power conversion unit An object is to provide a conversion device.

In order to solve the above problems, for example, the configuration described in the claims is adopted.
The present application includes a plurality of means for solving the above problems.
A drive circuit provided corresponding to each of a plurality of power semiconductor elements connected in parallel and driving the power semiconductor elements,
A storage unit for storing characteristic information of the power semiconductor element;
A gate drive control unit that controls the gate drive condition of the power semiconductor element based on the characteristic information stored in the storage unit;
It is characterized by providing.

According to the present invention, since not only current imbalance during switching operation but also current imbalance during steady operation can be improved, current unbalance caused by individual differences in characteristics such as threshold voltage and on-voltage of power semiconductor elements can be improved. The balance can be improved reliably.
Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is an example of a block diagram which shows the basic composition of the drive circuit of a power semiconductor element. It is an example of a block diagram showing an example of a circuit configuration for increasing conversion power capacity by parallel connection of power semiconductor elements. It is an example of the perspective view which shows the outline of a structure of a power converter unit (power unit) and a power converter device. 1 is an example of a block diagram illustrating a configuration of a drive circuit for a power semiconductor element according to Embodiment 1. FIG. It is an example of the characteristic map figure which shows an example of the information of the characteristic map of the power semiconductor element memorize | stored in a memory | storage part. It is an example of a waveform diagram showing a delay variation Δton of a rise or fall timing of a current during a switching operation of a power semiconductor element, a gate voltage gradient dVge / dt, and a gate voltage Δ | Vge |. FIG. 3 is an example of a waveform diagram for explaining the effect of the drive circuit for the power semiconductor element according to the first embodiment. FIG. 6 is an example of a block diagram illustrating a configuration of a drive circuit for a power semiconductor element according to a second embodiment. It is an example of the block diagram which shows an example of a current sensor. It is an example of the flowchart which shows an example of the process sequence of the feedback control with respect to a delay circuit part. It is an example of the flowchart which shows an example of the process sequence of the feedback control with respect to a gate voltage inclination variable circuit part. It is an example of the flowchart which shows an example of the process sequence of the feedback control with respect to a gate voltage variable circuit part. It is an example of the circuit diagram which shows an example of the circuit structure of a gate voltage inclination variable circuit part. It is an example of the circuit diagram which shows an example of the circuit structure of a gate voltage variable circuit part.

  Hereinafter, modes for carrying out the present invention (hereinafter referred to as “embodiments”) will be described in detail with reference to the drawings. The present invention is not limited to the embodiment. In the present specification and drawings, the same components or components having substantially the same function are denoted by the same reference numerals, and redundant description is omitted.

<Power conversion device>
The power conversion device has an inverter function (inverter device) that converts DC power into AC power, or a converter function (converter device) that converts AC power into DC power. This type of power conversion device is, for example, an uninterruptible power system that aims to supply AC power to a load such as a server without interruption using energy stored in a storage battery. : UPS).

  However, the use illustrated here is an example and is not limited to the use for an uninterruptible power supply. In other words, in addition to the uninterruptible power supply, it is used for various applications such as power converters for industrial equipment, power converters for railways, power converters for elevators, power converters for automobiles, and power converters for household electrical products. Can do.

[Basic configuration of power semiconductor element drive circuit]
First, the basic configuration of the drive circuit for the power semiconductor element of the main circuit in the power conversion device will be described. FIG. 1 is an example of a block diagram showing a basic configuration of a drive circuit for a power semiconductor element.

  In FIG. 1, a power semiconductor element drive circuit 1 includes an upper arm drive circuit 4 that drives an upper arm power semiconductor element 2, a lower arm drive circuit 5 that drives a lower arm power semiconductor element 3, and an upper control circuit unit 6. It has the composition which has. Hereinafter, the drive circuit 1 of the power semiconductor element may be simply referred to as the drive circuit 1. In some cases, the upper arm driving circuit 4 is simply referred to as a driving circuit 4, and the lower arm driving circuit 5 is simply referred to as a driving circuit 5. Diodes 7 and 8 are connected in parallel with reverse polarity to each of the power semiconductor elements 2 and 3.

  The upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 are switching elements that switch a high power supply voltage according to a gate voltage, and perform power conversion by this switching operation. Hereinafter, the upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 may be simply referred to as the power semiconductor element 2 and the power semiconductor element 3. As the power semiconductor elements 2 and 3, an insulated gate bipolar transistor (IGBT), which is an example of a voltage-driven element, can be used.

  The upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 are main circuits in the power converter, and are connected in series between the high potential side power source and the low potential side power source. That is, the drain of the upper arm power semiconductor element 2 is connected to the high potential side power source, the source of the lower arm power semiconductor element 3 is connected to the low potential side power source, and the source of the upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 is connected to the output terminal 9 in common. The voltage (output voltage) derived to the output terminal 9 is supplied to a load (not shown).

  The upper arm power semiconductor element 2, the lower arm power semiconductor element 3, and the diodes 7 and 8 are modularized. Hereinafter, a module including the upper arm power semiconductor element 2, the lower arm power semiconductor element 3, and the diodes 7 and 8 is referred to as a power module 10.

  The upper control circuit unit 6 supplies the upper arm drive circuit 4 and the lower arm drive circuit 5 with a pulse train signal for controlling them. The pulse train signal is, for example, a pulse width modulation (PWM) signal using a carrier wave that changes at a constant frequency. When the pulse train signal is a PWM signal, the accuracy of control can be increased by increasing the frequency of the carrier wave.

[Increase in conversion power capacity]
By the way, a plurality of upper arm power semiconductor elements 2 and a plurality of lower arm power semiconductor elements 3 are connected in parallel, and the plurality of power semiconductor elements are simultaneously switched and driven, whereby the conversion power capacity can be increased.

  FIG. 2 is an example of a circuit diagram showing an example of a circuit configuration for increasing the conversion power capacity by parallel connection of power semiconductor elements. In this example, two upper arm power semiconductor elements 2 and two lower arm power semiconductor elements 3 are connected in parallel. In this example, two parallel connections are given as an example, but the number of parallel connections of the power semiconductor elements 2 and 3 is not limited to two, and the effect of increasing the conversion power capacity as the number of parallel connections increases. growing.

  In FIG. 2, a power module 10 (10-1, 10-2) comprising an upper arm power semiconductor element 2, a lower arm power semiconductor element 3, and diodes 7, 8, an upper arm drive circuit 4 and a lower arm drive circuit 5, Are unitized. Hereinafter, this unit is referred to as a power conversion unit (power unit) 11. In this example, there are two power conversion units 11, and these two power conversion units 11-1 and 11-2 are used in parallel with each other.

  More specifically, the drain of the upper arm power semiconductor element 2 on the power conversion unit 11-1 side and the drain of the upper arm power semiconductor element 2 on the power conversion unit 11-2 side are common to the high potential side power supply terminal 12. It is connected to the. Further, the source of the lower arm power semiconductor element 3 on the power conversion unit 11-1 side and the source of the lower arm power semiconductor element 3 on the power conversion unit 11-2 side are commonly connected to the low potential side power supply terminal 13. Yes. The source of the upper arm power semiconductor element 2 on the power conversion unit 11-1 side and the power conversion unit 11-2 side and the drain of the lower arm power semiconductor element 3 are connected to the output terminal 9 in common.

  In this example, a power module 10 having a 2-in-1 configuration in which the upper arm power semiconductor element 2 and the lower arm power semiconductor element 3 on both the high potential side and the low potential side are mounted on the power conversion units 11-1 and 11-2. However, the present invention is not limited to this. That is, in addition to the 2-in-1 configuration, a power module with a 1-in-1 configuration in which a power semiconductor element of one arm is mounted may be used.

[Configuration of power conversion unit and power conversion device]
Next, the configuration of the power conversion unit and the power conversion device will be described. FIG. 3 is an example of a perspective view showing an outline of the configuration of the power conversion unit and the power conversion device. However, the configuration of the power conversion device illustrated in FIG. 3 is an example, and is not limited to this configuration.

  In FIG. 3, the power conversion unit 11 (11-1, 11-2) is configured by integrating components such as a heat receiving block 14, a smoothing capacitor 15, a heat pipe 16, a heat radiating fin 17, a bus bar 18, fuses 19n, 19p. Unit unit. The heat receiving block 14 is provided so as to sandwich the power semiconductor elements 2 and 3 from both sides. The heat pipe 16 is built in the heat receiving block 14. The radiating fins 17 function to release heat from the heat pipe 16. The bus bar 18 is a member for connecting the power semiconductor elements 2 and 3 and the smoothing capacitor 15. The fuses 19n and 19p are connected to the bus bar 18. A control board 20 is further attached to the power conversion unit 11. On the control board 20, drive circuits 4 and 5 for the power semiconductor elements 2 and 3 are mounted.

  The power conversion device 30 is configured by combining a fan unit 31 for discharging cooling air, a passive component 32 of the power conversion device 30, and the like using a plurality of power conversion units 11 having the above-described configuration. In the case of this example, six power conversion units 11 are arranged in the middle part of the power conversion device 30. The six power conversion units 11 include, for example, three power conversion units for three phases of inverters and three power conversion units for three phases of converters. However, the number of power conversion units 11 arranged in the power conversion device 30 is not limited to six, and the number is arbitrary. The fan unit 31 is disposed on the upper portion of the power conversion device 30, and the passive component 32 is disposed on the lower portion of the power conversion device 30.

  In the power conversion device 30 configured as described above, the power module 10 including the power semiconductor elements 2 and 3 and the diodes 7 and 8, and the upper arm drive circuit 4 and the lower arm drive circuit 5 are unitized. Exchange and expansion are possible in units of 11. Thereby, the maintainability of the power converter device 30 can be improved.

  Here, in the power conversion device 30, as shown in FIG. 2, a plurality of power semiconductor elements 2 and 3 are connected in parallel for the purpose of increasing the conversion power capacity, and the plurality of power semiconductor elements 2 and 3 are connected. Let us consider the case of switching driving simultaneously. In this case, since individual power semiconductor elements have variations in characteristics inherent to the elements such as threshold voltage and on-voltage, there is a problem that the current values flowing through the power semiconductor elements are unbalanced when they are conducted. .

<Embodiment of the present invention>
Therefore, in the present embodiment, when the plurality of power semiconductor elements 2 and 3 connected in parallel are switched and driven simultaneously in the power semiconductor element drive circuit 1 shown in FIG. Improve current imbalance during steady state operation. Here, the “steady operation” is an operation during a period from when the power semiconductor elements 2 and 3 are turned on to before the turn-off, that is, when the power semiconductor elements 2 and 3 are in conduction.

  The drive circuit 1 according to the present embodiment includes an upper arm drive circuit 4 and a lower arm drive provided in correspondence to the plurality of power semiconductor elements 2 and 3 in the power conversion units 11-1 and 11-2 connected in parallel. Each circuit 5 includes a storage unit 51 (see FIG. 4) that stores characteristic information of the power semiconductor elements 2 and 3. Examples of the characteristic information of the power semiconductor elements 2 and 3 include current change start time, switching speed, threshold voltage, on-voltage, and the like. Then, the upper arm drive circuit 4 and the lower arm drive circuit 5 determine the gate drive conditions of the power semiconductor elements 2 and 3, specifically, based on the characteristic information of the power semiconductor elements 2 and 3 stored in the storage unit 51. Controls the gate current or gate voltage.

  As described above, the storage unit 51 for storing the characteristic information of the power semiconductor elements 2 and 3 is provided for each of the drive circuits 4 and 5, and the gate drive condition (gate current or gate) of the power semiconductor elements 2 and 3 is based on the characteristic information. By controlling the voltage, the following actions and effects can be obtained. That is, since not only the current imbalance during the switching operation of the power semiconductor elements 2 and 3 but also the current imbalance during the steady operation can be improved, the characteristics of the power semiconductor elements 2 and 3 such as the threshold voltage and the ON voltage can be improved. Current imbalance caused by individual differences can be reliably improved.

  Further, since the storage unit 51 is provided for each of the drive circuits 4 and 5, when the power conversion unit 11 is replaced in units, the storage unit 51 of the replaced power conversion unit 11 includes the power conversion unit. Thus, the characteristic information of the power semiconductor element mounted on 11 is stored. Therefore, even if the power conversion unit 11 is replaced, it is not necessary to rewrite the characteristic information in the storage unit 51 each time. In addition, when the structure which provides the memory | storage part 51 in common with respect to the some power conversion unit 11 is taken, whenever the power conversion unit 11 is replaced | exchanged, the memory content of the memory | storage part 51 is replaced | exchanged for the power conversion unit 11 after replacement | exchange. It is necessary to rewrite the characteristic information corresponding to the power semiconductor element.

  Specific examples of the power semiconductor element drive circuit 1 according to the present embodiment will be described below.

[Example 1]
FIG. 4 is an example of a block diagram illustrating the configuration of the drive circuit 1 for the power semiconductor element according to the first embodiment. Hereinafter, a specific configuration of the lower arm drive circuit 5 of the power conversion units 11-1 and 11-2 will be described, but the upper arm drive circuit 4 has the same configuration. The lower arm drive circuit 5 (hereinafter simply referred to as “drive circuit 5”) includes a storage unit (storage device) 51, an interface (I / F) circuit unit 52, a delay circuit unit 53, and a gate voltage slope variable circuit unit 54. And a gate voltage variable circuit section 55.

  The storage unit 51 stores characteristic information of the lower arm power semiconductor element 3. The information stored in the storage unit 51 is preferably, for example, information on a characteristic map of each power semiconductor element acquired at the time of shipping inspection of the power semiconductor element 3. FIG. 5 is an example of a characteristic map diagram illustrating an example of information on a characteristic map of the power semiconductor element stored in the storage unit 51.

  FIG. 5A shows a characteristic map showing the relationship between the on-voltage and switching speed (SW speed) of the lower arm power semiconductor element 3 on the power conversion unit 11-1 side, and a characteristic map showing the relationship between the on-voltage and delay time. Is shown. FIG. 5B shows a characteristic map showing the relationship between the on-voltage and switching speed (SW speed) of the lower arm power semiconductor element 3 on the power conversion unit 11-2 side, and a characteristic showing the relationship between the on-voltage and delay time. Shows the map. The characteristic maps shown in FIGS. 5A and 5B are examples, and the present invention is not limited to this.

  The interface circuit unit 52 transmits the information supplied from the upper control circuit unit 6 to the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate voltage variable circuit unit 55. The delay circuit unit 53, the gate voltage gradient variable circuit unit 54, and the gate voltage variable circuit unit 55 are controlled by the upper control circuit unit 6 based on the characteristic information stored in the storage unit 51. A gate drive control unit for controlling gate drive conditions is configured.

  Specifically, the delay circuit unit 53 adjusts the delay variation Δton of the rising or falling timing of the current during the switching operation of the power semiconductor element 3. The gate voltage gradient variable circuit unit 54 changes the gate voltage gradient dVge / dt in order to adjust the variation in the current gradient di / dt during the switching operation of the power semiconductor element 3. The gate voltage variable circuit unit 55 changes the gate (gate-emitter) voltage Δ | Vge | in order to adjust the current during the steady operation (conduction) of the power semiconductor element 3. FIG. 6 is an example of a waveform diagram showing the delay variation Δton of the rise or fall timing of the current during the switching operation of the power semiconductor element 3, the slope dVge / dt of the gate voltage, and the gate voltage Δ | Vge |.

  In the power semiconductor element drive circuit 1 according to the first embodiment having the above-described configuration, the upper control circuit unit 6 reads out the characteristic map information (see FIG. 5A) that is the characteristic information of the power semiconductor element 3 from the storage unit 51. Then, the upper control circuit unit 6 calculates difference information between the power semiconductor elements 3 connected in parallel based on the read information, and controls the delay circuit unit 53, the gate through the interface circuit unit 52 as a control signal. The voltage gradient variable circuit unit 54 and the gate voltage variable circuit unit 55 are supplied.

  The delay circuit unit 53, the gate voltage gradient variable circuit unit 54, and the gate voltage variable circuit unit 55 control the gate driving conditions of the power semiconductor element 3 based on the control signal supplied from the higher control circuit unit 6. In this case, even if the signal input from the input terminal 21 is the same as the drive signal of the power semiconductor element 3, it is different from the power semiconductor element 3 mounted in each of the power conversion units 11-1 and 11-2. A gate voltage waveform is applied.

  On the other hand, although the detailed internal configuration is not shown, the upper arm power semiconductor element 2 on the high potential side of the power modules 10-1 and 10-2 mounted in the power conversion units 11-1 and 11-2, respectively, The drive circuits 4 having the same configuration are connected to each other. In addition, characteristic map information corresponding to the upper arm power semiconductor element 2 is recorded in a storage unit (corresponding to the storage unit 51 in FIG. 4) mounted on the drive circuit 4 on the high potential side. Then, when driving the upper arm power semiconductor element 2, the upper control circuit unit 6 displays the difference information between the power semiconductor elements 2 connected in parallel as in the case of driving the lower arm power semiconductor element 3. The drive circuit 4 is controlled based on the calculated difference information.

  Next, the operation and effect of the power semiconductor element drive circuit 1 according to the first embodiment will be described with reference to FIG. FIG. 7 is an example of a waveform diagram for explaining the effect of the drive circuit 1 for the power semiconductor element according to the first embodiment. FIG. 7A is an example of a driving waveform when power semiconductor elements connected in parallel having characteristic variations are controlled by a conventional driving circuit. FIG. 7B is an example of a drive waveform when controlled by the drive circuit 1 according to the first embodiment.

  When power semiconductor elements connected in parallel having characteristic variations are driven by a conventional drive circuit, as shown in FIG. 7A, the gate drive waveforms match, but the currents I1 and I2 flowing through the power semiconductor elements are the same. It is unbalanced. First, a difference Δton may occur in the current change start time due to mutual timing delay variation. Further, a difference Δdi / dt may occur in the current switching speed. Furthermore, a difference ΔI may occur in the current during steady operation due to variations in characteristics such as threshold voltage and on-voltage.

  Examples of information on the characteristic map recorded in the storage unit (recording device) 51 included in the power semiconductor element drive circuit 1 according to the first embodiment include current change start time, switching speed, threshold voltage, and on-voltage. The upper control circuit unit 6 calculates the difference information Δton, Δdi / dt, ΔI from the information of the characteristic map stored in the storage unit 51, and delay circuit unit 53, gate voltage so as to cancel the difference. Control signals are output to the slope variable circuit unit 54 and the gate voltage variable circuit unit 55.

  Then, the delay circuit unit 53 adjusts the delay variation Δton of the rising or falling timing of the current during the switching operation. Further, the gate voltage gradient variable circuit unit 54 changes the gate voltage gradient dVge / dt, and the gate voltage variable circuit unit 55 changes the gate voltage Δ | Vge |. As a result, as shown in FIG. 7B, since different gate drive waveforms are output, the unbalance of the output current of the power semiconductor element during the switching operation and the steady operation is reduced.

  In the present embodiment, the case where the power semiconductor elements are arranged in parallel is described as an example. However, even when the number of parallel power semiconductor elements is increased to n (n is an integer of 3 or more), the present embodiment The drive circuit 1 according to the above is applicable. When the number of parallel power semiconductor elements is n, the upper control circuit unit 6 calculates the difference information. For example, the information of the characteristic map of the nth power semiconductor element is used as the reference information, and the remaining first (n -1) Control for calculating a difference with respect to the information of the characteristic map of the first power semiconductor element can be considered.

[Example 2]
The second embodiment is a modification of the first embodiment. FIG. 8 is an example of a block diagram illustrating the configuration of the power semiconductor element drive circuit 1 according to the second embodiment. As shown in FIG. 8, the power semiconductor element drive circuit 1 according to the second embodiment includes current sensors 61-1 and 61-2, in addition to the components of the power semiconductor element drive circuit 1 according to the first embodiment. The current calculation units 62-1 and 62-2 are provided.

  The current sensors 61-1 and 61-2 detect information corresponding to the current flowing through the power semiconductor elements 2 and 3. The current calculation units 62-1 and 62-2 calculate the current that actually flows through the power semiconductor elements 2 and 3 based on the detection outputs (detection information) of the current sensors 61-1 and 61-2. In this example, the current sensors 61-1 and 61-2 and the current calculation units 62-1 and 62-2 are illustrated as separate components, but may be integrated. Here, the current sensors 61-1 and 61-2 and the current calculation units 62-1 and 62-2 constitute a plurality of current detection units that detect the current flowing through the power semiconductor elements 2 and 3.

  In this embodiment, the detection results of the current sensors 61-1 and 61-2 and the current calculation units 62-1 and 62-2 are fed back to the upper control circuit unit 6. The upper control circuit unit 6 is configured by, for example, a CPU (Central Processing Unit), and has characteristics stored in the storage unit 51 with respect to the delay circuit unit 53, the gate voltage gradient variable circuit unit 54, and the gate voltage variable circuit unit 55. In addition to control based on information, control based on feedback information is executed.

  In the power semiconductor element drive circuit 1 according to the first embodiment, the characteristic information stored in the storage unit 51 is information on a characteristic map acquired at the time of shipping inspection. Control of the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate voltage variable circuit unit 55 based on the information of the characteristic map acquired at the time of the shipping inspection can sufficiently obtain the effect of reducing the current imbalance.

  However, when the power conversion units 11-1 and 11-2 are in a heat run state, a temperature difference occurs between the power conversion units 11-1 and 11-2, or a mounting system is deteriorated due to a heat cycle. Compared with the information of the characteristic map at the time of shipping inspection, the actual characteristic changes. In such a case, the current imbalance may be deteriorated.

  On the other hand, in the power semiconductor element drive circuit 1 according to the second embodiment, the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate based on the detection result of the current that actually flows in the power semiconductor elements 2 and 3 are used. Feedback control of the voltage variable circuit unit 55 is performed. Therefore, according to the feedback control by the power semiconductor element drive circuit 1 according to the second embodiment, the current imbalance can be reduced even when the current imbalance is deteriorated after the heat cycle of the power conversion units 11-1 and 11-2. Can be obtained.

(Current sensor)
Here, the current sensor 61 (61-1, 61-2) will be described with reference to FIG. FIG. 9 is an example of a configuration diagram illustrating an example of the current sensor 61. Here, as the current sensor 61, a coreless current sensor that is not used in the core for detecting a magnetic field, specifically, a sensor using a Rogowski coil is illustrated. However, the current sensor 61 is not limited to a sensor using a Rogowski coil.

  As shown in FIG. 9, the current sensor 61 using the Rogowski coil has a configuration in which an air-core coil 612 is arranged around the primary conductor 611. In the current sensor 61, a voltage corresponding to the current flowing through the primary conductor 611 is induced at both ends of the coil 612. This voltage (induced electromotive force) is derived between the terminals 613a and 613b as a differential waveform of the current flowing through the primary conductor 611.

  The current calculation unit 62 (62-1, 62-2) shown in FIG. 9 takes in the voltage of the differential waveform derived between the terminals 613a, 613b as information corresponding to the current flowing through the power semiconductor elements 2, 3, Based on this voltage, the current that actually flows through the power semiconductor elements 2 and 3 is calculated. As an example, the current calculation unit 62 includes an integration circuit 621 and an effective value circuit 622. The current calculation unit 62 reproduces the current flowing through the power semiconductor elements 2 and 3 by integrating the differential waveform voltage. Calculate the current that actually flows.

(Feedback control)
Subsequently, the feedback control of the upper control circuit unit 6 based on the detection result of the current flowing through the power semiconductor elements 2 and 3 with respect to the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate voltage variable circuit unit 55 is specifically Explained. In this example, it is assumed that the feedback control is executed under the control of the CPU constituting the upper control circuit unit 6.

  FIG. 10 is an example of a flowchart illustrating an example of a processing procedure of feedback control for the delay circuit unit 53.

  The CPU takes in the outputs of the current calculation units 62-1 and 62-2, that is, the detected currents of the power semiconductor elements 2 and 3, and obtains the current rise delay time Δton (step S11), and then the current rise delay time Δton is obtained. It is determined whether or not it is equal to or less than a predetermined value (step S12). If the current rise delay time Δton is equal to or less than the predetermined value (YES in S12), the CPU leaves the gate drive condition as it is and ends the feedback control process. On the other hand, if the current rise delay time Δton is not less than or equal to the predetermined value (NO in S12), the CPU calculates the delay time adjustment amount (step S13), and then controls the delay circuit unit 53 to thereby delay the current rise. The time Δton is adjusted (step S14).

  FIG. 11 is an example of a flowchart illustrating an example of a processing procedure of feedback control for the gate voltage gradient variable circuit unit 54.

  The CPU takes in the outputs of the current calculation units 62-1 and 62-2, that is, the detected currents of the power semiconductor elements 2 and 3, and obtains the current gradient di / dt (step S21), and then the current gradient di / dt is obtained. It is determined whether it is within a predetermined value (step S22). Then, if the current gradient di / dt is within the predetermined value (YES in S22), the CPU keeps the gate drive condition as it is and ends the process of the feedback control. On the other hand, if the current gradient di / dt is not within the predetermined value (NO in S22), the CPU calculates the gate voltage gradient adjustment amount (step S23), and then controls the gate voltage gradient variable circuit unit 54. The current gradient di / dt is adjusted (step S24).

  FIG. 12 is an example of a flowchart illustrating an example of a processing procedure of feedback control for the gate voltage variable circuit unit 55.

  The CPU takes in the outputs of the current calculation units 62-1 and 62-2, that is, the detected currents of the power semiconductor elements 2 and 3, and obtains a current (steady current) during steady operation (step S31). It is determined whether it is within the range (step S32). If the steady current is within the predetermined range (YES in S32), the CPU leaves the gate drive condition as it is and ends the feedback control process. On the other hand, if the steady current is not within the predetermined range (NO in S32), the CPU calculates the gate voltage adjustment amount (step S33), and then adjusts the gate voltage by controlling the gate voltage variable circuit unit 55 (step S33). Step S34).

  In the feedback control described above, the upper control circuit unit 6 (specifically, the CPU) is detected by the current sensors 61-1 and 61-2 and the current calculation units 62-1 and 62-2 under a predetermined condition. The characteristic information stored in advance in the storage unit 51 may be updated based on the current. As the predetermined condition, for example, current imbalance at the time of control based on the information of the characteristic map at the time of shipping inspection is detected by the current sensors 61-1 and 61-2 and the current calculation units 62-1 and 62-2. This is a case where the host control circuit unit 6 determines that the current imbalance is worsened.

  In this case, for the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate voltage variable circuit unit 55, the characteristic data that is the basis of the new control information output by the upper control circuit unit 6 is re-stored in the storage unit 51. Remember (update). By performing this update process, the control information from the upper control circuit unit 6 becomes information corresponding to the actual current imbalance. As a result, the delay circuit unit 53, the gate voltage slope variable circuit unit 54, and the gate voltage variable circuit unit 55 can be controlled so that the current imbalance is always improved.

[Example 3]
The third embodiment is a specific example of the gate voltage gradient variable circuit section 54 and the gate voltage variable circuit section 55 in the power semiconductor element drive circuit 1 according to the first embodiment.

  FIG. 13 is an example of a circuit diagram illustrating an example of a specific circuit configuration of the gate voltage gradient variable circuit unit 54. As illustrated in FIG. 13, the gate voltage gradient variable circuit unit 54 includes a pre-driver 71, a variable resistance control unit 72, a buffer unit 73, and a variable resistance unit 74. As shown in FIGS. 4 and 8, the delay circuit unit 53 is arranged at the front stage of the gate voltage gradient variable circuit unit 54, and the gate voltage variable circuit unit 55 is arranged at the rear stage. Then, these illustrations are omitted.

  A signal for driving the power semiconductor element 3 is input to the input terminal 75 via the delay circuit unit 53. This signal is transmitted to the buffer unit 73 via the pre-driver 71. The signal that has passed through the buffer unit 73 becomes a gate input of the power semiconductor element 3 through the variable resistor unit 74. A switching speed control signal sent from the host control circuit unit 6 is input to the input terminal 76. The switching speed control signal changes the value of the gate input current (gate injection current) of the power semiconductor element 3 by controlling the resistance value of the variable resistor 74.

  In general, since the gate parasitic capacitance of the power semiconductor element 3 is constant, the slope of the gate voltage can be changed by changing the value of the gate injection current when the power semiconductor element 3 is switched.

  FIG. 14 is an example of a circuit diagram illustrating an example of a specific circuit configuration of the gate voltage variable circuit unit 55. As shown in FIG. 14, the gate voltage variable circuit unit 55 includes a gate power supply 81, a switch control unit 82, a resistance element 83, and three Zener diodes (constant voltage diodes) 84-1, having different Zener voltages. 84-2, 84-3 and three switches 85-1, 85-2, 85-3.

  A power supply voltage is input to the gate power supply 81 via power supply terminals 86 and 87. An on-voltage control signal sent from the upper control circuit unit 6 is input to the switch control unit 82 via the input terminal 88. The switch control unit 82 performs on (close) / off (open) control of the switches 85-1, 85-2, and 85-3 according to the on voltage control signal, and the zener diodes 84-1 and 84 having different zener voltages. -2 Toggles the connection of 84-3.

Here, if the output voltage of the gate power supply 81 is V _out and the voltage across the Zener diodes 84-1, 84-2, 84-3 (the Zener voltage) is V _ZD , the voltage V _r applied across the resistance element 83 is It can represent with following Formula (1).
V _r = V _out −V _ZD (1)

By switching the switch 85-1,85-2,85-3, it means that the connection of the Zener diode 84-1,84-2,84-3 having different Zener voltage V _ZD is switched, the Zener voltage V _ZD is By changing, the voltage V _r applied to both ends of the resistance element 83 can be changed.

As shown in FIG. 14, the voltage between the positive bias power source and the negative bias power source is the output voltage V _out of the gate power source 81. Further, the voltage between the positive bias power supply and the reference potential is a voltage V _r applied across the resistance element 83. On the other hand, as shown in FIG. 13, the voltage applied to the gate of the power semiconductor element 3 is equal to the inter-terminal voltage V _r between the positive bias power supply and the reference potential, so that the Zener voltage V _ZD can be changed. For example, the gate applied voltage of the power semiconductor element 3 can be changed.

  Generally, changing the gate applied voltage of the power semiconductor element 3 changes the on-voltage and current characteristics, so that the steady current can be changed. Therefore, by controlling the gate voltage of the power semiconductor element 3 based on the characteristic information stored in the storage unit 51, the current imbalance during steady operation can be improved.

  In the third embodiment, specific examples of the gate voltage gradient variable circuit unit 54 and the gate voltage variable circuit unit 55 have been described. However, the delay control in the delay circuit unit 53 includes a delay due to digital control by the upper control circuit unit 6 and the like. A well-known technique can be applied.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations. Further, a part of the configuration of a certain embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of a certain embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  DESCRIPTION OF SYMBOLS 1 ... Drive circuit of power semiconductor element, 2 ... Upper arm power semiconductor element, 3 ... Lower arm power semiconductor element, 4 ... Upper arm drive circuit 4, 5 ... Lower arm drive circuit, 6 ... Upper control circuit part, 10 (10 -1, 10-2) ... power module, 11 (11-1, 11-2) ... power conversion unit, 20 ... control board, 30 ... power conversion device, 51 ... storage unit (storage device), 53 ... delay circuit 54: Gate voltage gradient variable circuit unit, 55 ... Gate voltage variable circuit unit, 61 (61-1, 61-2) ... Current sensor, 62 (62-1, 62-2) ... Current calculation unit

Claims (7)

A drive circuit provided corresponding to each of a plurality of power semiconductor elements connected in parallel and driving the power semiconductor elements,
A storage unit for storing characteristic information of the power semiconductor element;
A gate drive control unit that controls a gate drive condition of the power semiconductor element based on the characteristic information stored in the storage unit;
A drive circuit for a power semiconductor element, comprising: The power semiconductor element drive circuit according to claim 1, wherein the gate drive control unit controls a gate voltage of the power semiconductor element based on the characteristic information stored in the storage unit. A delay control unit configured to control a delay time between an input signal input as a drive signal of the power semiconductor element and an output signal based on the input signal based on the characteristic information stored in the storage unit; The drive circuit of the power semiconductor element according to claim 1, wherein the drive circuit is provided. A power conversion unit equipped with a power semiconductor element and a drive circuit for driving the power semiconductor element and used in parallel connection,
An upper control circuit unit for controlling the drive circuit;
The drive circuit is
A storage unit for storing characteristic information of the power semiconductor element;
A gate drive control unit that controls a gate drive condition of the power semiconductor element based on the characteristic information stored in the storage unit, and
The upper control circuit unit controls the gate drive condition of the power semiconductor element by controlling the gate drive control unit based on the characteristic information stored in the storage unit. unit. The drive circuit controls a delay time between an input signal input as a drive signal for the power semiconductor element and an output signal based on the input signal based on the characteristic information stored in the storage unit. A delay control unit,
5. The power conversion unit according to claim 4, wherein the upper control circuit unit changes the delay time by controlling the delay control unit based on the characteristic information stored in the storage unit. . A power semiconductor element and a drive circuit for driving the power semiconductor element are mounted, and a plurality of power conversion units used connected in parallel;
A plurality of current detection units for detecting a current flowing in each of the power semiconductor elements of the plurality of power conversion units connected in parallel;
An upper control circuit unit for controlling the drive circuit,
The drive circuit is
A storage unit for storing characteristic information of the power semiconductor element;
A gate drive control unit that controls a gate drive condition of the power semiconductor element based on the characteristic information stored in the storage unit, and
The upper control circuit unit controls the gate drive control unit based on the characteristic information stored in the storage unit and a difference between currents detected by the plurality of current detection units, thereby controlling the power semiconductor element. A power converter that controls gate driving conditions. The power conversion device according to claim 6, wherein the upper control circuit unit updates the characteristic information stored in the storage unit based on currents detected by the plurality of current detection units.

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