JP2017034006A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a withstanding voltage without increasing a device area.SOLUTION: A P-type electric-field relaxation layer (5) has a difference in depth from a surface of a P-type semiconductor substrate (1) between a part contacted with a P-type well (3) and a part located below an electric-field relaxation oxide film (11). A depth at the part located below the electric-field relaxation oxide film (11) is set depending on a thickness of the electric-field relaxation oxide film (11).SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to an LDMOS transistor (Laterally Diffused MOS Transistor) and a manufacturing method thereof.

  LDMOS transistors, which are semiconductor devices, are used in switching regulators, various drivers, DC-DC converters, etc., taking advantage of their fast switching speed and ease of use because of their voltage drive system. It is a device.

  In general, the performance of an LDMOS transistor is expressed by its breakdown voltage (breakdown breakdown voltage) and on-resistance. However, these are usually in a trade-off relationship, and it is difficult to achieve both high breakdown voltage and low on-resistance. For this reason, development has been conducted for many years in terms of how to achieve this balance.

  The semiconductor device of Patent Document 1 employs an SOI (Silicon-On-Insulator) wafer instead of a normal wafer in order to realize a high breakdown voltage and a low on-resistance.

  In the semiconductor device of Patent Document 2, an LDMOS is formed by adopting an embedded EPI wafer in order to realize a high breakdown voltage and a low on-resistance.

  The semiconductor device of Patent Document 3 is arranged below the n-type drain contact region in a direction parallel to the surface of the p-type semiconductor substrate so as to be in contact with the bottom surface of the p-type body region in which the n-type source contact region is formed. By providing the p-type buried diffusion region extending to the end, the electric field concentration at the end of the gate electrode on the drain side is alleviated and the breakdown voltage is improved.

  In the semiconductor devices of Patent Documents 1 to 3, a LOCOS oxide film is formed between the drift region and the gate electrode, and a part of the gate electrode is located on the LOCOS oxide film. This relaxes the electric field concentration at the gate end and improves the breakdown voltage.

JP 11-251597 A (published September 17, 1999) JP 2006-144410 A (published November 30, 2006) JP 2013-69750 A (published April 18, 2013)

  However, since the semiconductor devices of Patent Documents 1 and 2 use SOI wafers or embedded EPI wafers that are more expensive than normal wafers, the manufacturing cost is high and the device price is also expensive.

  Further, in the semiconductor device of Patent Document 3, in order to further improve the breakdown voltage, a method is generally realized by increasing the length of the LOCOS oxide film between the drift region and the gate region. However, increasing the length of the LOCOS oxide film increases the device area. Further, as a method for improving the breakdown voltage, it is conceivable to increase the thickness of the LOCOS oxide film. However, when the thickness of the LOCOS oxide film is increased, the p-type buried diffusion region needs to be formed at a deeper position.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a low-cost semiconductor device and a method for manufacturing the semiconductor device, in which the breakdown voltage is improved without increasing the device area. .

  In order to solve the above-described problems, a semiconductor device according to one embodiment of the present invention includes a second conductivity type first well formed in a surface layer of a first conductivity type semiconductor substrate, and a surface layer of the first well. A first well of the first conductivity type formed, a source region formed in the second well, a drain region formed in a surface layer of the first well spaced apart from the source region, and the first On the surface of the well, the gate electrode formed on the region between the source region and the drain region, and formed on the surface layer of the semiconductor substrate so as to overlap with the end of the gate electrode on the drain region side And a first conductivity type electric field relaxation layer in contact with the bottom of the second well, wherein the electric field relaxation layer is positioned below the oxide film and a portion in contact with the second well. From the surface of the semiconductor substrate Have different depths, the depth of the portion located below the oxide film is characterized by being set in accordance with the thickness of the oxide film.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to one embodiment of the present invention includes a second conductivity type first well formed in a surface layer of a first conductivity type semiconductor substrate, and the first well. A second well of the first conductivity type formed in the surface layer, a source region formed in the second well, a drain region formed in the surface layer of the first well apart from the source region, On the surface of the first well, a gate electrode formed on a region between the source region and the drain region and an end of the gate electrode on the drain region side overlap with the gate electrode. A method of manufacturing a semiconductor device comprising: an oxide film formed on a surface layer; and a first conductivity type electric field relaxation layer in contact with a bottom of the second well, the step of forming a recess in the semiconductor substrate; The recess is formed with respect to the semiconductor substrate. By implanting ions from the made the surface, characterized in that it includes a step of forming the field relaxation layer, forming an oxide film on the inside of the recess, the.

  According to one embodiment of the present invention, it is possible to provide a low-cost semiconductor device and a method for manufacturing the semiconductor device, in which the breakdown voltage is improved without increasing the device area.

It is sectional drawing of the LDMOS transistor which concerns on Embodiment 1 of this invention. (A)-(i) is sectional drawing which shows the manufacturing process of the LDMOS transistor which concerns on Embodiment 1 of this invention in order of a process. It is sectional drawing of the LDMOS transistor which concerns on Embodiment 2 of this invention. It is sectional drawing of the LDMOS transistor which concerns on Embodiment 3 of this invention.

Embodiment 1
Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

  In this embodiment, an N-channel LDMOS transistor having a RESURF structure will be described as an example of the semiconductor device of the present invention. That is, the N-channel type LDMOS transistor in the following description is a semiconductor device in which the first conductivity type in the present invention is a P-type and the second conductivity type is an N-type.

  However, the semiconductor device of the present invention is not limited to an N-channel type LDMOS transistor, and may be a P-channel type LDMOS transistor. In this case, the P-channel type LDMOS transistor is a semiconductor device in which the first conductivity type in the present invention is N-type and the second conductivity type is P-type.

<LDMOS transistor>
FIG. 1 is a cross-sectional view of the LDMOS transistor of this embodiment.

  As shown in FIG. 1, an N-channel LDMOS transistor 100 (semiconductor device) includes an N-type well 2 (first well) formed on the surface layer of a P-type silicon substrate 1 (semiconductor substrate), and an N-type well 2. P-type well 3 (second well) formed on the surface layer of the N-type well, and an N-type drain electric field relaxation layer 4 formed on the surface layer of the N-type well 2 so as to be separated from the P-type well 3.

  An N-type source region 9 (source region) and a P-type diffusion layer 10 are formed in the P-type well 3. Although not shown, a source electrode is formed on the N-type source region 9 and the P-type diffusion layer 10.

  An N-type drain region 12 (drain region) is formed in the N-type drain electric field relaxation layer 4. The N-type drain electric field relaxation layer 4 is a region provided for reducing the on-resistance. The longer the width of the N-type drain electric field relaxation layer 4 and the higher the impurity concentration, the lower the on-resistance. Although not shown, a drain electrode is formed on the N-type drain region 12.

  A gate electrode 8 is formed on the surface of the N-type well 2 via a gate oxide film 7 at a position between the N-type source region 9 and the N-type drain region 12.

  In the LDMOS transistor 100, by applying a positive potential to the gate electrode 8, a channel is formed in the P-type well 3 sandwiched between the N-type source region 9 and the N-type well 2. As a result, electrons move in a path from the source electrode formed on the N-type source region 9 and the P-type diffusion layer 10 to the drain electrode formed on the N-type drain region 12, A current flows between the drain electrode.

  The N-type source region 9 and the N-type drain region 12 are formed on the surface layer of the N-type well 2 so as to be separated from each other. An electric field relaxation oxide film 11 (oxide film) having a predetermined depth from the surface of the P-type silicon substrate 1 is formed between the N-type source region 9 and the N-type drain region 12. An end portion of the gate electrode 8 on the N-type drain region 12 side overlaps a part of the electric field relaxation oxide film 11.

  The electric field relaxation oxide film 11 is located between the end of the gate electrode 8 and the N-type drain region 12, and the end of the gate electrode 8 is offset from the N-type drain region 12, thereby the end of the gate electrode 8. Electric field concentration at the portion can be prevented, and the breakdown voltage of the LDMOS transistor 100 can be improved.

  By increasing the thickness of the electric field relaxation oxide film 11, the breakdown voltage (OFF breakdown voltage) of the LDMOS transistor 100 can be further improved. Therefore, the thickness of the electric field relaxation oxide film 11 is set according to the breakdown voltage required for the LDMOS transistor 100, and when the required breakdown voltage is large, the thickness of the electric field relaxation oxide film 11 can be increased.

  The LDMOS transistor 100 includes a P-type electric field relaxation layer 5 formed in the N-type well 2 below the P-type well 3 so as to be in contact with the bottom of the P-type well 3.

<P-type electric field relaxation layer>
As shown in FIG. 1, the P-type field relaxation layer 5 is formed from below the P-type well 3 to below the field relaxation oxide film 11 and the N-type drain field relaxation layer 4.

  Since the LDMOS transistor 100 includes the P-type field relaxation layer 5, when a reverse bias is applied between the P-type well 3 and the N-type well 2, the P-type field relaxation layer 5 and the N-type field relaxation layer 5 are provided. A depletion layer generated along the interface of the well 2 extends in a direction in which the N-type drain field relaxation layer 4 and the P-type well 3 are separated from each other. For this reason, the concentration of the electric field at the end of the N-type drain electric field relaxation layer 4 on the P-type well 3 side is alleviated, and the breakdown voltage in the separation direction is improved.

  The depth of the P-type field relaxation layer 5 from the surface of the P-type silicon substrate 1 in the portion located below the field relaxation oxide film 11 is set according to the thickness of the field relaxation oxide film 11.

  As a result, the upper surface of the P-type electric field relaxation layer 5 has a level difference, and a portion in contact with the P-type well 3 and a portion located below the electric field relaxation oxide film 11 from the surface of the P-type silicon substrate 1. The depth of is different. More specifically, the P-type field relaxation layer 5 includes a depth from the surface of the P-type silicon substrate 1 in a portion in contact with the P-type well 3 and a field relaxation oxide film in a portion located below the field relaxation oxide film 11. The depth from the bottom surface of 11 is equal to each other.

  When the P-type field relaxation layer 5 has a flat shape having no step, the thickness of the field relaxation oxide film 11 is increased in accordance with the breakdown voltage required for the LDMOS transistor 100. It is necessary to form the type electric field relaxation layer 5 at a deeper position. As a result, it is necessary to form the P-type well 3 in contact with the P-type field relaxation layer 5 to a deep position.

  On the other hand, in the LDMOS transistor 100 of the present embodiment, the P-type field relaxation layer 5 has a step, and the P-type silicon substrate 1 of the P-type field relaxation layer 5 according to the thickness of the field relaxation oxide film 11. The depth from the surface is set. Therefore, even when the thickness of the electric field relaxation oxide film 11 is increased, it is not necessary to form the P-type well 3 in contact with the P-type electric field relaxation layer 5 or to increase the device area.

<Manufacturing method>
A method for manufacturing the LDMOS transistor 100 of this embodiment will be described.

  2A to 2I are cross-sectional views showing the manufacturing steps of the LDMOS transistor of this embodiment in the order of steps.

  In the manufacturing process of the LDMOS transistor 100, first, as shown in FIG. 2A, a thermal oxide film 16 having a film thickness of about 10 to 100 nm is formed on the P-type silicon substrate 1. As the P-type silicon substrate 1, for example, a substrate having a specific resistance of 1 to 200 Ωcm can be used.

Next, as shown in FIG. 2A, patterning for a region where the deep N-type well 2 is to be formed is performed by a lithography process to form a resist 15. Next, phosphorus (P) ions having a dose of 1.0 × 10 ^{12 to} 5.0 × 10 ¹³ / cm are implanted with an acceleration energy of 1000 to 10000 keV using the resist 15 as a mask, so that the ion implantation layer 14. Form.

  Next, after removing the resist 15, a drive-in diffusion of the implanted phosphorus (P) is performed as shown in FIG. 2B by performing a thermal diffusion treatment at 1000 to 1200 ° C. for 300 to 600 minutes. A deep N-type well 2 is formed. When performing the drive-in diffusion of phosphorus (P), the diffusion depth Xj of the N-type well 2 is adjusted to 6.0 to 12.0 μm. After the N-type well 2 is formed, the thermal oxide film 16 is peeled off by wet etching with hydrogen fluoride, and a thermal oxide film 18 is formed on the surface of the P-type silicon substrate 1 by thermal oxidation. Then, a silicon nitride film 17 that has been subjected to silicon patterning by CVD (Chemical Vapor Deposition) or the like is formed.

  Next, as shown in FIG. 2C, silicon etching is performed using the silicon nitride film 17 as a mask to form a groove having a depth of 200 to 800 nm on the surface of the P-type silicon substrate 1. Next, a thermal oxide film is formed in the groove and CVD or the like using HDP (High Density Plasma) is performed to form an element isolation film 6 (STI element isolation film) in the groove. The element isolation film 6 is flattened by chemical mechanical polishing. The element isolation film 6 can be formed by STI (Shallow Trench isolation) method. Next, after the silicon nitride film 17 and the thermal oxide film 18 are removed by wet etching with phosphoric acid and hydrogen fluoride, a thermal oxide film 19 is formed on the surface of the P-type silicon substrate 1.

  Next, as shown in FIG. 2D, a silicon nitride film 20 patterned to have the etching portion 21 is formed on the surface of the thermal oxide film 19 and the element isolation film 6 by CVD or the like.

Next, as shown in FIG. 2E, silicon etching is performed using the silicon nitride film 20 as a mask to form grooves 22 (concave portions) having a depth of 500 to 1000 nm on the surface of the P-type silicon substrate 1. As will be described later, since the electric field relaxation oxide film 11 is formed in the groove 22, the groove 22 is adjusted to a depth corresponding to the thickness of the electric field relaxation oxide film 11 necessary for ensuring a desired breakdown voltage. Next, a thermal oxide film 23 is formed in the groove 22. Next, a resist 24 is patterned on the silicon nitride film 20 by a lithography process. The resist 24 defines a region where the P-type electric field relaxation layer 5 is to be formed, and is patterned so that the opening width is wider than the opening width of the groove 22 and one end of the opening coincides with one end of the groove 22. Using the formed resist 24 as a mask, phosphorus (P) ions having a dose of 1.0 × 10 ^{12 to} 5.0 × 10 ¹³ / cm are implanted at an acceleration energy of 500 to 5000 keV, thereby A P-type electric field relaxation layer 5 is formed inside. Next, the resist 24 is peeled off. Since the surface of the P-type silicon substrate 1 in the opening of the resist 24 has a step between a portion where the groove 22 is formed and a portion where the groove 22 is not formed, a P-type formed by ion implantation. The electric field relaxation layer 5 has a step corresponding to the step on the surface of the P-type silicon substrate 1.

Next, as shown in FIG. 2F, a resist 25 defining a region for forming the N-type drain electric field relaxation layer 4 is patterned on the surfaces of the silicon nitride film 20 and the groove 22 by a lithography process. The resist 25 is formed so as to open from a part of the groove 22 to the end of the element isolation film 6. By implanting boron (B) ions with a dose of 1.0 × 10 ^{12 to} 5.0 × 10 ¹⁴ / cm at an acceleration energy of 500 to 1000 keV using the formed resist 25 as a mask, An N-type drain electric field relaxation layer 4 is formed inside. Thereafter, the resist 25 is peeled off.

  Next, as shown in FIG. 2G, the field relaxation oxide film 11 is formed in the trench 22 by performing CVD or the like using HDP, and the field relaxation oxide film 11 is planarized by CMP. . Next, the silicon nitride film 20 is removed by wet etching with phosphoric acid and hydrogen fluoride.

Next, as shown in FIG. 2 (h), patterning is performed in the lithography process to form the P-type well 3, and boron (B) ions are applied at several different acceleration energies (30 to 5000 keV). Ion implantation (dose amount is preferably in the range of 1.0 × 10 ^{12 to} 5.0 × 10 ¹³ / cm) is performed to form the P-type well 3 inside the N-type well 2. At this time, it is desirable that the P-type well 3 is connected to the previously formed P-type field relaxation layer 5. Thereafter, the thermal oxide film 19 is removed by wet etching with hydrogen fluoride, and a thermal oxide film is formed by thermal oxidation. This thermal oxide film is shared as the gate oxide film 7 of other devices. Next, a polysilicon film is deposited by a CVD method, and phosphorus is doped to reduce resistance. In order to further reduce the resistance, a tungsten silicide film is deposited by CVD, followed by patterning by lithography and etching by dry etching. Thereafter, the resist is removed, and a gate electrode 8 is formed on the surface of the P-type silicon substrate 1.

Next, as shown in FIG. 2I, an N-type source region 9 is formed in each of the P-type well 3, the N-type drain electric field relaxation layer 4, and the N-type well 2 between the two element isolation films 6. In order to form a diffusion layer 13 for taking the potential of the N-type drain region 12 and the P-type silicon substrate 1, a resist is formed, and BF ₂ ions are implanted, whereby the N-type source region 9, the N-type drain Region 12 and diffusion layer 13 are formed. Next, a resist is formed to form a P-type diffusion layer 10 for taking the potential of the P-type well 3, and arsenic (As) ions are implanted, so that a P is formed at a position adjacent to the N-type source region 9. A mold diffusion layer 10 is formed. When arsenic (As) ions are implanted, LDD (Lightly Doped Drain) implantation for forming another transistor may be performed.

  Next, the resist is peeled off. Thereafter, the LDMOS transistor 100 can be manufactured by the same manufacturing process as that of the conventional MOS transistor. In addition, said manufacturing method is an example and the conditions of ion implantation etc. can be changed suitably.

[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIG. For convenience of explanation, members having the same functions as those described in the embodiment are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 3 is a cross-sectional view of the LDMOS transistor according to the present embodiment.

  As shown in FIG. 3, the LDMOS transistor 101 (semiconductor device) of the present embodiment includes a P-type electric field relaxation layer 50 instead of the P-type electric field relaxation layer 5, and is different from the LDMOS transistor 100 of the first embodiment. Is different.

  The P-type field relaxation layer 50 includes a first P-type field relaxation layer 51 (first field relaxation layer) and a second P-type field relaxation layer 52 (second field relaxation layer) that are separated from each other. 51 is in contact with the P-type well 3, and the second P-type field relaxation layer 52 is located below the field relaxation oxide film 11.

  Even if the P-type field relaxation layer 50 including the first P-type field relaxation layer 51 and the second P-type field relaxation layer 52 is provided as the field relaxation layer as in the present embodiment, the RESURF is formed. A breakdown voltage higher than that of the conventional LDMOS transistor can be realized.

  In the manufacturing process of the LDMOS transistor 100 of the first embodiment, the resist 24 pattern shown in FIG. 2E is changed, and an island of the resist 24 is added in the vicinity of the end of the groove 22 so as to be separated from each other. The LDMOS transistor 101 including the P-type field relaxation layer 50 composed of the first P-type field relaxation layer 51 and the second P-type field relaxation layer 52 can be manufactured.

[Embodiment 3]
The following will describe another embodiment of the present invention with reference to FIG. For convenience of explanation, members having the same functions as those described in the embodiment are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 4 is a cross-sectional view of the LDMOS transistor according to this embodiment.

  As shown in FIG. 4, the LDMOS transistor 102 (semiconductor device) of this embodiment includes a LOCOS element isolation film 60 (element isolation film) instead of the element isolation film 6. 100 is different.

  The LOCOS element isolation film 60 is an element isolation film formed by a LOCOS (Local Oxidation of Silicon) method, which is a method of forming a thick oxide film only at a necessary location by oxidizing silicon using SiN as a mask. By forming the LOCOS element isolation film 60 by the LOCOS method, the manufacturing process can be simplified.

  In the manufacturing process of the LDMOS transistor 102, each ion implantation step for forming the P-type field relaxation layer 5 and the N-type drain field relaxation layer 4 is divided into two times, and the ion implantation is performed before the P-type well 3 is formed. I do.

[Summary]
The semiconductor device (LDMOS transistors 100, 101, 102) according to the first aspect of the present invention has a second well-type first well (N) formed on a surface layer of a first-conductivity-type semiconductor substrate (P-type silicon substrate 1). Type well 2), a first conductivity type second well (P type well 3) formed in the surface layer of the first well, and a source region (N type source region 9) formed in the second well. And a drain region (N-type drain region 12) formed in the surface layer of the first well so as to be separated from the source region, and on the surface of the first well, between the source region and the drain region. A gate electrode (8) formed on the region; an oxide film (electric field relaxation oxide film 11) formed on a surface layer of the semiconductor substrate so as to overlap an end of the gate electrode on the drain region side; Touch the bottom of the second well A first conductivity type electric field relaxation layer (P-type electric field relaxation layer 5), wherein the electric field relaxation layer includes a portion in contact with the second well and a portion located below the oxide film. The depth from the surface of the substrate is different, and the depth of the portion located below the oxide film is set according to the thickness of the oxide film.

  According to said structure, the electric field relaxation layer sets the depth from the surface of a semiconductor substrate according to the thickness of an oxide film. Therefore, even when the thickness of the oxide film is increased, it is not necessary to form the second well in contact with the electric field relaxation layer or to increase the device area.

  Therefore, it is possible to provide a low-cost semiconductor device in which the breakdown voltage is improved by the RESURF structure without increasing the device area.

  The semiconductor device according to Aspect 2 of the present invention is the semiconductor device according to Aspect 1, wherein the electric field relaxation layer is formed at a depth from a surface of the semiconductor substrate at a portion in contact with the second well and at a portion located below the oxide film. The depth from the bottom surface of the oxide film may be equal to each other.

  The semiconductor device according to aspect 3 of the present invention is the semiconductor device according to aspect 1 or 2, wherein the electric field relaxation layer includes a first electric field relaxation layer (first P-type electric field relaxation layer 51) in contact with the second well and the oxide film. It may be configured to include a second electric field relaxation layer (second P-type electric field relaxation layer 52) positioned below and spaced from the first electric field relaxation layer.

  Even in the case of having the electric field relaxation layer composed of the first electric field relaxation layer and the second electric field relaxation layer as in the above configuration, the RESURF is formed and has a higher breakdown voltage than that of the conventional LDMOS transistor. Can be realized.

  The semiconductor device according to aspect 4 of the present invention may have a configuration in which the thickness of the oxide film is set in accordance with a required withstand voltage in any of the above aspects 1 to 3.

  The semiconductor device according to Aspect 5 of the present invention may have a configuration including the LOCOS element isolation film (60) or the STI element isolation film as the element isolation film (6) in any of the above aspects 1 to 4. Good.

  According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first well of a second conductivity type formed in a surface layer of a semiconductor substrate of a first conductivity type; and a first conductivity formed in a surface layer of the first well. A second well of the mold, a source region formed in the second well, a drain region formed in a surface layer of the first well so as to be separated from the source region, and a surface of the first well, A gate electrode formed on a region between the source region and the drain region, and an oxide film formed on a surface layer of the semiconductor substrate so as to overlap an end of the gate electrode on the drain region side; A method of manufacturing a semiconductor device, comprising: a first conductivity type electric field relaxation layer in contact with a bottom of the second well, wherein the step of forming a recess in the semiconductor substrate; Ions are implanted from the formed surface By Rukoto, characterized in that it includes a step of forming the field relaxation layer, forming an oxide film on the inside of the recess, the.

  According to the above manufacturing method, the depth from the surface of the semiconductor substrate differs between the portion in contact with the second well and the portion located below the oxide film, and the depth of the portion located below the oxide film is An electric field relaxation layer set according to the depth of the recess (thickness of the oxide film) can be formed.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.

1 P-type silicon substrate (semiconductor substrate)
2 N-type well (first well)
3 P-type well (second well)
5, 50 P-type electric field relaxation layer (electric field relaxation layer)
6 Element isolation film (STI element isolation film)
8 Gate electrode 9 N-type source region (source region)
11 Electric field relaxation oxide film (oxide film)
12 N-type drain region (drain region)
60 LOCOS element isolation film 100, 101, 102 LDMOS transistor (semiconductor device)

Claims (5)

A first well of a second conductivity type formed in the surface layer of the semiconductor substrate of the first conductivity type;
A second well of the first conductivity type formed in the surface layer of the first well;
A source region formed in the second well;
A drain region formed in a surface layer of the first well apart from the source region;
A gate electrode formed on a surface between the source region and the drain region on the surface of the first well;
An oxide film formed on a surface layer of the semiconductor substrate so as to overlap an end of the gate electrode on the drain region side;
An electric field relaxation layer of a first conductivity type in contact with the bottom of the second well,
The electric field relaxation layer has different depths from the surface of the semiconductor substrate between a portion in contact with the second well and a portion located below the oxide film, and a depth of a portion located below the oxide film. The thickness is set according to the thickness of the oxide film.   In the electric field relaxation layer, the depth from the surface of the semiconductor substrate in the portion in contact with the second well and the depth from the bottom surface of the oxide film in the portion located below the oxide film are equal to each other. The semiconductor device according to claim 1.   The electric field relaxation layer includes: a first electric field relaxation layer in contact with the second well; and a second electric field relaxation layer located below the oxide film and spaced apart from the first electric field relaxation layer. The semiconductor device according to claim 1 or 2.   4. The semiconductor device according to claim 1, wherein the thickness of the oxide film is set according to a required breakdown voltage. A first well of a second conductivity type formed in the surface layer of the semiconductor substrate of the first conductivity type;
A second well of the first conductivity type formed in the surface layer of the first well;
A source region formed in the second well;
A drain region formed in a surface layer of the first well apart from the source region;
A gate electrode formed on a surface between the source region and the drain region on the surface of the first well;
An oxide film formed on a surface layer of the semiconductor substrate so as to overlap an end of the gate electrode on the drain region side;
A method of manufacturing a semiconductor device comprising: a first conductivity type electric field relaxation layer in contact with a bottom of the second well,
Forming a recess in the semiconductor substrate;
Forming the electric field relaxation layer by implanting ions from the surface where the recess is formed in the semiconductor substrate;
Forming an oxide film inside the recess, and a method for manufacturing a semiconductor device.

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