JP2017028307A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics of a semiconductor device having a nonvolatile memory.SOLUTION: A semiconductor device manufacturing method comprises the steps of: forming a MISFET(LT), a MISFET(HT) and a memory cell MC; forming a stopper film 9 made of a silicon oxide film on the MISFET(LT), the MISFET(HT) and the memory cell; subsequently, forming a stress application film 10 made of a silicon nitride film on the stopper film 9; removing the stress application film 10 on the MISFET(HT) and the memory cell MC; and subsequently, performing a heat treatment to apply stress to the MISFET(LT). As described above, SMT(Stress Memorization Technique) is not applied to all elements but selectively applied. This can reduce a degree of characteristic deterioration in the MISFET(HT) by H(Hydrogen) in the silicon nitride film composing the stress application film 10. Further, this can reduce a degree of characteristic deterioration in the memory cell MC by H(Hydrogen) in the silicon nitride film composing the stress application film 10.SELECTED DRAWING: Figure 57

Description

  The present invention relates to a method for manufacturing a semiconductor device, and can be suitably used for, for example, a method for manufacturing a semiconductor device having a MISFET or a nonvolatile memory cell.

  There is SMT (Stress Memorization Technique) as a technique for improving the characteristics of the MISFET. This SMT is a technique for improving the carrier mobility in the channel by distorting the crystal of the channel by applying a stress to the channel from above the gate electrode.

  For example, in Japanese Patent Application Laid-Open No. 2010-205951 (Patent Document 1), a first stress liner film (81) is formed so as to cover only the NMOS transistor (50N) of the peripheral circuit section (15). A solid-state imaging device in which a stress liner film (82) is formed so as to cover only the PMOS transistor (52P) is disclosed ([0036] to [0039], see FIG. 2). Thus, by not forming the stress liner film on the pixel portion (13), generation of noise due to the stress liner film can be suppressed.

  JP 2009-32962 A (Patent Document 2) discloses that the activation rate of B decreases due to hydrogen in the silicon nitride film regarding the relationship between the SMT film and B (boron) activation rate during annealing. (See [0006] and [0007]). Then, by providing the stressor film (24) in the n-type MOS transistor region (A) and not providing the stressor film (24) in the p-type MOS transistor region (B, C), the current driving capability of the p-type MOS transistor is increased. A technique for improving the current drive capability of an n-type MOS transistor without degrading is disclosed (see [0024] to [0026], [0034], [0035], FIG. 1, etc.).

  Japanese Patent Laying-Open No. 2009-252841 (Patent Document 3) discloses that diffusion of hydrogen into a gate insulating film of a transistor reduces device reliability, and hydrogen atoms from an interlayer insulating film to a memory cell are disclosed. A technique for improving the reliability of the operation of the memory cell by suppressing the diffusion of the memory cell is disclosed.

  In this column, the numbers in parentheses are the symbols described in the document.

JP 2010-205951 A JP 2009-32962 A JP 2009-252841 A

  The present inventor is engaged in research and development of a semiconductor device having a MISFET and is examining improvement in characteristics of a semiconductor device using SMT.

  Here, there are various types of MISFETs provided in the semiconductor device depending on the application, and other forms of elements such as MISFETs and nonvolatile memories may be mounted together. In order to improve the overall characteristics of the semiconductor device in such various forms of semiconductor devices, it is not simply applied SMT, but there is room for improvement in the application location. It became clear by examination of those.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  The outline of the configuration shown in the typical embodiment disclosed in the present application will be briefly described as follows.

  A manufacturing method of a semiconductor device shown in a typical embodiment disclosed in the present application is a manufacturing method of a semiconductor device having a plurality of elements, and SMT is applied to a predetermined element among the plurality of elements. It has a process.

  According to the method for manufacturing a semiconductor device shown in the representative embodiment disclosed in the present application, a semiconductor device having good characteristics can be manufactured.

1 is a main part sectional view showing a configuration of a semiconductor device according to a first embodiment; 7 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of First Embodiment; FIG. FIG. 3 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 2; FIG. 4 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 3 and showing the manufacturing process of the semiconductor device; FIG. 5 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 4 and showing the manufacturing process of the semiconductor device; FIG. 6 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 5; FIG. 7 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 6; FIG. 8 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 7; FIG. 9 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 8; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 9 and showing the manufacturing process of the semiconductor device; FIG. 11 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 10; FIG. 12 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 11; FIG. 13 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 12; FIG. 14 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the first embodiment, following the step shown in FIG. 13; It is a figure which shows the characteristic of MISFET (LT) and MISFET (HT) after SMT application. It is sectional drawing of MISFET which provided the silicon nitride film which is a stress application film | membrane. 7 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device according to the application example of the first embodiment; FIG. FIG. 18 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the application example of Embodiment 1, which is subsequent to FIG. 17; FIG. 10 is a main-portion cross-sectional view for explaining the effect of the manufacturing process of the semiconductor device of the application example of the first embodiment. FIG. 10 is a main-portion cross-sectional view showing the configuration of the semiconductor device of the second embodiment. FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 22 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 21; FIG. 23 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the second embodiment, following the step shown in FIG. 22; FIG. 24 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 23; FIG. 25 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 24; FIG. 26 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the second embodiment, following the step shown in FIG. 25; FIG. 27 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 26; FIG. 28 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 27; FIG. 29 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 28; FIG. 30 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 29; FIG. 31 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 30; FIG. 32 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 31; FIG. 33 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2, which is subsequent to FIG. 32; FIG. 34 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the second embodiment, following the step shown in FIG. 33; FIG. 35 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the second embodiment, following the step shown in FIG. 34; FIG. 36 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the second embodiment, following the step shown in FIG. 35; FIG. 37 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the second embodiment, following the step shown in FIG. 36; It is a figure which shows the characteristic of MISFET (LT) and memory cell MC after SMT application. It is sectional drawing of the memory cell which provided the silicon nitride film which is a stress application film | membrane. FIG. 11 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the application example of the second embodiment. FIG. 41 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the application example of Embodiment 2, which is subsequent to FIG. 40; FIG. 10 is a main-portion cross-sectional view for explaining the effect of the manufacturing process of the semiconductor device of the application example of the second embodiment. It is sectional drawing of the FG type memory cell which provided the silicon nitride film | membrane which is a stress application film | membrane. FIG. 10 is a main-portion cross-sectional view showing the configuration of the semiconductor device of Embodiment 3; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 3; FIG. 46 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 45; FIG. 47 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 46; FIG. 48 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the third embodiment, following the step shown in FIG. 47; FIG. 49 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the third embodiment, following the step shown in FIG. 48; FIG. 50 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 49; FIG. 51 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 50; FIG. 52 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 51; FIG. 53 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the third embodiment, following the step shown in FIG. 52; FIG. 54 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 53; FIG. 55 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 54; FIG. 56 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 55; FIG. 57 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 56; FIG. 58 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 57; FIG. 59 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the third embodiment, following the step shown in FIG. 58; FIG. 60 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 59; FIG. 61 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3, which is subsequent to FIG. 60; It is a figure which shows the characteristic of MISFET (LT), MISFET (HT), and memory cell MC after SMT application. FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the application example of the third embodiment. FIG. 64 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the application example of Embodiment 3, which is subsequent to FIG. 63; FIG. 10 is a main-portion cross-sectional view for explaining the effect of the manufacturing process of the semiconductor device of the application example of the third embodiment. FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 4; FIG. 67 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 4, which is subsequent to FIG. 66; FIG. 68 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the fourth embodiment, following the step shown in FIG. 67; FIG. 69 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 4, which is subsequent to FIG. 68, showing the manufacturing process of the semiconductor device; FIG. 70 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 4, which is subsequent to FIG. 69; FIG. 71 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the fourth embodiment, following the step shown in FIG. 70; FIG. 72 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 4, which is subsequent to FIG. 71; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the application example of the fourth embodiment. FIG. 74 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the application example of Embodiment 4, which is subsequent to FIG. 73; FIG. 25 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 5; FIG. 76 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 75; FIG. 77 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 76; FIG. 78 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the fifth embodiment, following the step shown in FIG. 77; FIG. 78 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 78; FIG. 78 is a cross-sectional view showing a main part of another manufacturing step of the semiconductor device in the fifth embodiment, following the step shown in FIG. 79; FIG. 81 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 80; FIG. 82 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 81; FIG. 83 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 82; FIG. 32 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first example of Embodiment 6; FIG. 85 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first example of Embodiment 6, which is subsequent to FIG. 84; FIG. 86 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first example of Embodiment 6, which is subsequent to FIG. 85; FIG. 32 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the second example of Embodiment 6; FIG. 88 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the second example of Embodiment 6, which is subsequent to FIG. 87, showing the manufacturing process of the semiconductor device; FIG. 89 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the second example of Embodiment 6, which is subsequent to FIG. 88; FIG. 26 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first example of Embodiment 7; FIG. 91 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first example of Embodiment 7, which is subsequent to FIG. 90; FIG. 92 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first example of Embodiment 7, which is subsequent to FIG. 91; FIG. 92 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first example of Embodiment 7, which is subsequent to FIG. 92; FIG. 96 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first example of Embodiment 7, which is subsequent to FIG. 93; FIG. 95 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the first example of Embodiment 7, which is subsequent to FIG. 94; FIG. 32 is a main-portion cross-sectional view showing the manufacturing process of the second example of the semiconductor device in Embodiment 7; FIG. 97 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the second example of Embodiment 7, which is subsequent to FIG. 96; FIG. 99 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the second example of Embodiment 7, which is subsequent to FIG. 97; FIG. 99 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the second example of Embodiment 7, which is subsequent to FIG. 98; FIG. 99 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the second example of Embodiment 7, which is subsequent to FIG. 99; FIG. 100 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the second example of Embodiment 7, which is subsequent to FIG. 100; FIG. 101 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in the second example of Embodiment 7, which is subsequent to FIG. 101;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In addition, when there are a plurality of similar members (parts), a symbol may be added to the generic symbol to indicate an individual or specific part. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see.

  In the cross-sectional view, the size of each part does not correspond to the actual device, and a specific part may be displayed relatively large in order to make the drawing easy to understand.

(Embodiment 1)
Hereinafter, the structure of the semiconductor device of the present embodiment will be described with reference to the drawings.

[Description of structure]
FIG. 1 is a cross-sectional view of the main part showing the configuration of the semiconductor device of the present embodiment. The semiconductor device of this embodiment has a MISFET (LT) and a MISFET (HT).

  The MISFET (LT) is a MISFET formed in the core MIS formation region 1A and having a smaller gate length than the MISFET (HT). The gate length of the MISFET (LT) is, for example, about 40 nm when the manufacturing process is a 40 nm rule generation. Such a MISFET having a relatively small gate length is used, for example, in a circuit (also referred to as a core circuit or a peripheral circuit) for driving other elements such as the memory cell MC. Further, the drive voltage of MISFET (LT) tends to be lower than that of MISFET (HT). Further, the insulating film 3 of the MISFET (LT) may be thinner than the insulating film 3 of the MISFET (HT).

  On the other hand, the MISFET (HT) is a MISFET formed in the I / OMIS formation region 2A and having a larger gate length than the MISFET (LT). The gate length of the MISFET (HT) is, for example, about 1000 nm. Such a MISFET having a relatively large gate length is used, for example, in an input / output circuit (also referred to as an I / O circuit). The MISFET (HT) tends to have a higher drive voltage than the MISFET (LT). Further, the insulating film 3 of the MISFET (HT) may be thicker than the insulating film 3 of the MISFET (LT).

The MISFET (LT) is disposed in the semiconductor substrate 1 (p-type well PW1) on the semiconductor substrate 1 (p-type well PW1) and the semiconductor substrate 1 (p-type well PW1) on both sides of the gate electrode GE. Source and drain regions. A side wall insulating film (side wall, side wall spacer) SW made of an insulating film is formed on the side wall portion of the gate electrode GE. Here, the sidewall insulating film SW is formed of a stacked body of the silicon oxide film SO and the silicon nitride film SN. The source and drain regions have an LDD structure and are composed of an n ⁺ type semiconductor region 8 and an n ⁻ type semiconductor region 7. The n ⁻ type semiconductor region 7 is formed in a self-aligned manner with respect to the side wall of the gate electrode GE. The n ⁺ type semiconductor region 8 is formed in a self-aligned manner with respect to the side surface of the sidewall insulating film SW, and has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 7.

The MISFET (HT) is arranged in the semiconductor substrate 1 (p-type well PW2) on the semiconductor substrate 1 (p-type well PW2) and the semiconductor substrate 1 (p-type well PW2) on both sides of the gate electrode GE. Source and drain regions. A sidewall insulating film SW made of an insulating film is formed on the sidewall portion of the gate electrode GE. Here, the sidewall insulating film SW is formed of a stacked body of the silicon oxide film SO and the silicon nitride film SN. The source and drain regions have an LDD structure and are composed of an n ⁺ type semiconductor region 8 and an n ⁻ type semiconductor region 7. The n ⁻ type semiconductor region 7 is formed in a self-aligned manner with respect to the side wall of the gate electrode GE. The n ⁺ type semiconductor region 8 is formed in a self-aligned manner with respect to the side surface of the sidewall insulating film SW, and has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 7.

  Here, in the present embodiment (FIG. 1), out of the MISFET (LT) and the MISFET (HT), the MISFET (LT) is stressed to the channel region by the SMT, but the MISFET (HT) In SMT, no stress is applied to the channel region.

  This SMT is a technique for improving the carrier mobility in the channel region by applying stress to the channel region from the upper part and the side part of the gate electrode of the MISFET, thereby distorting the crystal in the channel region.

  Specifically, a stress applying film is formed on the upper portion and the side portion of the gate electrode, and heat treatment is performed. By this heat treatment, stress (compressive stress or tensile stress) is applied to the stress application film. Carrier stress can be improved by this stress changing to the channel region below the gate electrode GE and changing the crystal spacing of the channel region. The stress applied to the channel region is maintained even after the stress application film is removed.

  Therefore, in the present embodiment (FIG. 1), the crystal spacing of the channel region of the MISFET (LT) is changed by SMT in the MISFET (LT) and the MISFET (HT). On the other hand, since SMT is not applied to MISFET (HT), there is no change in the crystal spacing of the channel region due to SMT. As described above, in the semiconductor device of this embodiment, the characteristics of the semiconductor device can be comprehensively improved by selectively applying SMT instead of applying SMT to all elements. This will be described in more detail in the “Production Method” section below.

[Product description]
Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 2 to 14 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment.

<Process for forming MISFET (LT) and MISFET (HT)>
First, an example of a process for forming MISFET (LT) and MISFET (HT) will be described.

  As shown in FIG. 2, a silicon substrate made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is prepared as the semiconductor substrate 1. A semiconductor substrate 1 other than the silicon substrate may be used.

  Next, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1. For example, the element isolation region 2 is formed by forming an element isolation groove in the semiconductor substrate 1 and embedding an insulating film such as a silicon oxide film in the element isolation groove.

  Next, the p-type well PW1 is formed in the core MIS formation region 1A of the semiconductor substrate 1, and the p-type well PW2 is formed in the I / OMIS formation region 2A. The p-type wells PW1 and PW2 are formed by ion implantation of a p-type impurity (for example, boron (B)).

  Next, after cleaning the surface of the semiconductor substrate 1 (p-type wells PW1, PW2) by dilute hydrofluoric acid cleaning or the like, as shown in FIG. 3, the main surface of the semiconductor substrate 1 (surfaces of the p-type wells PW1, PW2) Further, as the insulating film (gate insulating film) 3, for example, a silicon oxide film is formed by a thermal oxidation method. As the insulating film 3, in addition to the silicon oxide film, another insulating film such as a silicon oxynitride film may be used. In addition, a metal oxide film having a dielectric constant higher than that of a silicon nitride film, such as a hafnium oxide film, an aluminum oxide film (alumina), or a tantalum oxide film, and a laminated film of the oxide film and the metal oxide film are formed. May be. Further, in addition to the thermal oxidation method, a CVD (Chemical Vapor Deposition) method may be used. Further, the insulating film (gate insulating film) 3 on the core MIS formation region 1A and the insulating film (gate insulating film) 3 on the I / OMIS formation region 2A may have different film thicknesses or different film types. .

  Next, a silicon film 4 is formed on the entire surface of the semiconductor substrate 1 as a conductive film (conductor film). As the silicon film 4, for example, a polycrystalline silicon film is formed using a CVD method or the like. As the silicon film 4, an amorphous silicon film may be deposited and crystallized by heat treatment (crystallization process). This silicon film 4 becomes the gate electrode GE of the MISFET (LT) in the core MIS formation region 1A, and becomes the gate electrode GE of the MISFET (HT) in the I / OMIS formation region 2A.

  Next, impurities are introduced into the silicon film 4. For example, an n-type impurity such as phosphorus is implanted into the silicon film 4.

  Next, a photoresist film (not shown) is formed on the silicon film 4 in the region where the gate electrode GE of the MISFET (LT) is to be formed and the region where the gate electrode GE of the MISFET (HT) is to be formed using photolithography. The silicon film 4 is etched using this photoresist film as a mask. Thereafter, the photoresist film (not shown) is removed by ashing or the like, thereby forming the gate electrode GE of the MISFET (LT) in the core MIS formation region 1A as shown in FIG. 3, thereby forming the I / OMIS. A MISFET (HT) gate electrode GE is formed in the region 2A. The gate length of the gate electrode GE of the MISFET (LT) is about 40 nm, for example, and the gate length of the gate electrode GE of the MISFET (HT) is about 1000 nm, for example.

  In addition, the insulating film 3 remaining under each gate electrode GE becomes a gate insulating film of each MISFET (LT, HT). The insulating film 3 other than the portion covered with the gate electrode GE may be removed when the gate electrode GE is formed, or may be removed by a subsequent patterning process or the like.

Next, in the core MIS formation region 1A and the I / OMIS formation region 2A, an n-type impurity such as arsenic (As) or phosphorus (P) is present in the semiconductor substrate 1 (p-type wells PW1, PW2) on both sides of the gate electrode GE. Is implanted to form the n ⁻ type semiconductor region 7 (FIG. 4). At this time, the n ⁻ type semiconductor region 7 is formed in self-alignment with the sidewall of the gate electrode GE. N in the core MIS formation region 1A ^- -type semiconductor regions 7 and the I / Omis forming region 2A n ^- a type semiconductor region 7 may be different depths of the impurity concentrations and different joining.

  Next, as shown in FIG. 5, in the core MIS formation region 1A and the I / OMIS formation region 2A, a sidewall insulating film SW is formed on the sidewall portion of the gate electrode GE. For example, by depositing a silicon oxide film SO on the entire main surface of the semiconductor substrate 1 and further depositing a silicon nitride film SN thereon, an insulating film made of a laminated film of the silicon oxide film SO and the silicon nitride film SN. Form. By etching back the insulating film, a side wall insulating film SW is formed on the side wall portion of the gate electrode GE. As the sidewall insulating film SW, an insulating film such as a single-layer silicon oxide film or a single-layer silicon nitride film may be used in addition to a stacked film of a silicon oxide film and a silicon nitride film.

Next, as shown in FIG. 6, in the core MIS formation region 1A and the I / OMIS formation region 2A, arsenic (As) or phosphorus (P) is formed in the semiconductor substrate 1 (p-type wells PW1, PW2) on both sides of the gate electrode GE. An n ⁺ type semiconductor region 8 is formed by implanting an n type impurity such as P). At this time, the n ⁺ type semiconductor region 8 is formed in self-alignment with the sidewall insulating film SW on the sidewall portion of the gate electrode GE. The n ⁺ type semiconductor region 8 is formed as a semiconductor region having an impurity concentration higher than that of the n ⁻ type semiconductor region 7 and a deep junction. And ^{n +} -type semiconductor region 8 of the core MIS formation region 1A ^{n +} -type semiconductor region 8 and the I / Omis formation region 2A, may be different depths of the impurity concentrations and different joining.

Through the above steps, the source and drain regions of the LDD structure composed of the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 8 are formed in the core MIS formation region 1A and the I / OMIS formation region 2A.

  Next, a heat treatment (activation process) for activating the impurities introduced into the source / drain regions (7, 8) is performed.

  Through the above steps, the MISFET (LT) is formed in the core MIS formation region 1A, and the MISFET (HT) is formed in the I / OMIS formation region 2A (FIG. 6).

  In addition, about the formation process of MISFET (LT) and MISFET (HT), it is not limited to the said process.

<SMT and silicide process>
Next, as shown in FIG. 7, a silicon oxide film having a thickness of about 13 nm is formed as a stopper film 9 on the semiconductor substrate 1 including the MISFET (LT) and the MISFET (HT) by the CVD method. . For example, a silicon oxide film is formed by a CVD method using TEOS (tetraethoxysilane) and ozone (O ₃ ) as source gases. The stopper film 9 serves as an etching stopper when the stress applying film 10 described later is etched. The stopper film 9 can prevent undesired etching of each pattern (for example, a portion made of a silicon film) constituting the MISFET (LT) and the MISFET (HT). Next, as shown in FIG. 8, a silicon nitride film having a thickness of about 20 nm is formed on the stopper film 9 as the stress applying film 10 by the CVD method. For example, a silicon nitride film is formed by a CVD method using HCD (disilicon hexachloride) and NH ₃ (ammonia) as source gases.

Next, the stress application film 10 in the I / OMIS formation region 2A is removed. First, as shown in FIG. 9, a photoresist film PR1 is formed on the stress application film 10 in the core MIS formation region 1A by using a photolithography method. Next, as shown in FIG. 10, the stress application film 10 is etched using the photoresist film PR1 as a mask. Here, the silicon nitride film constituting the stress applying film 10 is dry-etched. For example, isotropic dry etching is performed using CF ₄ as an etching gas. Thereby, only the core MIS formation region 1 </ b> A is covered with the stress application film 10. In other words, only the MISFET (LT) is covered with the stress application film 10. Further, the stopper film 9 in the I / OMIS formation region 2A is exposed.

  Here, the etching is performed under the condition that the etching selectivity is increased, that is, the etching rate of the stress applying film 10 / the etching rate of the stopper film 9 is increased, but the stopper film 9 is also slightly etched. Thereby, the film thickness of the stopper film 9 in the I / OMIS formation region 2A is smaller than the film thickness of the stopper film 9 remaining under the stress application film 10 in the core MIS formation region 1A (FIG. 10). When the thickness of the stopper film 9 in the I / OMIS formation region 2A is T92 and the thickness of the stopper film 9 in the core MIS formation region 1A is T91, the relationship is T92 <T91.

  Next, as shown in FIG. 11, the photoresist film PR1 is removed by ashing or the like, and then heat treatment (also referred to as annealing) is performed. For example, as the first treatment, instantaneous annealing (also referred to as spike RTA (Rapid Thermal Annealing)) within about 1 second is performed at about 1000 ° C. Next, as a second treatment, laser annealing at about 1200 ° C. is performed. Thereby, stress is generated in the stress application film 10. The stress application film after heat treatment, that is, in a state where stress is applied, is indicated by “10S”. Stress is applied to the MISFET (LT) in the core MIS formation region 1A by the stress application film 10S. On the other hand, since the stress application film 10 in the I / OMIS formation region 2A is removed, no stress is applied to the MISFET (HT).

  Note that this heat treatment may be used to activate impurities introduced into the source and drain regions (7, 8), and the previous heat treatment (activation treatment) may be omitted. Further, the silicon film 4 made of an amorphous silicon film may be crystallized by this heat treatment (crystallization process).

Next, as shown in FIG. 12, the stress application film 10S in the core MIS formation region 1A is removed. Here, the silicon nitride film constituting the stress application film 10S is wet-etched under the condition that the etching selection ratio increases, that is, the etching speed of the stress application film 10S / the etching speed of the stopper film 9 increases. For example, a phosphoric acid (H ₃ PO ₄ ) solution is used as an etchant, and wet etching is performed at 155 ° C. for 600 seconds. As a result, the stopper film 9 in the core MIS formation region 1A and the I / OMIS formation region 2A is exposed.

  Next, as shown in FIG. 13, the stopper film 9 is removed. Here, the silicon oxide film constituting the stopper film 9 is wet-etched under the condition that the etching selection ratio increases, that is, the etching speed of the stopper film 9 / the etching speed of the semiconductor substrate 1 increases. For example, HF solution is used as an etchant, and wet etching is performed at 25 ° C. for 100 seconds.

Next, as shown in FIG. 14, metal silicide layers SIL are formed on the gate electrode GE and the n ⁺ type semiconductor region 8 in the core MIS formation region 1A and the I / OMIS formation region 2A, respectively, using the salicide technique. To do.

  With this metal silicide layer SIL, diffusion resistance, contact resistance, and the like can be reduced. The metal silicide layer SIL can be formed as follows.

For example, a metal film (not shown) is formed on the entire main surface of the semiconductor substrate 1 and the semiconductor substrate 1 is subjected to a heat treatment, whereby the upper layer portion of the gate electrode GE and the n ⁺ type semiconductor region 8 and the above-described portion are formed. The metal film is reacted. Thereby, metal silicide layers SIL are formed on the gate electrode GE and the n ⁺ type semiconductor region 8 respectively. The metal film is made of, for example, a cobalt (Co) film or a nickel (Ni) film, and can be formed using a sputtering method or the like. Next, the unreacted metal film is removed.

Thereafter, although not shown, an interlayer insulating film (not shown) is formed on the entire main surface of the semiconductor substrate 1. Next, in the interlayer insulating film, for example, a contact hole (not shown) that exposes the surface of the n ⁺ type semiconductor region 8 is formed, and a conductive film is embedded in the contact hole to form a plug (not shown). ). Next, wiring (not shown) is formed on the interlayer insulating film in which the plug is embedded.

  Thus, according to the present embodiment, since the SMT is applied only to the MISFET (LT) of the MISFET (LT) and the MISFET (HT), the characteristics of the semiconductor device can be improved comprehensively. .

  When the present inventors examined the case where SMT was applied to both the MISFET (LT) and the MISFET (HT), the result shown in FIG. 15 was obtained. FIG. 15 is a diagram illustrating the characteristics of the MISFET (LT) and the MISFET (HT) after application of SMT.

  That is, in the state where the silicon nitride film as the stress application film 10 exists on the core MIS formation region 1A and the I / OMIS formation region 2A (see, for example, FIG. 8), heat treatment is performed and stress is applied to each element. Considered the case.

  As shown in FIG. 15, for MISFET (LT), an increase in channel current (simply indicated as “current” in FIG. 15) was confirmed due to the effect of SMT. However, the channel current of MISFET (HT) was not changed. This is considered that the MISFET (HT) having a relatively large gate length has a poor effect of SMT and the channel current has not increased.

  On the other hand, HC decreased in both MISFET (LT) and MISFET (HT) elements. Here, “HC” indicates deterioration due to hot carriers, and for example, the time during which the channel current decreases by 10% is defined as the HC life. This is considered to be due to the influence of hydrogen (H) contained in the silicon nitride film used as the stress application film 10.

  FIG. 16 is a cross-sectional view of a MISFET provided with a silicon nitride film as a stress application film. In the MISFET shown in FIG. 16, members having the same functions as those of the MISFET (HT) shown in FIG. 1 are denoted by the same reference numerals, and repeated description thereof is omitted. PW indicates a p-type well.

  As shown in FIG. 16, the silicon nitride film used as the stress application film 10 contains a large amount of H (hydrogen). H (hydrogen) in the silicon nitride film is diffused into the MISFET by heat treatment for applying stress. For example, when H (hydrogen) reaches the interface between the semiconductor substrate 1 (p-type well) and the insulating film 3, it bonds to silicon (Si) and generates a Si—H bond. When hot carriers are generated on the side of the drain region to which a high potential is applied when the MISFET is driven, the Si—H bond is cut and an interface state is obtained. When many interface states are formed, carriers are captured and the driving capability of the MISFET is lowered.

  On the other hand, in the present embodiment, since the SMT is not applied to the MISFET (HT) having a poor SMT effect, the stress application film (silicon nitride film) 10 on the MISFET (HT) is removed. A decrease in the driving capability of the MISFET due to H (hydrogen) in the silicon nitride film can be avoided.

  Thus, by selectively applying SMT, the characteristics of the semiconductor device can be improved comprehensively.

(Explanation of application examples)
In the above process, the stress application film 10 in the I / OMIS formation region 2A is completely removed and the stopper film 9 is exposed in the region (see FIGS. 9 and 10), but the stress application in the I / OMIS formation region 2A is performed. A predetermined film thickness may be removed from the surface of the film 10 so as to reduce the film thickness.

  17 and 18 are cross-sectional views of relevant parts showing the manufacturing steps of the semiconductor device of the application example of the present embodiment.

<Process for forming MISFET (LT) and MISFET (HT)>
As described with reference to FIGS. 2 to 6, the MISFET (LT) is formed in the core MIS formation region 1A, and the MISFET (HT) is formed in the I / OMIS formation region 2A (FIG. 6).

<SMT and silicide process>
Next, as shown in FIG. 17, a silicon oxide film having a thickness of about 5 nm is formed as a stopper film 9 on the semiconductor substrate 1 including the MISFET (LT) and the MISFET (HT) using the CVD method. . Next, a silicon nitride film having a thickness of about 35 nm is formed on the stopper film 9 as the stress application film 10 by the CVD method.

Next, a photoresist film PR2 is formed on the stress application film 10 in the core MIS formation region 1A by using a photolithography method. Next, a predetermined film thickness is etched from the surface of the stress application film 10 using the photoresist film PR2 as a mask. Here, anisotropic etching is anisotropically or isotropically etched to a thickness of about 25 nm from the surface of the silicon nitride film constituting the stress applying film 10. In other words, dry etching is performed until the thickness of the silicon nitride film reaches about 10 nm. For example, dry etching is performed using CF ₄ as an etching gas. Thereby, the film thickness of the stress application film 10 in the I / OMIS formation region 2A is smaller than the film thickness of the stress application film 10 in the core MIS formation region 1A (FIG. 17). When the thickness of the stress application film 10 in the I / OMIS formation region 2A is T102 and the thickness of the stress application film 10 in the core MIS formation region 1A is T101, the relationship of T102 <T101 is established.

  Next, as shown in FIG. 18, the photoresist film PR2 is removed by ashing or the like. Thereafter, heat treatment is performed. For example, as the first treatment, instantaneous annealing (also referred to as spike RTA) within about 1 second is performed at about 1000 ° C. Next, as a second treatment, laser annealing at about 1200 ° C. is performed. Thereby, stress is generated in the stress application film 10. The stress application film 10 applies stress to the MISFET (LT) in the core MIS formation region 1A. Here, the heat treatment condition for applying stress to the stress applying film 10 is preferably a heat treatment of 1000 ° C. or more and within 1 second. On the other hand, since the thickness of the stress application film 10 in the I / OMIS formation region 2A is small, no large stress is applied to the MISFET (HT). The thickness of the stress application film 10 in the I / OMIS formation region 2A is preferably 20 nm or less.

  Thereafter, as described with reference to FIGS. 11 to 14, the stress application film 10 after the heat treatment is removed, and the stopper film 9 is further removed. Next, a metal silicide layer (metal silicide film) SIL is formed using a salicide technique.

  As described above, according to the present embodiment, although the stress application film 10 is formed on the MISFET (LT) and the MISFET (HT) and subjected to the heat treatment, the stress application film 10 of the I / OMIS formation region 2A Since the film thickness is reduced, the influence of H (hydrogen) in the silicon nitride film used as the stress application film can be reduced. Therefore, the degree of characteristic deterioration of the MISFET (HT) due to H (hydrogen) in the silicon nitride film described above can be reduced.

  In the present embodiment, since the thin stress applying film 10 remains in the I / OMIS formation region 2A, the stopper film 9 in the I / OMIS formation region 2A and the stopper film 9 in the core MIS formation region 1A No film thickness difference occurs.

  That is, in FIG. 12, the thickness of the stopper film 9 in the I / OMIS formation region 2A is smaller than the thickness of the stopper film 9 in the core MIS formation region 1A. In such a case, the controllability of etching becomes difficult depending on the remaining film thickness and the film thickness difference of the stopper film 9.

  That is, when etching is performed with reference to the thick film portion, the thin film portion is over-etched. For example, the end portion of the silicon oxide film SO constituting the sidewall insulating film SW, the circled portion in FIG. 19 is etched. Will be. When the metal silicide layer SIL grows in such a location, an increase in leakage current and a breakdown voltage may occur. FIG. 19 is a fragmentary cross-sectional view for explaining the effect of the manufacturing process of the semiconductor device of the application example of the present embodiment.

  Further, when etching is performed based on the thin film portion, a residue of the stopper film 9 may be generated in the thick film portion. On such a residue, the metal silicide layer SIL does not grow sufficiently, and a defect may occur.

  On the other hand, according to the present embodiment, by eliminating the difference in the thickness of the stopper film 9, the metal silicide layer SIL grows in the undesired portion, and the metal silicide layer SIL due to the residue of the stopper film 9. Can be avoided. Therefore, for example, even if the silicon oxide film is formed as a thin film of about 5 nm, the difference in film thickness of the stopper film 9 can be eliminated, and a good metal silicide layer SIL can be formed.

(Embodiment 2)
The structure of the semiconductor device (semiconductor memory device) of the present embodiment will be described below with reference to the drawings.

[Description of structure]
FIG. 20 is a fragmentary cross-sectional view showing the configuration of the semiconductor device of the present embodiment. The semiconductor device of this embodiment includes a MISFET (LT) and a memory cell (also referred to as a nonvolatile memory cell, a nonvolatile memory element, a nonvolatile semiconductor memory device, an EEPROM, or a flash memory) MC.

  The MISFET (LT) is a MISFET formed in the core MIS formation region 1A and having a relatively small gate length. For example, the gate length of the MISFET (LT) is smaller than the sum of the gate length of the control gate electrode CG and the gate length of the memory gate electrode MG of the memory cell MC, for example, about 40 nm. Such a MISFET having a relatively small gate length is used, for example, in a circuit (also referred to as a core circuit or a peripheral circuit) for driving the memory cell MC. MISFET (LT) tends to have a relatively low driving voltage.

The MISFET (LT) is disposed in the semiconductor substrate 1 (p-type well PW1) on the semiconductor substrate 1 (p-type well PW1) and the semiconductor substrate 1 (p-type well PW1) on both sides of the gate electrode GE. Source and drain regions. A side wall insulating film (side wall, side wall spacer) SW made of an insulating film is formed on the side wall portion of the gate electrode GE. Here, the sidewall insulating film SW is formed of a stacked body of the silicon oxide film SO and the silicon nitride film SN. The source and drain regions have an LDD structure and are composed of an n ⁺ type semiconductor region 8 and an n ⁻ type semiconductor region 7. The n ⁻ type semiconductor region 7 is formed in a self-aligned manner with respect to the side wall of the gate electrode GE. The n ⁺ type semiconductor region 8 is formed in a self-aligned manner with respect to the side surface of the sidewall insulating film SW, and has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 7.

  The memory cell MC is disposed above the semiconductor substrate 1 (p-type well PW3), the control gate electrode (gate electrode) CG above the semiconductor substrate 1 (p-type well PW3), and the control gate electrode CG. It has an adjacent memory gate electrode (gate electrode) MG. A thin silicon oxide film CP1 and a silicon nitride film (cap insulating film) CP2 are disposed on the control gate electrode CG. Memory cell MC is further arranged between control gate electrode CG and semiconductor substrate 1 (p-type well PW3), and between insulating film 3 and memory gate electrode MG and semiconductor substrate 1 (p-type well PW3). The insulating film 5 is disposed between the memory gate electrode MG and the control gate electrode CG.

The memory cell MC further includes a source region MS and a drain region MD formed in the p-type well PW3 of the semiconductor substrate 1. A sidewall insulating film (sidewall, sidewall spacer) SW made of an insulating film is formed on the sidewall portion of the combined pattern of the memory gate electrode MG and the control gate electrode CG. Here, the sidewall insulating film SW is formed of a stacked body of the silicon oxide film SO and the silicon nitride film SN. The source region MS includes an n ⁺ type semiconductor region 8a and an n ⁻ type semiconductor region 7a. The n ⁻ type semiconductor region 7a is formed in a self-aligned manner with respect to the sidewall of the memory gate electrode MG. The n ⁺ type semiconductor region 8a is formed in a self-aligned manner with respect to the side surface of the sidewall insulating film SW on the memory gate electrode MG side, and has a deeper junction depth and higher impurity concentration than the n ⁻ type semiconductor region 7a. . The drain region MD includes an n ⁺ type semiconductor region 8b and an n ⁻ type semiconductor region 7b. The n ⁻ type semiconductor region 7b is formed in a self-aligned manner with respect to the side wall of the control gate electrode CG. The n ⁺ type semiconductor region 8b is formed in a self-aligned manner with respect to the side surface of the sidewall insulating film SW on the control gate electrode CG side, and has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 7b. .

  Here, in the present embodiment (FIG. 20), among the MISFET (LT) and the memory cell MC, stress is applied to the channel region by SMT in the MISFET (LT), but the memory cell MC , No stress is applied to the channel region by SMT.

  As described above, this SMT is a technique for improving the carrier mobility in the channel region by distorting the crystal in the channel region by applying stress to the channel region from the top and side surfaces of the gate electrode of the MISFET. is there.

  Therefore, in the present embodiment (FIG. 20), among the MISFET (LT) and the memory cell MC, the crystal spacing of the channel region of the MISFET (LT) is changed by SMT. On the other hand, since SMT is not applied to the memory cell MC, there is no change in the crystal spacing of the channel region due to SMT. As described above, in the semiconductor device of this embodiment, the characteristics of the semiconductor device can be comprehensively improved by selectively applying SMT instead of applying SMT to all elements. This will be described in more detail in the “Production Method” section below.

[Product description]
Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 21 to 37 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment.

<Process for Forming MISFET (LT) and Memory Cell MC>
First, an example of a process for forming the MISFET (LT) and the memory cell MC will be described.

  As shown in FIG. 21, a silicon substrate made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is prepared as the semiconductor substrate 1. A semiconductor substrate 1 other than the silicon substrate may be used.

  Next, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1. For example, the element isolation region 2 is formed by forming an element isolation groove in the semiconductor substrate 1 and embedding an insulating film such as a silicon oxide film in the element isolation groove.

  Next, a p-type well PW1 is formed in the core MIS formation region 1A of the semiconductor substrate 1, and a p-type well PW3 is formed in the memory cell region 3A. The p-type wells PW1 and PW3 are formed by ion implantation of a p-type impurity (for example, boron (B)).

  Next, after cleaning the surface of the semiconductor substrate 1 (p-type wells PW1, PW3) by dilute hydrofluoric acid cleaning or the like, as shown in FIG. 22, the main surface of the semiconductor substrate 1 (surfaces of the p-type wells PW1, PW3) Further, as the insulating film (gate insulating film) 3, for example, a silicon oxide film is formed with a film thickness of about 2 to 3 nm by a thermal oxidation method. As the insulating film 3, in addition to the silicon oxide film, another insulating film such as a silicon oxynitride film may be used. In addition, a metal oxide film having a dielectric constant higher than that of a silicon nitride film, such as a hafnium oxide film, an aluminum oxide film (alumina), or a tantalum oxide film, and a laminated film of the oxide film and the metal oxide film are formed. May be. In addition to the thermal oxidation method, a CVD method may be used. Further, the insulating film (gate insulating film) 3 on the core MIS formation region 1A and the insulating film (gate insulating film) 3 on the memory cell region 3A may have different film thicknesses or different film types.

  Next, a silicon film 4 is formed on the entire surface of the semiconductor substrate 1 as a conductive film (conductor film). As the silicon film 4, for example, a polycrystalline silicon film is formed with a film thickness of about 100 to 200 nm using a CVD method or the like. As the silicon film 4, an amorphous silicon film may be deposited and crystallized by heat treatment (crystallization process). This silicon film 4 becomes the gate electrode GE of the MISFET (LT) in the core MIS formation region 1A, and becomes the control gate electrode CG of the memory cell MC in the memory cell region 3A.

  Next, an n-type impurity (such as arsenic (As) or phosphorus (P)) is implanted into the silicon film 4 in the memory cell region 3A.

  Next, a thin silicon oxide film CP1 is formed by thermally oxidizing the surface of the silicon film 4 to about 3 to 10 nm, for example. The silicon oxide film CP1 may be formed using a CVD method. Next, a silicon nitride film (cap insulating film) CP2 having a thickness of about 50 to 150 nm is formed on the silicon oxide film CP1 using a CVD method or the like.

  Next, a photoresist film (not shown) is formed using a photolithography method in a region where the control gate electrode CG is to be formed, and using this photoresist film as a mask, a silicon nitride film CP2, a silicon oxide film CP1, and The silicon film 4 is etched. Thereafter, the photoresist film is removed by ashing or the like, thereby forming a control gate electrode CG (for example, a gate length of about 80 nm). A series of steps from photolithography to removal of the photoresist film is called patterning. Here, the silicon nitride film CP2 and the silicon oxide film CP1 are formed above the control gate electrode CG, but these films may be omitted.

  Here, in the memory cell region 3A, the insulating film 3 remaining under the control gate electrode CG becomes the gate insulating film of the control transistor. The insulating film 3 other than the portion covered with the control gate electrode CG can be removed by a subsequent patterning process or the like. In the core MIS formation region 1A, the silicon nitride film CP2, the silicon oxide film CP1, and the silicon film 4 are left.

  Next, the silicon nitride film CP2 over the silicon film 4 is removed in the core MIS formation region 1A.

  Next, as shown in FIG. 23, the insulating film 5 (5A, 5N, 5B) is formed on the semiconductor substrate 1 including the upper portions of the silicon nitride film CP2 and the silicon oxide film CP1. First, after the main surface of the semiconductor substrate 1 is cleaned, a silicon oxide film 5A is formed on the semiconductor substrate 1 including the silicon nitride film CP2 and the silicon oxide film CP1 as shown in FIG. The silicon oxide film 5A is formed with a film thickness of, for example, about 4 nm by, for example, a thermal oxidation method (preferably ISSG (In Situ Steam Generation) oxidation). Note that the silicon oxide film 5A may be formed by a CVD method. In the figure, the shape of the silicon oxide film 5A when formed by the CVD method is shown. Next, a silicon nitride film 5N is deposited on the silicon oxide film 5A by a CVD method to a thickness of about 10 nm, for example. The silicon nitride film 5N serves as a charge storage part of the memory cell and serves as an intermediate layer constituting the insulating film (ONO film) 5. Next, a silicon oxide film 5B is deposited on the silicon nitride film 5N by a CVD method to a thickness of about 5 nm, for example.

  Through the above steps, an insulating film (ONO film) 5 composed of the silicon oxide film 5A, the silicon nitride film 5N, and the silicon oxide film 5B can be formed. Note that the insulating film (ONO film) 5 may remain on the silicon oxide film CP1 in the core MIS formation region 1A shown in FIG.

  In the present embodiment, the silicon nitride film 5N is formed as a charge storage portion (charge storage layer, insulating film having a trap level) inside the insulating film 5. For example, a silicon oxynitride film, Another insulating film such as an aluminum oxide film, a hafnium oxide film, or a tantalum oxide film may be used. These films are high dielectric constant films having a higher dielectric constant than the silicon nitride film. Alternatively, the charge storage layer may be formed using an insulating film having silicon nanodots.

  The insulating film 5 formed in the memory cell region 3A functions as a gate insulating film of the memory gate electrode MG and has a charge holding (charge accumulation) function. Therefore, it has a laminated structure of at least three layers and is configured such that the potential barrier height of the inner layer (silicon nitride film 5N) is lower than the potential barrier height of the outer layers (silicon oxide films 5A and 5B). To do. The thickness of each layer has an optimum value for each operation mode of the memory cell.

  Next, a silicon film 6 is formed on the insulating film 5 as a conductive film (conductor film). On the insulating film 5, as the silicon film 6, for example, a polycrystalline silicon film is formed with a film thickness of about 50 to 200 nm using a CVD method or the like. As the silicon film 6, an amorphous silicon film may be deposited and crystallized by heat treatment (crystallization process). An impurity may be introduced into the silicon film 6 as necessary. Further, as will be described later, the silicon film 6 becomes a memory gate electrode MG (for example, a gate length of about 50 nm) in the memory cell region 3A.

  Next, as shown in FIG. 24, the silicon film 6 is etched back. In this etch back process, the silicon film 6 is removed from the surface by anisotropic dry etching by a predetermined thickness. By this step, the silicon film 6 can be left in a sidewall shape (sidewall film shape) via the insulating film 5 on the sidewall portions on both sides of the control gate electrode CG. At this time, in the core MIS formation region 1A and the I / OMIS formation region 2A, the silicon film 6 is etched on the silicon film 4 and the insulating film 5 is exposed. At the boundary between the core MIS formation region 1A and the memory cell region 3A, the silicon film 6 is formed in a sidewall shape (sidewall film) on the side wall of the laminated film of the silicon oxide film CP1 and the silicon film 4 via the insulating film 5. Remains as silicon spacer SP2.

  A memory gate electrode MG is formed by the silicon film 6 remaining on one of the side walls of the control gate electrode CG. Further, the silicon spacer SP1 is formed by the silicon film 6 remaining on the other side wall. The insulating film 5 under the memory gate electrode MG becomes a gate insulating film of the memory transistor. The memory gate length (the gate length of the memory gate electrode MG) is determined corresponding to the deposited film thickness of the silicon film 6.

  Next, as shown in FIG. 25, the silicon spacer SP1 on the side where the memory gate electrode MG is not formed on the side wall of the control gate electrode CG, and the silicon spacer SP2 at the boundary between the core MIS formation region 1A and the memory cell region 3A ( The silicon film 6) is removed.

  Next, the insulating film 5 is removed by etching. As a result, in the memory cell region 3A, the silicon nitride film CP2 above the control gate electrode CG is exposed, and the p-type well PW3 is exposed. In the core MIS formation region 1A, the silicon oxide film CP1 is also removed, and the silicon film 4 is exposed.

  Next, impurities are introduced into the silicon film 4 in the core MIS formation region 1A. For example, an n-type impurity such as phosphorus is implanted into the silicon film 4.

  Next, a photoresist film (not shown) is formed using a photolithography method in a region where the gate electrode GE of the MISFET (LT) of the silicon film 4 is to be formed, and a silicon film is formed using this photoresist film as a mask. 4 is etched. Thereafter, the photoresist film (not shown) is removed by ashing or the like, thereby forming the gate electrode GE of the MISFET (LT) in the core MIS formation region 1A as shown in FIG. The gate length of the gate electrode GE of the MISFET (LT) is, for example, about 40 μm.

  The insulating film 3 remaining under the gate electrode GE becomes a gate insulating film of the MISFET (LT). The insulating film 3 other than the portion covered with the gate electrode GE may be removed when the gate electrode GE is formed, or may be removed by a subsequent patterning process or the like.

  Next, as shown in FIG. 27, p-type impurities are obliquely implanted using a photoresist film (not shown) having an opening on one side of the control gate electrode CG (the side opposite to the memory gate electrode MG) as a mask. (Inclined implantation). Thereby, a p-type halo region (p-type impurity region) HL is formed in the semiconductor substrate 1 below the control gate electrode CG. The p-type halo region HL is not necessarily formed. However, when the p-type halo region HL is formed, the spread of the depletion layer from the drain region MD to the channel region of the memory transistor is suppressed, and the short channel effect of the memory transistor is reduced. It is suppressed. Therefore, a decrease in the threshold voltage of the memory transistor can be suppressed. Thereafter, the photoresist film (not shown) is removed.

Next, in the memory cell region 3A, an n-type impurity such as arsenic (As) or phosphorus (P) is implanted into the semiconductor substrate 1 (p-type well PW1), so that the n ⁻ -type semiconductor region 7a and the n ⁻ -type are implanted. A semiconductor region 7b is formed. At this time, the n ⁻ type semiconductor region 7a is formed in a self-aligned manner on the side wall of the memory gate electrode MG (the side wall opposite to the side adjacent to the control gate electrode CG via the insulating film 5). The n ⁻ type semiconductor region 7b is formed in a self-aligned manner on the side wall of the control gate electrode CG (the side wall opposite to the side adjacent to the memory gate electrode MG via the insulating film 5). In the core MIS formation region 1A, an n ⁻ type impurity such as arsenic (As) or phosphorus (P) is implanted into the semiconductor substrate 1 (p type well PW1) on both sides of the gate electrode GE. A semiconductor region 7 is formed. At this time, the n ⁻ type semiconductor region 7 is formed in self-alignment with the sidewall of the gate electrode GE.

The n ⁻ type semiconductor region 7a, the n ⁻ type semiconductor region 7b, and the n ⁻ type semiconductor region 7 may be formed by the same ion implantation process, but here are formed by different ion implantation processes. In this manner, the n ⁻ type semiconductor region 7a, the n ⁻ type semiconductor region 7b, and the n ⁻ type semiconductor region 7 are formed with a desired impurity concentration and a desired junction depth by forming them in different ion implantation steps. It becomes possible.

  Next, as shown in FIG. 28, in the memory cell region 3A, a sidewall insulating film SW is formed on the sidewall portion of the combined pattern of the control gate electrode CG and the memory gate electrode MG. Further, in the core MIS formation region 1A, a sidewall insulating film SW is formed on the sidewall portion of the gate electrode GE. For example, by depositing a silicon oxide film SO on the entire main surface of the semiconductor substrate 1 and further depositing a silicon nitride film SN thereon, an insulating film made of a laminated film of the silicon oxide film SO and the silicon nitride film SN. Form. By etching back this insulating film, a side wall insulating film SW is formed on the side wall portion of the composite pattern (CG, MG) and the side wall portion of the gate electrode GE. As the sidewall insulating film SW, an insulating film such as a single-layer silicon oxide film or a single-layer silicon nitride film may be used in addition to a stacked film of a silicon oxide film and a silicon nitride film.

Next, as shown in FIG. 29, using the control gate electrode CG, the memory gate electrode MG, and the sidewall insulating film SW as a mask, an n-type impurity such as arsenic (As) or phosphorus (P) is introduced into the semiconductor substrate 1 (p-type well). By implantation into PW3), high impurity concentration n ⁺ type semiconductor regions 8a and n ⁺ type semiconductor regions 8b are formed. At this time, the n ⁺ type semiconductor region 8a is formed in self-alignment with the sidewall insulating film SW on the memory gate electrode MG side in the memory cell region 3A. The n ⁺ type semiconductor region 8b is formed in self-alignment with the sidewall insulating film SW on the control gate electrode CG side in the memory cell region 3A. The n ⁺ type semiconductor region 8a is formed as a semiconductor region having a higher impurity concentration and a deeper junction than the n ⁻ type semiconductor region 7a. The n ⁺ type semiconductor region 8b is formed as a semiconductor region having an impurity concentration higher than that of the n ⁻ type semiconductor region 7b and a deep junction. Further, in the core MIS formation region 1A, an n ⁺ type impurity such as arsenic (As) or phosphorus (P) is implanted into the semiconductor substrate 1 (p type well PW1) on both sides of the gate electrode GE. A semiconductor region 8 is formed. At this time, the n ⁺ type semiconductor region 8 is formed in self-alignment with the sidewall insulating film SW on the sidewall portion of the gate electrode GE. The n ⁺ type semiconductor region 8 is formed as a semiconductor region having an impurity concentration higher than that of the n ⁻ type semiconductor region 7 and a deep junction. The n ⁺ type semiconductor region 8a, the n ⁺ type semiconductor region 8b, and the n ⁺ type semiconductor region 8 may have different impurity concentrations and different junction depths.

Through the above process, in the memory cell region 3A, the n ⁻ type semiconductor region 7b and the n ⁺ type semiconductor region 8b, and the n type drain region MD functioning as the drain region of the memory transistor is formed, and the n ⁻ type semiconductor region 7a. And an n ⁺ type semiconductor region 8a, and an n type source region MS functioning as a source region of the memory transistor is formed. In the core MIS formation region 1A, source and drain regions having an LDD structure including the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 8 are formed.

Next, the source region MS (n ⁻ type semiconductor region 7a and n ⁺ type semiconductor region 8a), the drain region MD (n ⁻ type semiconductor region 7b and n ⁺ type semiconductor region 8b), and the source and drain regions (7, 8). A heat treatment (activation treatment) for activating the impurities introduced into the substrate is performed.

  Through the above steps, a MISFET (LT) is formed in the core MIS formation region 1A, and a memory cell MC is formed in the memory cell region 3A (FIG. 29).

  Note that the process of forming the MISFET (LT) and the memory cell MC is not limited to the above process.

<SMT and silicide process>
Next, as shown in FIG. 30, a silicon oxide film having a thickness of about 13 nm is formed as a stopper film 9 on the semiconductor substrate 1 including the MISFET (LT) and the memory cell MC by the CVD method. For example, a silicon oxide film is formed by a CVD method using TEOS (tetraethoxysilane) and ozone (O ₃ ) as source gases. The stopper film 9 serves as an etching stopper when the stress applying film 10 described later is etched. The stopper film 9 can prevent undesired etching of each pattern (for example, a portion made of a silicon film) constituting the MISFET (LT) and the memory cell MC.

Next, as shown in FIG. 31, a silicon nitride film having a thickness of about 20 nm is formed on the stopper film 9 as the stress applying film 10 by the CVD method. For example, a silicon nitride film is formed by a CVD method using HCD (disilicon hexachloride) and NH ₃ (ammonia) as source gases.

Next, the stress application film 10 in the memory cell region 3A is removed. First, as shown in FIG. 32, a photoresist film PR3 is formed on the stress application film 10 in the core MIS formation region 1A by using a photolithography method. Next, as shown in FIG. 33, the stress applying film 10 is etched using the photoresist film PR3 as a mask. Here, the silicon nitride film constituting the stress applying film 10 is dry-etched. For example, isotropic dry etching is performed using CH ₄ as an etching gas. Thereby, only the core MIS formation region 1 </ b> A is covered with the stress application film 10. In other words, only the MISFET (LT) is covered with the stress application film 10. Further, the stopper film 9 in the memory cell region 3A is exposed.

  Here, the etching is performed under the condition that the etching selectivity is increased, that is, the etching rate of the stress applying film 10 / the etching rate of the stopper film 9 is increased, but the stopper film 9 is also slightly etched. Thereby, the film thickness of the stopper film 9 in the memory cell region 3A is smaller than the film thickness of the stopper film 9 remaining under the stress application film 10 in the core MIS formation region 1A (FIG. 33). When the thickness of the stopper film 9 in the memory cell region 3A is T93 and the thickness of the stopper film 9 in the core MIS formation region 1A is T91, the relationship is T93 <T91.

  Next, as shown in FIG. 34, after the photoresist film PR3 is removed by ashing or the like, heat treatment (also referred to as annealing) is performed. For example, as the first treatment, instantaneous annealing (also referred to as spike RTA) within about 1 second is performed at about 1000 ° C. Next, as a second treatment, laser annealing at about 1200 ° C. is performed. Thereby, stress is generated in the stress application film 10. The stress application film after heat treatment, that is, in a state where stress is applied, is indicated by “10S”. Stress is applied to the MISFET (LT) in the core MIS formation region 1A by the stress application film 10S. On the other hand, since the stress application film 10 in the memory cell region 3A is removed, no stress is applied to the memory cell MC.

Note that, using this heat treatment, the source region MS (n ⁻ type semiconductor region 7a and n ⁺ type semiconductor region 8a), the drain region MD (n ⁻ type semiconductor region 7b and n ⁺ type semiconductor region 8b), and the source and drain Impurities introduced into the regions (7, 8) may be activated, and the previous heat treatment (activation process) may be omitted. Moreover, the silicon films 4 and 6 made of an amorphous silicon film may be crystallized by this heat treatment (crystallization process).

Next, as shown in FIG. 35, the stress application film 10S in the core MIS formation region 1A is removed. Here, the silicon nitride film constituting the stress application film 10S is wet-etched under the condition that the etching selection ratio increases, that is, the etching speed of the stress application film 10S / the etching speed of the stopper film 9 increases. For example, a phosphoric acid (H ₃ PO ₄ ) solution is used as an etchant, and wet etching is performed at 155 ° C. for 600 seconds. As a result, the stopper film 9 in the core MIS formation region 1A and the memory cell region 3A is exposed.

  Next, as shown in FIG. 36, the stopper film 9 is removed. Here, the silicon oxide film constituting the stopper film 9 is wet-etched under the condition that the etching selection ratio increases, that is, the etching speed of the stopper film 9 / the etching speed of the semiconductor substrate 1 increases. For example, HF solution is used as an etchant, and wet etching is performed at 25 ° C. for 100 seconds.

Next, as shown in FIG. 37, using the salicide technique, in the memory cell region 3A, a metal silicide layer (metal silicide layer) is formed on the memory gate electrode MG, the n ⁺ type semiconductor region 8a, and the n ⁺ type semiconductor region 8b, respectively. Membrane) SIL is formed. In the core MIS formation region 1A, metal silicide layers SIL are formed on the gate electrode GE and the n ⁺ type semiconductor region 8, respectively.

  With this metal silicide layer SIL, diffusion resistance, contact resistance, and the like can be reduced. The metal silicide layer SIL can be formed as follows.

For example, a metal film (not shown) is formed on the entire main surface of the semiconductor substrate 1 and the semiconductor substrate 1 is subjected to heat treatment, whereby the memory gate electrode MG, the gate electrode GE, and the n ⁺ type semiconductor region 8. , 8a, 8b are reacted with the metal film. Thereby, the metal silicide layers SIL are formed on the memory gate electrode MG, the gate electrode GE, and the n ⁺ type semiconductor regions 8, 8a, and 8b, respectively. The metal film is made of, for example, a cobalt (Co) film or a nickel (Ni) film, and can be formed using a sputtering method or the like. Next, the unreacted metal film is removed.

Thereafter, although not shown, an interlayer insulating film (not shown) is formed on the entire main surface of the semiconductor substrate 1. Next, in the interlayer insulating film, for example, contact holes (not shown) that expose the surfaces of the n ⁺ type semiconductor regions 8, 8a, and 8b are formed, and a conductive film is embedded in the contact holes to form plugs. (Not shown). Next, wiring (not shown) is formed on the interlayer insulating film in which the plug is embedded.

  As described above, according to the present embodiment, since the SMT is applied only to the MISFET (LT) among the MISFET (LT) and the memory cell MC, the characteristics of the semiconductor device can be improved comprehensively.

  The inventors examined the case where SMT is applied to both the MISFET (LT) and the memory cell MC, and the result shown in FIG. 38 was obtained. FIG. 38 is a diagram illustrating characteristics of the MISFET (LT) and the memory cell MC after application of SMT.

  That is, in the case where the silicon nitride film as the stress application film 10 exists on the core MIS formation region 1A and the memory cell region 3A (see, for example, FIG. 31), heat treatment is performed and stress is applied to each element. investigated.

  As shown in FIG. 38, for MISFET (LT), an increase in channel current (indicated simply as “current” in FIG. 38) was confirmed due to the effect of SMT. However, the channel currents of the MISFET (HT) and the memory cell MC were not changed. This is considered that the memory cell MC having a relatively large gate length has a poor SMT effect and the channel current has not increased.

  On the other hand, HC decreased in all elements of the MISFET (LT) and the memory cell MC. This is considered to be due to the influence of hydrogen (H) contained in the silicon nitride film used as the stress application film 10.

  FIG. 39 is a cross-sectional view of a memory cell provided with a silicon nitride film as a stress application film. In the memory cell shown in FIG. 39, members having the same functions as those of the memory cell MC shown in FIG. 20 are denoted by the same reference numerals, and repetitive description thereof is omitted. PW indicates a p-type well.

  As shown in FIG. 39, H (hydrogen) in the silicon nitride film used as the stress application film 10 is diffused into the memory cell by the heat treatment for applying the stress. For example, when H (hydrogen) reaches the silicon nitride film 5N that is an intermediate layer constituting the insulating film (ONO film) 5, a shallow trap level increases in the charge storage portion of the memory cell. When the charge to be written in the memory cell is held in such a shallow trap level, the charge is easily released, and the retention characteristic of the memory cell is deteriorated.

  On the other hand, in the present embodiment, since the stress application film (silicon nitride film) 10 on the memory cell MC is removed without applying SMT to the memory cell MC having a poor SMT effect, the silicon nitride Degradation of the characteristics of the memory cell MC due to H (hydrogen) in the film can be avoided.

  Of course, for MISFET (LT), channel current can be improved by SMT.

  Thus, by selectively applying SMT, the characteristics of the semiconductor device can be improved comprehensively.

(Explanation of application examples)
In the above process, all of the stress application film 10 in the memory cell region 3A is removed and the stopper film 9 is exposed in the region (see FIGS. 32 and 33), but the stress application film 10 in the memory cell region 3A is A predetermined film thickness may be removed from the surface so as to reduce the film thickness.

  40 and 41 are main-portion cross-sectional views illustrating the manufacturing steps of the semiconductor device of the application example of the present embodiment.

<Process for Forming MISFET (LT) and Memory Cell MC>
As described with reference to FIGS. 21 to 29, a MISFET (LT) is formed in the core MIS formation region 1A, and a memory cell MC is formed in the memory cell region 3A (FIG. 29).

<SMT and silicide process>
Next, as shown in FIG. 40, a silicon oxide film having a thickness of about 5 nm is formed as a stopper film 9 on the semiconductor substrate 1 including the MISFET (LT) and the memory cell MC using the CVD method. Next, a silicon nitride film having a thickness of about 35 nm is formed on the stopper film 9 as the stress application film 10 by the CVD method.

Next, a photoresist film PR4 is formed on the stress application film 10 in the core MIS formation region 1A by using a photolithography method. Next, a predetermined film thickness is etched from the surface of the stress application film 10 using the photoresist film PR4 as a mask. Here, anisotropic etching is anisotropically or isotropically etched to a thickness of about 25 nm from the surface of the silicon nitride film constituting the stress applying film 10. In other words, dry etching is performed until the thickness of the silicon nitride film reaches about 10 nm. For example, dry etching is performed using CF ₄ as an etching gas. Thereby, the film thickness of the stress application film 10 in the memory cell region 3A is smaller than the film thickness of the stress application film 10 in the core MIS formation region 1A (FIG. 40). When the thickness of the stress application film 10 in the memory cell region 3A is T103 and the thickness of the stress application film 10 in the core MIS formation region 1A is T101, the relationship is T103 <T101.

  Next, as shown in FIG. 41, the photoresist film PR4 is removed by ashing or the like. Thereafter, heat treatment is performed. For example, instantaneous annealing (also referred to as spike RTA) within 10 seconds at 1010 ° C. is performed as the first treatment. Next, laser annealing at 1230 ° C. is performed as the second treatment. Thereby, stress is generated in the stress application film 10. The stress application film 10 applies stress to the MISFET (LT) in the core MIS formation region 1A. Here, the heat treatment condition for applying stress to the stress applying film 10 is preferably a heat treatment of 1000 ° C. or more and within 1 second. On the other hand, since the thickness of the stress application film 10 in the memory cell region 3A is small, a large stress is not applied to the memory cell MC. The thickness of the stress application film 10 in the memory cell region 3A is preferably 20 nm or less.

  Thereafter, as described with reference to FIGS. 34 to 37, the stress application film 10 after the heat treatment is removed, and the stopper film 9 is further removed. Next, a metal silicide layer (metal silicide film) SIL is formed using a salicide technique.

  As described above, according to the present embodiment, the stress application film 10 is formed on the MISFET (LT) and the memory cell MC and subjected to the heat treatment, but the thickness of the stress application film 10 in the memory cell region 3A is reduced. Since the size is reduced, the influence of H (hydrogen) in the silicon nitride film used as the stress application film can be reduced. Therefore, the degree of deterioration of the characteristics of the memory cell MC due to H (hydrogen) in the silicon nitride film described above can be reduced.

  In the present embodiment, since the thin stress applying film 10 remains in the memory cell region 3A, there is a difference in film thickness between the stopper film 9 in the memory cell region 3A and the stopper film 9 in the core MIS formation region 1A. Does not occur.

  That is, in FIG. 35, the thickness of the stopper film 9 in the memory cell region 3A is smaller than the thickness of the stopper film 9 in the core MIS formation region 1A. In such a case, the controllability of etching becomes difficult depending on the remaining film thickness and the film thickness difference of the stopper film 9.

  That is, when etching is performed with reference to the thick film portion, the thin film portion is over-etched. For example, the end portion of the silicon oxide film SO constituting the sidewall insulating film SW, the circled portion in FIG. 42 is etched. Will be. When the metal silicide layer SIL grows in such a location, an increase in leakage current and a breakdown voltage may occur. FIG. 42 is a fragmentary cross-sectional view for explaining the effect of the manufacturing process of the semiconductor device of the application example of the present embodiment.

  Further, when etching is performed based on the thin film portion, a residue of the stopper film 9 may be generated in the thick film portion. On such a residue, the metal silicide layer SIL does not grow sufficiently, and a defect may occur.

  On the other hand, according to the present embodiment, by eliminating the difference in the thickness of the stopper film 9, the metal silicide layer SIL grows in the undesired portion, and the metal silicide layer SIL due to the residue of the stopper film 9. Can be avoided. Therefore, for example, even if the silicon oxide film is formed as a thin film of about 5 nm, the difference in film thickness of the stopper film 9 can be eliminated, and a good metal silicide layer SIL can be formed.

  In the present embodiment, a memory cell MC having an insulating film (ONO film) 5 as the memory cell MC, that is, a split gate type having a silicon nitride film 5N as an intermediate layer of the insulating film 5 as a charge storage portion. The memory cell MC has been described as an example, but the structure of the memory cell may be a configuration of a memory cell having a charge storage film of an insulating film (ONO film) only with the memory gate electrode MG without the control gate electrode CG. Further, a memory cell having a charge storage portion made of a conductive film such as polysilicon instead of an insulating film may be used.

  For example, a memory cell having a floating gate electrode FG in an insulating film (hereinafter referred to as “FG type memory cell”; also referred to as a NOR type flash memory or a NAND type flash memory) may be used as the memory cell.

  FIG. 43 is a cross-sectional view of an FG type memory cell provided with a silicon nitride film as a stress applying film. This FG type memory cell includes a floating gate electrode (gate electrode) FG disposed above a semiconductor substrate 1 (p type well PW) via a tunnel oxide film (insulating film) TO, and a floating gate electrode (gate electrode). ) A control gate electrode (gate electrode) CG disposed on the FG via the insulating film IL. Memory cell MC further has a source region S and a drain region D formed in p-type well PW of semiconductor substrate 1. A sidewall insulating film SW made of an insulating film is formed on the sidewall portions of the stacked portions such as the floating gate electrode FG and the control gate electrode CG. As described above, the memory cell includes the floating gate electrode FG surrounded by the insulating film (also referred to as a gate insulating film, TO, IL, and SW) as a charge storage portion.

  Also in this type of memory cell, as shown in FIG. 43, H (hydrogen) in the silicon nitride film used as the stress application film diffuses into the memory cell by the heat treatment for applying the stress. . For example, when H (hydrogen) reaches the tunnel oxide film TO below the floating gate electrode FG, it combines with silicon (Si) to generate a Si—H bond. When hot carriers are generated during a memory cell rewrite operation or the like, the Si—H bond is cut and an interface state is obtained. If a large number of such interface states are formed, carriers are captured and the rewriting characteristics (writing characteristics and erasing characteristics) deteriorate.

  Therefore, in the semiconductor device having the MISFET (LT) and the FG type memory cell, the stress applying film 10 in the memory cell region is removed and SMT is selectively applied as in the present embodiment, so that The characteristics can be improved comprehensively.

  Further, in a semiconductor device having a MISFET (LT) and an FG type memory cell, a stress application film in the memory cell region is applied to a predetermined thickness from the surface so as to reduce the film thickness as in the application example of the present embodiment. By removing the film thickness, the degree of deterioration of the memory cell characteristics due to H (hydrogen) in the silicon nitride film used as the stress application film can be reduced. Further, the difference in film thickness of the stopper film 9 can be eliminated, and a good metal silicide layer can be formed.

  As a memory cell having the floating gate electrode FG, a memory cell having a single gate structure as shown in FIG. 43 is exemplified. However, like the memory cell of the present embodiment, a memory cell having a split gate structure has a floating gate electrode FG. Such a memory cell may be used.

(Embodiment 3)
The structure of the semiconductor device (semiconductor memory device) of the present embodiment will be described below with reference to the drawings.

[Description of structure]
FIG. 44 is a main-portion cross-sectional view showing the configuration of the semiconductor device of the present embodiment. The semiconductor device of this embodiment includes a MISFET (LT), a MISFET (HT), and a memory cell MC.

  The MISFET (LT) is a MISFET formed in the core MIS formation region 1A and having a smaller gate length than the MISFET (HT). For example, the gate length of MISFET (LT) is about 40 nm. Such a MISFET having a relatively small gate length is used, for example, in a circuit (also referred to as a core circuit or a peripheral circuit) for driving the memory cell MC. Further, the drive voltage of MISFET (LT) tends to be lower than that of MISFET (HT). Further, the insulating film 3 of the MISFET (LT) may be thinner than the insulating film 3 of the MISFET (HT).

  On the other hand, the MISFET (HT) is a MISFET formed in the I / OMIS formation region 2A and having a larger gate length than the MISFET (LT). For example, the gate length of MISFET (HT) is about 1000 nm. Such a MISFET having a relatively large gate length is used, for example, in an input / output circuit (also referred to as an I / O circuit). The MISFET (HT) tends to have a higher drive voltage than the MISFET (LT). Further, the insulating film 3 of the MISFET (HT) may be thicker than the insulating film 3 of the MISFET (LT).

The MISFET (LT) is disposed in the semiconductor substrate 1 (p-type well PW1) on the semiconductor substrate 1 (p-type well PW1) and the semiconductor substrate 1 (p-type well PW1) on both sides of the gate electrode GE. Source and drain regions. A sidewall insulating film SW made of an insulating film is formed on the sidewall portion of the gate electrode GE. Here, the sidewall insulating film SW is formed of a stacked body of the silicon oxide film SO and the silicon nitride film SN. The source and drain regions have an LDD structure and are composed of an n ⁺ type semiconductor region 8 and an n ⁻ type semiconductor region 7. The n ⁻ type semiconductor region 7 is formed in a self-aligned manner with respect to the side wall of the gate electrode GE. The n ⁺ type semiconductor region 8 is formed in a self-aligned manner with respect to the side surface of the sidewall insulating film SW, and has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 7.

The MISFET (HT) is arranged in the semiconductor substrate 1 (p-type well PW2) on the semiconductor substrate 1 (p-type well PW2) and the semiconductor substrate 1 (p-type well PW2) on both sides of the gate electrode GE. Source and drain regions. A sidewall insulating film SW made of an insulating film is formed on the sidewall portion of the gate electrode GE. Here, the sidewall insulating film SW is formed of a stacked body of the silicon oxide film SO and the silicon nitride film SN. The source and drain regions have an LDD structure and are composed of an n ⁺ type semiconductor region 8 and an n ⁻ type semiconductor region 7. The n ⁻ type semiconductor region 7 is formed in a self-aligned manner with respect to the side wall of the gate electrode GE. The n ⁺ type semiconductor region 8 is formed in a self-aligned manner with respect to the side surface of the sidewall insulating film SW, and has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 7.

  The memory cell MC is disposed above the semiconductor substrate 1 (p-type well PW3), the control gate electrode (gate electrode) CG above the semiconductor substrate 1 (p-type well PW3), and the control gate electrode CG. It has an adjacent memory gate electrode (gate electrode) MG. A thin silicon oxide film CP1 and a silicon nitride film (cap insulating film) CP2 are disposed on the control gate electrode CG. Memory cell MC is further arranged between control gate electrode CG and semiconductor substrate 1 (p-type well PW3), and between insulating film 3 and memory gate electrode MG and semiconductor substrate 1 (p-type well PW3). The insulating film 5 is disposed between the memory gate electrode MG and the control gate electrode CG.

The memory cell MC further includes a source region MS and a drain region MD formed in the p-type well PW3 of the semiconductor substrate 1. A sidewall insulating film SW made of an insulating film is formed on the sidewall portion of the combined pattern of the memory gate electrode MG and the control gate electrode CG. Here, the sidewall insulating film SW is formed of a stacked body of the silicon oxide film SO and the silicon nitride film SN. The source region MS includes an n ⁺ type semiconductor region 8a and an n ⁻ type semiconductor region 7a. The n ⁻ type semiconductor region 7a is formed in a self-aligned manner with respect to the sidewall of the memory gate electrode MG. The n ⁺ type semiconductor region 8a is formed in a self-aligned manner with respect to the side surface of the sidewall insulating film SW on the memory gate electrode MG side, and has a deeper junction depth and higher impurity concentration than the n ⁻ type semiconductor region 7a. . The drain region MD includes an n ⁺ type semiconductor region 8b and an n ⁻ type semiconductor region 7b. The n ⁻ type semiconductor region 7b is formed in a self-aligned manner with respect to the side wall of the control gate electrode CG. The n ⁺ type semiconductor region 8b is formed in a self-aligned manner with respect to the side surface of the sidewall insulating film SW on the control gate electrode CG side, and has a deeper junction depth and a higher impurity concentration than the n ⁻ type semiconductor region 7b. .

  Here, in the present embodiment (FIG. 44), of the MISFET (LT), the MISFET (HT), and the memory cell MC, a stress is applied to the channel region by SMT in the MISFET (LT). On the other hand, in the MISFET (HT) and the memory cell MC, no stress is applied to the channel region by SMT.

  As described above, this SMT is a technique for improving the carrier mobility in the channel region by distorting the crystal in the channel region by applying stress to the channel region from the top and side surfaces of the gate electrode of the MISFET. is there.

  Specifically, a stress application film is formed on the gate electrode, and heat treatment is performed. By this heat treatment, stress (compressive stress or tensile stress) is applied to the stress application film. Carrier stress can be improved by this stress changing to the channel region below the gate electrode GE and changing the crystal spacing of the channel region. The stress applied to the channel region is maintained even after the stress application film is removed.

  Therefore, in the present embodiment (FIG. 44), among the MISFET (LT), the MISFET (HT), and the memory cell MC, the crystal spacing of the channel region of the MISFET (LT) is changed by the SMT. On the other hand, since SMT is not applied to the MISFET (HT) and the memory cell MC, there is no change in the crystal spacing of the channel region due to SMT. As described above, in the semiconductor device of this embodiment, the characteristics of the semiconductor device can be comprehensively improved by selectively applying SMT instead of applying SMT to all elements. This will be described in more detail in the “Production Method” section below.

[Product description]
Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 45 to 61 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment.

<Process of forming MISFET (LT), MISFET (HT) and memory cell MC>
First, an example of a process for forming MISFET (LT), MISFET (HT), and memory cell MC will be described.

  As shown in FIG. 45, a silicon substrate made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is prepared as the semiconductor substrate 1. A semiconductor substrate 1 other than the silicon substrate may be used.

  Next, the element isolation region 2 is formed on the main surface of the semiconductor substrate 1. For example, the element isolation region 2 is formed by forming an element isolation groove in the semiconductor substrate 1 and embedding an insulating film such as a silicon oxide film in the element isolation groove. Such an element isolation method is called an STI (Shallow Trench Isolation) method. In addition, the element isolation region 2 may be formed using a LOCOS (Local Oxidization of Silicon) method or the like.

  Next, a p-type well PW1 is formed in the core MIS formation region 1A of the semiconductor substrate 1, a p-type well PW2 is formed in the I / OMIS formation region 2A, and a p-type well PW3 is formed in the memory cell region 3A. The p-type wells PW1, PW2, and PW3 are formed by ion implantation of p-type impurities (for example, boron (B)).

  Next, after cleaning the surface of the semiconductor substrate 1 (p-type wells PW1, PW2, and PW3) by dilute hydrofluoric acid cleaning or the like, as shown in FIG. 46, the main surface (p-type wells PW1, PW2,. As the insulating film (gate insulating film) 3, for example, a silicon oxide film is formed with a film thickness of about 2 to 3 nm on the surface of the PW 3 by a thermal oxidation method. As the insulating film 3, in addition to the silicon oxide film, another insulating film such as a silicon oxynitride film may be used. In addition, a metal oxide film having a dielectric constant higher than that of a silicon nitride film, such as a hafnium oxide film, an aluminum oxide film (alumina), or a tantalum oxide film, and a laminated film of the oxide film and the metal oxide film are formed. May be. In addition to the thermal oxidation method, a CVD method may be used. Also, an insulating film (gate insulating film) 3 on the core MIS formation region 1A, an insulating film (gate insulating film) 3 on the I / OMIS formation region 2A, and an insulating film (gate insulating film) 3 on the memory cell region 3A are formed. The film thicknesses may be different from each other, or different film types may be used.

  Next, a silicon film 4 is formed on the entire surface of the semiconductor substrate 1 as a conductive film (conductor film). As the silicon film 4, for example, a polycrystalline silicon film is formed with a film thickness of about 100 to 200 nm using a CVD method or the like. As the silicon film 4, an amorphous silicon film may be deposited and crystallized by heat treatment (crystallization process). The silicon film 4 becomes the gate electrode GE of the MISFET (LT) in the core MIS formation region 1A, the gate electrode GE of the MISFET (HT) in the I / OMIS formation region 2A, and the control gate of the memory cell MC in the memory cell region 3A. It becomes the electrode CG.

  Next, an n-type impurity (such as arsenic (As) or phosphorus (P)) is implanted into the silicon film 4 in the memory cell region 3A.

  Next, a thin silicon oxide film CP1 is formed by thermally oxidizing the surface of the silicon film 4 to about 3 to 10 nm, for example. The silicon oxide film CP1 may be formed using a CVD method. Next, a silicon nitride film (cap insulating film) CP2 having a thickness of about 50 to 150 nm is formed on the silicon oxide film CP1 using a CVD method or the like.

  Next, a photoresist film (not shown) is formed using a photolithography method in a region where the control gate electrode CG is to be formed, and using this photoresist film as a mask, a silicon nitride film CP2, a silicon oxide film CP1, and The silicon film 4 is etched. Thereafter, the photoresist film is removed by ashing or the like, thereby forming a control gate electrode CG (for example, a gate length of about 80 nm). A series of steps from photolithography to removal of the photoresist film is called patterning. Here, the silicon nitride film CP2 and the silicon oxide film CP1 are formed above the control gate electrode CG, but these films may be omitted.

  Here, in the memory cell region 3A, the insulating film 3 remaining under the control gate electrode CG becomes the gate insulating film of the control transistor. The insulating film 3 other than the portion covered with the control gate electrode CG can be removed by a subsequent patterning process or the like. In the core MIS formation region 1A and the I / OMIS formation region 2A, the silicon nitride film CP2, the silicon oxide film CP1, and the silicon film 4 are left.

  Next, the silicon nitride film CP2 over the silicon film 4 is removed in the core MIS formation region 1A.

  Next, as shown in FIG. 47, the insulating film 5 (5A, 5N, 5B) is formed on the semiconductor substrate 1 including the upper portions of the silicon nitride film CP2 and the silicon nitride film CP1. First, after cleaning the main surface of the semiconductor substrate 1, as shown in FIG. 47, a silicon oxide film 5A is formed on the semiconductor substrate 1 including the silicon nitride film CP2 and the upper portion of the silicon nitride film CP1. The silicon oxide film 5A is formed with a film thickness of about 4 nm, for example, by a thermal oxidation method (preferably ISSG oxidation). Note that the silicon oxide film 5A may be formed by a CVD method. In the figure, the shape of the silicon oxide film 5A when formed by the CVD method is shown. Next, a silicon nitride film 5N is deposited on the silicon oxide film 5A by a CVD method to a thickness of about 10 nm, for example. The silicon nitride film 5N serves as a charge storage part of the memory cell and serves as an intermediate layer constituting the insulating film (ONO film) 5.

  Next, a silicon oxide film 5B is deposited on the silicon nitride film 5N by a CVD method to a thickness of about 5 nm, for example.

  Through the above steps, an insulating film (ONO film) 5 composed of the silicon oxide film 5A, the silicon nitride film 5N, and the silicon oxide film 5B can be formed. Note that the insulating film (ONO film) 5 may remain on the silicon nitride film (cap insulating film) CP2 in the core MIS formation region 1A and the I / OMIS formation region 2A shown in FIG.

  In the present embodiment, the silicon nitride film 5N is formed as a charge storage portion (charge storage layer, insulating film having a trap level) inside the insulating film 5. For example, a silicon oxynitride film, Another insulating film such as an aluminum oxide film, a hafnium oxide film, or a tantalum oxide film may be used. These films are high dielectric constant films having a higher dielectric constant than the silicon nitride film. Alternatively, the charge storage layer may be formed using an insulating film having silicon nanodots.

  The insulating film 5 formed in the memory cell region 3A functions as a gate insulating film of the memory gate electrode MG and has a charge holding (charge accumulation) function. Therefore, it has a laminated structure of at least three layers and is configured such that the potential barrier height of the inner layer (silicon nitride film 5N) is lower than the potential barrier height of the outer layers (silicon oxide films 5A and 5B). To do. The thickness of each layer has an optimum value for each operation mode of the memory cell.

  Next, a silicon film 6 is formed on the insulating film 5 as a conductive film (conductor film). On the insulating film 5, as the silicon film 6, for example, a polycrystalline silicon film is formed with a film thickness of about 50 to 200 nm using a CVD method or the like. As the silicon film 6, an amorphous silicon film may be deposited and crystallized by heat treatment (crystallization process). An impurity may be introduced into the silicon film 6 as necessary. Further, as will be described later, the silicon film 6 becomes a memory gate electrode MG (for example, a gate length of about 50 nm) in the memory cell region 3A.

  Next, as shown in FIG. 48, the silicon film 6 is etched back. In this etch back process, the silicon film 6 is removed from the surface by anisotropic dry etching by a predetermined thickness. By this step, the silicon film 6 can be left in a sidewall shape (sidewall film shape) via the insulating film 5 on the sidewall portions on both sides of the control gate electrode CG. At this time, in the core MIS formation region 1A and the I / OMIS formation region 2A, the silicon film 6 is etched and the insulating film 5 is exposed. Note that, at the boundary between the I / OMIS formation region 2A and the memory cell region 3A, the silicon film 6 is formed in a sidewall shape (sidewall) on the sidewall of the laminated film of the silicon oxide film CP1 and the silicon film 4 via the insulating film 5. The film remains as silicon spacer SP2.

  A memory gate electrode MG is formed by the silicon film 6 remaining on one of the side walls of the control gate electrode CG. Further, the silicon spacer SP1 is formed by the silicon film 6 remaining on the other side wall. The insulating film 5 under the memory gate electrode MG becomes a gate insulating film of the memory transistor. The memory gate length (the gate length of the memory gate electrode MG) is determined corresponding to the deposited film thickness of the silicon film 6.

  Next, as shown in FIG. 49, the silicon spacer SP1 on the side where the memory gate electrode MG is not formed at the side wall of the control gate electrode CG, and the silicon spacer SP2 (at the boundary between the core MIS formation region 1A and the memory cell region 3A) The silicon film 6) is removed.

  Next, the insulating film 5 is removed by etching. As a result, in the memory cell region 3A, the silicon nitride film CP2 above the control gate electrode CG is exposed, and the p-type well PW3 is exposed. In the core MIS formation region 1A, the silicon oxide film CP1 is also removed, and the silicon film 4 is exposed.

  Next, impurities are introduced into the silicon film 4 in the core MIS formation region 1A. For example, an n-type impurity such as phosphorus is implanted into the silicon film 4.

  Next, a photoresist film (not shown) is formed on the silicon film 4 in the region where the gate electrode GE of the MISFET (LT) is to be formed and the region where the gate electrode GE of the MISFET (HT) is to be formed using photolithography. The silicon film 4 is etched using this photoresist film as a mask. Thereafter, the photoresist film (not shown) is removed by ashing or the like to form the gate electrode GE of the MISFET (LT) in the core MIS formation region 1A as shown in FIG. A MISFET (HT) gate electrode GE is formed in the region 2A. The gate length of the gate electrode GE of the MISFET (LT) is about 40 nm, for example, and the gate length of the gate electrode GE of the MISFET (HT) is about 1000 nm, for example.

  In addition, the insulating film 3 remaining under each gate electrode GE becomes a gate insulating film of each MISFET (LT, HT). The insulating film 3 other than the portion covered with the gate electrode GE may be removed when the gate electrode GE is formed, or may be removed by a subsequent patterning process or the like.

  Next, as shown in FIG. 51, a p-type impurity is obliquely implanted using a photoresist film (not shown) having an opening on one side of the control gate electrode CG (the side opposite to the memory gate electrode MG) as a mask. (Inclined implantation). Thereby, a p-type halo region (p-type impurity region) HL is formed in the semiconductor substrate 1 below the control gate electrode CG. The p-type halo region HL is not necessarily formed. However, when the p-type halo region HL is formed, the spread of the depletion layer from the drain region MD to the channel region of the memory transistor is suppressed, and the short channel effect of the memory transistor is reduced. It is suppressed. Therefore, a decrease in the threshold voltage of the memory transistor can be suppressed. Thereafter, the photoresist film (not shown) is removed.

Next, in the memory cell region 3A, an n-type impurity such as arsenic (As) or phosphorus (P) is implanted into the semiconductor substrate 1 (p-type well PW1), so that the n ⁻ -type semiconductor region 7a and the n ⁻ -type are implanted. A semiconductor region 7b is formed. At this time, the n ⁻ type semiconductor region 7a is formed in a self-aligned manner on the side wall of the memory gate electrode MG (the side wall opposite to the side adjacent to the control gate electrode CG via the insulating film 5). The n ⁻ type semiconductor region 7b is formed in a self-aligned manner on the side wall of the control gate electrode CG (the side wall opposite to the side adjacent to the memory gate electrode MG via the insulating film 5). In the core MIS formation region 1A and the I / OMIS formation region 2A, n-type impurities such as arsenic (As) or phosphorus (P) are present in the semiconductor substrate 1 (p-type wells PW1, PW2) on both sides of the gate electrode GE. N ⁻ type semiconductor region 7 is formed. At this time, the n ⁻ type semiconductor region 7 is formed in self-alignment with the sidewall of the gate electrode GE.

The n ⁻ type semiconductor region 7a, the n ⁻ type semiconductor region 7b, and the n ⁻ type semiconductor region 7 may be formed by the same ion implantation process, but here are formed by different ion implantation processes. In this manner, the n ⁻ type semiconductor region 7a, the n ⁻ type semiconductor region 7b, and the n ⁻ type semiconductor region 7 are formed with a desired impurity concentration and a desired junction depth by forming them in different ion implantation steps. It becomes possible. Further, n in the core MIS formation region 1A ^- -type semiconductor regions 7 and the I / Omis forming region 2A n ^- a type semiconductor region 7 may be different depths of the impurity concentrations and different joining.

  Next, as shown in FIG. 52, in the memory cell region 3A, a sidewall insulating film SW is formed on the sidewall portion of the combined pattern of the control gate electrode CG and the memory gate electrode MG. Further, in the core MIS formation region 1A and the I / OMIS formation region 2A, a sidewall insulating film SW is formed on the sidewall portion of the gate electrode GE. For example, by depositing a silicon oxide film SO on the entire main surface of the semiconductor substrate 1 and further depositing a silicon nitride film SN thereon, an insulating film made of a laminated film of the silicon oxide film SO and the silicon nitride film SN. Form. By etching back this insulating film, a side wall insulating film SW is formed on the side wall portion of the composite pattern (CG, MG) and the side wall portion of the gate electrode GE. As the sidewall insulating film SW, an insulating film such as a single-layer silicon oxide film or a single-layer silicon nitride film may be used in addition to a stacked film of a silicon oxide film and a silicon nitride film.

Next, as shown in FIG. 53, using the control gate electrode CG, the memory gate electrode MG, and the sidewall insulating film SW as a mask, an n-type impurity such as arsenic (As) or phosphorus (P) is introduced into the semiconductor substrate 1 (p-type well). By implantation into PW3), high impurity concentration n ⁺ type semiconductor regions 8a and n ⁺ type semiconductor regions 8b are formed. At this time, the n ⁺ type semiconductor region 8a is formed in self-alignment with the sidewall insulating film SW on the memory gate electrode MG side in the memory cell region 3A. The n ⁺ type semiconductor region 8b is formed in self-alignment with the sidewall insulating film SW on the control gate electrode CG side in the memory cell region 3A. The n ⁺ type semiconductor region 8a is formed as a semiconductor region having a higher impurity concentration and a deeper junction than the n ⁻ type semiconductor region 7a. The n ⁺ type semiconductor region 8b is formed as a semiconductor region having an impurity concentration higher than that of the n ⁻ type semiconductor region 7b and a deep junction. In the core MIS formation region 1A and the I / OMIS formation region 2A, n-type impurities such as arsenic (As) or phosphorus (P) are present in the semiconductor substrate 1 (p-type wells PW1, PW2) on both sides of the gate electrode GE. N ⁺ type semiconductor region 8 is formed. At this time, the n ⁺ type semiconductor region 8 is formed in self-alignment with the sidewall insulating film SW on the sidewall portion of the gate electrode GE. The n ⁺ type semiconductor region 8 is formed as a semiconductor region having an impurity concentration higher than that of the n ⁻ type semiconductor region 7 and a deep junction. The n ⁺ type semiconductor region 8a, the n ⁺ type semiconductor region 8b, and the n ⁺ type semiconductor region 8 may have different impurity concentrations and different junction depths. Further, the ^{n +} -type semiconductor region 8 of the core MIS formation region 1A ^{n +} -type semiconductor region 8 and the I / Omis formation region 2A, may be different depths of the impurity concentrations and different joining.

Through the above process, in the memory cell region 3A, the n ⁻ type semiconductor region 7b and the n ⁺ type semiconductor region 8b, and the n type drain region MD functioning as the drain region of the memory transistor is formed, and the n ⁻ type semiconductor region 7a. And an n ⁺ type semiconductor region 8a, and an n type source region MS functioning as a source region of the memory transistor is formed. In the core MIS formation region 1A and the I / OMIS formation region 2A, source and drain regions having an LDD structure including the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 8 are formed.

Next, the source region MS (n ⁻ type semiconductor region 7a and n ⁺ type semiconductor region 8a), the drain region MD (n ⁻ type semiconductor region 7b and n ⁺ type semiconductor region 8b), and the source and drain regions (7, 8). A heat treatment (activation treatment) for activating the impurities introduced into the substrate is performed.

  Through the above steps, a MISFET (LT) is formed in the core MIS formation region 1A, a MISFET (HT) is formed in the I / OMIS formation region 2A, and a memory cell MC is formed in the memory cell region 3A (FIG. 53). .

  Note that the process of forming the MISFET (LT), the MISFET (HT), and the memory cell MC is not limited to the above process.

<SMT and silicide process>
Next, as shown in FIG. 54, a silicon oxide film is formed as a stopper film 9 on the semiconductor substrate 1 including the MISFET (LT), the MISFET (HT), and the memory cell MC, and a CVD method is performed with a film thickness of about 13 nm. Use to form. For example, a silicon oxide film is formed by a CVD method using TEOS (tetraethoxysilane) and ozone (O ₃ ) as source gases. The stopper film 9 serves as an etching stopper when the stress applying film 10 described later is etched. The stopper film 9 can prevent undesired etching of each pattern (for example, a portion made of a silicon film) constituting the MISFET (LT), the MISFET (HT), and the memory cell MC.

Next, as shown in FIG. 55, a silicon nitride film having a thickness of about 20 nm is formed on the stopper film 9 as the stress application film 10 by the CVD method. For example, a silicon nitride film is formed by a CVD method using HCD (disilicon hexachloride) and NH ₃ (ammonia) as source gases.

Next, the stress application film 10 in the I / OMIS formation region 2A and the memory cell region 3A is removed. First, as shown in FIG. 56, a photoresist film PR5 is formed on the stress application film 10 in the core MIS formation region 1A by using a photolithography method. Next, as shown in FIG. 57, the stress applying film 10 is etched using the photoresist film PR5 as a mask. Here, the silicon nitride film constituting the stress applying film 10 is dry-etched. For example, isotropic dry etching is performed using CH ₄ as an etching gas. Thereby, only the core MIS formation region 1 </ b> A is covered with the stress application film 10. In other words, only the MISFET (LT) is covered with the stress application film 10. Further, the stopper film 9 in the I / OMIS formation region 2A and the memory cell region 3A is exposed.

  Here, the etching is performed under the condition that the etching selectivity is increased, that is, the etching rate of the stress applying film 10 / the etching rate of the stopper film 9 is increased, but the stopper film 9 is also slightly etched. Thereby, the film thickness of the stopper film 9 in the I / OMIS formation region 2A and the memory cell region 3A is smaller than the film thickness of the stopper film 9 remaining under the stress application film 10 in the core MIS formation region 1A (FIG. 57). ). When the thickness of the stopper film 9 in the I / OMIS formation region 2A is T92, the thickness of the stopper film 9 in the memory cell region 3A is T93, and the thickness of the stopper film 9 in the core MIS formation region 1A is T91. The relationship is T92≈T93 <T91.

  Next, as shown in FIG. 58, after removing the photoresist film PR5 by ashing or the like, heat treatment (also referred to as annealing) is performed. For example, as the first treatment, instantaneous annealing (also referred to as spike RTA) within about 1 second is performed at about 1000 ° C. Next, as a second treatment, laser annealing at about 1200 ° C. is performed. Thereby, stress is generated in the stress application film 10. The stress application film after heat treatment, that is, in a state where stress is applied, is indicated by “10S”. Stress is applied to the MISFET (LT) in the core MIS formation region 1A by the stress application film 10S. On the other hand, since the stress application film 10 in the I / OMIS formation region 2A and the memory cell region 3A is removed, no stress is applied to the MISFET (HT) and the memory cell MC.

Note that, using this heat treatment, the source region MS (n ⁻ type semiconductor region 7a and n ⁺ type semiconductor region 8a), the drain region MD (n ⁻ type semiconductor region 7b and n ⁺ type semiconductor region 8b), and the source and drain Impurities introduced into the regions (7, 8) may be activated, and the previous heat treatment (activation process) may be omitted. Moreover, the silicon films 4 and 6 made of an amorphous silicon film may be crystallized by this heat treatment (crystallization process).

Next, as shown in FIG. 59, the stress application film 10S in the core MIS formation region 1A is removed. Here, the silicon nitride film constituting the stress application film 10S is wet-etched under the condition that the etching selection ratio increases, that is, the etching speed of the stress application film 10S / the etching speed of the stopper film 9 increases. For example, a phosphoric acid (H ₃ PO ₄ ) solution is used as an etchant, and wet etching is performed at 155 ° C. for 600 seconds. As a result, the stopper film 9 in the core MIS formation region 1A, the I / OMIS formation region 2A, and the memory cell region 3A is exposed.

  Next, as shown in FIG. 60, the stopper film 9 is removed. Here, the silicon oxide film constituting the stopper film 9 is wet-etched under the condition that the etching selection ratio increases, that is, the etching speed of the stopper film 9 / the etching speed of the semiconductor substrate 1 increases. For example, HF solution is used as an etchant, and wet etching is performed at 25 ° C. for 100 seconds.

Next, as shown in FIG. 61, in the memory cell region 3A, metal silicide layers (metal silicide layers (metal silicide layers) are respectively formed on the memory gate electrode MG, the n ⁺ type semiconductor region 8a, and the n ⁺ type semiconductor region 8b using the salicide technique. Membrane) SIL is formed. In the core MIS formation region 1A and the I / OMIS formation region 2A, metal silicide layers SIL are formed on the gate electrode GE and the n ⁺ type semiconductor region 8, respectively.

  With this metal silicide layer SIL, diffusion resistance, contact resistance, and the like can be reduced. The metal silicide layer SIL can be formed as follows.

For example, a metal film (not shown) is formed on the entire main surface of the semiconductor substrate 1 and the semiconductor substrate 1 is subjected to heat treatment, whereby the memory gate electrode MG, the gate electrode GE, and the n ⁺ type semiconductor region 8 , 8a, 8b are reacted with the metal film. Thereby, the metal silicide layers SIL are formed on the memory gate electrode MG, the gate electrode GE, and the n ⁺ type semiconductor regions 8, 8a, and 8b, respectively. The metal film is made of, for example, a cobalt (Co) film or a nickel (Ni) film, and can be formed using a sputtering method or the like. Next, the unreacted metal film is removed.

Thereafter, although not shown, an interlayer insulating film (not shown) is formed on the entire main surface of the semiconductor substrate 1. Next, in the interlayer insulating film, for example, contact holes (not shown) that expose the surfaces of the n ⁺ type semiconductor regions 8, 8a, and 8b are formed, and a conductive film is embedded in the contact holes to form plugs. (Not shown). Next, wiring (not shown) is formed on the interlayer insulating film in which the plug is embedded.

  As described above, according to the present embodiment, the SMT is applied only to the MISFET (LT) among the MISFET (LT), the MISFET (HT), and the memory cell MC, so that the characteristics of the semiconductor device are comprehensively improved. Can be made.

  When the present inventors examined the case where SMT was applied to all the elements of MISFET (LT), MISFET (HT), and memory cell MC, the result shown in FIG. 62 was obtained. FIG. 62 is a diagram showing characteristics of the MISFET (LT), the MISFET (HT), and the memory cell MC after application of SMT.

  That is, in the state where the silicon nitride film as the stress application film 10 exists on the core MIS formation region 1A, the I / OMIS formation region 2A, and the memory cell region 3A (see, for example, FIG. 55), heat treatment is performed to The case where stress was applied to was examined.

  As shown in FIG. 62, for MISFET (LT), an increase in channel current (simply indicated as “current” in FIG. 62) was confirmed due to the effect of SMT. However, the channel currents of the MISFET (HT) and the memory cell MC were not changed. This is considered that the MISFET (HT) or the memory cell MC having a relatively large gate length has a poor effect of SMT and the channel current has not increased.

  On the other hand, HC decreased in all elements of MISFET (LT), MISFET (HT) and memory cell MC. This is considered to be due to the influence of hydrogen (H) contained in the silicon nitride film used as the stress application film 10.

  As described with reference to FIG. 16, the silicon nitride film used as the stress application film 10 contains a large amount of H (hydrogen). H (hydrogen) in the silicon nitride film is diffused into the MISFET by heat treatment for applying stress. For example, when H (hydrogen) reaches the interface between the semiconductor substrate 1 (p-type well) and the insulating film 3, it bonds to silicon (Si) and generates a Si—H bond. When hot carriers are generated on the side of the drain region to which a high potential is applied when the MISFET is driven, the Si—H bond is cut and an interface state is obtained. When many interface states are formed, carriers are captured and the driving capability of the MISFET is lowered.

  As described with reference to FIG. 39, H (hydrogen) in the silicon nitride film used as the stress application film 10 diffuses into the memory cell by the heat treatment for applying the stress. For example, when H (hydrogen) reaches the silicon nitride film 5N that is an intermediate layer constituting the insulating film (ONO film) 5, a shallow trap level increases in the charge storage portion of the memory cell. When the charge to be written in the memory cell is held in such a shallow trap level, the charge is easily released, and the retention characteristic of the memory cell is deteriorated.

  On the other hand, in the present embodiment, since the SMT is not applied to the MISFET (HT) having a poor SMT effect, the stress application film (silicon nitride film) 10 on the MISFET (HT) is removed. A decrease in the driving capability of the MISFET due to H (hydrogen) in the silicon nitride film can be avoided.

  Similarly, for the memory cell MC having a poor SMT effect, the stress application film (silicon nitride film) 10 on the memory cell MC is removed without applying the SMT. Degradation of the characteristics of the memory cell MC due to () can be avoided.

  Of course, for MISFET (LT), channel current can be improved by SMT.

  Thus, by selectively applying SMT, the characteristics of the semiconductor device can be improved comprehensively.

(Explanation of application examples)
In the above process, the stress application films 10 in the I / OMIS formation region 2A and the memory cell region 3A are all removed, and the stopper film 9 is exposed in the regions (see FIGS. 56 and 57), but the I / OMIS formation is performed. A predetermined film thickness may be removed from the surface of the stress application film 10 in the region 2A and the memory cell region 3A so as to reduce the film thickness.

  63 and 64 are main-portion cross-sectional views illustrating the manufacturing steps of the semiconductor device of the application example of the present embodiment.

<Process of forming MISFET (LT), MISFET (HT) and memory cell MC>
As described with reference to FIGS. 45 to 53, a MISFET (LT) is formed in the core MIS formation region 1A, a MISFET (HT) is formed in the I / OMIS formation region 2A, and a memory cell MC is formed in the memory cell region 3A. (FIG. 53).

<SMT and silicide process>
Next, as shown in FIG. 63, a silicon oxide film is formed as a stopper film 9 on the semiconductor substrate 1 including the MISFET (LT), the MISFET (HT), and the memory cell MC, with a film thickness of about 5 nm, and a CVD method is performed. Use to form. Next, a silicon nitride film having a thickness of about 35 nm is formed on the stopper film 9 as the stress application film 10 by the CVD method.

Next, a photoresist film PR6 is formed on the stress application film 10 in the core MIS formation region 1A by using a photolithography method. Next, a predetermined film thickness is etched from the surface of the stress application film 10 using the photoresist film PR6 as a mask. Here, anisotropic etching is anisotropically or isotropically etched to a thickness of about 25 nm from the surface of the silicon nitride film constituting the stress applying film 10. In other words, dry etching is performed until the thickness of the silicon nitride film reaches about 10 nm. For example, dry etching is performed using CF ₄ as an etching gas. Thereby, the thickness of the stress application film 10 in the I / OMIS formation region 2A and the memory cell region 3A is smaller than the thickness of the stress application film 10 in the core MIS formation region 1A (FIG. 63). The thickness of the stress application film 10 in the I / OMIS formation region 2A is T102, the thickness of the stress application film 10 in the memory cell region 3A is T103, and the thickness of the stress application film 10 in the core MIS formation region 1A is T101. In this case, T102≈T103 <T101.

  Next, as shown in FIG. 64, the photoresist film PR6 is removed by ashing or the like. Thereafter, heat treatment is performed. For example, as the first treatment, instantaneous annealing (also referred to as spike RTA) within about 1 second is performed at about 1000 ° C. Next, as a second treatment, laser annealing at about 1200 ° C. is performed. Thereby, stress is generated in the stress application film 10. The stress application film 10 applies stress to the MISFET (LT) in the core MIS formation region 1A. Here, the heat treatment condition for applying stress to the stress applying film 10 is preferably a heat treatment of 1000 ° C. or more and within 1 second. On the other hand, since the stress application film 10 in the I / OMIS formation region 2A and the memory cell region 3A has a small thickness, no large stress is applied to the MISFET (HT) and the memory cell MC. The thickness of the stress application film 10 in the I / OMIS formation region 2A and the memory cell region 3A is preferably 25 nm or less.

  Thereafter, as described with reference to FIGS. 58 to 61, the stress application film 10 after the heat treatment is removed, and the stopper film 9 is further removed. Next, a metal silicide layer (metal silicide film) SIL is formed using a salicide technique.

  As described above, according to the present embodiment, the stress application film 10 is formed on the MISFET (LT), the MISFET (HT), and the memory cell MC and subjected to the heat treatment, but the I / OMIS formation region 2A and the memory Since the thickness of the stress application film 10 in the cell region 3A is reduced, the influence of H (hydrogen) in the silicon nitride film used as the stress application film can be reduced. Therefore, the degree of deterioration of the characteristics of the MISFET (HT) and the memory cell MC due to H (hydrogen) in the silicon nitride film described above can be reduced.

  In the present embodiment, since the thin stress applying film 10 remains in the I / OMIS formation region 2A and the memory cell region 3A, the stopper film 9 and the core in the I / OMIS formation region 2A and the memory cell region 3A No difference in film thickness from the stopper film 9 in the MIS formation region 1A occurs.

  That is, in FIG. 59, the thickness of the stopper film 9 in the I / OMIS formation region 2A and the memory cell region 3A is smaller than the thickness of the stopper film 9 in the core MIS formation region 1A. In such a case, the controllability of etching becomes difficult depending on the remaining film thickness and the film thickness difference of the stopper film 9.

  That is, when etching is performed with reference to the thick film portion, the thin film portion is over-etched. For example, the end portion of the silicon oxide film SO constituting the sidewall insulating film SW, the circled portion in FIG. It will be. When the metal silicide layer SIL grows in such a location, an increase in leakage current and a breakdown voltage may occur. FIG. 65 is a main-portion cross-sectional view for explaining the effect of the manufacturing process of the semiconductor device of the application example of the present embodiment.

  Further, when etching is performed based on the thin film portion, a residue of the stopper film 9 may be generated in the thick film portion. On such a residue, the metal silicide layer SIL does not grow sufficiently, and a defect may occur.

  On the other hand, according to the present embodiment, by eliminating the difference in the thickness of the stopper film 9, the metal silicide layer SIL grows in the undesired portion, and the metal silicide layer SIL due to the residue of the stopper film 9. Can be avoided. Therefore, for example, even if the silicon oxide film is formed as a thin film of about 5 nm, the difference in film thickness of the stopper film 9 can be eliminated, and a good metal silicide layer SIL can be formed.

  In this embodiment also, an FG type memory cell may be used as the memory cell. That is, in the semiconductor device having the MISFET (LT), the MISFET (HT), and the FG type memory cell, the stress application film 10 in the memory cell region and the like is removed and the SMT is selectively applied as in the present embodiment. As a result, the characteristics of the semiconductor device can be improved comprehensively.

  Further, in a semiconductor device having a MISFET (LT), a MISFET (HT), and an FG type memory cell, the thickness of the stress application film in the memory cell region or the like is reduced as in the application example of the present embodiment. Then, a predetermined film thickness is removed from the surface. Thereby, the degree of deterioration of the characteristics of the memory cell due to H (hydrogen) in the silicon nitride film used as the stress application film can be reduced. Further, the difference in film thickness of the stopper film 9 can be eliminated, and a good metal silicide layer can be formed.

(Embodiment 4)
The structure of the semiconductor device (semiconductor memory device) of the present embodiment will be described below with reference to the drawings. 66 to 72 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. Of the drawings showing the manufacturing process of the semiconductor device of the present embodiment, the structure of the semiconductor device of the present embodiment will be described with reference to FIG.

[Description of structure]
As shown in FIG. 72, the semiconductor device of the present embodiment has a MISFET (LT), a MISFET (HT), and a memory cell MC as in the third embodiment.

  The main structures of MISFET (LT), MISFET (HT), and memory cell MC are the same as those in the third embodiment.

  Here, in the present embodiment (FIG. 72), MISFET (LT) and MISFET (HT) among MISFET (LT), MISFET (HT) and memory cell MC are subjected to stress in the channel region by SMT. Has been. On the other hand, no stress is applied to the channel region by the SMT in the memory cell MC.

  As described above, this SMT is a technique for improving the carrier mobility in the channel region by distorting the crystal in the channel region by applying stress to the channel region from the top and side surfaces of the gate electrode of the MISFET. is there.

  Therefore, in the present embodiment (FIG. 72), among the MISFET (LT), the MISFET (HT), and the memory cell MC, the crystal spacing of the channel region of the MISFET (LT) and the MISFET (HT) is changed by the SMT. Yes. On the other hand, since SMT is not applied to the memory cell MC, there is no change in the crystal spacing of the channel region due to SMT. As described above, in the semiconductor device of this embodiment, the characteristics of the semiconductor device can be comprehensively improved by selectively applying SMT instead of applying SMT to all elements. This will be described in more detail in the “Production Method” section below.

[Product description]
Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS.

<Process of forming MISFET (LT), MISFET (HT) and memory cell MC>
In the third embodiment, as described with reference to FIGS. 45 to 53, the MISFET (LT) is formed in the core MIS formation region 1A, the MISFET (HT) is formed in the I / OMIS formation region 2A, and the memory cell region 3A. A memory cell MC is formed (FIG. 53).

<SMT and silicide process>
Next, as shown in FIG. 66, on the semiconductor substrate 1 including the MISFET (LT), the MISFET (HT), and the memory cell MC, a silicon oxide film having a thickness of about 13 nm is formed as a stopper film 9 by a CVD method. Use to form. For example, a silicon oxide film is formed by a CVD method using TEOS (tetraethoxysilane) and ozone (O ₃ ) as source gases. The stopper film 9 serves as an etching stopper when the stress applying film 10 described later is etched. The stopper film 9 can prevent undesired etching of each pattern (for example, a portion made of a silicon film) constituting the MISFET (LT), the MISFET (HT), and the memory cell MC.

Next, a silicon nitride film having a thickness of about 20 nm is formed as a stress applying film 10 on the stopper film 9 using a CVD method. For example, a silicon nitride film is formed by a CVD method using HCD (disilicon hexachloride) and NH ₃ (ammonia) as source gases.

Next, the stress application film 10 in the memory cell region 3A is removed. First, as shown in FIG. 67, a photoresist film PR7 is formed on the stress application film 10 in the core MIS formation region 1A and the I / OMIS formation region 2A by using a photolithography method. Next, as shown in FIG. 68, the stress applying film 10 is etched using the photoresist film PR7 as a mask. Here, the silicon nitride film constituting the stress applying film 10 is dry-etched. For example, isotropic dry etching is performed using CH ₄ as an etching gas. As a result, the core MIS formation region 1A and the I / OMIS formation region 2A are covered with the stress application film 10. In other words, the MISFET (LT) and the MISFET (HT) are covered with the stress application film 10. Further, the stopper film 9 in the memory cell region 3A is exposed.

  Here, the etching is performed under the condition that the etching selectivity is increased, that is, the etching rate of the stress applying film 10 / the etching rate of the stopper film 9 is increased, but the stopper film 9 is also slightly etched. Thereby, the thickness of the stopper film 9 in the memory cell region 3A is smaller than the thickness of the stopper film 9 remaining under the stress application film 10 in the core MIS formation region 1A and the I / OMIS formation region 2A (FIG. 68). ). When the thickness of the stopper film 9 in the I / OMIS formation region 2A is T92, the thickness of the stopper film 9 in the memory cell region 3A is T93, and the thickness of the stopper film 9 in the core MIS formation region 1A is T91. The relationship is T93 <T92≈T91.

  Next, as shown in FIG. 69, after removing the photoresist film PR7 by ashing or the like, heat treatment (also referred to as annealing) is performed. For example, as the first treatment, instantaneous annealing (also referred to as spike RTA) within about 1 second is performed at about 1000 ° C. Next, as a second treatment, laser annealing at about 1200 ° C. is performed. Thereby, stress is generated in the stress application film 10. The stress application film after heat treatment, that is, in a state where stress is applied, is indicated by “10S”. Stress is applied to the MISFET (LT) in the core MIS formation region 1A and the MISFET (HT) in the I / OMIS formation region 2A by the stress application film 10S. On the other hand, since the stress application film 10 in the memory cell region 3A is removed, no stress is applied to the memory cell MC.

Note that, using this heat treatment, the source region MS (n ⁻ type semiconductor region 7a and n ⁺ type semiconductor region 8a), the drain region MD (n ⁻ type semiconductor region 7b and n ⁺ type semiconductor region 8b), and the source and drain Impurities introduced into the regions (7, 8) may be activated, and the previous heat treatment (activation process) may be omitted. Moreover, the silicon films 4 and 6 made of an amorphous silicon film may be crystallized by this heat treatment (crystallization process).

Next, as shown in FIG. 70, the stress application film 10S in the core MIS formation region 1A and the I / OMIS formation region 2A is removed. Here, the silicon nitride film constituting the stress application film 10S is wet-etched under the condition that the etching selection ratio increases, that is, the etching speed of the stress application film 10S / the etching speed of the stopper film 9 increases. For example, a phosphoric acid (H ₃ PO ₄ ) solution is used as an etchant, and wet etching is performed at 155 ° C. for 600 seconds. As a result, the stopper film 9 in the core MIS formation region 1A, the I / OMIS formation region 2A, and the memory cell region 3A is exposed.

  Next, as shown in FIG. 71, the stopper film 9 is removed. Here, the silicon oxide film constituting the stopper film 9 is wet-etched under the condition that the etching selection ratio increases, that is, the etching speed of the stopper film 9 / the etching speed of the semiconductor substrate 1 increases. For example, HF solution is used as an etchant, and wet etching is performed at 25 ° C. for 100 seconds.

Next, as shown in FIG. 72, a metal silicide layer (metal silicide layer) is formed on the memory gate electrode MG, the n ⁺ type semiconductor region 8a, and the n ⁺ type semiconductor region 8b in the memory cell region 3A using the salicide technique. Membrane) SIL is formed. In the core MIS formation region 1A and the I / OMIS formation region 2A, metal silicide layers SIL are formed on the gate electrode GE and the n ⁺ type semiconductor region 8, respectively.

  With this metal silicide layer SIL, diffusion resistance, contact resistance, and the like can be reduced. This metal silicide layer SIL can be formed in the same manner as in the third embodiment.

Thereafter, although not shown, an interlayer insulating film (not shown) is formed on the entire main surface of the semiconductor substrate 1. Next, in the interlayer insulating film, for example, contact holes (not shown) that expose the surfaces of the n ⁺ type semiconductor regions 8, 8a, and 8b are formed, and a conductive film is embedded in the contact holes to form plugs. (Not shown). Next, wiring (not shown) is formed on the interlayer insulating film in which the plug is embedded.

  As described above, according to this embodiment, since the SMT is not applied to the memory cell MC having a poor SMT effect, the stress application film (silicon nitride film) 10 on the memory cell MC is removed. As described in detail in FIG. 3, deterioration of the characteristics of the memory cell MC due to H (hydrogen) in the silicon nitride film can be avoided (see FIG. 39).

  Of course, for MISFET (LT), channel current can be improved by SMT.

  As for MISFET (HT), although the effect of SMT is poor and HC is reduced by H (hydrogen) in the silicon nitride film (see FIG. 62), the degree is not as large as that of the memory cell MC. Since the HC deterioration of the memory cell is about 10%, even if the stress application film (silicon nitride film) 10 is left on the MISFET (HT), the influence of the HC reduction is small. Therefore, also in this embodiment, the characteristics of the semiconductor device can be improved comprehensively.

  Thus, by selectively applying SMT, the characteristics of the semiconductor device can be improved comprehensively.

(Explanation of application examples)
In the above process, the stress applying film 10 in the memory cell region 3A is completely removed and the stopper film 9 is exposed in the region (see FIGS. 67 and 68). However, the stress applying film 10 in the memory cell region 3A is A predetermined film thickness may be removed from the surface so as to reduce the film thickness.

  73 and 74 are cross-sectional views of relevant parts showing manufacturing steps of a semiconductor device of an application example of the present embodiment.

<Process of forming MISFET (LT), MISFET (HT) and memory cell MC>
In the third embodiment, as described with reference to FIGS. 45 to 53, the MISFET (LT) is formed in the core MIS formation region 1A, the MISFET (HT) is formed in the I / OMIS formation region 2A, and the memory cell region 3A. A memory cell MC is formed (FIG. 53).

<SMT and silicide process>
Next, as shown in FIG. 73, a silicon oxide film having a thickness of about 5 nm is formed as a stopper film 9 on the semiconductor substrate 1 including the MISFET (LT), the MISFET (HT), and the memory cell MC. Use to form. Next, a silicon nitride film having a thickness of about 35 nm is formed on the stopper film 9 as the stress application film 10 by the CVD method.

Next, a photoresist film PR8 is formed on the stress application film 10 in the core MIS formation region 1A and the I / OMIS formation region 2A using a photolithography method. Next, a predetermined film thickness is etched from the surface of the stress application film 10 using the photoresist film PR8 as a mask. Here, anisotropic etching is anisotropically or isotropically etched to a thickness of about 25 nm from the surface of the silicon nitride film constituting the stress applying film 10. In other words, dry etching is performed until the thickness of the silicon nitride film reaches about 10 nm. For example, dry etching is performed using CF ₄ as an etching gas. Thereby, the thickness of the stress application film 10 in the memory cell region 3A is smaller than the thickness of the stress application film 10 in the core MIS formation region 1A and the I / OMIS formation region 2A (FIG. 73). The thickness of the stress application film 10 in the I / OMIS formation region 2A is T102, the thickness of the stress application film 10 in the memory cell region 3A is T103, and the thickness of the stress application film 10 in the core MIS formation region 1A is T101. In this case, T103 <T102≈T101.

  Next, as shown in FIG. 74, the photoresist film PR8 is removed by ashing or the like. Thereafter, heat treatment is performed. For example, as the first treatment, instantaneous annealing (also referred to as spike RTA) within about 1 second is performed at about 1000 ° C. Next, as a second treatment, laser annealing at about 1200 ° C. is performed. Thereby, stress is generated in the stress application film 10. The stress application film 10 applies stress to the MISFET (LT) in the core MIS formation region 1A. Here, the heat treatment condition for applying stress to the stress applying film 10 is preferably a heat treatment of 1000 ° C. or more and within 1 second. On the other hand, since the thickness of the stress application film 10 in the memory cell region 3A is small, a large stress is not applied to the memory cell MC. The thickness of the stress application film 10 in the memory cell region 3A is preferably 20 nm or less.

  Thereafter, as described with reference to FIGS. 69 to 72, the stress application film 10 after the heat treatment is removed, and the stopper film 9 is further removed. Next, a metal silicide layer (metal silicide film) SIL is formed using a salicide technique.

  As described above, according to the present embodiment, the stress application film 10 is formed on the MISFET (LT), the MISFET (HT), and the memory cell MC, and subjected to the heat treatment, but the stress application film in the memory cell region 3A. Since the film thickness of 10 is reduced, the influence of H (hydrogen) in the silicon nitride film used as the stress application film can be reduced. Therefore, the degree of deterioration of the characteristics of the memory cell MC due to H (hydrogen) in the silicon nitride film described above can be reduced.

  In the present embodiment, since the thin stress applying film 10 remains in the memory cell region 3A, the stopper film 9 in the memory cell region 3A and the stopper film in the core MIS formation region 1A and the I / OMIS formation region 2A No difference in film thickness from 9 occurs.

  Therefore, as described in detail in the application example of the third embodiment, it is possible to avoid the growth of the metal silicide layer SIL in an undesired place and the non-growth of the metal silicide layer SIL due to the residue of the stopper film 9. it can. Therefore, for example, even if the silicon oxide film is formed as a thin film of about 5 nm, the difference in film thickness of the stopper film 9 can be eliminated, and a good metal silicide layer SIL can be formed.

  As described above, MISFET (HT) has a poor effect of SMT, and although HC is reduced by H (hydrogen) in the silicon nitride film (see FIG. 62), the extent is as large as memory cell MC. The effect is small because there is no.

  In this embodiment also, an FG type memory cell may be used as the memory cell. That is, in the semiconductor device having the MISFET (LT), the MISFET (HT), and the FG type memory cell, the stress application film 10 in the memory cell region and the like is removed and the SMT is selectively applied as in the present embodiment. As a result, the characteristics of the semiconductor device can be improved comprehensively.

  Further, in a semiconductor device having a MISFET (LT), a MISFET (HT), and an FG type memory cell, the thickness of the stress application film in the memory cell region or the like is reduced as in the application example of the present embodiment. Then, a predetermined film thickness is removed from the surface. Thereby, the degree of deterioration of the characteristics of the memory cell due to H (hydrogen) in the silicon nitride film used as the stress application film can be reduced. Further, the difference in film thickness of the stopper film 9 can be eliminated, and a good metal silicide layer can be formed.

(Embodiment 5)
In the fourth embodiment, the stress application film 10 is isotropically dry-etched using the photoresist film PR7 as a mask (see FIG. 68), but stress is applied using a hard mask made of a silicon oxide film or the like as a mask. The film 10 may be etched.

  75 to 83 are main-portion cross-sectional views illustrating the manufacturing steps of the semiconductor device of the present embodiment. The structure of the semiconductor device of this embodiment is the same as that of the fourth embodiment.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS.

<Process of forming MISFET (LT), MISFET (HT) and memory cell MC>
In the third embodiment, as described with reference to FIGS. 45 to 53, the MISFET (LT) is formed in the core MIS formation region 1A, the MISFET (HT) is formed in the I / OMIS formation region 2A, and the memory cell region 3A. A memory cell MC is formed (FIG. 53).

<SMT and silicide process>
Next, as shown in FIG. 75, a silicon oxide film having a thickness of about 5 nm is formed as a stopper film 9 on the semiconductor substrate 1 including the MISFET (LT), the MISFET (HT), and the memory cell MC. Use to form. For example, a silicon oxide film is formed by a CVD method using TEOS (tetraethoxysilane) and ozone (O ₃ ) as source gases. The stopper film 9 serves as an etching stopper when the stress applying film 10 described later is etched. The stopper film 9 can prevent undesired etching of each pattern (for example, a portion made of a silicon film) constituting the MISFET (LT), the MISFET (HT), and the memory cell MC.

Next, a silicon nitride film having a thickness of about 20 nm is formed as a stress applying film 10 on the stopper film 9 using a CVD method. For example, a silicon nitride film is formed by a CVD method using HCD (disilicon hexachloride) and NH ₃ (ammonia) as source gases.

Next, an insulating film made of the same material as the stopper film 9 is formed on the stress application film 10 as a hard mask (mask film) 11. Here, the silicon oxide film is formed by a CVD method using TEOS (tetraethoxysilane) and ozone (O ₃ ) as source gases, for example.

  Next, as shown in FIG. 76, a photoresist film PR9 is formed on the stress application film 10 in the core MIS formation region 1A and the I / OMIS formation region 2A using a photolithography method.

Next, as shown in FIG. 76, the hard mask 11 is etched using the photoresist film PR9 as a mask. Here, the silicon oxide film constituting the hard mask 11 is dry-etched. For example, isotropic dry etching is performed using CF ₄ as an etching gas. As a result, the core MIS formation region 1A and the I / OMIS formation region 2A are covered with the hard mask 11. Here, the etching is performed under the condition that the etching selectivity is increased, that is, the etching rate of the hard mask 11 / the etching rate of the stress application film 10 is increased. Next, as shown in FIG. 77, the photoresist film PR9 is removed by ashing or the like.

Next, as shown in FIG. 78, the stress applying film 10 is etched using the hard mask 11 as a mask. Here, the silicon nitride film constituting the stress applying film 10 is wet-etched. For example, wet etching is performed using a phosphoric acid (H ₃ PO ₄ ) solution as an etchant. As a result, the core MIS formation region 1A and the I / OMIS formation region 2A are covered with the stress application film 10. Further, the stopper film 9 in the memory cell region 3A is exposed.

  Next, heat treatment (also referred to as annealing) is performed. For example, as the first treatment, instantaneous annealing (also referred to as spike RTA) within about 1 second is performed at about 1000 ° C. Next, as a second treatment, laser annealing at about 1200 ° C. is performed. Thereby, stress is generated in the stress application film 10. The stress application film after heat treatment, that is, in a state where stress is applied, is indicated by “10S”. Stress is applied to the MISFET (LT) in the core MIS formation region 1A and the MISFET (HT) in the I / OMIS formation region 2A by the stress application film 10S. On the other hand, since the stress application film 10 in the memory cell region 3A is removed, no stress is applied to the memory cell MC.

Note that, using this heat treatment, the source region MS (n ⁻ type semiconductor region 7a and n ⁺ type semiconductor region 8a), the drain region MD (n ⁻ type semiconductor region 7b and n ⁺ type semiconductor region 8b), and the source and drain Impurities introduced into the regions (7, 8) may be activated, and the previous heat treatment (activation process) may be omitted. Moreover, the silicon films 4 and 6 made of an amorphous silicon film may be crystallized by this heat treatment (crystallization process).

  Next, as shown in FIG. 79, a photoresist film PR10 is formed on the stopper film 9 in the memory cell region 3A by using a photolithography method. Next, the hard mask 11 is etched using the photoresist film PR10 as a mask. Here, the silicon oxide film constituting the hard mask 11 is wet-etched. For example, wet etching is performed using HF as an etchant. Next, as shown in FIG. 80, the photoresist film PR10 is removed by ashing or the like.

Next, as shown in FIG. 81, the stress application film 10S in the core MIS formation region 1A and the I / OMIS formation region 2A is removed. Here, the silicon nitride film constituting the stress application film 10S is wet-etched under the condition that the etching selection ratio increases, that is, the etching speed of the stress application film 10S / the etching speed of the stopper film 9 increases. For example, a phosphoric acid (H ₃ PO ₄ ) solution is used as an etchant, and wet etching is performed at 155 ° C. for 600 seconds. As a result, the stopper film 9 in the core MIS formation region 1A, the I / OMIS formation region 2A, and the memory cell region 3A is exposed.

  Next, as shown in FIG. 82, the stopper film 9 is removed. Here, the silicon oxide film constituting the stopper film 9 is wet-etched under the condition that the etching selection ratio increases, that is, the etching speed of the stopper film 9 / the etching speed of the semiconductor substrate 1 increases. For example, HF solution is used as an etchant, and wet etching is performed at 25 ° C. for 100 seconds.

Next, as shown in FIG. 83, a metal silicide layer (metal silicide layer) is respectively formed on the memory gate electrode MG, the n ⁺ type semiconductor region 8a, and the n ⁺ type semiconductor region 8b in the memory cell region 3A using the salicide technique. Membrane) SIL is formed. In the core MIS formation region 1A and the I / OMIS formation region 2A, metal silicide layers SIL are formed on the gate electrode GE and the n ⁺ type semiconductor region 8, respectively.

  With this metal silicide layer SIL, diffusion resistance, contact resistance, and the like can be reduced. This metal silicide layer SIL can be formed in the same manner as in the third embodiment.

Thereafter, although not shown, an interlayer insulating film (not shown) is formed on the entire main surface of the semiconductor substrate 1. Next, in the interlayer insulating film, for example, contact holes (not shown) that expose the surfaces of the n ⁺ type semiconductor regions 8, 8a, and 8b are formed, and a conductive film is embedded in the contact holes to form plugs. (Not shown). Next, wiring (not shown) is formed on the interlayer insulating film in which the plug is embedded.

  As described above, according to the present embodiment, in addition to the effects described in the fourth embodiment, the stress applying film 10 is wet-etched using the hard mask 11 as a mask. Since it is easy to remove the stress application film 10 in the portion, the residue of the stress application film 10 can be reduced.

(Embodiment 6)
In the fourth embodiment and the fifth embodiment, when the stress application film 10 in the memory cell region 3A is removed, the stopper film 9 in the memory cell region 3A, the core MIS formation region 1A, and the I / OMIS formation region 2A A film thickness difference from the stopper film 9 may occur (see FIGS. 68 and 78). This film thickness difference may be corrected using a film thickness adjusting film.

(First example)
84 to 86 are main-portion cross-sectional views showing the manufacturing steps of the semiconductor device of the first example of the present embodiment. The structure of the semiconductor device of this embodiment is the same as that of the fourth embodiment. The manufacturing process up to FIG. 69 is the same as that of the fourth embodiment. However, a silicon oxide film having a thickness of about 5 nm is formed as the stopper film 9.

  In the fourth embodiment, as shown in FIG. 69, the thickness of the stopper film 9 in the memory cell region 3A is smaller than the thickness of the stopper film 9 in the core MIS formation region 1A and the I / OMIS formation region 2A. ing. When the thickness of the stopper film 9 in the I / OMIS formation region 2A is T92, the thickness of the stopper film 9 in the memory cell region 3A is T93, and the thickness of the stopper film 9 in the core MIS formation region 1A is T91, T93 < The relationship is T92≈T91.

Therefore, as shown in FIG. 84, a film made of the same material as the stopper film 9 is formed as the film thickness adjusting film 12 on the semiconductor substrate 1 including the MISFET (LT), the MISFET (HT), and the memory cell MC. . Here, a silicon oxide film (insulating film) is formed with a thickness of about 5 nm by a CVD method. For example, a silicon oxide film is formed by a CVD method using TEOS (tetraethoxysilane) and ozone (O ₃ ) as source gases.

  Next, as shown in FIG. 85, a photoresist film PR11 is formed on the film thickness adjusting film 12 in the memory cell region 3A by using a photolithography method.

  Next, the film thickness adjusting film 12 is etched using the photoresist film PR11 as a mask. Here, the silicon oxide film constituting the film thickness adjusting film 12 is dry-etched. Next, the photoresist film PR11 is removed by ashing or the like, and the stress application film 10S is removed. As a result, as shown in FIG. 86, a stacked film of the stopper film 9 and the film thickness adjusting film 12 is formed in the memory cell region 3A, and the stopper film is formed in the core MIS formation region 1A and the I / OMIS formation region 2A. 9 is exposed.

  Although the film thickness of the film thickness adjusting film 12 is about 5 nm here, the film thickness of the film thickness adjusting film 12 can be adjusted as appropriate based on the difference between T92 and T91.

  Next, as in the fourth embodiment, the film thickness adjusting film 12 and the stopper film 9 are removed. Here, according to the present embodiment, the film thickness adjustment film 12 causes the film thicknesses of the MISFET (LT), the MISFET (HT), and the silicon oxide film (the film thickness adjustment film 12 and the stopper film 9) on the memory cell MC. Since the difference is corrected, the controllability of etching becomes easy. For example, a defect due to a difference in film thickness described in detail in the application example of the third embodiment, for example, growth of a metal silicide layer SIL in an undesired place, or non-growth of a metal silicide layer SIL due to a residue of the stopper film 9 Can be avoided.

  Thereafter, similarly to the fourth embodiment, a metal silicide layer (metal silicide film) SIL is formed by using a salicide technique.

  Thus, according to the present embodiment, in addition to the effects described in the fourth embodiment, it is possible to avoid problems due to the film thickness difference of the stopper film 9.

(Second example)
87 to 89 are main-portion cross-sectional views showing the manufacturing steps of the semiconductor device of the second example of the present embodiment. The structure of the semiconductor device of this embodiment is the same as that of the fifth embodiment. The manufacturing process up to FIG. 78 is the same as that of the fifth embodiment.

  In the fifth embodiment, as shown in FIG. 78, the thickness of the stopper film 9 in the memory cell region 3A is smaller than the thickness of the stopper film 9 in the core MIS formation region 1A and the I / OMIS formation region 2A. ing. When the thickness of the stopper film 9 in the I / OMIS formation region 2A is T92, the thickness of the stopper film 9 in the memory cell region 3A is T93, and the thickness of the stopper film 9 in the core MIS formation region 1A is T91, T93 < The relationship is T92≈T91.

Therefore, as shown in FIG. 87, a film made of the same material as the stopper film 9 is formed as the film thickness adjusting film 12 on the semiconductor substrate 1 including the MISFET (LT), the MISFET (HT), and the memory cell MC. . Here, a silicon oxide film (insulating film) is formed with a thickness of about 5 nm by a CVD method. For example, a silicon oxide film is formed by a CVD method using TEOS (tetraethoxysilane) and ozone (O ₃ ) as source gases.

  Next, as shown in FIG. 88, a photoresist film PR12 is formed on the film thickness adjusting film 12 in the memory cell region 3A by using a photolithography method.

  Next, the film thickness adjusting film 12 and the hard mask 11 are etched using the photoresist film PR12 as a mask. Here, the silicon oxide film constituting the film thickness adjusting film 12 and the hard mask 11 is dry-etched. Next, the photoresist film PR12 is removed by ashing or the like, and the stress application film 10S is further removed. As a result, as shown in FIG. 89, a stacked film of the stopper film 9 and the film thickness adjusting film 12 is formed in the memory cell region 3A, and the stopper film is formed in the core MIS formation region 1A and the I / OMIS formation region 2A. 9 is exposed.

  Although the film thickness of the film thickness adjusting film 12 is about 5 nm here, the film thickness of the film thickness adjusting film 12 can be adjusted as appropriate based on the difference between T92 and T91.

  Next, the film thickness adjusting film 12 and the stopper film 9 are removed as in the fifth embodiment. Here, according to the present embodiment, the film thickness adjustment film 12 causes the film thicknesses of the MISFET (LT), the MISFET (HT), and the silicon oxide film (the film thickness adjustment film 12 and the stopper film 9) on the memory cell MC. Since the difference is corrected, the controllability of etching becomes easy. For example, a defect due to a difference in film thickness described in detail in the application example of the third embodiment, for example, growth of a metal silicide layer SIL in an undesired place, or non-growth of a metal silicide layer SIL due to a residue of the stopper film 9 Can be avoided.

  Thereafter, similarly to the fifth embodiment, a metal silicide layer (metal silicide film) SIL is formed by using a salicide technique.

  Thus, according to the present embodiment, in addition to the effects described in the fifth embodiment, it is possible to avoid problems due to the film thickness difference of the stopper film 9.

  Note that the correction process for the film thickness difference of the stopper film 9 by the film thickness adjusting film 12 described in the present embodiment can also be applied to the first to third embodiments.

  For example, the film thickness adjusting film 12 may be formed before the step of removing the stress applying film 10S of Embodiment 1 (see FIG. 11). Further, the film thickness adjusting film 12 may be formed before the step of removing the stress applying film 10S of the second embodiment (see FIG. 34). Further, the film thickness adjusting film 12 may be formed before the step of removing the stress applying film 10S of the third embodiment (see FIG. 58).

(Embodiment 7)
In the fourth embodiment and the fifth embodiment, when the stress application film 10 in the memory cell region 3A is removed, the stopper film 9 in the memory cell region 3A, the core MIS formation region 1A, and the I / OMIS formation region 2A A film thickness difference from the stopper film 9 may occur (see FIGS. 68 and 78). In consideration of this film thickness difference, the film thickness of the stopper film 9 may be adjusted in advance.

(First example)
90 to 95 are main-portion cross-sectional views showing the manufacturing steps of the semiconductor device of the first example of the present embodiment.

  First, as in the fourth embodiment, a MISFET (LT) is formed in the core MIS formation region 1A, a MISFET (HT) is formed in the I / OMIS formation region 2A, and a memory cell MC is formed in the memory cell region 3A (see FIG. 90). ).

  Next, as shown in FIG. 90, on the semiconductor substrate 1 including the MISFET (LT), the MISFET (HT), and the memory cell MC, a silicon oxide film is formed as a stopper film 9 on the order of 13 nm as in the fourth embodiment. The film is formed using the CVD method.

  Next, a photoresist film PR13 is formed on the stopper film 9 in the memory cell region 3A by using a photolithography method.

Next, as shown in FIG. 91, the stopper film 9 is etched by a predetermined thickness from the surface using the photoresist film PR13 as a mask. Here, anisotropic etching is anisotropically or isotropically performed for a film thickness of about 5 nm from the surface of the silicon oxide film constituting the stopper film 9. For example, dry etching is performed using CF ₄ as an etching gas. Next, the photoresist film PR13 is removed by ashing or the like.

Next, as shown in FIG. 92, a silicon nitride film having a thickness of about 20 nm is formed on the stopper film 9 as the stress applying film 10 by the CVD method. For example, a silicon nitride film is formed by a CVD method using HCD (disilicon hexachloride) and NH ₃ (ammonia) as source gases.

Next, the stress application film 10 in the memory cell region 3A is removed. First, as shown in FIG. 93, a photoresist film PR14 is formed on the stress application film 10 in the core MIS formation region 1A and the I / OMIS formation region 2A by photolithography. Next, the stress applying film 10 is etched using the photoresist film PR14 as a mask. Here, the silicon nitride film constituting the stress applying film 10 is dry-etched. For example, isotropic dry etching is performed using CF ₄ as an etching gas. As a result, the core MIS formation region 1A and the I / OMIS formation region 2A are covered with the stress application film 10. In other words, the MISFET (LT) and the MISFET (HT) are covered with the stress application film 10. Further, the stopper film 9 in the memory cell region 3A is exposed.

  Here, the etching is performed under the condition that the etching selectivity is increased, that is, the etching rate of the stress applying film 10 / the etching rate of the stopper film 9 is increased, but the stopper film 9 is slightly (for example, about 5 nm). ) Etched.

  However, in the present embodiment, since the stopper film 9 in the core MIS formation region 1A and the I / OMIS formation region 2A is pre-etched by about 5 nm from the surface thereof, the stress application film 10 in the memory cell region 3A is removed. After the process, the film thickness difference of the stopper film 9 is corrected. In other words, the film thickness difference of the stopper film 9 is reduced as compared with the case of the fourth embodiment (FIG. 68). For example, when the thickness of the stopper film 9 in the I / OMIS formation region 2A is T92, the thickness of the stopper film 9 in the memory cell region 3A is T93, and the thickness of the stopper film 9 in the core MIS formation region 1A is T91. The relationship can be T93≈T92≈T91.

  Next, as shown in FIG. 94, after removing the photoresist film PR14 by ashing or the like, heat treatment (also referred to as annealing) is performed. For example, as the first treatment, instantaneous annealing (also referred to as spike RTA) within about 1 second is performed at about 1000 ° C. Next, as a second treatment, laser annealing at about 1200 ° C. is performed. Thereby, stress is generated in the stress application film 10. The stress application film after heat treatment, that is, in a state where stress is applied, is indicated by “10S”. Stress is applied to the MISFET (LT) in the core MIS formation region 1A and the MISFET (HT) in the I / OMIS formation region 2A by the stress application film 10S. On the other hand, since the stress application film 10 in the memory cell region 3A is removed, no stress is applied to the memory cell MC.

  Next, as shown in FIG. 95, the stress application film 10S in the core MIS formation region 1A and the I / OMIS formation region 2A is removed. As a result, the stopper film 9 in the core MIS formation region 1A, the I / OMIS formation region 2A, and the memory cell region 3A is exposed.

Next, the stopper film 9 is removed (dry etching). For example, isotropic dry etching is performed using CF ₄ as an etching gas. Here, according to the present embodiment, the stopper film 9 in the core MIS formation region 1A and the I / OMIS formation region 2A is etched in advance by a predetermined film thickness from the surface, so that the stress application film 10S is removed. The film thickness difference of the stopper film 9 remaining after the process is corrected (FIG. 95). Therefore, the controllability of etching of the stopper film 9 becomes easy. For example, a defect due to a difference in film thickness described in detail in the application example of the third embodiment, for example, growth of a metal silicide layer SIL in an undesired place, or non-growth of a metal silicide layer SIL due to a residue of the stopper film 9 Can be avoided.

  Thereafter, similarly to the fourth embodiment, a metal silicide layer (metal silicide film) SIL is formed by using a salicide technique.

  Thus, according to the present embodiment, in addition to the effects described in the fourth embodiment, it is possible to avoid problems due to the film thickness difference of the stopper film 9.

(Second example)
96 to 102 are main-portion cross-sectional views showing the manufacturing steps of the semiconductor device of the second example of the present embodiment.

  First, as in the fifth embodiment, a MISFET (LT) is formed in the core MIS formation region 1A, a MISFET (HT) is formed in the I / OMIS formation region 2A, and a memory cell MC is formed in the memory cell region 3A (see FIG. 96). ).

  Next, as shown in FIG. 96, a silicon oxide film is formed as a stopper film 9 on the semiconductor substrate 1 including the MISFET (LT), the MISFET (HT), and the memory cell MC by the CVD method as in the fifth embodiment. It forms using. Here, a silicon oxide film having a thickness of about 13 nm is formed.

  Next, a photoresist film PR15 is formed on the stopper film 9 in the memory cell region 3A by using a photolithography method.

Next, as shown in FIG. 97, the stopper film 9 is etched by a predetermined thickness from the surface using the photoresist film PR15 as a mask. Here, anisotropic etching is anisotropically or isotropically performed for a film thickness of about 5 nm from the surface of the silicon oxide film constituting the stopper film 9. For example, dry etching is performed using CF ₄ as an etching gas. Next, the photoresist film PR15 is removed by ashing or the like.

Next, as shown in FIG. 98, a silicon nitride film having a thickness of about 20 nm is formed on the stopper film 9 as the stress applying film 10 by the CVD method. For example, a silicon nitride film is formed by a CVD method using HCD (disilicon hexachloride) and NH ₃ (ammonia) as source gases.

Next, an insulating film made of the same material as the stopper film 9 is formed as a hard mask 11 on the stopper film 9. Here, the silicon oxide film is formed by a CVD method using TEOS (tetraethoxysilane) and ozone (O ₃ ) as source gases, for example.

  Next, as shown in FIG. 99, a photoresist film PR16 is formed on the hard mask 11 in the core MIS formation region 1A and the I / OMIS formation region 2A by using a photolithography method. Next, using the photoresist film PR16 as a mask, the hard mask 11 is etched as in the fifth embodiment. Next, the photoresist film PR16 is removed by ashing or the like.

Next, as shown in FIG. 100, the stress applying film 10 is etched using the hard mask 11 as a mask. Here, the silicon nitride film constituting the stress applying film 10 is wet-etched. For example, wet etching is performed using phosphoric acid (H ₃ PO ₄ ) as an etchant. As a result, the core MIS formation region 1A and the I / OMIS formation region 2A are covered with the stress application film 10. Further, the stopper film 9 in the memory cell region 3A is exposed.

  Next, heat treatment (also referred to as annealing) is performed. For example, as the first treatment, instantaneous annealing (also referred to as spike RTA) within about 1 second is performed at about 1000 ° C. Next, as a second treatment, laser annealing at about 1200 ° C. is performed. Thereby, stress is generated in the stress application film 10. The stress application film after heat treatment, that is, in a state where stress is applied, is indicated by “10S”. Stress is applied to the MISFET (LT) in the core MIS formation region 1A and the MISFET (HT) in the I / OMIS formation region 2A by the stress application film 10S. On the other hand, since the stress application film 10 in the memory cell region 3A is removed, no stress is applied to the memory cell MC.

  Next, as shown in FIG. 101, a photoresist film PR17 is formed on the stopper film 9 in the memory cell region 3A by using a photolithography method. Next, the hard mask 11 is etched using the photoresist film PR17 as a mask. Here, the silicon oxide film constituting the hard mask 11 is wet-etched. For example, wet etching is performed using HF as an etchant. Next, as shown in FIG. 102, the photoresist film PR17 is removed by ashing or the like.

  Next, the stress application film 10S in the core MIS formation region 1A and the I / OMIS formation region 2A is removed. As a result, the stopper film 9 in the core MIS formation region 1A, the I / OMIS formation region 2A, and the memory cell region 3A is exposed.

Next, the stopper film 9 is removed (dry etching). For example, isotropic dry etching is performed using CF ₄ as an etching gas. Here, according to the present embodiment, the stopper film 9 in the core MIS formation region 1A and the I / OMIS formation region 2A is etched in advance by a predetermined film thickness from the surface, so that the stress application film 10S is removed. The film thickness difference of the stopper film 9 remaining after the process is corrected (FIG. 102). Therefore, the controllability of etching of the stopper film 9 becomes easy. For example, a defect due to a difference in film thickness described in detail in the application example of the third embodiment, for example, growth of a metal silicide layer SIL in an undesired place, or non-growth of a metal silicide layer SIL due to a residue of the stopper film 9 Can be avoided.

  Thereafter, similarly to the fifth embodiment, a metal silicide layer (metal silicide film) SIL is formed by using a salicide technique.

  Thus, according to the present embodiment, in addition to the effects described in the fifth embodiment, it is possible to avoid problems due to the film thickness difference of the stopper film 9.

  It should be noted that the process of correcting the film thickness difference of the stopper film 9 by previously adjusting the film thickness of the stopper film 9 described in the present embodiment can also be applied to the first to third embodiments.

  For example, the film thickness of the stopper film 9 may be adjusted in advance before the step of forming the stress applying film 10 of Embodiment 1 (see FIG. 7). Further, the film thickness of the stopper film 9 may be adjusted in advance before the step of forming the stress applying film 10 of the second embodiment (see FIG. 30). Further, the film thickness of the stopper film 9 may be adjusted in advance before the step of forming the stress applying film 10 of the third embodiment (see FIG. 54).

  Furthermore, in the first to seventh embodiments, the n-channel MISFET has been described as an example for the MISFET (LT) and the MISFET (HT). However, the present inventor also has the same effect for the p-channel MISFET. This has been confirmed by these studies. That is, even when a p-channel MISFET is used as the MISFET (LT) and the MISFET (HT), the effects described in the respective embodiments can be obtained by applying the SMT process of the first to seventh embodiments. .

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

[Appendix 1]
(A) preparing a semiconductor substrate having a first MISFET formed in the first region, a second MISFET formed in the second region, and a nonvolatile memory cell formed in the third region;
(B) forming a first insulating film on the first MISFET, the second MISFET, and the nonvolatile memory cell;
(C) forming a second insulating film on the first insulating film;
(D) removing the second insulating film in the second region and the third region;
(E) applying a stress to the first MISFET by performing a heat treatment after the step (d),
The gate length of the first MISFET is smaller than the gate length of the second MISFET,
The nonvolatile memory cell includes a first gate electrode formed on the semiconductor substrate, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and having a charge storage portion therein. A method for manufacturing a semiconductor device, comprising:

[Appendix 2]
(A) preparing a semiconductor substrate having a first MISFET formed in the first region, a second MISFET formed in the second region, and a nonvolatile memory cell formed in the third region;
(B) forming a first insulating film on the first MISFET, the second MISFET, and the nonvolatile memory cell;
(C) forming a second insulating film on the first insulating film;
(D) removing the second insulating film in the third region;
(E) applying a stress to the first MISFET by performing a heat treatment after the step (d),
The gate length of the first MISFET is smaller than the gate length of the second MISFET,
The nonvolatile memory cell includes a first gate electrode formed on the semiconductor substrate, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and having a charge storage portion therein. A method for manufacturing a semiconductor device, comprising:

[Appendix 3]
(A) preparing a semiconductor substrate having a first MISFET formed in the first region and a second MISFET formed in the second region;
(B) forming a first insulating film on the first MISFET and the second MISFET;
(C) forming a second insulating film on the first insulating film;
(D) From the surface of the second insulating film in the second region so that the film thickness of the second insulating film in the second region is smaller than the film thickness of the second insulating film in the first region. A step of removing a portion,
(E) applying a stress to the first MISFET by performing a heat treatment after the step (d),
The method of manufacturing a semiconductor device, wherein a gate length of the first MISFET is smaller than a gate length of the second MISFET.

[Appendix 4]
In the method for manufacturing a semiconductor device according to attachment 3,
(F) After the step (e), a step of removing the second insulating film,
(G) After the step (f), a step of removing the first insulating film;
(H) After the step (g), a step of forming a silicide film on the source and drain regions of the first MISFET or the second MISFET formed in the semiconductor substrate made of a silicon substrate. Production method.

[Appendix 5]
In the method for manufacturing a semiconductor device according to attachment 3,
The method of manufacturing a semiconductor device, wherein the first insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film.

[Appendix 6]
(A) preparing a semiconductor substrate having a first MISFET formed in the first region and a nonvolatile memory cell formed in the second region;
(B) forming a first insulating film on top of the first MISFET and the nonvolatile memory cell;
(C) forming a second insulating film on the first insulating film;
(D) From the surface of the second insulating film in the second region so that the film thickness of the second insulating film in the second region is smaller than the film thickness of the second insulating film in the first region. A step of removing a portion,
(E) applying a stress to the first MISFET by performing a heat treatment after the step (d),
The nonvolatile memory cell includes a first gate electrode formed on the semiconductor substrate, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and having a charge storage portion therein. A method for manufacturing a semiconductor device, comprising:

[Appendix 7]
(A) preparing a semiconductor substrate having a first MISFET formed in the first region, a second MISFET formed in the second region, and a nonvolatile memory cell formed in the third region;
(B) forming a first insulating film on the first MISFET, the second MISFET, and the nonvolatile memory cell;
(C) forming a second insulating film on the first insulating film;
(D) The second region and the third region so that the film thickness of the second insulating film in the second region and the third region is smaller than the film thickness of the second insulating film in the first region. Removing a part of the region from the surface of the second insulating film;
(E) applying a stress to the first MISFET by performing a heat treatment after the step (d),
The gate length of the first MISFET is smaller than the gate length of the second MISFET,
The nonvolatile memory cell includes a first gate electrode formed on the semiconductor substrate, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and having a charge storage portion therein. A method for manufacturing a semiconductor device, comprising:

[Appendix 8]
(A) preparing a semiconductor substrate having a first MISFET formed in the first region, a second MISFET formed in the second region, and a nonvolatile memory cell formed in the third region;
(B) forming a first insulating film on the first MISFET, the second MISFET, and the nonvolatile memory cell;
(C) forming a second insulating film on the first insulating film;
(D) the second region of the third region so that the film thickness of the second insulating film in the third region is smaller than the film thickness of the second insulating film in the first region and the second region. Removing a part from the surface of the insulating film;
(E) applying a stress to the first MISFET by performing a heat treatment after the step (d),
The gate length of the first MISFET is smaller than the gate length of the second MISFET,
The nonvolatile memory cell includes a first gate electrode formed on the semiconductor substrate, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and having a charge storage portion therein. A method for manufacturing a semiconductor device, comprising:

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1A Core MIS formation area 2 Element isolation area 2A I / OMIS formation area 3 Insulating film 3A Memory cell area 4 Silicon film 5 Insulating film (ONO film)
5A Silicon oxide film 5B Silicon oxide film 5N Silicon nitride film 6 Silicon film 7 n ⁻ type semiconductor region 7 a n ⁻ type semiconductor region 7 b n ⁻ type semiconductor region 8 n ⁺ type semiconductor region 8 a n ⁺ type semiconductor region 8 b n ⁺ type semiconductor Region 9 Stopper film 10 Stress application film 10S Stress application film 11 Hard mask CG Control gate electrode CP1 Silicon oxide film CP2 Silicon nitride film GE Gate electrode HL Halo region HT MISFET
LT MISFET
MC memory cell MD drain region MG memory gate electrode MS source regions PR1 to PR17 photoresist film PW1 p-type well PW2 p-type well PW3 p-type well SIL metal silicide layer SN silicon nitride film SO silicon oxide film SP1 silicon spacer SW side wall insulating film

Claims (10)

(A) preparing a semiconductor substrate having a first MISFET formed in the first region and a nonvolatile memory cell formed in the second region;
(B) forming a first insulating film on top of the first MISFET and the nonvolatile memory cell;
(C) forming a second insulating film on the first insulating film;
(D) removing the second insulating film in the second region;
(E) applying a stress to the first MISFET by performing a heat treatment after the step (d),
The nonvolatile memory cell includes a first gate electrode formed on the semiconductor substrate, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and having a charge storage portion therein. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
(F) A method for manufacturing a semiconductor device, comprising the step of removing the second insulating film after the step (e). In the manufacturing method of the semiconductor device according to claim 1,
After the step (d), the thickness of the first insulating film in the second region is smaller than the thickness of the first insulating film in the first region. In the manufacturing method of the semiconductor device according to claim 3,
(F) A method for manufacturing a semiconductor device, comprising the step of removing the first insulating film after the step (e). In the manufacturing method of the semiconductor device according to claim 4,
(G) After the step (f), a step of forming a silicide film on the source and drain regions of the first MISFET or the nonvolatile memory cell formed in the semiconductor substrate made of a silicon substrate. Device manufacturing method. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film. In the manufacturing method of the semiconductor device according to claim 3,
(F1) forming a third insulating film made of the same material as the first insulating film on the first insulating film and the second insulating film before the step (e);
(F2) removing the third insulating film and the second insulating film in the first region;
(F3) After the step (f2), a step of removing the first insulating film and the third insulating film in the second region and the first insulating film in the first region Manufacturing method. The method of manufacturing a semiconductor device according to claim 2.
Between the step (b) and the step (c), the film thickness of the first insulating film in the first region is smaller than the film thickness of the first insulating film in the second region. Removing a part from the surface of the first insulating film in the first region. In the manufacturing method of the semiconductor device according to claim 1,
The nonvolatile memory cell includes a second gate electrode formed on the semiconductor substrate and adjacent to the first gate electrode; a second gate insulating film formed between the second gate electrode and the semiconductor substrate; A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 1,
The nonvolatile memory cell has a second gate electrode formed as a charge storage portion on the semiconductor substrate via a fourth insulating film,
The first gate insulating film having the charge storage portion therein includes the fourth insulating film, the second gate electrode, and a fifth insulating film on the second gate electrode. Method.

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