JP2017027012A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device that is capable of reducing electric power consumption of a driver IC chip and useful in increasing the number of pixels to achieve higher definition of a display image.SOLUTION: In a display device in which pixels are arrayed in a matrix state in a display area, the pixel has a display element and a capacitance element series circuit of at least first and second capacitance elements C1, C2 which is parallelly connected to the display element LQ. The pixel comprises a boost circuit which is controlled by a gate signal within one pulse period of an input source signal in order to boost electric potential of the capacitance element series circuit, and has a plurality of switches which are turned on or off in a first half and turned off or on in a latter half of the one pulse period.SELECTED DRAWING: Figure 2A

Description

  This embodiment relates to a display device.

  Recently, portable terminals (personal computers, personal digital assistants (PDAs), tablet computers, etc.) have become widespread, and display images have become higher in definition. In a high-definition portable terminal, the number of pixels of a liquid crystal display device as a display unit thereof is greatly increased. The liquid crystal display device is driven by a driver IC chip. This driver IC chip is composed of an integrated circuit made of silicon semiconductor elements, and the number of output lines from the integrated circuit is increased because the display image has been refined as described above.

As a result, in the liquid crystal display device with high definition, the power consumption of the driver IC chip is significantly larger than the conventional one. When the power consumption of the driver IC chip increases, it becomes difficult to drive the portable terminal with a battery for a long time.
As a concept for reducing the power consumption, there is a method of suppressing the voltage amplitude applied to the liquid crystal display device and driving the liquid crystal display device with a low voltage amplitude. Therefore, in order to realize this method, it is necessary to realize a new liquid crystal material that can operate at a low voltage amplitude. However, a new liquid crystal material that can operate at a low voltage amplitude and that can be realized at low cost has not been realized at present.

  In addition, it has been studied to manufacture an amplifier in a pixel using a low-temperature polysilicon element that can be expected to have low power consumption. However, when an amplifier using a low-temperature polysilicon element is formed on a glass substrate, there are problems such as large variations in characteristics of the low-temperature polysilicon element and difficulty in obtaining sufficient amplification characteristics as an amplifier.

JP 2009-282119 A

  As described above, in the liquid crystal display device, the number of outputs from the integrated circuit is increasing because the display image has become high definition. For this reason, the power consumption of the driver IC chip (sometimes referred to as a liquid crystal driver) is significantly higher than that of the conventional one, and the power consumption of the driver IC chip is increased.

  Therefore, an object of the present embodiment is to provide a display device that can reduce the power consumption of the driver IC chip and is useful for increasing the number of pixels and increasing the definition of a display image.

  According to this embodiment, in the display device in which pixels are arranged in a matrix in the display area, the pixels are connected in parallel to the display element and the display element LQ, and at least first and second And a capacitive element series circuit of capacitive elements C1 and C2. In order to boost the potential of the capacitor element series circuit, a plurality of signals are controlled by a gate signal within one pulse period of the input source signal and turned on or off in the first half of the one pulse period and turned off or on in the second half. A boost control circuit having a switch is provided.

FIG. 1 is a diagram schematically showing a configuration of a liquid crystal display panel used in a liquid crystal display device according to an embodiment and an equivalent circuit thereof. FIG. 2A shows a pixel circuit according to an embodiment, and is a diagram for explaining an example of a basic configuration of the pixel circuit and a first stage of its positive polarity operation. FIG. 2B shows a pixel circuit in one embodiment, and is a diagram shown for explaining a basic configuration of the pixel circuit and an example of a second stage of its positive polarity operation. FIG. 2C shows a pixel circuit in one embodiment, and is a diagram shown for explaining a basic configuration of the pixel circuit and an example of a third stage as a display (voltage holding) state. FIG. 2D shows a pixel circuit according to an embodiment, and is a diagram for explaining an example of a basic configuration of the pixel circuit and a first stage of its negative polarity operation. FIG. 2E shows a pixel circuit according to an embodiment, and is a diagram for explaining a basic configuration of the pixel circuit and an example of a second stage of its negative polarity operation. FIG. 3A is an operational characteristic diagram shown to explain an example of the first stage operation of the pixel circuit in one embodiment. FIG. 3B is an operational characteristic diagram shown to explain an example of the second stage operation of the pixel circuit in one embodiment. FIG. 4A shows a pixel circuit in another embodiment, and is a diagram for explaining an example of a basic configuration of the pixel circuit and a first stage of its positive polarity operation. FIG. 4B shows a pixel circuit in another embodiment, and is a diagram shown for explaining a basic configuration of the pixel circuit and an example of a second stage of its positive polarity operation. FIG. 4C shows a pixel circuit according to another embodiment, and is a diagram for explaining an example of a basic configuration of the pixel circuit and a first stage of its negative polarity operation. FIG. 4D shows a pixel circuit in another embodiment, and is a diagram for explaining a basic configuration of the pixel circuit and an example of a second stage of the negative polarity operation. FIG. 5 is a diagram showing an example of a semiconductor switching characteristic diagram and a drive signal (gate signal) shown for explaining the operation of the pixel circuit shown in FIGS. 4A to 4D. FIG. 6A is a diagram showing a pixel circuit in still another embodiment. FIG. 6B is an example of a gate signal shown to explain the operation of the pixel circuit of FIG. 6A. FIG. 7 is a schematic cross-sectional view showing a configuration example of the first switch SW1 and the third switch SW3 made of semiconductor elements formed on the first substrate SUB1 in the embodiment of FIG. 4A. FIG. 8 is a diagram for explaining a schematic arrangement when the first switch SW1, the second switch SW2, and the third switch SW3 are viewed in plan in the configuration example shown in FIG. FIG. 9 is still another embodiment, and is a schematic cross-sectional view showing a configuration example of the first switch SW1 and the second switch SW2 made of semiconductor elements formed on the first substrate SUB1. FIG. 10 is a diagram for explaining a schematic arrangement in a plan view of the first switch SW1, the second switch SW2, and the third switch SW3 made of semiconductor elements formed on the first substrate SUB1. FIG. 11 is a schematic cross-sectional view showing a configuration example of the first switch SW1 and the second switch SW2 made of semiconductor elements formed on the first substrate SUB1 in still another embodiment. FIG. 12 is a schematic cross-sectional view showing a configuration example of the second switch SW2 made of a semiconductor element formed on the first substrate SUB1 in still another embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate modifications while maintaining the gist of the invention are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may be schematically represented with respect to the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this does not limit the interpretation of the present invention. Absent. In addition, in the present specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are denoted by the same reference numerals, and redundant detailed description may be omitted.

  In FIG. 1, the configuration of an active matrix type liquid crystal display panel PNL used in the liquid crystal display device according to an embodiment and an equivalent circuit thereof will be described. In addition, the principal part of embodiment is not limited to a liquid crystal display device, but uses the light-emitting body (Organic light-emitting diode (Organic light-emitting diode: OLED)) using an organic electroluminescent (organic EL) element. May be. FIG. 1 shows a liquid crystal display device as a representative.

  The liquid crystal display panel PNL includes a flat plate-like first substrate SUB1, a flat plate-like second substrate SUB2 arranged opposite to the first substrate SUB1, and a liquid crystal held between the first substrate SUB1 and the second substrate SUB2. And a layer. Note that the liquid crystal layer is extremely thin compared to the thickness of the liquid crystal display panel PNL, and is located inside the sealing material for bonding the first substrate SUB1 and the second substrate SUB2. The second substrate SUB2 includes a color filter, which is not shown in the drawing.

The liquid crystal display panel PNL has a display area DA for displaying an image in a region where the first substrate SUB1 and the second substrate SUB2 face each other. In the illustrated example, the display area DA is formed in a rectangular shape and may be referred to as an active area.
The liquid crystal display panel PNL is a reflective type that displays an image by selectively reflecting external light at a pixel electrode, or a transmission that displays an image by selectively transmitting light from a backlight (not shown). Any type. The liquid crystal display panel PNL has a configuration corresponding to a transverse electric field mode that mainly uses a transverse electric field substantially parallel to the main surface of the substrate as a mode for driving liquid crystals. A pixel electrode of a display panel using a backlight is composed of a transparent electrode.

  The example of FIG. 1 shows a liquid crystal display panel PNL of a liquid crystal display device that is in a horizontal electric field mode and uses a backlight. As a signal supply source for supplying signals necessary for driving the liquid crystal display panel PNL, a device drive integrated circuit (also referred to as a liquid crystal driver) ICI is mounted on the first substrate SUB1.

    The display area DA corresponds to a region where the liquid crystal layer LQ is held between the first substrate SUB1 and the second substrate SUB2, and is, for example, a quadrangular shape and a plurality of pixels PX ( PX11, PX12,... PX21, PX22,... PX31, PX32, PX33,.

  In the display area DA, the first substrate SUB1 includes a plurality of gate lines G (G1, G2, G3, G4,... Gn) extending along the first direction X, and a second direction Y that intersects the first direction X. A plurality of source lines S (S1, S2, S3, S4 to Sm) are provided.

  Each pixel (which may be referred to as a pixel circuit) PX is configured so as to represent one pixel on the right side of FIG. 1 (an area surrounded by an alternate long and short dash line). This figure shows the basic configuration of the pixel PX, and is not necessarily limited to the configuration shown in this figure. The pixel PX includes first to third switches SW1, SW2, and SW3 that are electrically connected to the gate line G1 and the source line S5. The pixel PX includes a pixel electrode PE electrically connected to the first switch SW1, a common electrode CE facing the pixel electrode PE, and the like. Further, the pixel PX includes first and second capacitive elements C1 and C2 connected in series. The series circuit of the first and second capacitive elements C1 and C2 is electrically in parallel with the liquid crystal layer LQ. Here, the liquid crystal layer LQ may be referred to as a display element because it is driven independently from the viewpoint of each pixel. The switch may be referred to as a semiconductor switch.

  One terminal of the first capacitive element C1 is connected to one terminal of the display element (liquid crystal layer) LQ. One terminal of the first switch SW1 is connected to the one terminal of the display element LQ. One terminal of the second switch SW2 is connected to the other terminal of the first capacitive element C1. Here, the display element LQ is shown as a symbol, and this symbol includes a capacitance between a common electrode and a pixel electrode, which will be described later.

The other terminals of the first switch SW1 and the second switch SW2 are connected to the source line S5. Further, one terminal of the second capacitor element C2 is connected to the other terminal of the first capacitor element C1, and the other terminal of the second capacitor element C2 is connected to the other terminal of the display element LQ. It is connected.
One terminal of the third switch SW3 is connected to the other terminal of the first capacitive element C1, and one terminal of the third switch SW3 is connected to the other terminal of the display element LQ. It is connected to the.

  That is, at least first and second capacitive elements C1 and C2 are connected in parallel to the display element LQ (two capacitive elements are shown, but the number is not limited). Is done. Then, in order to boost the potential of the capacitive element series circuit by the capacitive elements C1 and C2, within one pulse period of the input source signal (within one input period, within one signal period, or within one input signal period by the gate signal, A boost control circuit having a plurality of switches that are turned on and off. Note that the number of gate lines for supplying a gate signal is not necessarily limited to one. The boost control circuit includes, for example, the first, second, and third switches SW1, SW2, and SW3. The number of switches in the boost control circuit need not be limited to three. A capacitive element series circuit including capacitive elements C1 and C2 and the first, second, and third switches SW1, SW2, and SW3 are included. The boost control circuit constitutes a boost circuit that boosts the potential related to the display element LQ. The operation of this boost circuit will be described later. In this way, each pixel circuit is configured in a partition region partitioned by a plurality of source lines through which source signals are guided and a plurality of gate lines to which gate signals for turning on and off switches (semiconductor elements) are supplied. Yes.

  Each pixel PX is configured as described above. Each gate line G (G1 to Gn) is drawn out of the display area DA and connected to a gate drive circuit (also referred to as a first drive circuit) GD. Each source line S (S1 to Sm) is drawn outside the display area DA and is connected to a source driving circuit (also referred to as a second driving circuit) SD. For example, at least a part of the gate drive circuit GD and the source drive circuit SD is formed on the first substrate SUB1, and is connected to the device drive integrated circuit ICI.

In order to realize the column inversion driving method, the source driving circuit SD can output pixel signals having different polarities when outputting pixel signals to the source lines of adjacent columns.
The device driving integrated circuit ICI incorporates a controller that controls the gate driving circuit GD and the source driving circuit SD, and functions as a signal supply source that supplies signals necessary for driving the liquid crystal display panel LPN. In the illustrated example, the device driving integrated circuit ICI is mounted on the first substrate SUB1 outside the display area DA of the liquid crystal display panel LPN.

    The device driving integrated circuit ICI includes a timing pulse generator for generating various timing pulses and supplying them to the gate driving circuit GD and the source driving circuit SD. The device drive integrated circuit ICI includes a power supply circuit, a booster circuit, and the like in order to generate and output various power supply voltages. Accordingly, the potential of the source line S, the gate line G, the potential of the common electrode CE, and the like also depend on various voltages generated by the device driving integrated circuit IC1.

  The common electrode CE extends over the entire display area DA and is formed in common for the plurality of pixels PX. The common electrode CE is drawn outside the display area DA and is connected to, for example, a power feeding unit in the device driving integrated circuit ICI. The common electrode CE is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

  2A and 2B are shown for explaining an operation example of a pixel which is an example of the present embodiment. Now, assume that a high-level (positive gate voltage) pulsed gate signal is applied to the gate line G1, and a write signal is applied to the source line S5 in synchronization with the gate signal. Then, based on the positive polarity gate voltage, the first and third switches SW1, SW3 are turned on, and the second switch SW2 is turned off. As a result, current is supplied to the capacitive element C1 and the display element LQ via the first switch SW1 based on the write signal from the source line S5. Now, it is assumed that the write signal (video signal) is 6.5V and the voltage of the common electrode CE is 5.0V. A voltage of 1.5 V is supplied between one and the other electrodes of the display element LQ. Further, since the third switch SW3 is on, the voltage 5.0 V of the common electrode CE is also applied to the connection point (node N) between the capacitive element C1 and the capacitive element C2. In this embodiment, the first, second, and third switches SW1, SW2, and SW3 are configured by the same channel, for example, an N-channel transistor (thin film transistor (TFT)). Here, when the first and third switches SW1 and SW3 are turned on, the second switch SW2 needs to be turned off. Since all the transistors are controlled by the gate signal from one gate line G1, the gate signal is supplied to the gate of the transistor SW2 via the inverter INV.

  Here, it is assumed that the gate signal changes to the negative gate voltage within a period in which the write signal (video signal) is 6.5V. Then, the first and third switches SW1 and SW3 are turned off, and the second switch SW2 is turned on. Thereby, 6.5 V is applied to the connection point (node N) between the capacitive elements C1 and C2 through the second switch SW2. Since the node N was supplied with 6.5V compared to 5.0V, if the difference of 1.5V is approximately equal between the capacitance values of the capacitive element C1 and the display element LQ, the capacitive element C1 ( 0.75V) and the voltage applied to the display element LQ (0.75V). For this reason, the other electrode side of the capacitive element C1, that is, the electrode side connected to the display element LQ is pushed up to 6.5V + 0.75V = 7.25V (that is, boosted). Thereafter, the switch SW2 is turned off. As a result, a positive voltage of 2.25 V boosted from 1.5 V to 0.75 V applied from the outside is applied to the liquid crystal as the display element. That is, a voltage of 2.25 V is applied between the common electrode CE and the pixel electrode.

Thereby, the drive voltage of the display element LQ becomes a sufficient voltage. That is, even if the output voltage for pixel driving output from the device driving integrated circuit IC1 is lower than the conventional voltage, the display element is driven with a sufficient driving voltage.
FIG. 2C shows a state in which the gate signal temporarily changes to positive polarity and the second switch SW2 is controlled to be turned off. As a result, the potential applied to the display element LQ is maintained. Note that the gate signal does not necessarily have a waveform that temporarily changes to positive polarity, as shown in FIG. 3B, due to the switching characteristics of the semiconductor element. Due to the switching characteristics of the semiconductor elements, it is possible to turn off all the switches SW1, SW2 and SW3 without temporarily changing to positive polarity.

In the circuit described above, the polarity of the display element LQ is inverted and driven in the next frame. Therefore, in the next frame, with the switches SW1 and SW3 turned on and SW2 turned off, a 3.5V write signal (video signal) is input to the source line S5 (that is, the signal line) as shown in FIG. 2D. The Since the pixel electrode is 3.5V and the common electrode is 5.0V, at this time, a differential voltage of 1.5V is applied to the series circuit of the display element LQ and the capacitor C1. The difference voltage 1.5V is divided into the capacitance C1 (0.75V) and the display element LQ (0.75V) because the capacitance values of the capacitance element C1 and the display element LQ are substantially equal.
Next, as shown in FIG. 2E, when the switches SW1 and SW3 are turned off and SW2 is turned on, a pixel voltage boost operation is performed. That is, the potential at the connection point (node N) between the capacitor C1 and the capacitor C2 changes from 5.0V to 3.5V. Then, since the potential difference between both terminals of the capacitive element C1 is 0.75V, the potential at the connection point between the capacitive C1 and the pixel electrode of the display element LQ is (3.5V−0.75) = 2. .75V. Then, the switch SW2 is turned off and the holding state is established. Then, a potential difference (5.0V-2.75V = 2.25V) between the common electrode CE and the pixel electrode is applied to the display element LQ. That is, a voltage of 2.25 V is applied to the liquid crystal in the negative positive direction.
3A and 3B show an example of the operation characteristics of the circuit including the first to third switches SW1, SW2, SW3 and the inverter INV. In the operating characteristics, the horizontal axis indicates the gate voltage (gate-source voltage) Vgs, and the vertical axis indicates the current Ids flowing between the controlled terminals of the switch (source-drain). When the display element LQ is an organic EL element, a built-in circuit that temporarily holds a write signal from the signal line may be provided. The signal from this built-in circuit may be boosted by a boost circuit.

  Further, the first to third switches SW1, SW2, and SW3 maintain their states when the gate voltage is in a certain range (± v1) (this range is referred to as a holding region) (for example, the off state). maintain). When the gate voltage is in the region of + v1 or higher, the first and third switches SW1 and SW3 are turned on and the second switch SW2 is turned off. When the gate voltage is in the region of −v1 or lower In this region, the second switch SW2 is turned on and the first and third switches SW1 and SW3 are turned off.

In the above-described embodiment, the case where the semiconductor elements forming the first to third switches SW1, SW2, and SW3 are all the same channel (for example, N channel) has been described. However, the present invention is not limited to this embodiment. For example, the semiconductor element forming the first and third switches SW1 and SW2 may be an N channel, for example, and the semiconductor element forming the second switch SW2 may be a P channel.
FIG. 4A shows an example in which the first and third switches SW1 and SW3 are composed of N-channel transistors, and the second switch SW2 is composed of a P-channel transistor. 4A is further different from the configuration shown in FIG. 2A in that the inverter INV shown in FIG. 2A is not necessary. Therefore, according to this embodiment, an inverter is unnecessary, and the aperture ratio of the pixel region can be increased as compared with the previous embodiment.

4A and 4B show switch states when the pixel circuit of this embodiment operates in a positive polarity. As shown in FIG. 4A, when the switches SW1 and SW3 are turned on by a positive gate signal, a video (pixel) signal of, for example, 6.5 V is supplied from the source line S5 via the switch SW1 to one of the display element LQ and the capacitive element C1. To be supplied. A voltage of 5.0 V of the common electrode CE is applied to the other terminal of the capacitive element C1 via the third switch SW3. In this state, a potential difference of 1.5 V between the voltages of 6.5 V and 5.0 V is divided by the capacitive element C1 and the display element LQ. Since both capacitance values are designed to be substantially equal, 1.5 V is divided so that the voltage between the terminals of the capacitive element C1 is 0.75 V and the voltage between the terminals of the display element LQ is 0.75 V. Is done.
Next, when the gate signal changes to negative polarity, as shown in FIG. 4B, the first switch SW1 and the third switch SW3 are turned off, and the second switch SW2 is turned on. For this reason, the other voltage of the capacitive element C1 is changed from 5.0 to 6.5V. For this reason, one voltage of the capacitive element C1 changes to (6.6V + 0.75V) = 7.25V. Thereafter, the switch SW2 is turned off. As a result, the terminal voltage (voltage between the common electrode C and the pixel electrode) of the display element LQ changes from 0.75V to 2.25V. Thereby, the drive voltage of the display element LQ becomes a sufficient voltage. That is, even if the output voltage for pixel driving output from the device driving integrated circuit IC1 is lower than the conventional voltage, the display element is driven with a sufficient driving voltage.

In the circuit described above, the polarity of the display element LQ is inverted and driven in the next frame. Therefore, in the next frame, a 3.5V write signal (video signal) is input to the source line S5 with the switches SW1 and SW3 on and SW2 off as shown in FIG. 4C. Since the pixel electrode is 3.5V and the common electrode is 5.0V, at this time, a differential voltage of 1.5V is applied to the series circuit of the display element LQ and the capacitor C1. This differential voltage 1.5V is divided into a capacitor C1 (0.75V) and a display element LQ (0.75V).
Next, as shown in FIG. 4D, when the switches SW1 and SW3 are turned off and SW2 is turned on, a pixel voltage boost operation is performed. That is, the potential of the connection point (pixel electrode) between the capacitor C1 and the capacitor C2 changes from 5.0V to 3.5V. Here, the capacitance values of the capacitive element C1 and the display element LQ are substantially equal. For this reason, the potential difference (1.5 V) between the voltage (5.0 V) of the common electrode CE and the voltage (3.5) of the pixel electrode is divided into 0.75 V by the capacitive element C1 and the display element LQ. Therefore, since the potential difference between both terminals of the capacitor C1 is 0.75 V, the potential at the connection point between the capacitor C1 and the pixel electrode of the display element LQ is (3.5V−0.75) = 2. .75V. As a result, a potential difference (5.0V-2.75V = 2.25V) between the common electrode CE and the pixel electrode is applied to the display element LQ. A voltage of 2.25 V is applied to the liquid crystal in the negative or extreme direction.

FIG. 5 shows operating characteristics of the first and third switches SW1 and SW3 composed of N-channel transistors (FIG. 5A) and P-channel transistors in the embodiment shown in FIGS. 4A to 4D. The example of the operation characteristic ((b) of FIG. 5) of 2nd switch SW2 comprised by this is shown. FIG. 5C shows an example of a gate signal for ON / OFF control of the first to third switches SW1-SW3. 5A and 5B, the vertical axis indicates the current between the drain and the source of the semiconductor element, and the horizontal axis Vgs indicates the voltage between the gate and the source of the semiconductor element.
FIG. 5A shows an example of the switching voltage SW (+ V) of the N-channel semiconductor elements (switches SW1 and SW3). +2.25 to -2.25 V is the range of the voltage (LQ voltage) by the video signal. The switching voltage SW (+ V) (the voltage at the on / off switching point) needs to be deeper than this + 2.25V. The threshold voltage Vth of the switches SW1 and SW3 is 2.25V. Therefore, the switching voltage SW (+ V) is
SW (+ V) = video signal (2.25V) + 2.25V = 4.5V.
On the other hand, as shown in FIG. 5B, the threshold voltage Vth of the P-channel semiconductor element (switch SW2) is −2.25V. The voltage of the negative video signal is −2.25V. Therefore, the switching voltage SW (−V) of the P-channel semiconductor element (switch SW2) is
SW (−V) = video signal (−2.25V) + (− 2.25V) = − 4.5V.
The switching voltage by the above gate signal was examined with the reference voltage set to zero. However, as shown in FIGS. 4A to 4D, the pixel circuit operates using the voltage (5.0 V) of the common electrode CE as a reference voltage. Therefore, the switching voltage based on the actual gate signal has a potential as shown in FIG.
That is, in the case of the switches SW1 and SW3 using N-channel transistors, the positive side is set with respect to 5.0V.
7.25V (= 5.0V + 2.25V) + Vth (2.25V) = 9.5V or more is required.
On the other hand, in the case of the switch SW2 using a P-channel transistor, the negative side is set with respect to 5.0V
2.75 V (= 5.0 V−2.25 V) + (− Vth (= −2.25 V)) = 0.5 V or less is required.

When the switching voltage is set as described above, when the voltage of the gate signal shifts to the range of 0.5V to 9.5V, all the switches SW1, SW2, and SW3 can be held in the off state. When keeping the switches SW1, SW2, and SW3 in the off state, it is actually preferable to keep the gate voltage at 5.0V as described above.
As described above, in order to turn off all of the switches SW1, SW2, and SW3, it is necessary to deepen Vth of each switch. The adjustment of the Vth depth of the semiconductor element can be executed by Vth control in the manufacturing process. In order to stabilize the operation even when there is a variation in the off voltage that turns off all the switches SW1, SW2, and SW3, it is effective to manufacture by controlling Vth in a deeper direction. In such a case, even if the voltage 5.0 V of the common electrode fluctuates or varies, the operation of the pixel circuit is guaranteed to be stable.
In the above semiconductor device manufacturing process, there may be a case where only the depth Vth of either the P-channel semiconductor device or the N-channel semiconductor device can be controlled. However, in such a case, the reference voltage may be set just in the middle between Vth of the P-channel and N-channel semiconductor elements.

The present invention is not limited to the above embodiment. In the above embodiment, the gate signal for turning on / off the switches SW1, SW2, and SW3 is input from one gate line G1 to the control terminal of each switch. However, two gate lines may be used.
FIG. 6A shows a pixel circuit in another embodiment. In this embodiment, the semiconductor elements forming the first to third switches SW1, SW2, and SW3 are all the same channel (for example, N channel). The first and third switches SW1 and SW3 are turned on or off by a gate signal from the gate line G1a, and the second switch SW2 is turned on or off by a gate signal from the gate line G1b. Other configurations are the same as those of the previous embodiment.
In the case of positive polarity operation, the switches SW1 and SW3 are turned on by a gate signal from the gate line G1a. Then, a writing signal (video signal) of 6.5 V is supplied from the signal line S5 to the pixel electrode of the display element LQ. As a result, the pixel electrode of the display element LQ becomes 6.5V, and the node N that is the connection point between the capacitive elements C1 and C2 becomes 5.0V. Then, a voltage of 0.75 V is distributed to the capacitive element C1 and the display element LQ. Next, the switches SW1 and SW3 are turned off, and the switch SW2 is turned on by a gate signal from the gate line G1b. Then, a write signal of 6.5 V is supplied from the signal line S5 to the node N. Then, the potential of the pixel electrode of the display element LQ is boosted from 6.5V to 7.25V. When the switch SW2 is turned off, the voltage between the terminals of the display element LQ increases from 0.75V to 2.25V, and becomes a sufficient liquid crystal driving voltage. This operation is similar to the positive polarity operation described in FIGS. 2A and 2B.
In the case of the negative polarity operation, since it is described in substantially the same manner as the operation described in FIG. 2C and FIG. 2D, detailed description is omitted.
FIG. 6B shows an example of a gate signal GS1 that controls on / off of the operations of the switches SW1 and SW3 configured by N-channel semiconductor elements, and a gate signal GS2 that controls the operation of the switch SW2 that is also configured by N-channel semiconductor elements. An example is shown. Since the positive polarity operation and the negative polarity operation of the pixel circuit are also described in substantially the same manner as the operations described with reference to FIGS.

FIG. 7 is a diagram showing a configuration example of the first and third switches SW1 and SW3 made of a semiconductor formed on the first substrate SUB1. In the drawing, it is to be understood that the relative thickness of the insulating layer, metal layer, glass substrate, etc., the relative length of the wiring, and the like are different from the actual ones for easy understanding of the configuration.
Reference numeral 10 denotes a first insulating substrate made of glass or the like. The semiconductor layer SC1 (N channel) constituting the first switch SW1 is formed on the first insulating substrate 10 and covered with the first insulating layer 11. The first insulating layer 11 is also disposed on the first insulating substrate 10. Such a first insulating layer 11 is formed of an inorganic material such as silicon oxide or nitrogen oxide.

  The gate electrode WG13 of the first switch SW1 is formed on the first insulating layer 11 and is located immediately above the semiconductor layer SC1. The gate electrode WG13 is electrically connected to the corresponding gate line G (or formed integrally with the gate wiring G), and is covered with the second insulating layer 12. The second insulating layer 12 is also disposed on the first insulating layer 11. The second insulating layer 12 is made of an inorganic material such as silicon nitride, for example.

  The source electrode WS1 and the drain electrode WD1 of the first switch SW1 are formed on the second insulating layer 12. A corresponding source line S (not shown in the figure) is also formed on the second insulating layer 12 in the same manner. The source electrode WS1 is electrically connected to the source line S (or formed integrally with the source line S). The source electrode WS1 and the drain electrode WD1 are in contact with the semiconductor layer SC1 through contact holes CH1 and CH2 penetrating the first insulating layer 11 and the second insulating layer 12, respectively.

    Further, a semiconductor layer SC3 (N channel) constituting the third switch SW3 is formed on the second insulating layer 12 and immediately above the gate electrode WG13. The source electrode WS3 and the drain electrode WD3 of the third switch SW3 including the semiconductor layer SC3 are also formed on the second insulating layer 12. The third switch SW3 is covered with the third insulating layer 13. The third insulating layer 13 is also disposed on the second insulating layer 12. The third insulating layer 13 is made of a transparent resin material.

  The first switch SW1 and the third switch SW3 described above share the gate electrode WG13. The first switch SW1 is referred to as a top gate type because the gate electrode WG13 is provided above the semiconductor layer. On the other hand, the third switch SW3 is referred to as a bottom gate type because the gate electrode is provided in the lower portion of the semiconductor layer. The first and third switches SW1 and SW3 are turned on and off in the same phase according to the gate voltage, and are, for example, N-channel semiconductor elements.

  Although FIG. 7 shows the first switch SW1 as a top gate type and the third switch SW3 as a bottom gate type, this relationship may be reversed. For example, the third switch SW3 may be configured as a top gate type, and the first switch SW1 may be configured as a bottom gate type. In this configuration, the gate electrodes of the first switch SW1 (top gate type transistor) and the third switch SW3 (bottom gate type transistor) are common. Therefore, at least a part of the channel portions of the top-gate and bottom-gate transistors can be configured as a multilayer structure when viewed in the vertical direction on the same cut surface. Note that in the dual structure of the transistor, the semiconductor layer of the switch SW1 formed in the previous step is configured using polysilicon, and the switch switch SW3 formed in the subsequent step is a transparent amorphous oxide semiconductor (TAOS: Transparent). Amorphous Oxide Semiconductor). Since this TAOS is easily produced at a lower temperature than polysilicon, it is effective to use this TAOS.

  A common electrode CE is formed on the upper surface of the third insulating layer 13. In this embodiment, the liquid crystal layer LQ side is described as the upper side when viewed from the first substrate SUB1. The common electrode CE covers the upper side of the source line corresponding to this pixel portion, and extends toward the adjacent pixel. The common electrode CE is formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). As shown in FIG. 1, the common electrode CE extends to the non-display area of the first substrate SUB1 and is connected to the common potential supply unit. The fourth insulating layer 14 is disposed on the common electrode CE.

  A contact hole CH3 penetrating to the drain electrode WD1 of the first switch SW1 is formed in the third insulating layer 13 and the fourth insulating layer 14. The fourth insulating layer 14 is formed to be thinner than the third insulating layer 13 and is made of an inorganic material such as silicon nitride, for example. The fourth insulating layer 14 corresponds to an interlayer insulating layer that covers the common electrode CE.

  The pixel electrode PE is formed on the fourth insulating layer 14 with a slit, for example, and faces the common electrode CE. The pixel electrode PE is electrically connected to the drain electrode WD1 of the first switch SW1 through the contact hole CH3. The pixel electrode PE is formed of a transparent conductive material such as ITO or IZO, for example. The pixel electrode PE is covered with a first horizontal alignment layer (not shown). This embodiment employs an FFS (Fringe Field Switching) method in which the pixel electrode PE has a slit as a method for driving the liquid crystal molecules of the liquid crystal layer LQ between the pixel electrode PE and the common electrode CE. ing.

In FIG. 7, the second switch SW2 is not shown. The second switch SW2 is configured at a location different from the first switch SW1 and the third switch SW3.
FIG. 8 is a plan view showing the position where the second switch SW2 is configured. FIG. 7 shows the state cut along the line x1-x2 shown in FIG. In FIG. 8, the source electrode WS1 of the first switch SW1 is connected to the source line S, and the drain electrode WD1 of the first switch SW1 is connected to the pixel electrode PE through the contact hole CH3. The third switch SW3 is disposed so as to overlap the first switch SW1 when viewed in plan.
The drain electrode WD3 of the third switch SW3 is connected to the drain electrode WD2 of the second switch SW2 via the multifunction electrode La23. The second switch SW2 is formed in the same layer as the first switch SW1, and is arranged in parallel with the first switch SW1. Therefore, the multifunction electrode La23 is connected to the drain electrode WD2 of the second switch SW2 through the contact hole CH5. Further, the source electrode WS2 of the second switch SW2 is connected to the source line S through the contact hole (CH4) similarly to the first switch SW1 of FIG. The second switch SW2 shares the gate electrode WG13 together with the first switch SW1 and the third switch SW3. The second switch SW2 has the gate electrode WG13 as a top gate. The shape of the common electrode CE does not have to be the pattern shown in FIG. 8, and various patterns are possible. The same can be said in the following description, and the common electrode CE may form the circuit shown in FIGS. 2A and 2B. Note that the multifunctional electrode La23 is preferably a transparent electrode. The multi-function electrode La23 is connected to the drain electrode of the second switch SW2 and the drain electrode of the third switch SW3 (1), and through the opening CE-O where the common electrode CE is opened. Thus, a role (2) of forming the capacitive element C1 with the pixel electrode PE and a role (3) of forming the capacitive element C2 so as to face the common electrode CE are provided.

In the above-described embodiment, the multifunctional electrode Lb23 and the common electrode CE form a unique shape and pattern. First, the common electrode CE includes an opening CE-O at a portion facing at least so as to overlap with the multifunctional electrode Lb23. Due to the presence of the opening CE-O, the multi-function electrode Lb23 includes a part (first part or second part) facing the pixel electrode PE so as to overlap. Part of this forms the capacitive element C1 described above together with the pixel electrode PE. Furthermore, the multifunctional electrode Lb23 has a part (second part or first part) that faces the common electrode CE so as to overlap. Part of this forms the capacitive element C2 described above together with the common electrode CE.
With the above configuration, the capacitive element C1 and the capacitive element C2 are formed. Therefore, in order to determine the value of each element, the area of the multifunction electrode Lb23 and / or the area of the opening CE-O of the common electrode CE is adjusted. doing. The third insulating layer 13 may be controlled in the manufacturing process so that the thickness of the region where the capacitive elements C1 and C2 are formed is reduced. That is, in order to earn a capacitance value, the thickness of a partial region of the insulating layer 13 may be controlled in the manufacturing process.

The second switch SW2 may be either an N-channel transistor or a P-channel transistor. However, the second switch SW2 needs to operate in a reverse-phase relationship with respect to the first switch SW1 and the third switch SW3. Therefore, when the first switch SW1, the third switch SW3, and the second switch SW2 are the same N-channel transistor, for example, the gate signal applied to the gate electrode WG2 of the second switch SW2 is the first The switch SW1 and the third switch SW3 must be out of phase with respect to the gate signal applied to the gate electrodes WG1 and WG3.
Therefore, if the gate signals input to the gate electrodes WG1 and WG3 of the first switch SW1 and the third switch SW3 are directly input from one gate line G, the gate of the second switch SW2 is supplied from the gate line G. The gate signal input to the electrode WG2 is input from the gate line G via the inverter INV as described with reference to FIGS. 2A to 2D, for example.
However, in this case, one of the group of the first and third switches SW1 and SW3 operating at the same time and the second switch SW2 operating on at different timing is one of N-channel (Nch) type transistors. When the other is constituted by a P-channel (Pch) type transistor, an inverter can be made unnecessary by the following design. That is, Vth is adjusted in the transistor manufacturing process so that the voltage difference between Vth of each Pch and Nch becomes larger than the total video signal amplitude including positive and negative voltage values after boosting held in the pixel. The By this adjustment, even if the inverter circuit as shown in FIGS. 2A and 2B is not used, the switches SW1, SW3, and SW2 are set by setting the gate voltage during the off operation to the intermediate point between the Nth and Pch Vth. Both of them can be turned off. That is, the switch of the pixel circuit that should maintain the OFF state is not erroneously turned on by the video signal supplied to the signal line (video signal supplied to another pixel circuit). In this case, since the inverter circuit is not necessary, the pixel circuit becomes simpler and the yield can be improved. In the case of the transmissive liquid crystal display device, the aperture ratio can be improved.
However, as shown in FIG. 6A, there are two dedicated gate lines for gate control of the first switch SW1 and the third switch SW3, and two dedicated gate lines for gate control of the second switch SW2. When prepared, the design freedom of the first switch SW1, the second switch SW2, and the third switch SW3 is expanded. For example, when the first switch SW1 and the third switch SW3 are the same N-channel transistor, for example, the second switch SW2 may be either the P-channel or the N-channel. When the first to third switches SW1, SW2 and SW3 are the same channel, the gate signal applied to the gate electrode WG2 of the second switch SW2 according to the polarity of the gate pulse applied to the two gate lines is The gate signals applied to the gate electrodes WG1 and WG3 of the first switch SW1 and the third switch SW3 can be easily reversed in phase (a configuration example is shown in FIG. 6A).

  FIG. 9 shows still another embodiment. In the embodiment shown in FIGS. 7 and 8, the first and third switches SW1 and SW3 are configured to overlap each other when seen in a plan view. However, the embodiment shown in FIG. In this example, the SW1 and the second switch SW2 are overlapped when viewed in plan. Also in this embodiment, a double structure of a transistor is used. In this structure, the semiconductor layer of the switch SW1 formed in the previous process is configured using polysilicon, and the switch switch SW2 formed in the subsequent process is configured using a transparent amorphous oxide semiconductor (TAOS). It is preferable. Since this TAOS is easily produced at a lower temperature than polysilicon, it is effective to use this TAOS.

  In FIG. 9, the same reference numerals are given to the common parts with FIG. The first switch SW1 has the same configuration as that described in FIG. The second switch SW2 will be described. A semiconductor layer SC2 (P channel) constituting the second switch SW2 is formed on the second insulating layer 12 and directly above the gate electrode WG13. The source electrode WS2 and the drain electrode WD2 of the switch SW2 including the semiconductor layer SC2 are also formed on the second insulating layer 12. The switch SW2 is covered with the third insulating layer 13. The third insulating layer 13 is also disposed on the second insulating layer 12. The third insulating layer 13 is made of a transparent resin material.

  The first switch SW1 and the second switch SW32 described above share the gate electrode WG13. The first switch SW1 is a top gate type. On the other hand, the second switch SW2 is a bottom gate type. Since the first and third switches SW1 and SW2 are in the relationship between the N-channel type and the P-channel type semiconductor switch element, they are turned on and off in opposite phases according to the gate voltage.

Although FIG. 9 shows the first switch SW1 as a top gate type and the second switch SW2 as a bottom gate type, this relationship may be reversed. For example, the second switch SW2 may be configured as a top gate type, and the first switch SW1 may be configured as a bottom gate type.
In FIG. 9, the third switch SW3 is not shown. The third switch SW3 is configured at a location different from the first and third switches SW1 and SW3.

FIG. 10 is a plan view showing a position where the third switch SW3 is configured. FIG. 9 shows the state cut along the line x1-x2 shown in FIG. In FIG. 10, the source electrode WS1 of the first switch SW1 is connected to the source line S, and the drain electrode WD1 of the first switch SW1 is connected to the pixel electrode PE through contact holes CH2 and CH3. The second switch SW2 is disposed so as to overlap the first switch SW1 when seen in a plan view, and the source electrode WS2 is connected to the source line S in the same manner as the first switch SW1. For this purpose, the source line S includes a convex portion protruding toward the source electrode WS2 of the second switch SW2.
The drain electrode WD2 of the second switch SW2 is connected to the drain electrode WD3 of the third switch SW3 via the multifunction electrode Lb23. The multifunctional electrode Lb23 is formed on the second insulating layer 12, and the third switch SW3 is formed in the same layer as the first switch SW1. Therefore, when the multifunction electrode Lb23 and the drain electrode SD3 of the third switch SW3 are connected, both are connected via the contact hole CH6.
The third switch SW3 is formed in the same layer as the first switch SW1, and is arranged in parallel with the first switch SW1. Therefore, the source electrode SW3 of the second switch SW2 is connected to the upper common electrode CE via the contact holes CH4 and CH5. The third switch SW3 shares the gate electrode WG13 together with the first switch SW1 and the second switch SW2.

In the above-described embodiment, the first capacitive element C1 is formed between the pixel electrode PE and the drain electrode WD2 of the second switch SW2, and the common electrode CE and the drain electrode WD2 of the second switch SW2 are connected. A second capacitive element C2 is formed therebetween. Therefore, the area of the drain electrode WD2 of the second switch may be arbitrarily adjusted at the time of design.
The multifunctional electrode Lb23 and the common electrode CE form a specific shape and pattern. First, the common electrode CE includes an opening CE-O at a portion facing at least so as to overlap with the multifunctional electrode Lb23. Due to the presence of the opening CE-O, the multi-function electrode Lb23 passes through the opening CE-O and is opposed to the pixel electrode PE (a first portion or a second portion). including. Part of this forms the capacitive element C1 described above together with the pixel electrode PE. Furthermore, the multifunctional electrode Lb23 has a part (second part or first part) that faces the common electrode CE so as to overlap. Part of this forms the capacitive element C2 described above together with the common electrode CE.
With the above configuration, the capacitive element C1 and the capacitive element C2 are formed. Therefore, in order to determine the value of each element, the area of the multifunction electrode Lb23 and / or the area of the opening CE-O of the common electrode CE is adjusted. doing. Thus, the multifunction electrode Lb23 functions as an element for constituting a plurality of capacitive elements together with the connection between the semiconductor electrodes.

  FIG. 11 shows still another embodiment. Since FIG. 11 is similar to the configuration shown in FIG. 9, the same reference numerals as those in FIG. 9 and 11 is different from the configuration of FIG. 9 in that the transparent electrode SE and the fifth insulating layer 15 are provided between the third insulating layer 13 and the fourth insulating layer 14. Is a point. The transparent electrode SE is made of, for example, transparent indium tin oxide: ITO, and is located between the fifth insulating layer 15 and the third insulating layer 13. The transparent electrode SE is connected to the drain electrode WD2 of the second switch SW2 through a contact hole CH4 provided in the third insulating layer 13. The transparent electrode SE can form the capacitive element C1 with the pixel electrode PE, and can form the capacitive element C2 with the common electrode CE. Therefore, the values of the capacitive elements C1 and C2 can be adjusted by controlling, for example, the area of the transparent electrode CE (by setting the area during manufacturing). Also in the above embodiment, the semiconductor layer of the switch SW1 formed in the previous step is configured using polysilicon, and the switch switch SW2 formed in the subsequent step is formed using a transparent amorphous oxide semiconductor (TAOS). Preferably, it is configured.

According to the above-described embodiment, a part of at least one of the first and second capacitive elements C1 and C2 is constituted by two or more layers of transparent electrodes such as ITO.
FIG. 12 shows still another embodiment. 12 is similar to the configuration shown in FIG. 7, and the same reference numerals as those in FIG. The difference between the embodiment of FIG. 7 and FIG. 12 is that the transparent electrode SE and the fifth insulating layer 15 are provided between the third insulating layer 13 and the fourth insulating layer 14 as compared with the configuration of FIG. Is a point. The transparent electrode SE is made of, for example, transparent indium tin oxide: ITO, and is located between the fifth insulating layer 15 and the third insulating layer 13. The transparent electrode SE is connected to the drain electrode WD2 of the second switch SW2 through a contact hole CH4 provided in the third insulating layer 13.

  In the above-described embodiment, the pixel electrode PE has a slit, and an FFS (Fringe Field Switching) method is adopted as a method for driving liquid crystal molecules between the pixel electrode PE and the common electrode CE1.

  In the above description, the display element LQ has been described as a liquid crystal display element. However, the present invention is not limited to the above embodiment, and the display element may be an organic EL element. The first capacitor element C1 may be used as a drive element that drives the organic EL display element.

The plurality of embodiments described above have a multifaceted configuration as follows. In a display device in which pixels are arranged in a matrix in the display area,
(1) In the pixel, at least capacitive element series circuits of first and second capacitive elements C1 and C2 are connected in parallel to the display element LQ. Then, in order to boost the potential of the capacitive element series circuit by the capacitive elements C1 and C2, it is controlled by the gate signal within one pulse period of the input source signal, and is turned on or off in the first half of the one pulse period, and the latter half A boost control circuit having a plurality of switches turned off or on.
The boost control circuit described above includes, for example, the first, second, and third switches SW1, SW2, and SW3.
(2) The display element LQ described in (1) controls a display state of an image by applying a voltage signal between one terminal and the other terminal,
The capacitive element series circuit includes first and second capacitive elements C1 and C2, and one terminal of the first capacitive element C1 is connected to the one terminal of the display element LQ. One terminal of the first switch SW1 is connected to the one terminal of the display element LQ, and one terminal of the second switch SW2 is connected to the other terminal of the first capacitor element C1. The A signal line is connected to the other terminals of the first switch SW1 and the second switch SW2, and one terminal of the second capacitor element C2 is connected to the other terminal of the first capacitor element C1. A terminal is connected, and the other terminal of the second capacitor element is connected to the other terminal of the display element. Further, one terminal of the third switch SW3 is connected to the other terminal of the first capacitor element C1, and the other terminal of the third switch SW3 is connected to the other terminal of the display element. Has been.
(3) In the device according to (2), the first, second, and third switches are configured by the same channel type transistor, and the first and third switches are first gates. The second switch is controlled by a second gate signal from a second gate line, controlled by a first gate signal from the line.
(4) In the device according to (2), the first and third switches are configured by the same channel type transistor, and the second switch is different from the first and third switches. The first, second, and third switches are configured by transistors of different channel types, and are controlled by gate signals from the same gate line.
(5) In the device described in (2) above, the first and third switches are paired, or the first and second switches are paired and two transistors paired In FIG. 1, one transistor is configured as a top gate type and the other as a bottom gate type.
(6) In the device described in (5) above, at least a part of the channel portion of the top-gate and bottom-gate transistors is configured as a multilayer structure.
(7) In the device according to (2), at least a part of at least one of the first and second capacitive elements is formed of two or more layers of transparent electrodes.
(8) In the device according to (1), the display element is a liquid crystal display element.
(9) In the device described in (1) above, the display element is an organic EL element.
(10) In the device described in (1) above, a control signal from a built-in circuit that controls the organic EL element is supplied to a signal input unit to the boost control circuit that drives the organic EL element. Is done.
(11) In a display device in which pixels are arranged in a matrix in a display area,
The pixel is a pixel in which at least first and second capacitive elements C1 and C2 are connected in parallel to the display element LQ.
A first switch SW1 having a first semiconductor layer SC1 on the first substrate and having a gate electrode WG13 on the first semiconductor layer SC1 via an insulating layer, and a second switch of the SUB1 on the first substrate A second switch SW2 having a semiconductor layer SC2 and having the gate electrode WG13 on the second semiconductor layer SC2 via an insulating layer overlaps the first semiconductor layer SC1 and is insulated on the gate electrode WG13. A third switch SW3 having a third semiconductor layer SC3 via a layer, and an insulating layer disposed on the third semiconductor layer SC3, and led to the outside of the display area to supply a common voltage Common electrode CE, and an image disposed on the common electrode CE in the corresponding pixel area via an insulating layer and connected to one terminal of the first switch SW1 via a contact hole. And an electrode PE, a multi-function electrode La23 that connects one terminal of the third switch SW3 and one terminal of the second switch SW2, and the common electrode CE partially includes an opening CE. -O, the first capacitive element C1 is formed between the multi-function electrode La23 and the pixel electrode PE through the opening CE-O, and the multi-function electrode La23 is opposed to the multi-function electrode La23. The second capacitor element C2 is formed between the common electrode CE.
(12) In a display device in which pixels are arranged in a matrix in a display area,
The pixel is a pixel in which at least first and second capacitive elements C1 and C2 are connected in parallel to the display element LQ.
A first switch SW1 having a first semiconductor layer SC1 on a first substrate and having a gate electrode WG13 over the first semiconductor layer SC1 via an insulating layer;
A second switch SW2 that overlaps the first semiconductor layer SC1 and has a second semiconductor layer SC2 on the gate electrode WG13 via an insulating layer, and a third semiconductor layer SC3 of the first substrate SUB1 A third switch SW3 having the gate electrode WG13 via an insulating layer on the third semiconductor layer SC3, and an insulating layer disposed on the second semiconductor layer SC2; A common electrode CE that is guided to the outside and supplied with a common voltage, and is disposed on the common electrode CE via an insulating layer in the corresponding pixel area, and is connected to one terminal of the first switch SW1. A pixel electrode PE connected through a contact hole; a multi-function electrode La23 that connects one terminal of the second switch SW2 and one terminal of the third switch SW3; The common electrode CE is partially provided with an opening CE-O, and the first capacitive element C1 is formed between the multi-function electrode La23 and the pixel electrode PE through the opening CE-O. The second capacitor element C2 is formed between the multi-function electrode La23 and the common electrode CE opposed thereto.
(13) In the above (11) or (12), the first and third switches use semiconductor elements of the same channel (N or P channel), and the second switch includes the first and second switches. The semiconductor element of the channel different from 3 switches is used.
(14) In the above (11) or (12), the first and second capacitive elements C1 and C2 constitute a boost circuit together with the first to third switches.
(15) In a display device having a liquid crystal layer between a first substrate and a second substrate,
A plurality of source lines formed on the first substrate to which a source signal is guided; a plurality of gate lines to which a gate signal for turning on and off a semiconductor switch is supplied; the plurality of source lines and the plurality of gate lines; And each pixel circuit configured in each partitioned area partitioned by
The pixel circuit is configured on the first substrate, and includes a pixel electrode disposed on the liquid crystal layer side, and a common electrode disposed on the first substrate side with respect to the pixel electrode via an insulating layer. When,
A source electrode is connected to the source line, a drain electrode is connected to a pixel electrode, a gate electrode is connected to the gate line, an N-channel or P-channel first semiconductor switch, and a source electrode is connected to the source line A gate electrode connected to the gate line; a second switch in a channel different from the first semiconductor switch; a source electrode connected to the common electrode; a gate electrode connected to the gate line; A third switch having the same channel as that of one semiconductor switch, a drain electrode of the second switch, and a drain electrode of the third switch are connected, and the pixel is passed through an opening provided in the common electrode. A first facing region facing the electrode and forming a first capacitor, and a second facing region facing the common electrode; And a multi-function electrodes forming a capacitor.
(16) In a display device in which pixels are arranged in a matrix in a display area,
The pixel is
A first semiconductor switch having a source electrode connected to the source line and a drain electrode connected to the pixel electrode;
A second semiconductor switch having a source electrode connected to the source line;
A third semiconductor switch having a source line connected to the common electrode;
A multifunctional electrode for connecting between the drain electrodes of the second semiconductor switch and the third semiconductor switch, the first electrode being formed by a region facing the pixel electrode through an opening provided in the common electrode. A capacitor element is formed, and a common electrode that forms a second capacitor element by a region facing the common electrode, and a liquid crystal element driven by an electric field formed between the common electrode and the pixel electrode are provided.

  Although several embodiments of the present invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

SUB1 ... first substrate, SUB2 ... second substrate, GD ... gate drive circuit, SD ... source drive circuit, IC1 ... device drive integrated circuit, PX (PX11, PX12,. ...... Pixel, CE..., G (G1, G2,...)... Gate line, S (S1, S2,...). 1 switch, SW2... Second switch, SW3... Third switch, C1... First capacitor element, C2... Second capacitor element, PE. ... multifunctional electrode.

Claims (10)

In a display device in which pixels are arranged in a matrix in the display area,
The pixel is
A display element;
A capacitive element series circuit of at least first and second capacitive elements connected in parallel to the display element;
In order to boost the potential of the capacitor element series circuit, a plurality of switches controlled by a gate signal within one pulse period of the input source signal and turned on or off in the first half of the one pulse period and turned off or on in the second half And a boost control circuit. The display device according to claim 1,
The display element controls a video display state by applying a voltage signal between one terminal and the other terminal,
One terminal of the first capacitor element included in the capacitor element series circuit is connected to the one terminal of the display element;
One terminal of the first switch included in the plurality of switches is connected to the one terminal of the display element,
One terminal of a second switch included in the plurality of switches is connected to the other terminal of the first capacitor;
The other terminals of the first switch and the second switch are connected to a signal line to which the source signal is input,
One terminal of the second capacitive element included in the capacitive element series circuit is connected to the other terminal of the first capacitive element, and the other terminal of the second capacitive element is connected to the display element. Connected to the other terminal,
One terminal of a third switch included in the plurality of switches is connected to the other terminal of the first capacitor element, and the other terminal of the third switch is the other terminal of the display element. It is connected to the. The display device according to claim 2,
The first, second and third switches are composed of the same channel type transistor, and the first and third switches are controlled by a first gate signal from a first gate line, and The second switch is controlled by a second gate signal from the second gate line. The display device according to claim 2,
The first and third switches are configured by the same channel type transistor, and the second switch is configured by a channel type transistor different from the first and third switches, and the first and third switches The second and third switches are controlled by gate signals from the same gate line. The display device according to claim 2,
The first and third switches are paired, or the first and second switches are paired, and in the paired two transistors, one transistor is a top gate type and the other is a bottom gate Configured as a mold. The display device according to claim 5,
At least a part of the channel portion of the top-gate and bottom-gate transistors has a multi-layer structure. The display device according to claim 2,
In the first and second capacitive elements, at least one of the electrodes is formed of two or more transparent electrodes. The display device according to claim 1,
The display element is a liquid crystal display element. The display device according to claim 1,
The display element is an organic EL element.   2. The display device according to claim 1, wherein a control signal from a built-in circuit that controls the organic EL element is supplied to a signal input unit to the boost control circuit that drives the organic EL element.

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