JP2017022584A - Surface-mounted filter array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a surface-mounted filter array which is small-sized while securing a design value of a circuit constant of a filter at a maximum.SOLUTION: A surface-mounted filter array 1 comprises a plurality of filters that are arrayed in a length direction within a laminate 1A configured by laminating a plurality of base material layers. Each of the plurality of filters includes: a coil element consisting of a coil pattern having a winding axis in a lamination direction; and a capacitor element consisting of capacitor patterns alternately disposed in the lamination direction, and formed in a base material layer different from the base material layer in which the coil element is formed. A capacitor pattern of an n-th ((n) is any natural number) filter positioned in a positive direction from a center point in an X-axis direction, among the plurality of filters, and a capacitor pattern of an n-th filter positioned in a negative direction from the center point are in point-symmetry with respect to the center point.SELECTED DRAWING: Figure 8A

Description

  The present invention relates to a surface-mounted filter array in which a plurality of filters composed of coil elements and capacitor elements are arranged.

  Conventionally, a surface mount filter including a coil element and a capacitor element incorporated in a laminate formed by laminating a plurality of base material layers is known.

  Patent Document 1 discloses a surface-mount electronic component in which low-pass filters are arranged in an array. Each filter is composed of a plurality of base material layers on which a conductor pattern is formed, and constitutes a T-type LC filter having a magnetic part (inductor) and a dielectric part (capacitor). Only one of an inductor pattern and a capacitor pattern is formed on each of the plurality of base material layers. A plurality of filters are arrayed by further stacking the filters having this stacked structure.

JP 7-45477 A

  However, in the structure of the electronic component described in Patent Document 1, a single filter formed by laminating a plurality of base material layers on which only inductors and capacitors are formed is further laminated to form an array. It is difficult to reduce the size in the direction, which is disadvantageous for surface mounting. Also, since different layers are used between the filters, variations in circuit constants such as inductance values and capacitance values between the filters are likely to occur. For this reason, it becomes difficult to ensure the maximum design values of the circuit constants of the filter such as the capacitance value and the inductance value.

  The present invention has been made to solve the above problem, and an object of the present invention is to provide a surface-mounted filter array that is miniaturized while ensuring the maximum design value of the circuit constant of the filter.

  In order to achieve the above object, a surface-mounted filter array according to an aspect of the present invention includes a rectangular parallelepiped substrate formed by laminating a plurality of base material layers, and a longitudinal direction in each plane of the plurality of base material layers. A plurality of filters arranged in the X-axis direction in the rectangular parallelepiped substrate when the X-axis direction and the short-side direction are the Y-axis direction and the stacking direction of the plurality of base material layers is the Z-axis direction. Each of the plurality of filters includes a coil element constituted by a coil pattern having a winding axis in the Z-axis direction, and a capacitor pattern alternately arranged in the Z-axis direction. And a capacitor element formed on a different substrate layer from the substrate layer on which the coil element is formed, and among the plurality of filters, the nth in the positive direction from the center point in the X-axis direction ( n is left And the capacitor pattern filter located natural number) of, and the capacitor pattern filter located at the n-th from the center point in the negative direction is symmetrical with respect to the center point.

  According to this, a plurality of coil elements are arranged in the same base material layer, a plurality of capacitor elements are arranged in the same base material layer, and a plurality of coil elements and a plurality of capacitor elements are laminated. It is arranged to become. Therefore, the number of base material layers constituting the rectangular parallelepiped substrate does not need to be increased according to the number of filters arranged, and can be as much as necessary for forming one filter. It is possible to Further, since the capacitor patterns are arranged point-symmetrically with respect to the center point in the X-axis direction, interlayer connection conductors connecting conductor patterns of different layers can be arranged symmetrically with respect to the center point. According to this arrangement, each capacitor pattern that is not connected to the interlayer connection conductor can be maximized. Therefore, it is possible to provide a surface-mounted filter array that is reduced in size while ensuring the maximum design value of the circuit constant (capacitance value) of the filter.

  The capacitor pattern includes a first capacitor pattern and a second capacitor pattern, the first capacitor pattern is an independent pattern for each of the plurality of capacitor elements, and the second capacitor pattern includes a plurality of capacitor patterns. The capacitor element may have a common pattern.

  The capacitance value of the capacitor element is determined by the overlapping area of the first capacitor pattern and the second capacitor pattern viewed from the Z-axis direction. A plurality of first capacitor patterns arranged in the same base material layer and a plurality of second capacitor patterns arranged in the same base material layer are respectively arranged symmetrically with respect to the center point. This makes it possible to maximize the overlapping area.

  The first capacitor patterns may be formed on a plurality of the base material layers, and the first capacitor patterns formed on different base material layers may have the same shape.

  Thereby, since the interlayer connection conductor provided in the base material layer on which the first capacitor pattern is formed can be arranged at the same position in each layer, the first capacitor pattern can be maximized.

  The plurality of filters are provided in an odd number in the X-axis direction, and the first capacitor pattern constituting the filter located in the center in the X-axis direction is the first capacitor constituting another filter. A conductor pattern does not need to be formed at the center of the second capacitor pattern that is larger than the pattern and that faces the first capacitor pattern constituting the filter located at the center.

  When an odd number of filters are provided, in order to arrange the second capacitor pattern point-symmetrically with respect to the center point, the Z-axis is not connected to the second capacitor pattern located at the center in the X-axis direction. It is necessary to arrange a conductor pattern for the interlayer connection conductor penetrating in the direction in the center portion of the second capacitor pattern. At this time, in order to make the capacitance of each capacitor element defined by the overlapping area of the first capacitor pattern and the second capacitor pattern uniform, the first capacitor pattern located at the center in the X-axis direction is replaced with another first capacitor pattern. It is necessary to make it larger than one capacitor pattern. Accordingly, even when an odd number of the plurality of filters are provided, it is possible to make the capacitance value of each capacitor element uniform while maximizing the capacitor pattern of each capacitor element.

  The coil pattern further includes a plurality of first I / O terminals, a plurality of second I / O terminals, and a GND terminal provided on the surface of the rectangular parallelepiped substrate, and the coil pattern is a positive direction in the Y-axis direction. And a first coil pattern connected to one of the plurality of first I / O terminals, a negative direction in the Y-axis direction and juxtaposed with the first coil pattern, and the first coil pattern and A second coil pattern connected to one of the plurality of second I / O terminals, wherein the first capacitor pattern is connected to a connection point between the first coil pattern and the second coil pattern, The second capacitor pattern is connected to the GND terminal, and among the plurality of filters, the first coil pattern of the filter located nth in the positive direction in the X-axis direction from the center point, and the middle The second coil pattern of the filter located at the n-th in the negative direction of the X-axis direction from the point may be a point symmetry with respect to the center point of the X-axis direction and the Y-axis direction.

  When the coil pattern is point-symmetric with respect to the center point due to the connection relationship between the coil element and the capacitor element and the stacking relationship between the plurality of coil elements and the plurality of capacitor elements, the capacitor pattern is It becomes easy to arrange them symmetrically with respect to the center point. In addition, it is possible to prevent the interlayer connection conductors connecting the coil patterns formed in different layers from being placed close to each other, so that it is possible to prevent the shape defect of the rectangular parallelepiped substrate and the occurrence of cracks, and to ensure high reliability. It becomes.

  Further, the first coil pattern and the second coil pattern in one of the plurality of filters may be line symmetric with respect to a center line extending in the X-axis direction.

  Thereby, since the first coil pattern and the second coil pattern are axisymmetric with respect to the center line, it is further arranged that the interlayer connection conductors connecting the coil patterns formed in different layers are arranged close to each other. Can be suppressed.

  Further, among the plurality of filters, two or more filters that are located in the negative direction in the X-axis direction and adjacent to the center point, or that are located in the positive direction in the X-axis direction and adjacent to the center point. The first coil patterns or the second coil patterns of two or more filters may have the same shape.

  Thereby, in two or more capacitor patterns connected to two or more adjacent coil patterns having the same shape, the interlayer connection conductor penetrating in the Z-axis direction without conducting to the two or more capacitor patterns is connected to the two or more capacitor patterns. It can be shared by patterns. Therefore, the capacitance value of each capacitor element can be made uniform while maximizing the capacitor pattern of each capacitor element.

  ADVANTAGE OF THE INVENTION According to this invention, the surface mount type filter array reduced in size, ensuring the design value of the circuit constant of a filter element to the maximum can be provided.

It is a perspective view which shows the external appearance of the surface mount type filter array which concerns on embodiment. It is a top view which shows the mounting surface of the surface mount type filter array which concerns on embodiment. It is a circuit diagram which shows the equivalent circuit of the surface mount type filter array which concerns on embodiment. It is a top view which shows an example of the conductor pattern of each base material layer which comprises the coil element which concerns on embodiment. It is a top view which shows an example of the conductor pattern of each base material layer which comprises the capacitor | condenser element which concerns on embodiment. It is sectional drawing of the surface mount type filter array which concerns on embodiment in the VV line | wire of FIG. It is sectional drawing of the surface mount type filter array which concerns on embodiment in the VI-VI line of FIG. It is sectional drawing of the surface mount type filter array which concerns on embodiment in the VII-VII line of FIG. It is a top view explaining the capacitance value of the capacitor element according to the embodiment. It is a top view explaining the capacity value of the capacitor element concerning a comparative example. It is a top view explaining arrangement | positioning of the coil pattern which concerns on embodiment. It is sectional drawing of the surface mount type filter array which concerns on the modification of embodiment in the VII-VII line of FIG.

  Hereinafter, a surface-mounted filter array according to an embodiment of the present invention will be described with reference to the drawings. Each of the embodiments described below shows a preferred specific example of the present invention. The numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of the constituent elements, manufacturing steps, and order of the manufacturing steps shown in the following embodiments are merely examples, and are not intended to limit the present invention. . In addition, among the constituent elements in the following embodiments, constituent elements that are not described in the independent claims indicating the highest concept are described as optional constituent elements. In addition, the size or size ratio of the components shown in the drawings is not necessarily strict.

  The surface mount filter array according to the present embodiment includes a plurality of filters arranged in the longitudinal direction of a rectangular parallelepiped substrate formed by laminating a plurality of base material layers. Each of the plurality of filters includes a coil element configured with a coil pattern having a winding axis in the stacking direction of the rectangular parallelepiped substrate, and a capacitor element formed on a base material layer different from the base material layer on which the coil element is formed. including. Here, among the plurality of filters, the capacitor pattern of the filter located nth (n is an arbitrary natural number) in the positive direction from the center point in the longitudinal direction, and nth in the negative direction from the center point. The capacitor pattern of the filter is point symmetric with respect to the center point.

[1. Schematic configuration of surface mount filter array]
First, a schematic configuration of the surface mount filter array according to the present embodiment will be described with reference to FIGS. 1 and 2.

  FIG. 1 is a perspective view showing an appearance of a surface mount filter array 1 according to an embodiment. FIG. 2 is a plan view showing a mounting surface of the surface mount filter array 1 according to the embodiment.

  As shown in FIGS. 1 and 2, the surface mount filter array 1 includes first I / O terminals 11 to 15, second I / O terminals 21 to 25, and GND terminals provided on the surface of the laminated body 1 </ b> A. 30. The first I / O terminals 11 to 15, the second I / O terminals 21 to 25, and the GND terminal 30 are planar electrode terminals (that is, LGA (Land Grid Array) type electrodes provided on the mounting surface 10b of the stacked body 1A. Terminal).

  As shown in FIG. 2, the GND terminal 30 has a linear shape, and the first I / O terminals 11 to 15 and the second I / O terminals 21 to 25 are arranged in line symmetry with respect to the GND terminal 30. Is done. Thereby, since the GND terminal 30 is arrange | positioned between each 1st I / O terminal and each 2nd I / O terminal, isolation can be improved.

  Laminate 1A is a rectangular parallelepiped substrate in which a plurality of base material layers 101 to 114 shown in FIGS. 4A and 4B are laminated. The detailed configuration of each base material layer will be described later.

  As shown in FIGS. 1 and 2, the surface of the stacked body 1A is composed of the mounting surface 10b (the end surface on the negative side in the z-axis direction in FIGS. 1 and 2) and the opposite side of the mounting surface 10b (that is, the stacked body 1A). And the side surface connecting the mounting surface 10b and the top surface 10a.

  As shown in FIG. 1, side electrodes 32 are provided on the side surfaces of the stacked body 1 </ b> A. Although not shown in FIGS. 1 and 2, a side electrode is also provided on the side opposite to the side where the side electrode 32 of the laminate 1A is provided (that is, the negative side in the x-axis direction in FIG. 1). ing. Each side electrode is connected to the GND terminal 30 inside the multilayer body 1A.

  In FIGS. 1 and 2, the number of the first I / O terminals and the second I / O terminals of the surface-mounted filter array 1 is five, but the number is not limited to five. For example, a surface-mounted filter including one first I / O terminal and one second I / O terminal is also included in one aspect of this embodiment.

[2. Circuit configuration of surface mount filter array]
Next, the circuit configuration of the surface mount filter array 1 and the surface mount filter according to the present embodiment will be described with reference to FIG.

  FIG. 3 is a circuit diagram showing an equivalent circuit of the surface mount filter array 1 according to the embodiment. As shown in the figure, the surface-mounted filter array 1 includes low-pass filters F1, F2, F3, F4, and F5, first I / O terminals 11 to 15, and second I / O terminals 21 to 25. , And a GND terminal 30.

  The low-pass filter F1 is a filter that passes a signal in a low frequency band, and includes coil elements L11 and L21 and a capacitor element C1. Coil elements L11 and L21 constitute an inductor. The coil element L11 is connected to the first I / O terminal 11, and the coil element L21 is connected to the coil element L11 and the second I / O terminal 21. The capacitor element C1 is connected to the connection point between the coil elements L11 and L21 and the GND terminal 30. Hereinafter, the connection configuration of the low-pass filters F2 to F5 is also as shown in FIG. 3 and the configuration is the same as that of the low-pass filter F1, and thus the description thereof is omitted.

  The coil elements L11 to L15 and the coil elements L21 to L25 are formed in an inductor laminated portion 40L in which a plurality of base material layers are laminated, and the capacitor elements C1 to C5 are formed by laminating a plurality of base material layers. It is formed in the capacitor laminated portion 40C.

[3. Conductor pattern layout configuration of each base material layer]
Then, the structure of the conductor pattern of each base material layer which comprises 1 A of laminated bodies which concern on this Embodiment is demonstrated using FIG. 4A and FIG. 4B.

  FIG. 4A is a plan view showing an example of a conductor pattern of each base material layer constituting the coil element according to the embodiment. FIG. 4B is a plan view showing an example of a conductor pattern of each base material layer constituting the capacitor element according to the embodiment.

  1 A of laminated bodies are comprised from the base material layers 101-114 shown by each top view of FIG. 4A and 4B. In FIG. 4A and FIG. 4B, the base material layers 101-114 are shown by the lamination order from the mounting surface 10b side of the laminated body 1A.

  The base layers 101 to 106 shown in the plan views (a) to (f) of FIG. 4A contain a magnetic material as a main component. The base material layers 101 to 106 are made of, for example, magnetic ceramics. For example, magnetic ferrite ceramics are used as the magnetic ceramics. Specifically, ferrite containing iron oxide as a main component and containing at least one of zinc, nickel, and copper can be used.

  The base material layers 107 to 114 shown in the plan views (a) to (h) of FIG. 4B contain a nonmagnetic material as a main component. The base material layers 107 to 114 are made of, for example, low magnetic permeability or nonmagnetic ceramics. As nonmagnetic ceramics, for example, nonmagnetic ferrite ceramics or alumina ceramics mainly composed of alumina can be used.

  A conductive pattern is formed on each base material layer. In FIGS. 4A and 4B, hatched portions indicate portions where conductor patterns are formed. Each coil element and each capacitor element constituting the low-pass filters F1 to F5 are formed by the conductor pattern. In addition, the solid line and the broken-line circle shown in each base material layer shown in FIGS. 4A and 4B indicate positions where via-hole electrodes are provided. The via-hole electrode is an interlayer connection conductor that penetrates the base material layer.

  As a material of the conductor pattern, a metal or alloy mainly containing silver is particularly preferable. Since a metal or alloy containing silver as a main component can be sintered at a relatively low firing temperature by using LTCC ceramics as a substrate layer, silver having a relatively low melting point is the main component. Any metal or alloy can be used. Further, by using a metal or alloy mainly composed of silver as a conductor pattern, conductor resistance can be reduced, and characteristics such as signal propagation delay can be improved. Moreover, as a material of a via-hole electrode, the same material as a conductor pattern can be used, for example. Each first I / O terminal, each second I / O terminal, and GND terminal 30 may be plated with, for example, nickel, palladium, or gold.

  The coil elements and the capacitor elements in the low-pass filters F1 to F5 are respectively provided on different base material layers. In this embodiment, the coil elements are on the mounting surface 10b side, and the capacitor elements are on the top surface 10a side from the coil elements. Each is arranged. Each coil element is provided on the base material layers 102 to 106 containing a magnetic material as a main component. Thereby, the inductance of each coil element can be increased compared with the case where each coil element is provided in the base material layer containing a non-magnetic material as a main component. On the other hand, each capacitor element is provided on the base material layers 107 to 113 containing a non-magnetic material as a main component.

  Hereinafter, each base material layer constituting the laminate 1A will be described with reference to FIGS. 4A and 4B.

  As shown in the plan view (a) of FIG. 4A, each electrode terminal is formed on the base material layer 101. Each electrode terminal is connected to each conductor pattern of the base material layer 102 by a via hole electrode.

  As shown in the plan view (b) of FIG. 4A, the base material layer 102 is provided with conductor patterns 35 and 121-130.

  The conductor pattern 35 is a conductor pattern connected to the GND terminal 30, and ends 351 and 352 in the longitudinal direction (x-axis direction in FIG. 4A) are longitudinal directions of the base material layer 102 (x-axis direction in FIG. 4A). Protrudes from the end of the. The end portions 351 and 352 are respectively connected to side electrodes 31 and 32 provided on the side surface of the multilayer body 1A (see FIG. 1 and FIG. 6 described later for the side electrodes 31 and 32).

  The conductor patterns 121 to 125 are conductors that form one ends of the coil elements L11 to L15, respectively. Conductive patterns 121-125 are connected to first I / O terminals 11-15, respectively. The conductor patterns 121 to 125 are connected to the first coil patterns 11a to 15a of the base material layer 103 by via hole electrodes, respectively.

  The conductor patterns 126 to 130 are conductors that form the other ends of the coil elements L21 to L25, respectively. The conductor patterns 126 to 130 are conductors connected to the second I / O terminals 21 to 25, respectively. The conductor patterns 126 to 130 are connected to the second coil patterns 21b to 25b of the base material layer 103 by via hole electrodes, respectively.

  As shown in the plan views (c) to (e) of FIG. 4A, the base material layers 103 to 105 are formed with loop-shaped conductor patterns constituting the coil elements. For example, the coil element L11 includes the first coil pattern 11a of the base material layer 103, the first coil pattern 31a of the base material layer 104, and the first coil pattern 51a of the base material layer 105. The coil element L21 includes a second coil pattern 21b of the base material layer 103, a second coil pattern 41b of the base material layer 104, and a second coil pattern 61b of the base material layer 105. Each conductor pattern is connected by a via hole electrode.

  The other coil elements L12 to L15 and L22 to L25 are similarly configured. That is, the coil elements L12 to L15 include the first coil patterns 12a to 15a of the base material layer 103, the first coil patterns 32a to 35a of the base material layer 104, and the first coil patterns 52a to 52a of the base material layer 105, respectively. 55a. The coil elements L22 to L25 include second coil patterns 22b to 25b of the base material layer 103, second coil patterns 42b to 45b of the base material layer 104, and second coil patterns 62b to 62b of the base material layer 105, respectively. 65b.

  As shown in the plan views (c) to (e) of FIG. 4A, the coil patterns constituting the coil elements of the respective low-pass filters are the first coil pattern and the second coil arranged adjacent to each other in the y-axis direction of FIG. 4A. Includes patterns. The coil elements L11 to L15 are configured by a first coil pattern. Further, the coil elements L21 to L25 are configured by a second coil pattern.

  As shown in the plan view (f) of FIG. 4A, the base material layer 106 is formed with conductor patterns 161 to 165 that constitute connection portions between the first coil patterns and the second coil patterns. That is, the conductor patterns 161 to 165 formed on the base material layer 106 constitute connection portions between the coil elements L11 to L15 and the coil elements L21 to L25, respectively.

  As shown in the plan view (a) of FIG. 4B, via hole electrodes 171 to 175 are formed in the base material layer 107. The via-hole electrodes 171 to 175 are conductors constituting one end of the capacitor elements C1 to C5, respectively. Via-hole electrodes 171 to 175 are connected to conductor patterns 161 to 165 that constitute connection portions between coil elements L11 to L15 and coil elements L21 to L25, respectively.

  The base material layers 108 to 113 shown in the plan views (b) to (g) of FIG. 4B are formed with conductor patterns constituting the electrodes of the capacitor elements. The conductor pattern (first capacitor pattern) formed on the base material layers 108, 110 and 112 constitutes an electrode connected to each coil element. On the other hand, the conductor pattern (second capacitor pattern) formed on the base material layers 109, 111 and 113 constitutes an electrode connected to the GND terminal 30. The second capacitor pattern formed on the base material layers 109, 111, and 113 is connected to the GND terminal 30 via the side electrodes 31 and 32 formed on the side surface of the multilayer body 1A.

  The first capacitor patterns C1d to C5d of the base material layer 108 are connected to the first capacitor patterns C1a to C5a of the base material layer 110 via the via-hole electrodes 196 to 200 of the base material layer 109, respectively. The first capacitor patterns C1a to C5a of the base material layer 110 are connected to the first capacitor patterns C1f to C5f of the base material layer 112 through the via-hole electrodes 216 to 220 of the base material layer 111, respectively.

  The second capacitor pattern C0e of the base material layer 109 is connected to the second capacitor pattern C0b of the base material layer 111 via the via-hole electrodes 206 to 209 of the base material layer 110. The second capacitor pattern C0b of the base material layer 111 is connected to the conductor pattern 231 of the base material layer 113 via the via-hole electrodes 226 to 229 of the base material layer 112.

  The conductor pattern 231 is a conductor pattern connected to the GND terminal 30 via the side electrodes 31 and 32, and ends 2311 and 2312 in the longitudinal direction (x-axis direction in FIG. 4B) are the longitudinal direction of the base material layer 113. It protrudes from the end in the x-axis direction in FIG. 4B. Ends 2311 and 2312 are connected to side electrodes 31 and 32 provided on the side surface of laminate 1A, respectively.

  As shown in FIG. 4B, for example, the electrodes connected to the coil element L11 among the electrodes of the capacitor element C1 are the first capacitor pattern C1d of the base material layer 108, the first capacitor pattern C1a of the base material layer 110, and The first capacitor pattern C1f of the base material layer 112 is configured. On the other hand, the electrodes connected to the GND terminal 30 among the electrodes of the capacitor element C1 are the second capacitor pattern C0e of the base material layer 109, the second capacitor pattern C0b of the base material layer 111, and the conductor pattern of the base material layer 113. 231.

  The other capacitor elements C2 to C5 are similarly configured. That is, of the electrodes of the capacitor elements C2 to C5, the electrodes connected to the coil elements L12 to L15 are the first capacitor patterns C2d to C5d of the base material layer 108, the first capacitor patterns C2a to C5a of the base material layer 110, and The first capacitor patterns C2f to C5f of the base material layer 112 are configured. Among the electrodes of the capacitor elements C2 to C5, the electrodes connected to the GND terminal 30 are the second capacitor pattern C0e of the base material layer 109, the second capacitor pattern C0b of the base material layer 111, and the base material layer 113. The conductor pattern 231 is configured. Thus, the capacitor elements C1 to C5 share the second capacitor pattern that is an electrode connected to the GND terminal 30.

  That is, each of the capacitor elements C1 to C5 includes a first capacitor pattern and a second capacitor pattern. The first capacitor pattern is an independent pattern for each of the capacitor elements C1 to C5, and the second capacitor pattern is a pattern common to the capacitor elements C1 to C5.

  The base material layer 114 shown in the plan view (h) of FIG. 4B is a base material layer constituting the top surface of the laminate 1A, and no conductor pattern is formed.

  A laminated body 1A formed by laminating the base material layers as described above has a plurality of non-magnetic or magnetic ceramic green sheets in which a conductor paste is arranged at a position where a conductor pattern is to be formed according to the arrangement of FIGS. 4A and 4B. Are prepared by stacking them in the order of lamination and integrating them into an unfired laminate block, and firing the unfired laminate block all at once. In the state of the unfired laminate block, conductors that form the side electrodes 31 and 32 are provided at positions corresponding to the side surfaces of the laminate 1A. In the state of the unfired laminated body block, the conductors forming the first I / O terminals, the second I / O terminals, and the GND terminals 30 may be transferred from the transfer sheet before firing.

[4. Cross-sectional structure of surface mount filter array]
Then, the outline | summary of the internal structure of 1 A of laminated bodies formed by laminating | stacking each base material layer as mentioned above is demonstrated using FIGS.

  FIG. 5 is a cross-sectional view of the surface mount filter array 1 according to the embodiment taken along the line VV in FIG. FIG. 6 is a cross-sectional view of the surface mount filter array 1 according to the embodiment taken along line VI-VI in FIG. FIG. 7 is a cross-sectional view of the surface mount filter array 1 according to the embodiment taken along line VII-VII in FIG. Each figure is a diagram conceptually showing a cross-sectional structure of the surface-mounted filter array 1 and is not necessarily a diagram showing an actual cross-sectional structure accurately.

  As shown in FIG. 5, the first I / O terminals 11 to 15, the coil elements L11 to L15, and the capacitor elements C1 to C5 are arranged in the longitudinal direction of the multilayer body 1A. Although not shown, similarly, the second I / O terminals 21 to 25 and the coil elements L21 to L25 are also arranged in the longitudinal direction of the multilayer body 1A.

  As shown in FIG. 5 to FIG. 7, each coil element and each capacitor element are provided on different base material layers among the base material layers constituting the laminate 1 </ b> A. Each coil element is provided in the inductor multilayer portion 40L including the magnetic material as a main component in the multilayer body 1A, and each capacitor element is provided in the capacitor multilayer portion 40C including the non-magnetic material as the main component in the multilayer body 1A. Provided.

  As shown in FIG. 6, the conductor pattern 231 constituting the electrode connected to the GND terminal 30 among the electrodes of each capacitor element is connected to the GND terminal via the side electrodes 31 and 32 provided on the side surface of the multilayer body 1A. 30. More specifically, the conductor pattern 231 is connected to the GND terminal 30 via the side electrodes 31 and 32 provided on the side surface of the multilayer body 1A, the conductor pattern 35, and the via hole electrode 56.

  Thereby, in the surface mount filter array 1 according to the present exemplary embodiment, in order to connect each capacitor element and the GND terminal 30, a via hole electrode that penetrates the base material layer provided with each coil element and each capacitor element. May not be used. For this reason, it is possible to obtain the maximum inductance and capacity, respectively, by effectively using the base material layer provided with each coil element and each capacitor element. Furthermore, in the present embodiment, the area occupied by side electrodes 31 and 32 which are surface electrodes provided other than mounting surface 10b is limited to a part of the side surface. For this reason, in the surface mount filter array 1, it is possible to suppress the occurrence of a short circuit with the components arranged in the periphery.

  As shown in FIG. 7, the coil elements L13 and L23 are connected to the first I / O terminal 13 and the second I / O terminal 23 via the via-hole electrodes 303 and 304 provided inside the multilayer body 1A, respectively. It is connected. Here, the via-hole electrodes 303 and 304 are electrodes that are electrically connected to the conductor pattern in each base material layer.

  As shown in FIG. 7, the surface-mount filter array 1 includes via-hole electrodes 306 and 308 in a capacitor stacked portion 40 </ b> C containing a nonmagnetic material as a main component. In the surface-mounted filter array 1 using the base material layer shown in FIG. 4B, the number of via-hole electrodes per capacitor element is not necessarily two or three.

  These via-hole electrodes 306 and 308 are electrodes for connecting between the second capacitor patterns forming the electrodes of the capacitor element C3 and between the first capacitor patterns, respectively. Therefore, these via-hole electrodes 306 and 308 are the minimum required via-hole electrodes when the conductor patterns forming the electrodes of the capacitor element C3 are connected inside the multilayer body 1A.

  As can be seen from the cross-sectional structure of the surface-mounted filter array 1 shown in FIGS. 5 to 7, each of the capacitor elements C <b> 1 to C <b> 5 includes first capacitor patterns and second capacitor patterns that are alternately arranged in the Z-axis direction. Are formed by overlapping when viewed from the Z-axis direction. The coil elements L11 to L15 are configured by a first coil pattern having a winding axis in the Z-axis direction, and the coil elements L21 to L25 are configured by a second coil pattern having a winding axis in the Z-axis direction. Yes.

  From the cross-sectional structure, the surface mount filter array 1 according to the present embodiment includes a plurality of coil elements arranged in the same base material layer (inductor laminate portion 40L) and a plurality of capacitor elements in the same base material. A plurality of layers (capacitor stacking portion 40C) are arranged, and a plurality of coil elements and a plurality of capacitor elements are arranged in a stacked relationship. Therefore, the laminated body 1A constituting the plurality of filters can be reduced in size.

  Hereinafter, the layout of the capacitor pattern and the coil pattern, which are the main features of the surface mount filter array 1 having the above-described configuration, will be described in detail.

[5. Capacitor pattern symmetry]
FIG. 8A is a plan view illustrating the capacitance value of the capacitor element according to the embodiment. 8A shows the first capacitor patterns C1a, C2a, C3a, C4a and C5a of the base material layer 110 constituting the capacitor elements C1, C2, C3, C4 and C5 shown in FIG. Has been. 8A shows the second capacitor pattern C0b of the base material layer 111 constituting the capacitor elements C1 to C5 shown in FIG. Further, in the lower part of FIG. 8A ((d) + (e)), a diagram in which the base material layer 110 and the base material layer 111 are superimposed is shown.

  Here, as shown in the upper part of FIG. 8A, among the low-pass filters F1 to F5, the first of the low-pass filters F4 and F5 located nth (n is an arbitrary natural number) in the positive direction from the center point in the X-axis direction. The capacitor patterns C4a and C5a and the first capacitor patterns C2a and C1a of the low-pass filters F2 and F1 located nth in the negative direction from the center point have a point-symmetric shape and positional relationship with respect to the center point. ing. As shown in the middle part of FIG. 8A, the second capacitor pattern C0b common to the low-pass filters F1 to F5 has a point-symmetric shape with respect to the center point.

  According to this, since the first capacitor patterns C1a to C5a and the second capacitor pattern C0b are arranged point-symmetrically with respect to the center point in the X-axis direction, the via holes that connect the conductor patterns of different base material layers to each other The electrodes can be arranged symmetrically with respect to the center point. For this reason, the via-hole electrode 206 shared by the adjacent capacitor elements C1 and C2 and the via-hole electrode 209 shared by the adjacent capacitor elements C4 and C5 can be arranged symmetrically with respect to the center point. According to this arrangement, the first capacitor patterns C1a to C5a can be maximized while avoiding the via-hole electrodes 206 to 209 connecting the second capacitor patterns. Therefore, it is possible to secure the maximum design capacitance values of the low-pass filters F1 to F5.

  FIG. 8B is a plan view illustrating the capacitance value of the capacitor element according to the comparative example. 8B shows the first capacitor patterns C51a, C52a, C53a, C54a and C55a of the base material layer 510 constituting the five capacitor elements arranged in the X-axis direction. 8B shows the second capacitor pattern C50b of the base material layer 511 constituting the five capacitor elements. Further, in the lower part of FIG. 8B, a view in which the base material layer 510 and the base material layer 511 are overlapped is shown.

  Here, as shown in the upper part of FIG. 8B, the first capacitor patterns C51a to C55a of the five low-pass filters arranged in the X-axis direction are not point-symmetric with respect to the center point but are viewed from the Z-axis direction. It has the same shape. Further, as shown in the middle part of FIG. 8B, the second capacitor pattern C50b common to the five low-pass filters is not point-symmetric with respect to the center point.

  With this arrangement, the via-hole electrodes 571 to 575 that connect the first capacitor patterns C51a to C55a of the base material layer 510 and the first capacitor patterns of the other base material layers are on the same side (upper side in the figure) in the y-axis direction. Be placed. Therefore, if the second capacitor pattern C50b of the base material layer 511 is arranged so as to avoid the via-hole electrodes 571 to 575, the second capacitor pattern C50b is compared with the second capacitor pattern C0b according to the present embodiment shown in the middle stage of FIG. 8A. And get smaller.

  Also, the via-hole electrodes 561 to 565 that connect the second capacitor pattern C50b of the base material layer 511 and the second capacitor pattern of another base material layer are arranged on the same side in the y-axis direction (lower side in the figure). . For this reason, since the first capacitor patterns C51a to C55a of the base material layer 510 do not share the via hole electrodes, the via hole electrodes 561 to 565 must be arranged in a one-to-one correspondence with the first capacitor patterns C51a to C55a. . Therefore, if the first capacitor patterns C51a to C55a of the base material layer 510 are arranged so as to avoid the via-hole electrodes 561 to 565, the second capacitor patterns C1a to C1a according to the present embodiment shown in the upper part of FIG. Smaller than C5a.

  The capacitance values of the capacitor elements C1 to C5 are determined by the size of the overlapping area between the first capacitor pattern and the second capacitor pattern as viewed from the Z-axis direction. As described above, the capacitor pattern according to the present embodiment is larger than the capacitor pattern according to the comparative example. Accordingly, as can be seen by comparing the lower stage of FIG. 8A and the lower stage of FIG. 8B, the overlapping area of the first capacitor pattern and the second capacitor pattern is the same as that of the capacitor elements C1 to C5 according to the present embodiment. Can be secured larger. In the lower part of FIG. 8A, the overlapping areas reflecting the capacitance values of the capacitor elements C1 to C5 according to the present embodiment are indicated by A1 to A5, respectively. On the other hand, in the lower part of FIG. 8B, the overlapping areas reflecting the capacitance values of the five capacitor elements according to the comparative example are indicated by B1 to B5, respectively. That is, A1 to A5> B1 to B5.

  That is, the first capacitor patterns C1a to C5a arranged in the same base material layer 110 and the second capacitor patterns C0b arranged in the same base material layer 111 are respectively pointed to the center point. By arranging them symmetrically, it is possible to maximize the overlapping area.

  As shown in FIG. 4B, the first capacitor pattern is formed on the plurality of base material layers 108, 110, and 112, and the first capacitor pattern formed on the base material layers 108, 110, and 112 has the same shape. It may be.

  As a result, via hole electrodes that are provided on the base material layers 108, 110, and 112 on which the first capacitor pattern is formed and are not connected to the first capacitor pattern can be arranged at the same position in each layer. Can be realized.

  Further, the surface-mounted filter array 1 according to the present embodiment is provided with an odd number (five) of low-pass filters F1 to F5 in the X-axis direction. In this case, as shown in FIG. 8A, the first capacitor pattern C3a located at the center in the X-axis direction is larger than the other first capacitor patterns C1a, C2a, C4a, and C5a, and the first capacitor pattern C3a No conductive pattern is formed in the central portion C0c of the second capacitor pattern C0b facing each other.

  If an odd number of filters are provided as in the present embodiment, the second capacitor pattern C0b is not electrically connected to the second capacitor pattern C0b in order to place the second capacitor pattern C0b symmetrically with respect to the center point. The via hole electrode 218 penetrating in the axial direction needs to be disposed in the central portion C0c of the second capacitor pattern C0b. At this time, in order to make the capacitance of the capacitor element defined by the overlapping area of the first capacitor pattern and the second capacitor pattern uniform among all the filters, the first capacitor pattern located at the center in the X-axis direction is used. C3a needs to be larger than the other first capacitor patterns. Thereby, even when an odd number of filters are provided, the overlapping area of the first capacitor pattern and the second capacitor pattern can be made the same, and each capacitor element can be maximized while each capacitor element is maximized. It becomes possible to make the capacitance values of the elements uniform.

[6. Coil pattern symmetry]
FIG. 9 is a plan view for explaining the arrangement of coil patterns according to the embodiment. 9 includes first coil patterns 11a to 15a, 31a to 35a, and 51a to 55a of the base material layers 103, 104, and 105 that constitute the coil elements L11 to L15 and L21 to L25 shown in FIG. Second coil patterns 21b to 25b, 41b to 45b, and 61b to 65b are shown.

  Here, as shown in the upper part (c) of FIG. 9, among the low-pass filters F1 to F5, the first coil pattern 14a of the filter located first in the positive direction from the center point in the X-axis direction and the center point The second coil pattern 22b of the filter positioned first in the negative direction from the point has a point-symmetric shape and arrangement relationship with respect to the center point in the X-axis direction and the Y-axis direction. Further, the first coil pattern 15a positioned second in the positive direction and the second coil pattern 21b positioned second in the negative direction have a point-symmetric shape and arrangement relationship. Further, the second coil pattern 24b positioned first in the positive direction and the first coil pattern 12a positioned first in the negative direction have a point-symmetric shape and arrangement relationship. Further, the second coil pattern 25b positioned second in the positive direction and the first coil pattern 11a positioned second in the negative direction have a point-symmetric shape and arrangement relationship.

  Further, the arrangement relationship between the coil pattern shown in FIG. 9D and the coil pattern shown in FIG. 9E is the same as the arrangement relationship of the coil pattern shown in FIG. is there. That is, the first coil pattern of the filter positioned nth (n is an arbitrary natural number) in the positive direction from the center point in the X-axis direction, and the second coil pattern of the filter positioned nth in the negative direction from the center point Is point-symmetric with respect to the center point in the X-axis direction and the Y-axis direction. The second coil pattern of the filter located nth (n is an arbitrary natural number) in the positive direction from the center point in the X-axis direction, and the first coil pattern of the filter located nth in the negative direction from the center point Is point-symmetric with respect to the center point in the X-axis direction and the Y-axis direction.

  The connection relationship between the coil elements and the capacitor elements (see FIG. 3) constituting the surface-mounted filter array 1 according to this embodiment (see FIG. 3), and the stacking relationship between the plurality of coil elements and the plurality of capacitor elements (FIGS. 5 to 5). 7), when the coil pattern is point-symmetric as described above, the capacitor pattern can be easily arranged point-symmetrically with respect to the center point. Moreover, it can suppress that the via-hole electrode which connects coil patterns adjoins. Therefore, it is possible to prevent a defective shape of the laminated body 1A, generation of cracks, and the like, and to ensure high reliability.

  As shown in FIG. 9, the first coil pattern and the second coil pattern constituting one low-pass filter may be axisymmetric with respect to a center line extending in the X-axis direction. In the present embodiment, for example, the first coil pattern 11a and the second coil pattern 21b constituting the low-pass filter F1 are line symmetric with respect to the center line. In addition, the relationship between the first coil pattern 12a and the second coil pattern 22b, the first coil pattern 14a and the second coil pattern 24b, and the first coil pattern 15a and the second coil pattern 25b is also relative to the center line. It is line symmetric. However, the first coil pattern 13a and the second coil pattern 23b arranged at the center in the X-axis direction are not in a line-symmetric relationship with respect to the center line, and are not in the X-axis direction and the Y-axis direction center point It is point-symmetric.

  Thereby, it can further suppress that the via-hole electrode which connects coil patterns adjoins.

  Further, the first coil patterns belonging to the group G1 located in the negative direction in the X-axis direction from the center point, the second coil patterns belonging to the group G4, and the group G3 located in the positive direction in the X-axis direction from the center point. The first coil patterns belonging to each other and the second coil patterns belonging to the group G2 may have the same shape. That is, two or more adjacent filters positioned in the negative direction in the X-axis direction from the center point, or first of two or more filters positioned in the positive direction in the X-axis direction from the center point. The coil patterns or the second coil patterns may have the same shape.

  In the surface-mounted filter array 1 according to the present embodiment, the first coil pattern of the group G3 located nth (n is an arbitrary natural number) in the positive direction from the center point in the X-axis direction, and negative from the center point. The second coil pattern of the group G4 located nth in the direction is point-symmetric with respect to the center point in the X-axis direction and the Y-axis direction. The second coil pattern of the group G2 located nth in the positive direction from the center point in the X axis direction and the first coil pattern of the group G1 located nth in the negative direction from the center point are the X axis And point symmetry with respect to the center point in the direction and the Y-axis direction. Further, the coil patterns in the group have the same shape.

  As a result, in two or more capacitor patterns connected to two or more adjacent coil patterns having the same shape, via-hole electrodes penetrating in the Z-axis direction without conduction with the two or more capacitor patterns can be made closer to each other. The two or more capacitor patterns can be shared while being suppressed. Therefore, the capacitance value of each capacitor element can be made uniform while maximizing the capacitor pattern of each capacitor element.

(Other embodiments)
The surface mount filter array according to the embodiment of the present invention has been described above, but the present invention is not limited to the above embodiment.

  For example, in the surface mount filter array 1 according to the above-described embodiment, the inductor multilayer portion 40L in which the coil elements are formed is disposed on the mounting substrate side, and the capacitor multilayer portion 40C in which the capacitor elements are formed is disposed on the top surface side. However, the reverse relationship may be used.

  FIG. 10 is a cross-sectional view of a surface mount filter array 1p according to a modification of the embodiment taken along line VII-VII in FIG. The cross-sectional structure shown in FIG. 10 corresponds to the cross-sectional structure of the surface mount filter array 1 according to the present embodiment shown in FIG.

  As shown in FIG. 10, the surface-mounted filter array 1p according to the present modification is the same as the surface-mounted filter array 1 according to the embodiment, provided on the mounting surface 10b of the multilayer body 1A. An I / O terminal 13p, a second I / O terminal 23p, and a GND terminal 30p are provided. The surface-mount filter array 1p includes a low-pass filter including coil elements L13p and L23p and a capacitor element C3p built in the multilayer body 1A. Although not shown, the surface-mounted filter array 1p is provided with five low-pass filters, as in the surface-mounted filter array 1 according to the present embodiment.

  As shown in FIG. 10, in the surface mount filter array 1p, a capacitor multilayer portion 40C including a nonmagnetic material as a main component in the multilayer body 1A is provided on the mounting surface 10b side, and an inductor including a magnetic material as a main component. The stacked portion 40L is disposed on the top surface 10a side. Accordingly, in the surface mount filter array 1p, each capacitor element is disposed on the mounting surface 10b side, and each coil element is disposed on the top surface 10a side.

  As shown in FIG. 10, the surface-mount filter array 1 p includes at least five via-hole electrodes 311 to 315 due to the above configuration. The via-hole electrodes 311 and 312 are electrodes that connect the coil elements L13p and L23p to the first I / O terminal 13p and the second I / O terminal 23p, respectively. Via-hole electrodes 313 and 314 are electrodes that connect between capacitor patterns constituting each electrode of capacitor element C3p. The via-hole electrode 315 is an electrode that connects the coil elements L13p and L23p and the capacitor element C3p.

  The via-hole electrodes 311 to 315 may penetrate through the base material layer on which the conductor pattern is formed without being electrically connected to the conductor pattern. That is, in the surface mount type filter array 1p, when forming a conductor pattern on each base material layer, the via hole electrodes 311 to 315 may be avoided in some cases. For this reason, due to the provision of the via-hole electrodes 311 to 315, the inductance of each coil element and the capacity of each capacitor element are limited.

  Even in the surface-mounted filter array 1p according to the present modification, as in the surface-mounted filter array 1 according to the first embodiment, the nth in the positive direction from the center point in the X-axis direction (n is an arbitrary natural number) ) And the capacitor pattern of the filter located nth in the negative direction from the center point are symmetrical with respect to the center point, thereby avoiding via-hole electrodes, It is possible to maximize the capacitor pattern. Therefore, it is possible to provide a surface-mounted filter array that is reduced in size while ensuring the maximum design value of the circuit constant (capacitance value) of the filter.

  In the present invention, various dimensional values such as the thickness and shape of each layer of the multilayer substrate and the positions and sizes of the conductors and voids are not particularly limited. In addition, the components of ceramic materials constituting each layer of the multilayer substrate and the physical property values such as component permeability, magnetic permeability, the material component values used for conductors in the multilayer substrate, the physical property values such as conductivity, etc. There is no particular limitation. These numerical values are appropriately determined in consideration of various electrical characteristics such as direct current superimposition characteristics and rated capacity required for laminated coil components.

  INDUSTRIAL APPLICABILITY The present invention can be widely used in electronic equipment such as a portable information terminal as a surface mount type filter array incorporating a coil element and a capacitor element.

1, 1p Surface mount type filter array 1A Laminate 10a Top surface 10b Mounting surface 11, 12, 13, 14, 15, 13p First I / O terminals 11a, 12a, 13a, 14a, 15a, 31a, 32a, 33a, 34a, 35a, 51a, 52a, 53a, 54a, 55a First coil pattern 21, 22, 23, 24, 25, 23p Second I / O terminal 21b, 22b, 23b, 24b, 25b, 41b, 42b, 43b, 44b, 45b, 61b, 62b, 63b, 64b, 65b Second coil pattern 30, 30p GND terminal 31, 32 Side electrode 35, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 161 , 162, 163, 164, 165, 231 Conductor pattern 40C Capacitor laminate 40L Dactor stack 56, 171, 172, 173, 174, 175, 196, 197, 198, 199, 200, 206, 207, 208, 209, 216, 217, 218, 219, 220, 226, 227, 228, 229 , 303, 304, 306, 308, 311, 312, 313, 314, 315, 561, 562, 563, 564, 565, 571, 572, 573, 574, 575 Via hole electrodes 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 510, 511 Substrate layer C0b, C0e, C50b Second capacitor pattern C0c Central portion C1, C2, C3, C4, C5, C3p Capacitor element C1a , C2a, C3a, C4a, C5a, C1d, C d, C3d, C4d, C5d, C1f, C2f, C3f, C4f, C5f, C51a, C52a, C53a, C54a, C55a First capacitor patterns F1, F2, F3, F4, F5 Low-pass filters L11, L12, L13, L14, L15, L21, L22, L23, L24, L25, L13p, L23p Coil element 351, 352, 2311, 312, end

Claims (7)

A rectangular parallelepiped substrate formed by laminating a plurality of base material layers, and a longitudinal direction in each plane of the plurality of base material layers as an X-axis direction and a short direction as a Y-axis direction, and a stacking direction of the plurality of base material layers Is a surface-mounted filter array comprising a plurality of filters arranged in the X-axis direction in the rectangular parallelepiped substrate,
Each of the plurality of filters is
A coil element composed of a coil pattern having a winding axis in the Z-axis direction;
Consists of capacitor patterns arranged alternately in the Z-axis direction, including a capacitor element formed on a different substrate layer from the substrate layer on which the coil element is formed,
Among the plurality of filters, the capacitor pattern of the filter located nth (n is an arbitrary natural number) in the positive direction from the center point in the X-axis direction, and nth in the negative direction from the center point The surface mount type filter array which is point-symmetric with respect to the center point with the capacitor pattern of the filter. The capacitor pattern includes a first capacitor pattern and a second capacitor pattern,
The first capacitor pattern is an independent pattern for each of the plurality of capacitor elements,
The surface-mounted filter array according to claim 1, wherein the second capacitor pattern is a pattern common to the plurality of capacitor elements. The first capacitor pattern is formed on a plurality of the base material layers,
The surface mount filter array according to claim 1 or 2, wherein the first capacitor patterns formed on different base material layers have the same shape. The plurality of filters are provided in an odd number in the X-axis direction,
The first capacitor pattern constituting the filter located in the center in the X-axis direction is larger than the first capacitor pattern constituting the other filter, and the first capacitor constituting the filter located in the center The surface mount type filter array according to any one of claims 1 to 3, wherein a conductor pattern is not formed at a center portion of the second capacitor pattern facing the pattern. further,
A plurality of first I / O terminals, a plurality of second I / O terminals, and a GND terminal provided on the surface of the rectangular parallelepiped substrate;
The coil pattern is
A first coil pattern disposed in the positive direction of the Y-axis direction and connected to one of the plurality of first I / O terminals;
A negative direction in the Y-axis direction, juxtaposed with the first coil pattern, and connected to the first coil pattern and one of the plurality of second I / O terminals,
The first capacitor pattern is connected to a connection point between the first coil pattern and the second coil pattern,
The second capacitor pattern is connected to the GND terminal,
Among the plurality of filters, the first coil pattern of the filter located nth in the positive direction in the X-axis direction from the center point, and the nth position in the negative direction in the X-axis direction from the center point The surface-mounted filter array according to any one of claims 2 to 4, wherein the second coil pattern of the filter that is to be point-symmetrical with respect to center points in the X-axis direction and the Y-axis direction. The surface-mount filter according to claim 5, wherein the first coil pattern and the second coil pattern in one of the plurality of filters are axisymmetric with respect to a center line extending in the X-axis direction. array. Among the plurality of filters, two or more filters located in the negative direction in the X-axis direction and adjacent to the center point, or two or more filters located in the positive direction in the X-axis direction from the center point and adjacent to each other The surface-mounted filter array according to claim 5, wherein the first coil patterns or the second coil patterns of the filter have the same shape.

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