JP2017017373A - Optical communication device and optical network - Google Patents

Abstract

PROBLEM TO BE SOLVED: To switch a modulation method using a single clock.SOLUTION: Each element which configures transmission-side OFDM signal processing means for generating, from a bit sequence, an OFDM electric signal which is a symbol sequence is operated by each clock having a common single period. The transmission-side OFDM signal processing means includes: first to n-th symbol signal generation means, having mutually different multi-level numbers set therein, for generating a symbol sequence from a bit sequence using each set multi-level number Mk; modulation control signal delay equipment which gives a delay to a modulation control signal indicating the multi-level number; and a switch which selects by the delayed modulation control signal and outputs each symbol sequence output from the first to the n-th symbol signal generation means.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an optical communication device suitable for use in an optical network using optical-orthogonal frequency division multiplexing (O-OFDM), and an optical network including the optical communication device.

  In recent years, the demand for communication has increased rapidly due to the spread of the Internet and the development of mobile applications used in smartphones and the like. In response to this increase in communication demand, high-speed and large-capacity optical networks using optical fibers are being developed.

  An optical network connecting a building (station) owned by a telecommunications carrier and a subscriber's house is called a subscriber optical network or access optical network. A network connecting access optical network stations is called a metro network. In the subscriber optical network, existing and new systems are mixed, and the conditions required for the optical network differ for each service. For this reason, there is a need for an optical network that can accommodate traffic having different properties for each service, and that can easily change a service or add a new service.

  In response to such demands, an elastic metro / access fusion type network (elastic λ aggregation network) that realizes various services and network configurations has been proposed (for example, Non-Patent Document 1). reference).

  In the elastic λ aggregation network (EλAN), research and development of an optical communication device that employs orthogonal frequency division multiplexing (OFDM) as a multiplexing scheme is being promoted in order to achieve maximum elasticity. .

  Optical communication apparatuses that achieve elastic properties are required to have variability for changing settings in accordance with network requirements.

  For example, by changing the signal modulation method according to the transmission distance between the station side device (OLT: Optical Line Terminal) and the subscriber side device (ONU: Optical Network Unit), it is possible to obtain optimum quality for each subscriber. A technique for transmitting a signal has been reported (see, for example, Non-Patent Document 2 or 3). According to the techniques reported in these Non-Patent Documents 2 and 3, it is possible to increase the number of communicable lines and improve the accommodation efficiency of the network.

  When the transmission distance differs among subscribers as a result of the addition or deletion of subscribers, it is necessary to transmit signals using a plurality of modulation schemes in order to maintain the network accommodation efficiency. Also, under heavy traffic conditions, it is necessary to increase the number of lines by narrowing the signal band per line. Under low traffic conditions, the signal band per line can be widened to improve transmission quality. It is. Also, depending on network conditions such as transmission distance and traffic, it may be desired to change the symbol rate instead of the modulation method.

  However, in general, resynchronization processing is required after switching the modulation method, and it is assumed that signal loss and delay are caused. In order to solve this problem, there has been proposed a communication apparatus and its communication method that do not require resynchronization processing after switching the modulation system by synchronizing the modulation control signal instructing switching of the modulation system and the symbol sequence. (For example, refer to Patent Document 1).

Patent No. 5716855

Satoshi Okamoto, “Retractable Optical Metro / Access Fusion Aggregation Network Technology for Realizing Various Services and Network Configurations-Elastic Lambda Aggregation Network-” IEICE Technical Report CS2012-96 (2013-1), pp. 13-28. 1-6 Hiroyuki Saito et al., “Effect of Bandwidth Efficiency Improvement of PON by Modulating Multi-level Optimization”, IEICE General Conference B-8-65, March 2013 Hiroyuki Saito et al. “Examination of multi-level and symbol rate optimization method in EλAN” IEICE General Conference B-8-67, March 2014

  Here, in the technique disclosed in Patent Document 1 described above, different multi-value numbers are set in a plurality of mappers, and bit sequences output from the plurality of mappers are selected by a control cycle signal in the switch. And output. This control cycle signal is generated by changing the modulation control signal indicating the multi-value number to a cycle given by the common multiple of the multi-value number set in the n mappers. As described above, the technique disclosed in Patent Document 1 requires a plurality of clock signals having different periods.

  When these mappers and switches are configured with an FPGA (Field Programmable Gate Array), it is preferable to form them with a single cycle clock. When a clock having a plurality of cycles is used, it takes time and cost for delay analysis in designing the FPGA. Further, when a clock having a plurality of cycles is generated from a clock having one cycle by a frequency divider / multiplier, a delay or jitter may occur.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a communication device that realizes switching of a modulation method using a single clock, and an optical network including the communication device. It is to provide.

  In order to achieve the above-described object, according to the present invention, transmission-side OFDM signal processing means for generating an OFDM electrical signal that is a symbol sequence from transmission information that is a bit sequence, and light that converts an OFDM electrical signal into an OFDM optical signal In an optical communication apparatus including a transmitter, each element constituting the transmission-side OFDM signal processing means operates with a common single-cycle clock.

  The transmission-side OFDM signal processing means sets different multi-value numbers, and uses the set multi-value number Mk (n is an integer of 2 or more, k is an integer of 1 to n), and a symbol signal from a bit sequence. 1 to n-th symbol signal generating means, a modulation control signal delay unit for delaying a modulation control signal indicating a multi-value number, and symbols output from the first to n-th symbol signal generating means And a switch for selecting and outputting the signal by the delayed modulation control signal.

  The k-th symbol signal generating means converts the input bit into an Mk series parallel bit string and outputs the k-th tap delay unit, and the k-th symbol signal that converts the parallel bit string into a symbol series with the set multi-level number Mk. Mapper, k-th FIFO to which symbol sequence is input, and k-th output of a value obtained by adding 1 to the value output in the previous clock period when a clock pulse is received in the range of 0 to Mk−1. When the output of the counter and the k-th counter is 0 or less, 1 is output; otherwise, the output of the k-th comparator that outputs 0 and the output of the k-th comparator are held for a certain time and a clock pulse is received. , Mn-Mk + 1, a k-th counter delay unit that outputs bits input before the clock period, and a k-th 1-bit delay unit.

  The output of the kth comparator is branched into two, one is sent to the Push terminal of the kth FIFO, and the other is delayed by one clock by the kth 1-bit delay, Input to the Pop terminal of the FIFO. The kth FIFO operates in synchronization with the clock, accumulates a symbol sequence when Push is 1, outputs a symbol sequence from Out as a symbol signal when Pop is 1, and sends the symbol sequence to the switch.

  In the implementation of the optical communication apparatus of the present invention, the kth symbol signal generation means is configured to set the maximum number of multi-values set to at least the first to nth symbol signal generation means with respect to the input bit string. It is preferable that the modulation control signal delay unit delays Mn + 2 clock cycles and gives the modulation control signal the same delay amount as that given to the symbol string by the k-th symbol signal generation means.

  Further, a k-th delay unit that gives a delay of Mn-Mk between the k-th tap delay unit and the k-th mapper, and a delay unit through which the output of the k-th comparator passes before being branched in two In this case, it is preferable to further include a k-th counter delay device that provides a delay of Mn−Mk + 1.

  Further, according to another embodiment of the present invention, an optical receiver that converts an OFDM optical signal into an OFDM electrical signal, and a reception-side OFDM signal processing that generates reception information that is a bit sequence from the OFDM electrical signal that is a symbol sequence In the optical communication apparatus comprising the means, each element constituting the receiving-side OFDM signal processing means operates with a common single-cycle clock. The receiving-side OFDM signal processing means includes first to n-th bit signal generating means for generating a bit signal from a symbol sequence with different multi-value numbers set and the set multi-value number Mk, and multi-value numbers. A modulation control signal delay device for delaying the modulation control signal instructing the signal, and a switch for selecting and outputting the bit signal output from the first to n-th bit signal generation means by the delayed modulation control signal It is prepared for. The kth bit signal generation means includes a kth demapper, a kth delay device, a kth bit selector, and a kth bit selection signal generation unit. The k-th demapper converts the input symbol sequence into an Mk sequence parallel bit signal with the set multi-level number Mk, and outputs a bit sequence generated from the same symbol during the Mk clock. The parallel bit signal that is the output of the kth demapper is branched into two, one being sent to the kth delay device and the other being sent to the kth bit selection signal generator. When the kth bit selection signal generation unit receives a clock pulse from 0 to Mk−1, it repeatedly outputs a bit selection signal added by one. When the bit selection signal indicates p (p is an integer of 0 or more and Mk−1 or less) according to the bit selection signal, the k-th bit selector selects the p + 1-th system bit string and sends it to the switch.

  In implementing the optical communication apparatus according to another embodiment of the present invention, the kth bit selection signal generation unit includes a kth demultiplexer, a kth parallel exclusive OR, and a kth tap delay. , The k-th totalizer, the k-th one clock delay device, the k-th subtracter, the k-th comparator, and the k-th counter, and the k-th demultiplexer is 1 from the parallel bit string of the Nk sequence. The bit sequence of the sequence is extracted, and the extracted bit sequence is branched into two, one is sent to the kth parallel exclusive OR, the other is sent to the kth tap delay, and the kth tap delay The generator generates Mk bit strings each having a different delay from 0 to Mk−1 from one bit string, and the k-th parallel exclusive OR is sent from the k-th demultiplexer. 1 series of bit strings and Mk system bits sent from the k-th tap delay unit And the kth summation unit calculates an arithmetic sum with respect to the result of the logical operation in the kth parallel exclusive OR circuit to obtain the kth summation. The output of the counter is branched into two, one being sent to the k-th subtractor, the other being sent to the k-th subtracter via the k-th one-clock delay, and the k-th subtractor is the k-th totalizer The output of the k-th 1-clock delay is subtracted from the output of k, and the k-th comparator outputs bit 1 if the output of the k-th subtracter is less than − (Mk−1) / 2, and otherwise. Bit 0 is output and sent to the k-th counter. When the input bit is 0, the k-th counter outputs a numerical value obtained by adding 1 to the output numerical value one clock before, and when the input bit is 1, Alternatively, it is preferable to output 0 after one clock cycle of the time when the output becomes Mk-1.

  In addition, the optical network of the present invention is configured to include the above-described optical communication device as a transmission side device and a reception side device.

  According to the optical communication apparatus and the optical network of the present invention, the transmitter-side OFDM signal processing means and the reception-side OFDM signal processing means for switching the modulation method are operated with a single clock, respectively, so that the FPGA can be designed. It is possible to reduce time and cost in the delay analysis, and to prevent delay and jitter that occur when a clock of a plurality of cycles is generated from a clock of one cycle by a frequency divider / multiplier.

It is a schematic diagram for demonstrating an optical network. It is a schematic diagram for demonstrating a transmission side OFDM signal processing means. It is a timing chart (1) for demonstrating operation | movement of a transmission side OFDM signal processing means. It is a timing chart (2) for demonstrating operation | movement of a transmission side OFDM signal processing means. It is a timing chart (3) for demonstrating operation | movement of a transmission side OFDM signal processing means. It is a timing chart (4) for demonstrating operation | movement of a transmission side OFDM signal processing means. It is a timing chart (5) for demonstrating operation | movement of a transmission side OFDM signal processing means. It is a timing chart (6) for demonstrating operation | movement of a transmission side OFDM signal processing means. It is a timing chart (7) for demonstrating operation | movement of a transmission side OFDM signal processing means. It is a schematic diagram for demonstrating a receiving side OFDM signal processing means. It is a schematic diagram for demonstrating the bit selection signal production | generation part with which a receiving side OFDM signal processing means is provided. It is a timing chart (1) for demonstrating operation | movement of the receiving side OFDM signal processing means. It is a timing chart (2) for demonstrating operation | movement of the receiving side OFDM signal processing means. It is a timing chart (3) for demonstrating operation | movement of the receiving side OFDM signal processing means.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the shape, size, and arrangement relationship of each component are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described. However, numerical conditions and the like are merely preferred examples. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention.

(Optical network)
The optical network of the present invention will be described with reference to FIG. FIG. 1 is a schematic diagram for explaining an optical network. In the optical network 10, downlink information is sent from the OLT 100, which is a communication device, to the ONU 300, and uplink information is sent from the ONU 300 to the OLT 100. The OLT 100 is connected to an upper network (not shown) such as the Internet. The ONU 300 is connected to a user terminal or the like (not shown).

  In a passive optical network (PON), a plurality of ONUs are accommodated in one OLT. Here, communication between one OLT 100 and one ONU 300 will be described, and other ONUs will be described. Description and illustration are omitted.

  Here, a downlink signal transmitted from the OLT 100 to the ONU 300 will be described. The uplink signal transmitted from the ONU 300 to the OLT 100 may be configured so that the ONU 300 includes a function related to transmission included in the OLT 100 and the OLT 100 includes a function related to reception included in the ONU 300.

  The OLT 100 includes a transmission-side OFDM signal processing unit 110, an optical transmitter 120, and a transmission-side control unit 130.

  The transmission-side OFDM signal processing means 110 generates a transmission OFDM electrical signal that is a symbol sequence from transmission information that is a bit sequence received from an upper network or the like. The transmission-side OFDM signal processing means 110 can be realized by, for example, an FPGA. Details of the configuration and operation of the transmission-side OFDM signal processing means 110 will be described later.

  The optical transmitter 120 converts the transmission OFDM electrical signal generated by the transmission-side OFDM signal processing means 110 into a transmission OFDM optical signal, and sends it to the ONU 300. The optical transmitter 120 can be realized by those skilled in the art using a conventionally known technique.

  The transmission side control unit 130 has a function of controlling communication between the OLT 100 and the ONU 300. The transmission-side control means 130 can be configured using any suitable conventionally known technique, and a function can be realized by executing a program. Further, the transmission-side control means 130 generates a modulation control signal in accordance with transmission information traffic or the like. The modulation control signal generated by the transmission-side control means 130 is sent to the transmission-side OFDM signal processing means 110 and used for switching the modulation method. The modulation control signal includes information representing the modulation method in numerical form.

When the modulation scheme is n (n is an integer of 2 or more), the modulation control signal can be realized by, for example, m parallel binary digital sequences. Here, m is the smallest number among the integers greater than or equal to log ₂ n. Here, the multi-value number Mk (k is an integer of 1 to n) indicates the number of bits transmitted in one symbol.

  The modulation method includes BPSK (Binary Phase Shift Keying) with a multilevel number Mk of 1, QPSK (Quadrature Phase Shift Keying) with a multilevel number Mk of 2, and 8QAM (Quadrature Amplitude) with a multilevel number Mk of 3. 16QAM with a number Mk of 4, 32QAM with a multivalued number Mk of 5, 64QAM with a multivalued number Mk of 6, 128QAM with a multivalued number Mk of 7, 256QAM with a multivalued number Mk of 8, and a multivalued number Mk of 9 512QAM, 1024QAM having a multi-value number Mk of 10, and the like are selected.

  The ONU 300 includes a receiving side OFDM signal processing unit 310, an optical receiver 320, and a receiving side control unit 330.

  The optical receiver 320 converts the received OFDM optical signal received from the OLT 100 to generate a received OFDM electrical signal. The optical receiver 320 can be realized by a person skilled in the art using a conventionally known technique.

  The receiving-side OFDM signal processing means 310 converts the received OFDM electrical signal, which is a symbol sequence, generated by the optical receiver 320 into received information that is a bit sequence. This reception information is sent to a user terminal (not shown). The receiving-side OFDM signal processing means 310 can be realized by, for example, an FPGA. Details of the configuration and operation of the receiving-side OFDM signal processing means 310 will be described later.

  The receiving side control unit 330 has a function of controlling communication between the OLT 100 and the ONU 300 in accordance with an instruction from the OLT 100. Here, in addition to the function of controlling communication between the normal OLT 100 and the ONU 300, the reception side control means 330 receives the modulation control signal used in the OLT 100 by any suitable method, and receives the OFDM signal processing means on the reception side. The function to send to 310 is provided. The reception-side control means 330 can be configured using any suitable conventionally known technique, and a function can be realized by executing a program. The modulation control signal can be transmitted from the OLT 100 to the ONU 300 using, for example, a subcarrier of the OFDM signal.

(Transmitter OFDM signal processing means)
The transmission-side OFDM signal processing means will be described with reference to FIGS. FIG. 2 is a schematic configuration diagram of the transmission-side OFDM signal processing means. 3 to 9 are timing charts for explaining the operation of the transmission-side OFDM signal processing means. The horizontal axis of the timing chart indicates time, and each bit of the signal is indicated by a rectangle. The width of the rectangle indicates the clock cycle, and the numbers in the rectangle indicate the time order of the bits. The value (initial value) before the first bit is input is x. x is either 0 or 1, but here it is uncertain whether x is 0 or 1.

  The transmission-side OFDM signal processing means 110 modulates an input bit sequence that is transmission information, and outputs a modulated symbol sequence selected from among modulation schemes having multi-values M1 to Mn according to the modulation control signal. Here, description will be made assuming that M1 <M2 <... <Mk <. In this case, the maximum multi-value number Mmax is Mn. The timing chart shows an example in which n = 4, that is, one of four types of modulation schemes is selected and output. In the example shown in this timing chart, M1 = 1, M2 = 2, M3 = 3, and M4 = 5.

  The transmission-side OFDM signal processing unit 110 includes a modulation control signal delay unit 140, first to n-th symbol signal generation units 150-1 to 150-n, and a switch 190. These components operate in synchronization with a common clock signal. That is, each component operates with a single cycle clock. Although the clock signal is input to each component, the illustration is omitted here. Although the clock signal can be configured arbitrarily, it will be described here as a signal having a pulse (also referred to as a clock pulse) for each clock cycle Tclk.

  The input bit sequence which is transmission information input to the transmission-side OFDM signal processing means 110 is branched into n and sent to the first to n-th symbol signal generation means 150-1 to 150-n, respectively (FIG. 3A). 4 (A), FIG. 5 (A), FIG. 6 (A), FIG. 7 (A), FIG. 8 (A) and FIG. 9 (A)). The k-th symbol signal generation means 150-k generates a multi-value Mk symbol signal based on the input bit sequence and sends it to the switch 190.

  The k-th symbol signal generation means 150-k includes a k-th tap delay unit (Mk-tap) 152-k, a k-th delay unit 154-k, a k-th mapper 156-k, and a k-th counter 162-. k, a kth comparator 164-k, a kth counter delayer 166-k, a kth 1 bit delayer 168-k and a kth FIFO 160-k.

  The k-th tap delay unit 152-k holds the input bit sequence for a certain period of time, and when receiving a clock pulse, the k-th tap delay unit 152-k is configured from a bit input before the Mk clock cycle to a bit input before one clock cycle. Is a means for outputting a parallel bit string. That is, the k-th tap delay unit 152-k can be configured by a so-called serial-parallel converter that converts an input bit into an Mk series parallel bit string and outputs the converted bit. When the multi-level number Mk is 1, the k-th tap delay unit 152-k is a delay unit that delays the input bit by one clock period and outputs it.

  With reference to the timing chart shown in FIG. 3, the operation of the k-th tap delay unit 152-k will be described. The first tap delay unit 152-1 outputs the input bit sequence (FIG. 3A) with a delay of one clock cycle (FIG. 3B). The second tap delay unit 152-2 outputs two series of parallel bit strings composed of a bit input two clock cycles before and a bit input one clock cycle before (FIG. 3C). . The third tap delay unit 152-3 outputs three series of parallel bit strings composed of bits input from three clock cycles before to one clock cycle before (FIG. 3D). The fourth tap delay unit 152-4 outputs five series of parallel bit strings composed of bits input from five clock cycles before to one clock cycle before (FIG. 3E).

  The k-th delay unit 154-k holds the parallel bit string, which is the output of the k-th tap delay unit 152-k, for a certain period of time. When the k-th delay unit 154-k receives a clock pulse, the k-th delay unit 152-k Output as a delayed parallel bit string. Note that the delay amount in the n-th delay device 154-n is 0 (= Mn-Mn), and thus the n-th delay device 154-n may not be provided. The delayed parallel bit string output from the kth delay unit 154-k is sent to the kth mapper 156-k.

  The operation of the k-th delay device 154-k will be described with reference to the timing chart shown in FIG. 4. When the first delay unit 154-1 receives the clock pulse by receiving the parallel bit string that is the output of the first tap delay unit 152-1, the first delay unit 154-1 receives 4 (= M4-M1 = 5-1) clock cycles ago. Is output as a delayed parallel bit string (FIG. 4B). Here, since M1 = 1, the delayed parallel bit string is one system bit string.

  When the second delay unit 154-2 receives the clock pulse by inputting the parallel bit string that is the output of the second tap delay unit 152-2, the second delay unit 154-2 receives 3 (= M4-M2 = 5-2) clock cycles ago. Are output as a delayed parallel bit string (FIG. 4C).

  When the third delay unit 154-3 receives the clock pulse by inputting the parallel bit string which is the output of the third tap delay unit 152-3, the third delay unit 154-3 is two (= M4-M3 = 5-3) clock cycles before Is output as a delayed parallel bit string (FIG. 4D).

  When the fourth delay unit 154-4 receives the parallel bit string that is the output of the fourth tap delay unit 152-4 and receives a clock pulse, the fourth delay unit 154-4 receives 0 (= M4-M4 = 5-5) clock cycles ago. Is output as a delayed parallel bit string (FIG. 4E). That is, the fourth delay unit 154-4 is not delayed.

  The k-th mapper 156-k converts the input delayed parallel bit string into a symbol sequence with the multi-valued number Mk set in the k-th mapper 156-k, and sends it to the In terminal of the k-th FIFO 160-k. .

  The operation of the kth mapper 156-k will be described with reference to the timing chart shown in FIG. The first mapper 156-1 converts the input delayed parallel bit string into a symbol series with the multi-value number M1 = 1 set in the first mapper 156-1 (FIG. 5B and FIG. 6B). )). Here, since M1 = 1, the symbol series is a single bit string.

The second mapper 156-2 converts the input delayed parallel bit string into a symbol series with the multi-value number M2 = 2 set in the second mapper 156-2 (FIG. 5C and FIG. 7B). )). The first 5 clocks are a symbol series in which x is included in the input bit string and are uncertain, so they are also expressed as x. Sixth clock is first bit and a second multi-level number according to bit M2 = 2 symbol sequences, which are expressed as A _{1, 2.} Similarly, the seventh clock is a symbol series of the multi-value number M2 = 2 by the second bit and the third bit, and is represented as _A2,3 .

The third mapper 156-3 converts the input delayed parallel bit string into a symbol series with the multi-value number M3 = 3 set in the third mapper 156-3 (FIG. 5D and FIG. 8B). )). The first 5 clocks are a symbol series in which x is included in the input bit string and are uncertain, so they are also expressed as x. The sixth clock is a symbol series of the multi-level number M3 = 3 by the first to third bits, and this is represented as _B1,3 . Similarly, the seventh clock is a multi-valued number M3 = 3 symbol series based on the second to fourth bits, and is represented as _B2,4 .

The fourth mapper 156-4 converts the input delayed parallel bit string into a symbol sequence with the multi-value number M4 = 5 set in the fourth mapper 156-4 (FIG. 5E and FIG. 9B). )). The first 5 clocks are a symbol series in which x is included in the input bit string and are uncertain, so they are also expressed as x. The 6th clock is a multi-valued number M4 = 5 symbol series by the 1st to 5th bits, and this is expressed as _C1,5 . Similarly, the 7th clock is a symbol series of multi-level number M4 = 5 by the 2nd to 6th bits and is expressed as _C2,6 .

  In addition to these symbol sequences, a Push signal and a Pop signal are also input to the k-th FIFO 160-k. The kth FIFO 160-k operates in synchronization with the clock. When the Push is 1, the delayed parallel bit string is accumulated. When the Pop is 1, the symbol series is output from Out and is sent to the switch 190.

  The Push signal and Pop signal input to the k-th FIFO 160-k are the k-th counter 162-k, the k-th comparator 164-k, the k-th counter delay unit 166-k, and the k-th 1-bit delay. Generated by the device 168-k.

  When the k-th counter 162-k receives the clock pulse, it outputs a numerical value obtained by adding 1 to the numerical value output in the previous clock cycle. The numerical value output by the k-th counter 162-k is set to 0 to Mk-1. That is, the k-th counter 162-k adds one by one in order from 0 and outputs it, and outputs 0 in the next clock cycle after outputting Mk-1.

  The kth comparator 164-k is a means for outputting 1 if the output of the kth counter 162-k is 0 or less, and outputting 0 otherwise.

  The k-th counter 162-k and the k-th comparator 164-k output 1 every Mk periods, and output 0 otherwise. When the multi-value number Mk is 1, a constant source that always outputs 1 may be used instead of the k-th counter 162-k and the k-th comparator 164-k.

  The k-th counter delay unit 166-k is a means for holding the output of the k-th comparator 164-k for a certain period of time and, when receiving a clock pulse, outputting a bit input before Mn-Mk + 1 clock period. . The output of the k-th counter delay unit 166-k is branched into two, one being sent to the Push terminal of the k-th FIFO 160-k and the other being sent to the k-th 1-bit delay unit 168-k.

  The k-th 1-bit delay unit 168-k is means for holding the output of the k-th counter delay unit 166-k for a certain period of time and outputting the bit input one clock period before receiving the clock pulse. . The output of the kth 1-bit delay unit 168-k is sent to the Pop terminal of the kth FIFO 160-k.

  The generation of the Push signal and the Pop signal will be described with reference to the timing charts shown in FIGS.

  When receiving the clock pulse, the first counter 162-1 outputs a numerical value obtained by adding 1 to the numerical value output at the previous timing. Since M1 = 1, the numerical value output by the first counter 162-1 is always 0 (FIG. 6C).

  The first comparator 164-1 outputs bit 1 if the output of the first counter 162-1 is 0 or less, and outputs bit 0 otherwise. Since the output of the first counter 162-1 is always 0, the output of the first comparator 164-1 is always 1 (FIG. 6D).

  The first counter delay unit 166-1 holds the output of the first comparator 164-1 for a predetermined time, and when a clock pulse is received, the first counter delay unit 166-1 is input before 5 (= Mn−Mk + 1 = 5-1 + 1) clock periods. Output the correct bit. The output of the first counter delay unit 166-1 is branched into two, one is sent to the Push terminal of the first FIFO 160-1 (FIG. 6E), and the other is the first 1-bit delay unit 168. -1.

  The first 1-bit delay unit 168-1 holds the output bit of the first counter delay unit 166-1 for a certain period of time, and when it receives a clock pulse, outputs the bit that was input one clock period before. The output of the first 1-bit delay unit 168-1 is sent to the Pop terminal of the first FIFO (FIG. 6F).

  The first FIFO 160-1 operates in synchronization with the clock. When the Push is 1, the delayed parallel bit string is accumulated. When the Pop is 1, the symbol series is output from the Out and sent to the switch 190 (FIG. 6 (G)).

  When receiving the clock pulse, the second counter 162-2 outputs a numerical value obtained by adding 1 to the numerical value output at the previous timing (FIG. 7C). The numerical value output by the second counter 162-2 is set to 0 to 1 (= Mk-1 = 2-1).

  The second comparator 164-2 outputs 1 if the output of the second counter 162-2 is 0 or less, and outputs 0 otherwise. The second counter 162-2 and the second comparator 164-2 output 1 every 2 (= M2) clock cycles, and output 0 otherwise (FIG. 7D).

  The second counter delay unit 166-2 holds the output of the second comparator 164-2 for a fixed time, and when a clock pulse is received, the second counter delay unit 166-2 is input before 4 (= Mn−Mk + 1 = 5-2 + 1) clock periods. Output the correct bit. The output of the second counter delay unit 166-2 is branched into two, one is sent to the Push terminal of the second FIFO 160-2 (FIG. 7E), and the other is the second 1-bit delay unit 168. -2.

  The second 1-bit delay unit 168-2 holds the output of the second counter delay unit 166-2 for a predetermined time, and when it receives a clock pulse, outputs the bit input one clock period before. The output of the second 1-bit delay unit 168-2 is sent to the Pop terminal of the second FIFO 160-2 (FIG. 7F).

  The second FIFO 160-2 operates in synchronization with the clock. When the Push is 1, the delayed parallel bit string is accumulated. When the Pop is 1, the symbol sequence is output from Out and sent to the switch 190 (see FIG. 7 (G)).

  When receiving the clock pulse, the third counter 162-3 outputs a numerical value obtained by adding 1 to the numerical value output at the previous timing (FIG. 8C). The numerical value output by the third counter 162-3 is set to 0 to 2 (= Mk-1 = 3-1).

  The third comparator 164-3 outputs 1 if the output of the third counter 162-3 is 0 or less, and outputs 0 otherwise. The third counter 162-3 and the third comparator 164-3 output 1 every 3 (= M3) clock cycles, and output 0 otherwise (FIG. 8D).

  When the third counter delay unit 166-3 holds the output of the third comparator 164-3 for a certain period of time and receives a clock pulse, the third counter delay unit 166-3 is input 3 clock cycles before (= Mn−Mk + 1 = 5−3 + 1). Output the correct bit. The output of the third counter delay unit 166-3 is branched into two, one is sent to the Push terminal of the third FIFO 160-3 (FIG. 8E), and the other is the third 1-bit delay unit 168. -3.

  The third 1-bit delay unit 168-3 holds the output of the third counter delay unit 166-3 for a certain period of time, and when it receives a clock pulse, outputs the bit input one clock period before. The output of the third 1-bit delay unit 168-3 is sent to the Pop terminal of the third FIFO 160-3 (FIG. 8F).

  The third FIFO 160-3 operates in synchronization with the clock. When the Push is 1, the delayed parallel bit string is accumulated. When the Pop is 1, the symbol series is output from the Out and sent to the switch 190 (see FIG. 8 (G)).

  When receiving the clock pulse, the fourth counter 162-4 outputs a numerical value obtained by adding 1 to the numerical value output at the previous timing (FIG. 9C). The numerical value output by the fourth counter 162-4 is set to 0 to 4 (= Mk-1 = 5-1).

  The fourth comparator 164-4 outputs 1 if the output of the fourth counter 162-4 is 0 or less, and outputs 0 otherwise. The fourth counter 162-4 and the fourth comparator 164-4 output 1 every 5 (= M4) clock cycles, and output 0 otherwise (FIG. 9D).

  The fourth counter delay unit 166-4 holds the output of the fourth comparator 164-4 for a fixed time, and when a clock pulse is received, it is input 1 (= Mn−Mk + 1 = 5−5 + 1) clock cycles before. Output bits. The output of the fourth counter delay unit 166-4 is branched into two, one is sent to the Push terminal of the fourth FIFO 160-4 (FIG. 9E), and the other is the fourth 1-bit delay unit 168. -4.

  The fourth 1-bit delay unit 168-4 holds the output of the fourth counter delay unit 166-4 for a certain period of time, and when it receives a clock pulse, outputs the bit input one clock period before. The output of the fourth 1-bit delay unit 168-4 is sent to the Pop terminal of the fourth FIFO 160-4 (FIG. 9F).

  The fourth FIFO 160-4 operates in synchronization with the clock. When the Push is 1, the delayed parallel bit string is accumulated. When the Pop is 1, the symbol series is output from the Out as a symbol signal and is sent to the switch 190. Send (FIG. 9G).

  The switch 190 selects and outputs one of the symbol sequences output from the Out of the first to nth FIFOs 160-1 to 160-n. The selection of the symbol series is instructed by the modulation control signal.

  Here, the input bit string is delayed by Mk clocks by the k-th tap delay unit 152-k and k-th delay unit 154-k, and output by receiving a delay of 2 clocks by the FIFO 160-k. Therefore, the modulation control signal delay unit 140 holds the modulation control signal for a certain period of time, and sends the input numerical value before Mn + 2 clocks to the switch 190 as the modulation control delay signal. The delay amount in the modulation control signal delay unit 140 may be matched with the delay amount in the first to nth symbol signal generation means 150-1 to 150-n.

  Here, the configuration in which the bit string is serial-parallel converted and then input to the mapper has been described, but the present invention is not limited thereto. The mapper may be provided with a function for serial / parallel conversion, and a bit string input to the mapper may be converted into a symbol string after being serial / parallel converted in the mapper.

(Reception side OFDM signal processing means)
The receiving-side OFDM signal processing means will be described with reference to FIGS. FIG. 10 is a schematic configuration diagram of the receiving-side OFDM signal processing means. FIG. 11 is a schematic diagram for explaining the bit selection signal generation unit provided in the reception-side OFDM signal processing means. 12 to 14 are timing charts for explaining the operation of the receiving-side OFDM signal processing means. The horizontal axis of the timing chart indicates time.

  The receiving-side OFDM signal processing means 310 selects an input symbol sequence, which is a received OFDM signal, from among modulation schemes having a multi-value number of M1 to Mn according to the modulation control signal, and demodulates and outputs it.

  The reception-side OFDM signal processing means 310 includes a modulation control signal delay unit 340, first to n-th bit signal generation means 350-1 to 350-n, and a switch 390. These components operate in synchronization with a common clock signal. That is, each component operates with a single cycle clock. Although the clock signal is input to each component, the illustration is omitted here.

  The input symbol series is n-branched and sent to the first to n-th bit signal generation means 350-1 to 350-n, respectively (FIG. 12A). The kth bit signal generation means 350-k generates a bit sequence from the input symbol sequence and sends it to the switch 390.

  The kth bit signal generation means 350-k includes a kth demapper 356-k, a kth delay unit 354-k, a kth bit selector (selector) 358-k, and a kth bit selection signal generation unit. 360-k.

  The k-th demapper 356-k converts the input symbol series into an Mk-sequence parallel bit string with the multi-valued number Mk set in the k-th demapper 356-k (FIG. 12B). The kth demapper 356-k outputs a bit sequence generated from the same symbol during the Mk clock. The parallel bit string that is the output of the k-th demapper 356-k is branched into two, one is sent to the k-th delay unit 354-k, and the other is sent to the k-th bit selection signal generator 360-k.

  The kth bit selection signal generator 360-k includes a kth demultiplexer 362-k, a kth parallel exclusive OR 364-k, a kth tap delay 366-k, and a kth sum. And a k-th 1-clock delay unit 370-k, a k-th subtracter 372-k, a k-th comparator 374-k, and a k-th counter 376-k ( FIG. 11).

  When the parallel bit string is sent to the k-th bit selection signal generator 360-k, the k-th demultiplexer 362-k extracts one series of bit strings from the Mk series parallel bit strings. The extracted bit sequence is branched into two and one is sent to the k-th parallel exclusive OR 364-k, and the other is sent to the k-th tap delay 366-k.

  The k-th tap delay unit 366-k generates an Mk sequence bit string from one sequence bit string. A different delay is given to each bit string of the Mk sequence. The first bit string is given a delay 0, the second bit string is given a delay 1, and similarly, the Mk-th bit string is given a delay Mk-1 (FIG. 12C). The bit string of the Mk sequence is sent to the kth parallel exclusive OR 364-k.

The k-th parallel exclusive OR 364-k includes one series of bit strings sent from the k-th demultiplexer 362-k and Mk series bit strings sent from the k-th tap delay unit 366-k. Perform an exclusive OR operation with each of the above. In the case of delay 0, since both coincide, the result of the logical operation is always 1. In the case of the delay 1, x is equal to one clock period during the Mk clock period, and 1 is equal to the subsequent Mk-1 clock period. Further, in the case of the delay Mk−1, it becomes 1 for one clock cycle during the Mk clock cycle, and x for the subsequent Mk−1 clock cycle. Here, x represents an uncertain value of 0 or 1. The exclusive OR of a and a is 1. In addition, the exclusive OR of x and a is expressed as x _x , the exclusive OR of _a and b is expressed as x _a, and the exclusive OR of b and c is expressed as x _b (FIG. 12D). .

  The k-th totalizer 368-k calculates the arithmetic sum with respect to the result of these logical operations (FIG. 13B). The output of the k-th totalizer 368-k is branched into two, one passing through the + terminal of the k-th subtractor 372-k and the other passing through the k-th 1-clock delay 370-k. Sent to the-terminal of 372-k. That is, the k-th subtractor 372-k subtracts the output (FIG. 13C) delayed by one clock cycle by the k-th one-clock delay unit 370-k from the output of the k-th totalizer 368-k. (FIG. 13D).

  The output of the kth subtractor 372-k is (Mk-1) (x-1) once every Mk clock period, and 1-x otherwise. Here, x is an uncertain value of 1 or 0. Therefore, the output of the subtracter is 0 or − (Mk−1) once every Mk clock period, and 0 or 1 otherwise.

  The output of the kth subtractor 372-k is sent to the kth comparator 374-k. The kth comparator 374-k outputs 1 if the output of the kth subtractor 372-k is less than-(Mk-1) / 2, and 0 otherwise, and the kth counter 378- k (FIG. 13E).

  The k-th counter 378-k outputs a numerical value obtained by adding 1 to the output numerical value one clock period before when the input bit is 0, and the output becomes Mk-1 when the input bit is 1 0 is output after one clock cycle of time. The output of the kth counter 378-k is 0 to Mk-1. The output of the k-th counter 378-k becomes a bit selection signal (FIG. 14C).

  The kth selector 358-k selects and outputs one of the parallel bit strings according to the bit selection signal. When the bit selection signal indicates 0, the first series of bit strings is selected, and when the bit selection signal indicates 1, the second series of bit strings is selected. Thus, when the bit selection signal indicates p (p is an integer not less than 1 and not more than Mk−1), the bit string of the (p + 1) th series is selected and sent to the switch 390.

  The switch 390 selects and outputs one of the bit strings output from the outputs of the first to nth selectors. The selection of this bit string is instructed by a modulation control signal.

  In the configuration described above, each delay unit such as a 1-bit delay unit can be configured by a flip-flop, for example. Further, the selector and the switch can be configured similarly. In addition, the delay amount in each delay unit may be set so that the modulation control signal input to the switches 190 and 390 and the bit signal or symbol signal are synchronized, and the delay amount is arbitrarily set so as to satisfy the condition. can do.

10 Optical network 100 OLT
DESCRIPTION OF SYMBOLS 110 Transmission side OFDM signal processing means 120 Optical transmitter 130 Transmission side control means 140, 340 Modulation control signal delay device 150 Symbol signal generation means 152 Tap delay device 154 Delay device 156 Mapper 160 FIFO
162, 376 Counter 164, 374 Comparator 166 Counter delay 168 1-bit delay 190, 390 Switch 300 ONU
310 Receiver OFDM signal processing means 320 Optical receiver
330 Receiving side control means
350 bit signal generating means 354 delay unit 356 demapper 358 bit selector (selector)
360 bit selection signal generation unit 362 demultiplexer 364 parallel exclusive OR 366 tap delay 368 totalizer 370 1 clock delay 372 subtractor

The k-th symbol signal generating means converts the input bit into an Mk series parallel bit string and outputs the k-th tap delay unit, and the k-th symbol signal that converts the parallel bit string into a symbol series with the set multi-level number Mk. A mapper, a k-th delay device provided between the k-th tap delay device and the k-th mapper, which gives a delay of Mn-Mk, and a symbol sequence to which a delay of Mn-Mk is given are input. K-th FIFO, a k-th counter that outputs a numerical value obtained by adding 1 to a numerical value output in the previous clock period when a clock pulse is received in a range of 0 to Mk−1, and an output of the k-th counter If 0 is less than 0, 1 is output, otherwise 0 is output and the output of the kth comparator is held for a certain period of time, and when a clock pulse is received, it is input before Mn-Mk + 1 clock period The specified bits k and counter delayer configured by a 1-bit delay device of the k.

The output of the kth counter delayer is branched into two, one being sent to the Push terminal of the kth FIFO, and the other being delayed by one clock by the kth 1-bit delayer, Is input to the Pop terminal of the FIFO. The kth FIFO operates in synchronization with the clock, accumulates a symbol sequence when Push is 1, outputs a symbol sequence from Out as a symbol signal when Pop is 1, and sends the symbol sequence to the switch.

Claims (6)

Transmission-side OFDM signal processing means for generating an orthogonal frequency division multiplexing (OFDM) electrical signal that is a symbol sequence from transmission information that is a bit sequence, and optical transmission that converts the OFDM electrical signal into an OFDM optical signal An optical communication device comprising a device,
Each element constituting the transmission-side OFDM signal processing means operates with a common single period clock,
The transmission side OFDM signal processing means includes:
Different multi-value numbers are set, and the first to n-th symbol signals are generated from the bit sequence with the set multi-value number Mk (n is an integer of 2 or more, k is an integer of 1 to n). Symbol signal generating means,
A modulation control signal delay device that delays the modulation control signal indicating the multi-value number;
A switch that selects and outputs the symbol signal output from the first to n-th symbol signal generation means by the delayed modulation control signal;
The k-th symbol signal generating means is
A k-th tap delay device for converting an input bit into a parallel bit string of an Mk sequence and outputting it;
A k-th mapper for converting the parallel bit string into a symbol sequence with a set multi-level number Mk;
A kth FIFO to which the symbol sequence is input;
A k-th counter that outputs a numerical value obtained by adding 1 to a numerical value output in the previous clock period when a clock pulse is received in a range of 0 to Mk−1;
A kth comparator that outputs 1 if the output of the kth counter is less than or equal to 0, and outputs 0 otherwise.
Holding the output of the k-th comparator for a certain period of time, and receiving a clock pulse, the k-th counter delayer that outputs a bit input before Mn-Mk + 1 clock period;
A k-th 1-bit delay device,
The output of the k-th comparator is branched into two, one is sent to the Push terminal of the k-th FIFO, and the other is delayed by one clock by the k-th 1-bit delay unit, Input to the Pop terminal of the kth FIFO;
The kth FIFO operates in synchronization with a clock, accumulates a symbol sequence when Push is 1, outputs a symbol sequence from Out as the symbol signal when Pop is 1, and sends the symbol sequence to the switch. An optical communication device. The k-th symbol signal generation means delays the symbol sequence with respect to the input bit string by at least the maximum multi-value number Mn + 2 clock period set in the first to n-th symbol signal generation means,
2. The optical communication apparatus according to claim 1, wherein the modulation control signal delay unit gives the modulation control signal the same delay amount as the delay given to the symbol sequence by the k-th symbol signal generation unit. A kth delay unit providing a Mn-Mk delay between the kth tap delayer and the kth mapper;
3. The delay circuit according to claim 2, further comprising: a delay device that passes through the output of the kth comparator before branching into two branches, and provides a delay of Mn-Mk + 1. The optical communication device described. An optical communication apparatus comprising: an optical receiver that converts an OFDM optical signal into an OFDM electrical signal; and a reception-side OFDM signal processing unit that generates reception information that is a bit sequence from an OFDM electrical signal that is a symbol sequence,
Each element constituting the receiving-side OFDM signal processing means operates with a common single-cycle clock,
The receiving-side OFDM signal processing means includes:
Different multi-value numbers are set, and the first to n-th bits for generating a bit signal from a symbol sequence with the set multi-value number Mk (n is an integer of 2 or more, k is an integer of 1 to n) Bit signal generating means;
A modulation control signal delay device that delays the modulation control signal indicating the multi-value number;
A switch that selects and outputs the bit signal output from the first to n-th bit signal generating means by the delayed modulation control signal;
The kth bit signal generation means includes a kth demapper, a kth delay device, a kth bit selector, and a kth bit selection signal generation unit,
The k-th demapper converts the input symbol sequence into an Mk sequence parallel bit signal with the set multi-value number Mk, and outputs a bit sequence generated from the same symbol sequence during the Mk clock,
The parallel bit signal that is the output of the k-th demapper is branched into two, one is sent to the k-th delay device, and the other is sent to the k-th bit selection signal generator,
The kth bit selection signal generation unit repeatedly outputs a bit selection signal added by 1 when receiving a clock pulse from 0 to Mk−1,
The k-th bit selector selects a p + 1-th bit sequence as the bit signal when the bit selection signal indicates p (p is an integer between 0 and Mk−1) according to the bit selection signal. And an optical communication device for sending to the switch. The kth bit selection signal generator includes a kth demultiplexer, a kth parallel exclusive OR, a kth tap delay, a kth summation device, a kth one clock delayer, a k subtractor, kth comparator, and kth counter,
The k-th demultiplexer extracts one bit sequence from a parallel bit sequence of Nk sequences;
The extracted bit sequence is branched into two, one is sent to the kth parallel exclusive OR, the other is sent to the kth tap delay,
The k-th tap delay unit generates an Mk bit string having different delays from 0 to Mk−1 from one bit string,
The k-th parallel exclusive OR circuit is configured to perform exclusive logic with each of one series of bit strings sent from the k-th demultiplexer and each of Mk-type bit strings sent from the k-th tap delay unit. Perform a sum operation,
The k-th totalizer calculates an arithmetic sum with respect to the result of the logical operation in the k-th parallel exclusive OR;
The output of the k-th summer is branched into two, one being sent to the k-th subtracter and the other being sent to the k-th subtracter via the k-th 1-clock delay device,
The k-th subtracter subtracts the output result of the k-th 1-clock delay device from the output of the k-th summer;
The kth comparator outputs bit 1 if the output of the kth subtracter is less than − (Mk−1) / 2, and outputs bit 0 otherwise, and sends it to the kth counter.
The kth counter outputs a numerical value obtained by adding 1 to the output numerical value one clock before when the input bit is 0, or 1 when the input bit is 1 or when the output becomes Mk−1. The optical communication apparatus according to claim 4, wherein 0 is output after the clock period. The optical communication device according to any one of claims 1 to 3 is provided as a transmission side device,
An optical network comprising the optical communication device according to claim 4 or 5 as a receiving side device.

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