JP2017016619A - Liquid crystal display device with touch panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify a wiring structure by decreasing the number of capacitance detection electrode lines and image signal lines and to maintain a high opening ratio of all pixel parts.SOLUTION: An LCD with a touch panel includes capacitance detection electrode lines CDL1∼ formed parallel to image signal lines SL1∼, and an image signal line drive circuit 4 on a surface on a liquid crystal 11 side of an array side substrate 1. The capacitance detection electrode line CDL1 is disposed in a portion between a first unit pixel electrode 23a and a second unit pixel electrode 23b, where the image signal line SL1 is not disposed. Thereby, the wired number of capacitance detection electrode lines CDL1∼ can be decreased and the wiring structure is simplified. The capacitance detection electrode line CDL1 is suppressed from intruding into the first unit pixel electrode 23a side or the second unit pixel electrode 23b side. Thus, an opening ratio in all pixel parts PR11∼ can be maintained high.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a liquid crystal display device (LCD) with a touch panel having capacitance detection electrode lines of a capacitance detection type touch panel in a cell of a liquid crystal display panel.

  2. Description of the Related Art Conventionally, an LCD includes an array side substrate on which a large number of pixel portions including thin film transistors (TFTs) are formed and a color filter side substrate on which a color filter and a black matrix are formed so as to face each other. Are bonded together at a predetermined interval, and a liquid crystal is filled and sealed between the substrates. In general, the color filter side substrate is commonly used to form a vertical electric field to be applied to the liquid crystal between the pixel electrode and the entire surface on the side facing the TFT and the pixel electrode (surface on the liquid crystal side). An electrode is formed. Further, when the LCD is an IPS (In-Plane Switching) type LCD that forms a lateral electric field applied to the liquid crystal between the pixel electrode and the common electrode, the common electrode is in the same plane as the pixel electrode of the array side substrate. It is formed. When the LCD is an FFS (Fringe Field Switching) type LCD that forms an end electric field to be applied to the liquid crystal between the pixel electrode and the common electrode, the common electrode is placed above or below the pixel electrode on the pixel portion of the array side substrate. Formed with an insulating layer interposed therebetween. Further, red (R), green (G), and blue (B) color filters corresponding to the respective pixel portions are formed on the liquid crystal side surface of the color filter side substrate, and pass through the respective pixel portions. A black matrix that prevents light from interfering with each other is formed so as to surround the outer periphery of the color filter.

  An example of the basic configuration of a conventional active matrix LCD is shown in FIG. For example, in the case of an IPS LCD, an array side substrate on which a large number of pixel portions P11, P12, P13 to Pmn including TFTs 52 are formed has a plurality of pieces formed in a first direction (for example, a row direction) thereon. The gate signal lines 57 (GL1, GL2, GL3 to GLm) intersect with the gate signal lines 57 (GL1, GL2, GL3 to GLm) in a second direction (for example, the column direction) that intersects the first direction. A plurality of formed image signal lines (source signal lines) 58 (SL1, SL2, SL3 to SLn), gate signal lines 57 (GL1, GL2, GL3 to GLm) and image signal lines 58 (SL1, SL2, SL3) To SLn), pixel electrodes PE11, PE12, PE13 to PEmn and a common electrode (reference electrode) for forming a horizontal electric field (horizontal electric field) to be applied to the TFT 52 and the liquid crystal formed corresponding to each intersection of Pixel portions P11, P12, P13 to Pmn including them, and a common voltage line 62 for supplying a common voltage (Vcom) to the common electrode, It is configured to. In FIG. 5, 59 is a display area, 70 is a drive circuit portion for driving the gate signal line selection circuit 71 and the image signal line selection circuit 72, and 71 is sequentially applied to the gate signal lines 57 (GL1, GL2, GL3 to GLm). A gate signal line selection circuit (first selector circuit) for inputting a gate signal, 72 is an image signal line selection circuit (second selector) for sequentially inputting the image signals to the image signal lines 58 (SL1, SL2, SL3 to SLn). Circuit) 73 is a first connection line for inputting / outputting a drive signal, a control signal, etc. between the drive circuit unit 70 and the gate signal line selection circuit 71, and 74 is a drive circuit unit 70 and an image signal line selection circuit. Reference numeral 80 denotes a second connection line for inputting / outputting drive signals, control signals, and the like to / from 72, and a liquid crystal display panel. IPS LCDs can improve viewing angle characteristics such as contrast, gray reversal, and color shift compared to LCDs that drive twisted nematic (TN) liquid crystal by a vertical electric field. As a result, since a wide viewing angle can be obtained, it is suitably used for a large LCD.

  The TFT 52 has a semiconductor film made of, for example, amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and the like, and has three terminal portions including a gate electrode portion, a source electrode portion, and a drain electrode portion. It is the structure which has. Then, by applying a voltage of a predetermined potential (for example, 6V) to the gate electrode portion, the current flows through the semiconductor film (channel) between the source electrode portion and the drain electrode portion and functions as a switching element (gate transfer element). To do. The pixel electrodes PE11, PE12, PE13... PEmn are generally composed of a transparent conductor layer made of indium tin oxide (ITO) or the like.

  FIG. 6 is a circuit diagram showing a detailed configuration of the image signal line selection circuit 72 in the LCD having the configuration of FIG. As shown in FIG. 6, the TFT and pixel electrodes R11, G11, B11˜ correspond to the intersections of the gate signal lines GL1, GL2, GL3 and the image signal lines SL1, SL2, SL3, SL4, SL5, SL6. B32 is formed. CMOS transfer gate elements 80a, 80b, 80c, 80d, 80e, and 80f are connected to the input ends of the image signals of the image signal lines SL1 to SL6, respectively, and the sources of the CMOS transfer gate elements 80a to 80c are connected. The electrodes are commonly connected to the image signal input terminal S1 of the drive circuit unit 70, and the source electrodes of the CMOS transfer gate elements 80d to 80f are commonly connected to the image signal input terminal S2 of the drive circuit unit 70. The second connection line 74 is an image signal input terminal S1 of the drive circuit unit 70 composed of an image signal line drive IC, LSI or the like mounted on the array side substrate by a chip on glass (COG) method. S2 is electrically connected to the image signal line selection circuit 72. The drain electrodes of the CMOS transfer gate elements 80a to 80c are connected to the image signal lines SL1, SL2, and SL3, respectively, and the drain electrodes of the CMOS transfer gate elements 80d to 80f are connected to the image signal lines SL4, SL5, and SL6, respectively. It is connected to the.

  Each of the CMOS transfer gate elements 80a to 80f is composed of a p-type MOS transistor (p-channel TFT) and an n-type MOS transistor (n-channel TFT), and their source electrode and drain electrode are connected in common. The gate electrode and the gate electrode of the n-type MOS transistor are used as control input electrodes. That is, when a low (L) signal is input to the gate electrode of the p-type MOS transistor and a high (H) signal is input to the gate electrode of the n-type MOS transistor, the gap between the source electrode and the drain electrode is increased. A current flows through and an image signal is input.

  MUXR, XMUXR, MUXG, XMUXG, MUXB, and XMUXB are time division signal input lines for driving the image signal lines SL1 to SL6 in a time division manner. MUXR is connected to the gate electrodes of the n-type MOS transistors of the CMOS transfer gate elements 80a and 80d, and XMUXR (inverted signal line of MUXR) is connected to the gate electrodes of the p-type MOS transistors of the CMOS transfer gate elements 80a and 80d. When the H signal is input to MUXR and the L signal is input to XMUXR, the image signals SigR1 and SigR2 input from the image signal input terminals S1 and S2 transmit the image signal lines SL1 and SL4. Is done. MUXG is connected to the gate electrode of the n-type MOS transistor of the CMOS transfer gate elements 80b and 80e, and XMUXG (inverted signal line of MUXG) is connected to the gate electrode of the p-type MOS transistor of the CMOS transfer gate elements 80b and 80e. When the H signal is input to MUXG and the L signal is input to XMUXG, the image signals SigG1 and SigG2 input from the image signal input terminals S1 and S2 transmit the image signal lines SL2 and SL5. Is done. MUXB is connected to the gate electrodes of the n-type MOS transistors of the CMOS transfer gate elements 80c and 80f, and XMUXB (inverted signal line of MUXB) is connected to the gate electrodes of the p-type MOS transistors of the CMOS transfer gate elements 80c and 80f. When the H signal is input to MUXB and the L signal is input to XMUXB, the image signals SigB1 and SigB2 input from the image signal input terminals S1 and S2 transmit the image signal lines SL3 and SL6. Is done.

  FIG. 7 is a timing chart for driving the pixel electrodes R11, G11, and B11 of FIG. 5 in a time division manner. The pixel electrode R11 is a unit pixel electrode (subpixel electrode) red 11, the pixel electrode G11 is a unit pixel electrode (subpixel electrode) green 11, and the pixel electrode B11 is a unit pixel electrode (subpixel electrode) blue 11. . When the gate signal line GL1 is in an ON state, when a high signal is input to MUXR and a low signal is input to XMUXR, a predetermined image signal is input to the pixel electrode R11. When the gate signal line GL1 is in an ON state, when a H signal is input to MUXG and an L signal is input to XMUXG, a predetermined image signal is input to the pixel electrode G11. When the gate signal line GL1 is in an ON state, when a high signal is input to MUXB and a low signal is input to XMUXB, a predetermined image signal is input to the pixel electrode B11.

  FIG. 8 is a plan view of the overall configuration including the frame portion of the LCD having the circuit configuration of FIG. As shown in FIG. 8, a frame portion 61 is provided around the display area 59 in a plan view, and the frame portion 61 generally has a light-shielding color such as black. The drive circuit unit 70 is arranged on the liquid crystal side surface of the projection P projecting outward from the color filter side substrate 60 of the array side substrate 51, and the drive circuit unit 70 side of the frame portion 61 having a rectangular frame shape. The image signal line selection circuit 72 is arranged so as to overlap the part GB1. An FPC (Flexible Printed Circuit) 77 for inputting / outputting drive signals, control signals, and the like to / from the drive circuit unit 70 is installed at the edge of the surface of the protrusion P on the liquid crystal side. A third connection line 75 that electrically connects the drive circuit unit 70 and the FPC 77 is formed on the surface of the protrusion P on the liquid crystal side. Further, the surface of the array-side substrate 51 on the liquid crystal side overlaps with another part GB2 extending from one end of the part GB1 on the drive circuit part 70 side of the frame part 61 in a direction substantially orthogonal to the longitudinal direction of the part GB1. In addition, a gate signal line selection circuit 71 is formed. The pixel portion 54 includes a TFT 52 and a pixel electrode 53. The pixel electrode 53 has a liquid crystal capacitor (Clc) and a storage capacitor (Cs), which are connected to a common electrode (indicated by Vcom in FIG. 8). Are connected.

  The gate signal line selection circuit 71 and the image signal line selection circuit 72 are formed by a thin film forming method such as a CVD (Chemical Vapor Deposition) method. In this case, the TFT 52 has a channel made of, for example, low-temperature polycrystalline silicon (LTPS). When an n-channel TFT and a p-channel TFT are formed using this LTPS, a CMOS circuit is used as a basis. The driving circuit, the SRAM circuit, the D / A converter, the image display unit and the like can be integrated on the glass substrate.

  Conventionally, the LCD may have a capacitance detection type touch panel. FIG. 9 is a plan view of the conventional LCD mainly showing the configuration of the capacitance detection electrode line of the touch panel, and FIG. 10 is a plan view of FIG. It is a fragmentary sectional view of LCD. As shown in these drawings, an LCD with a capacitance detection type touch panel includes a first capacitance detection electrode line 107 formed on the surface of the color filter side substrate 102 on the liquid crystal 111 side, and the color filter side substrate 102. The second capacitance detection electrode line 109 is formed on the surface opposite to the surface on the liquid crystal 111 side. A plurality of gate signal lines 121 and a plurality of image signal lines (source signal lines) 122 are formed on the surface of the array side substrate 101 on the liquid crystal 111 side. A semiconductor integrated circuit element 104 (corresponding to the drive circuit unit 70 in FIG. 5) made of IC, LSI, or the like for driving and controlling the image signal lines 122 is provided at one end of the surface on the liquid crystal 111 side of the array side substrate 101. It is mounted by the COG (Chip On Glass) method or the like. In addition, a first FPC 106 (corresponding to FPC 77 in FIG. 8) is provided on one end of the surface on the liquid crystal 111 side of the array-side substrate 101 more than the semiconductor integrated circuit element 104. A second FPC 110 is provided at an end adjacent to the one end of the surface of the color filter substrate 102 opposite to the liquid crystal 111 side, and the second FPC 110 is connected to the second capacitance detection electrode line 109. The detection signal output from is output to an external detection circuit or the like. The first capacitance detection electrode line 107 is a first capacitance that is extended outward from the image signal line 122 at one end portion facing the semiconductor integrated circuit element 104 on the surface of the color filter side substrate 102 on the liquid crystal 111 side. The end portion of the detection electrode line 107 is electrically connected to the connection electrode 150 and the extraction wiring 107L formed on the surface of the array side substrate 101 on the liquid crystal 111 side through the sealing portion 103 containing conductive particles. . The lead wiring 107L is patterned so as to be routed toward the first FPC 106, and the end of the lead wiring 107L on the first FPC 106 side is connected to the connection terminal of the first FPC 106 by anisotropic conduction. It is electrically connected via a film (Anisotropic Conductive Film: ACF). The first FPC 106 has a scan pulse input signal line for inputting a scan pulse to the first capacitance detection electrode line 107.

Further, as shown in FIG. 10, on the surface opposite to the surface on the liquid crystal 111 side of the color filter side substrate 102 (upper surface in FIG. 10), the second polarizing plate 113 is placed on the second capacitance detection electrode line 109. Is provided. Further, a first polarizing plate 112 is provided on the surface of the array side substrate 101 opposite to the surface on the liquid crystal 111 side (the lower surface in FIG. 10). On the other hand, on the surface of the array side substrate 101 on the liquid crystal 111 side, a gate signal line 121, a gate insulating film 131, an image signal line 122, a planarizing film 132 made of acrylic resin, a common electrode 133, silicon nitride (SiN _x ) , An interlayer insulating film 134 made of silicon oxide (SiO ₂ ) or the like and a pixel electrode 123 are sequentially formed. Further, a color filter 135 and a light blocking portion 136 such as a black matrix are formed on the surface of the color filter side substrate 102 on the liquid crystal 111 side.

  A first capacitance detection electrode line 107 is formed on the surface of the color filter side substrate 102 on the liquid crystal 111 side, and a second capacitance detection electrode line is formed on the display side surface (the surface opposite to the surface on the liquid crystal 111 side). 109 is formed. These capacitance detection electrode lines 107 and 109 constitute a projected capacitive touch panel. The plurality of first capacitance detection electrode lines 107 are formed so as to extend in the Y direction (for example, the column direction), respectively, and the plurality of second capacitance detection electrode lines 109 are respectively configured in the X direction (for example, the row direction). ). The plurality of first capacitance detection electrode lines 107 are drive lines (in which scanning pulses for detecting a change in capacitance when an electrostatic conductor such as a human finger approaches or comes into contact are sequentially input ( It functions as a drive line. The plurality of second capacitance detection electrode lines 109 function as detection lines (sensor lines) and reception lines for detecting changes in capacitance. The second capacitance detection electrode line 109 is made of ITO, indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), zinc oxide (ZnO), silicon (Si) containing phosphorus or boron, or the like. The conductive material is formed using a light-transmitting material. The first capacitance detection electrode line 107 may be a detection line (sensor line), and the second capacitance detection electrode line 109 may be a drive line (drive line).

  Furthermore, as another conventional example, an LCD having a plurality of sense lines wired in parallel at a predetermined ratio to signal lines for a plurality of columns has been proposed (see, for example, Patent Document 1).

JP 2001-42296 A

  However, in the above conventional LCD with a touch panel shown in FIGS. 5 to 10, the first capacitance detection electrode line 107 and the image signal line 122 are formed in different parts, so that the number of wirings is large. The wiring structure was complicated. As a result, it tends to be difficult to cope with high-speed driving and to reduce power consumption.

  In addition, since the LCD disclosed in Patent Document 1 forms a sense line adjacent to a signal line (image signal line), the sense line enters the pixel portion, and the aperture ratio of the pixel portion is high. There was a problem that it decreased.

  The present invention has been completed in view of the above-described problems, and an object thereof is to simplify the wiring structure by reducing the number of capacitance detection electrode lines and image signal lines. Another object is to provide an LCD that can keep the aperture ratio of all the pixel portions high.

  The liquid crystal display device with a touch panel according to the present invention includes a plurality of gate signal lines formed in a predetermined direction on a surface of the substrate on the liquid crystal side, and a plurality of image signal lines formed to intersect the gate signal lines. A thin film transistor and a unit pixel electrode respectively disposed corresponding to each intersection of the gate signal line and the image signal line, a capacitance detection electrode line disposed in parallel with the image signal line, and an image signal line drive The capacitance detection electrode line is arranged between the unit pixel electrodes where the image signal line is not arranged.

In the liquid crystal display device with a touch panel according to the present invention, preferably, the image signal line is disposed between the first unit pixel electrode and the second unit pixel electrode arranged in the predetermined direction, and the image signal line is disposed on the image signal line. And the first unit pixel electrode and the second unit pixel electrode constitute one unit.
Further, a plurality of the units constitute a group in the predetermined direction,
The capacitance detection electrode line is arranged between the units in which the image signal line is not arranged in the group.

  In the liquid crystal display device with a touch panel according to the present invention, it is preferable that the image signal line driving circuit includes each of the first unit pixel electrode, the second unit pixel electrode, and the capacitance detection electrode line constituting the group. The signal is supplied in time division.

  In the liquid crystal display device with a touch panel according to the present invention, it is preferable that a time width of a signal supplied to the capacitance detection electrode line is a time width of a signal supplied to the first unit pixel electrode and the second unit pixel. It is shorter than any of the time widths of signals supplied to the electrodes.

  In the liquid crystal display device with a touch panel according to the present invention, preferably, the image signal line driving circuit includes the first unit pixel electrode, the second unit pixel electrode, and the capacitance detection electrode line constituting the group. A signal is supplied to the capacitance detection electrode line first or last.

  In the liquid crystal display device with a touch panel according to the present invention, preferably, the image signal line driving circuit includes the first unit pixel electrode, the second unit pixel electrode, and the capacitance detection electrode line constituting the group. When a signal is first supplied to the capacitance detection electrode line, a signal is supplied to the capacitance detection electrode line before the first unit pixel electrode and the second unit pixel electrode are turned on.

In the liquid crystal display device with a touch panel of the present invention, preferably, the first unit pixel electrode, the second unit pixel electrode, and the third unit pixel electrode are arranged in the predetermined direction.
The image signal line is arranged between the first unit pixel electrode and the second unit pixel electrode or between the second unit pixel electrode and the third unit pixel electrode and these Thereby, the first unit pixel electrode, the second unit pixel electrode, and the third unit pixel electrode constitute one group,
The capacitance detection electrode lines are arranged between the groups where the image signal lines are not arranged.

  The liquid crystal display device with a touch panel according to the present invention includes a plurality of gate signal lines formed in a predetermined direction on a surface of the substrate on the liquid crystal side, and a plurality of image signal lines formed to intersect the gate signal lines. A thin film transistor and a unit pixel electrode, a capacitance detection electrode line formed in parallel with the image signal line, and an image signal line drive, respectively, corresponding to each intersection of the gate signal line and the image signal line. A capacitance detection electrode line, wherein the capacitance detection electrode line is arranged between the unit pixel electrodes where the image signal line is not arranged. This reduces the number of wires and simplifies the wiring structure. Further, since the capacitance detection electrode line is disposed between the unit pixel electrodes where the image signal line is not disposed, the capacitance detection electrode line can be prevented from entering the unit pixel electrode side. As a result, the aperture ratios of all the pixel portions can be kept high.

In the liquid crystal display device with a touch panel according to the present invention, preferably, the image signal line is disposed between the first unit pixel electrode and the second unit pixel electrode arranged in the predetermined direction, and the image signal line is disposed on the image signal line. And the first unit pixel electrode and the second unit pixel electrode constitute one unit.
Further, a plurality of the units constitute a group in the predetermined direction,
Since the capacitance detection electrode line is arranged between the units in which the image signal line is not arranged in the group, the number of image signal lines is reduced, and the wiring structure is further simplified.

  In the liquid crystal display device with a touch panel according to the present invention, it is preferable that the image signal line driving circuit includes each of the first unit pixel electrode, the second unit pixel electrode, and the capacitance detection electrode line constituting the group. Since the signal is supplied to the power supply in a time-sharing manner, another drive circuit dedicated to the capacitance detection electrode line becomes unnecessary. As a result, the wiring structure is further simplified. In addition, since the capacitance detection electrode line is supplied with a signal from the image signal line drive circuit without being supplied with a signal from another drive circuit dedicated to the capacitance detection electrode line, there is no need to switch a plurality of drive circuits. As a result, high-speed driving is realized and power consumption is reduced.

  In the liquid crystal display device with a touch panel according to the present invention, it is preferable that the time width of the signal supplied to the capacitance detection electrode line is the time width of the signal supplied to the first unit pixel electrode and the second unit. Since the time width of the signal supplied to the pixel electrode is shorter than any of the time widths, higher speed driving is realized and power consumption is further reduced.

  In the liquid crystal display device with a touch panel according to the present invention, preferably, the image signal line driving circuit includes the first unit pixel electrode, the second unit pixel electrode, and the capacitance detection electrode line constituting the group. Since the signal is supplied to the capacitance detection electrode line first or last, the signal supplied to the capacitance detection electrode line is supplied to the signal supplied to the first unit pixel electrode and the second unit pixel electrode. It is possible to suppress the noise from entering the signal.

  In the liquid crystal display device with a touch panel according to the present invention, preferably, the image signal line driving circuit includes the first unit pixel electrode, the second unit pixel electrode, and the capacitance detection electrode line constituting the group. When a signal is first supplied to the capacitance detection electrode line, a signal is supplied to the capacitance detection electrode line before the first unit pixel electrode and the second unit pixel electrode are turned on. It is possible to more reliably suppress the signal supplied to the electrode line from entering the signal supplied to the first unit pixel electrode and the signal supplied to the second unit pixel electrode as noise.

In the liquid crystal display device with a touch panel of the present invention, preferably, the first unit pixel electrode, the second unit pixel electrode, and the third unit pixel electrode are arranged in the predetermined direction.
The image signal line is arranged between the first unit pixel electrode and the second unit pixel electrode or between the second unit pixel electrode and the third unit pixel electrode and these Thereby, the first unit pixel electrode, the second unit pixel electrode, and the third unit pixel electrode constitute one group,
Since the capacitance detection electrode lines are arranged between the groups where the image signal lines are not arranged, the number of image signal lines and capacitance detection electrode lines is further reduced, and the wiring structure is further simplified. The

FIG. 1 is a diagram showing an example of an embodiment of a liquid crystal display device with a touch panel according to the present invention, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. FIGS. 2A and 2B are diagrams showing an example of the embodiment of the liquid crystal display device with a touch panel in FIG. 1, respectively, which are supplied to the unit pixel portion and the capacitance detection electrode line constituting the group. It is a timing chart of a signal. FIG. 3 is a diagram showing another example of the embodiment of the liquid crystal display device with a touch panel of the present invention, and is a plan view of the liquid crystal display device with a touch panel mainly showing capacitance detection electrode lines. FIG. 4 is a partial cross-sectional view of the liquid crystal display device with a touch panel of FIG. FIG. 5 is a diagram showing an example of a conventional liquid crystal display device, and is a block circuit diagram of the liquid crystal display device. FIG. 6 is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit in the liquid crystal display device of FIG. FIG. 7 is a timing chart of signals supplied to the unit pixel portions constituting the group in the liquid crystal display device of FIG. FIG. 8 is a plan view of the entire configuration including the frame portion of the liquid crystal display device of FIG. FIG. 9 is a plan view of a liquid crystal display device with a touch panel mainly showing capacitance detection electrode lines in the liquid crystal display device of FIG. FIG. 10 is a partial cross-sectional view of the liquid crystal display device of FIG. FIG. 11 is a diagram showing another example of the embodiment of the liquid crystal display device with a touch panel according to the present invention, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. FIG. 12 is a timing chart of signals supplied to the unit pixel units constituting the group in the liquid crystal display device of FIG. FIG. 13 is a diagram showing another example of the embodiment of the liquid crystal display device with a touch panel according to the present invention, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. FIG. 14 is a diagram showing another example of the embodiment of the liquid crystal display device with a touch panel according to the present invention, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. FIG. 15 is a diagram showing another example of the embodiment of the liquid crystal display device with a touch panel according to the present invention, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. FIG. 16 is a diagram showing another example of the embodiment of the liquid crystal display device with a touch panel according to the present invention, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit.

  Hereinafter, embodiments of an LCD with a touch panel according to the present invention will be described with reference to the drawings. However, each drawing referred to below shows a main part for explaining the LCD with a touch panel of the present invention among the constituent members in the embodiment of the LCD with a touch panel of the present invention. Therefore, the LCD with a touch panel of the present invention may include well-known components such as a circuit board, a wiring conductor, a control IC, and an LSI that are not shown in the drawing.

  FIG. 1 is a diagram showing an example of an embodiment of an LCD with a touch panel according to the present invention, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. As shown in FIG. 1, the LCD with a touch panel according to the present invention includes a plurality of gate signal lines GL1, formed in a predetermined direction (for example, a row direction) on a liquid crystal side surface of an array side substrate made of a glass substrate or the like. A plurality of image signal lines (source signal lines) SL1, SL2, SL3, SL4, which are formed to intersect with GL2, GL3, and gate signal lines GL1, GL2, GL3, and gate signal lines GL1, GL2, TFTs and unit pixel electrodes R11, G11, B11 to G23, and image signal lines SL1, SL2, SL3, which are arranged corresponding to the intersections of GL3 to GL and image signal lines SL1, SL2, SL3, SL4, respectively. A touch panel-equipped LCD having capacitance detection electrode lines CDL1, CDL2˜ formed parallel to SL4˜ and an image signal line drive circuit 4, wherein the capacitance detection electrode lines CDL1, CDL2˜ are image signal lines SL1, SL2, SL3, SL4˜ are arranged between the first unit pixel electrode 23a and the second unit pixel electrode 23b where no arrangement is made. It is the composition which is. With this configuration, the number of wirings of the capacitance detection electrode lines CDL1, CDL2 is reduced, and the wiring structure is simplified. Further, the capacitance detection electrode lines CDL1, CDL2˜ are prevented from entering the first unit pixel electrode 23a side and the second unit pixel electrode 23b side. As a result, the aperture ratios of all the pixel portions PR11, PG11, and PB11 can be kept high.

  Further, in the LCD with a touch panel of the present invention, as shown in FIG. 1, the image signal lines SL1, SL2, SL3, and SL4 are preferably arranged so that the first unit pixel electrode 23a and the second unit lined in the predetermined direction. The first unit pixel electrode 23a and the second unit pixel electrode 23b constitute one unit by being disposed between and connected to the pixel electrode 23b. A plurality form a group in the predetermined direction, and the capacitance detection electrode lines CDL1, CDL2˜ are arranged between the units in which the image signal lines SL1, SL2, SL3, SL4˜ are not arranged in the group. . That is, the image signal lines SL1, SL2, SL3, and SL4 are provided with a first unit pixel electrode 23a that is turned on by two adjacent gate signal lines (for example, GL1 and GL2) on one of the left and right sides. It is arranged and connected to the first unit pixel electrode 23a, and is turned on by one of the two gate signal lines (GL1, GL2) (for example, GL1) on the other side of the left and right. A second unit pixel electrode 23b is disposed and connected to the second unit pixel electrode 23b. In this case, the number of wirings of the image signal lines SL1, SL2, SL3, SL4 is reduced, and the wiring structure is further simplified. In FIG. 1, reference numeral 5 denotes a connection portion between the image signal line SL1 and the first unit pixel electrode 23a and the second unit pixel electrode 23b, but the connection portion 5 is connected to the first unit pixel electrode 23a and the first unit pixel electrode 23a. There may be two unit pixel electrodes 23b.

  The plurality of unit pixel electrodes constituting one group are preferably 4 to 12 unit pixel electrodes. In this case, the wiring structure is simplified, and sufficient power for holding one frame of display on each unit pixel electrode can be supplied by time-division driving. That is, when the number of unit pixel electrodes constituting the group is 13 or more, the pulse width (time width) of the image signal input to each unit pixel electrode in a time-sharing manner is reduced, and 1 unit of display is displayed on each unit pixel electrode. It tends to be difficult to supply sufficient power to hold the frame by time division driving.

  In the LCD with a touch panel of the present invention, as shown in FIG. 2, the image signal line driving circuit 4 includes a first unit pixel electrode 23a, a second unit pixel electrode 23b, a capacitance detection electrode line CDL1, It is preferable to supply the signals to each of CDL2 in a time division manner. In this case, the capacitance detection electrode lines CDL1, CDL2 to other dedicated drive circuits are not required. As a result, the wiring structure is further simplified. Further, since the capacitance detection electrode lines CDL1, CDL2˜ are supplied with signals from the image signal line drive circuit 4 without being supplied with signals from other dedicated drive circuits, there is no need to switch between the plurality of drive circuits. . As a result, high-speed driving is realized and power consumption is reduced.

  The configuration of the LCD with a touch panel of the present invention will be described in detail below. The image signal line drive circuit 4 is composed of an IC, LSI, or the like mounted by the COG method or the like, and drives the image signal line selection circuit 20. The image signal line drive circuit 4 may be a drive circuit that also drives a gate signal line selection circuit (not shown). The gate signal line selection circuit sequentially inputs gate signals to the gate signal lines GL1, GL2, and GL3. The connection line 4L electrically connects the signal input terminals S1 and S2 of the image signal line drive circuit 4 to the image signal lines SL1, SL2, SL3, and SL4 and the capacitance detection electrode lines CDL1 and CDL2 to. Then, the image signal and the drive signals for the capacitance detection electrode lines CDL1, CDL2˜ are transmitted to the image signal line selection circuit 20.

  The gate signal line selection circuit and the image signal line selection circuit 20 are formed by a thin film forming method such as a CVD method. In this case, the TFT preferably has a channel composed of LTPS. When an n-channel TFT and a p-channel TFT are formed using this LTPS, a driving circuit based on a CMOS circuit, an SRAM circuit, a D / A conversion, and the like. A device, an image display unit, and the like can be integrated on a glass substrate.

  Preferably, the unit pixel electrodes R11, G11, B11 to G23 form a group in a predetermined direction (direction in which the gate signal lines GL1, GL2, GL3 extend) with 2n (n being an integer of 2 or more). doing. In the configuration shown in FIG. 1, four unit pixel electrodes R11, G11, and B11 to G23 form one group. That is, this is a suitable configuration for performing full color display, and the four unit pixel electrodes (for example, R11, G11, B11, R12) constituting the group are unit pixel electrodes for red display (for example, R11, R12), a unit pixel electrode for green display (for example, G11), and a unit pixel electrode for blue display (for example, B11). Each group includes one or more and n−1 or less capacitance detection electrode lines CDL1, CDL2˜. Each group includes a group of unit pixel electrodes R11, G11, B11, R12 and a capacitance detection electrode line CDL1, a group of unit pixel electrodes G12, B12, R13, G13 and a group of capacitance detection electrode line CDL2, and a unit pixel electrode R21, G21, B21. , R22 and a capacitance detection electrode line CDL1, a group of unit pixel electrodes G22, B22, R23, G23 and a capacitance detection electrode line CDL2.

  Preferably, the image signal line driving circuit 4 supplies signals to the first unit pixel electrode 23a, the second unit pixel electrode 23b, and the capacitance detection electrode lines CDL1 and CDL2 to form a group in a time division manner. . For example, for the group of unit pixel electrodes R11, G11, B11, R12 and the capacitance detection electrode line CDL1, an image from the image signal line driving circuit 4 is transferred to each of the unit pixel electrodes R11, G11, B11, R12 and the capacitance detection electrode line CDL1. The signals SigR1, SigB1, SigG1, SigR2 and the drive signal SigCD1 are supplied in a time division manner. With this configuration, even if the number of the first unit pixel electrodes 23a and the second unit pixel electrodes 23b is increased in one group, at least one capacitance detection electrode line CDL is sufficient. As a result, the number of wirings of the capacitance detection electrode lines CDL1, CDL2 is reduced, and the wiring structure is further simplified. In addition, the first unit pixel electrode 23a, the second unit pixel electrode 23b, and the capacitance detection electrode lines CDL1, CDL2˜ constituting the group are supplied with signals from the image signal line driving circuit 4 shared by them. In addition, the capacitance detection electrode lines CDL1, CDL2 to other dedicated drive circuits are not necessary. As a result, the wiring structure is further simplified.

  MUX1, XMUX1, MUX2, XMUX2, MUX3, and XMUX3 are time-division signal input lines for time-division driving the unit pixel electrodes R11, G11, B11 to G23 and the capacitance detection electrode lines CDL1 and CDL2. MUX1 is connected to the gate electrode of the n-type MOS transistor of the CMOS transfer gate elements 20a and 20d, and XMUX1 (inverted signal line of MUX1) is connected to the gate electrode of the p-type MOS transistor of the CMOS transfer gate elements 20a and 20d. Yes. MUX2 is connected to the gate electrode of the n-type MOS transistor of the CMOS transfer gate elements 20c and 20f, and XMUX2 (inverted signal line of MUX2) is connected to the gate electrode of the p-type MOS transistor of the CMOS transfer gate elements 20c and 20f. Yes. MUX3 is connected to the gate electrode of the n-type MOS transistor of the CMOS transfer gate elements 20b and 20e, and XMUX3 (inverted signal line of MUX3) is connected to the gate electrode of the p-type MOS transistor of the CMOS transfer gate elements 20b and 20e. Yes.

  As shown in the timing chart of FIG. 2, the gate signal lines GL1 and GL2 are in an on state, that is, the first unit pixel electrode 23a is in an on state, an H signal is input to MUX1, and an L signal is input to XMUX1. When the signal is input and the H signal is input to MUX2 and the L signal is input to XMUX2, the image signals SigR1 and SigB1 sequentially input from the image signal input terminal S1 are the image signal lines SL1, SL2 is transmitted and sequentially input to the unit pixel electrodes R11 and B11. At this time, the CMOS transfer gate elements 20a and 20c are on. Next, the gate signal line GL1 is turned on and the gate signal line GL2 is turned off, that is, the second unit pixel electrode 23b is turned on, and an H signal is input to MUX1 and an L signal is input to XMUX1. When the H signal is input to MUX2 and the L signal is input to XMUX2, the image signals SigG1 and SigR2 sequentially input from the image signal input terminal S1 transmit the image signal lines SL1 and SL2. Then, it is sequentially input to the unit pixel electrodes G11 and R12. At this time, the CMOS transfer gate elements 20a and 20c are on. Thereby, the unit pixel electrodes R11, B11, G11, R12 are sequentially driven in a time division manner. As shown in FIG. 2, for one group, the unit pixel electrodes R11, B11, G11, and R12 are sequentially driven in a time division manner, and the drive signal SigCD1 is input to the capacitance detection electrode line CDL1 in a time division manner. The drive signal SigCD1 is supplied to the capacitance detection electrode line CDL1 when an H signal is input to MUX3 and an L signal is input to XMUX3.

  Next, for the group of unit pixel electrodes G12, B12, R13, G13 and the capacitance detection electrode line CDL2, by controlling on / off of the gate signal lines GL1, GL2 in the same manner as above, the unit pixels constituting the group The electrodes G12, B12, R13, G13 and the capacitance detection electrode line CDL2 are time-division driven. That is, the gate signal lines GL1 and GL2 are on, the first unit pixel electrode 23a is on, an H signal is input to MUX1, an L signal is input to XMUX1, and an H signal is input to MUX2. And an L signal is input to XMUX2, the image signals SigG2 and SigR3 sequentially input from the image signal input terminal S2 are transmitted through the image signal lines SL3 and SL4, and the unit pixel electrode G12 , R13 sequentially. At this time, the CMOS transfer gate elements 20d and 20f are on. Next, the gate signal line GL1 is turned on and the gate signal line GL2 is turned off, that is, the second unit pixel electrode 23b is turned on, and an H signal is input to MUX1 and an L signal is input to XMUX1. When the H signal is input to MUX2 and the L signal is input to XMUX2, the image signals SigB2 and SigG3 sequentially input from the image signal input terminal S2 transmit the image signal lines SL3 and SL4. Then, it is sequentially input to the unit pixel electrodes B12 and G13. At this time, the CMOS transfer gate elements 20d and 20f are on. The drive signal SigCD2 is supplied to the capacitance detection electrode line CDL2 when an H signal is input to MUX3 and an L signal is input to XMUX3. By repeating this time division driving in the direction in which the gate signal lines GL1 and GL2 extend, all the unit pixel electrodes arranged between the gate signal line GL1 and the gate signal line GL2 are time division driven.

  Next, with respect to the group of unit pixel electrodes R21, G21, B21, R22 and the capacitance detection electrode line CDL1, by controlling on / off of the gate signal lines GL2, GL3 in the same manner as described above, the unit pixels constituting the group The electrodes R21, G21, B21, R22 and the capacitance detection electrode line CDL1 are time-division driven. Next, with respect to the group of unit pixel electrodes G22, B22, R23, G23 and the capacitance detection electrode line CDL2, by controlling on / off of the gate signal lines GL2, GL3 in the same manner as above, the unit pixels constituting the group The electrodes G22, B22, R23, G23 and the capacitance detection electrode line CDL2 are time-division driven. By repeating this time division driving in the direction in which the gate signal lines GL2 and GL3 extend, all the unit pixel electrodes arranged between the gate signal line GL2 and the gate signal line GL3 are time division driven.

  Then, by sequentially executing the above time-division driving for all the gate signal lines, an image of one frame is displayed.

  In the LCD with a touch panel according to the present invention, it is preferable that the first unit pixel electrode 23a and the second unit pixel electrode 23b have a group of 2n (n is an integer of 2 or more) in a predetermined direction. In addition, each group includes one or more and n−1 or less capacitance detection electrode lines CDL1, CDL2˜, and the image signal line driving circuit 4 includes first unit pixel electrodes 23a constituting the group. In this configuration, signals are supplied to each of the second unit pixel electrode 23b and the capacitance detection electrode lines CDL1, CDL2 in a time division manner. With this configuration, the capacitance detection electrode lines CDL1, CDL2˜ are supplied with a signal from the image signal line drive circuit 4 without being supplied with a signal from another drive circuit dedicated thereto, so it is necessary to switch between the plurality of drive circuits. There is no. As a result, high-speed driving is realized and power consumption is reduced. In each group, at least one capacitance detection electrode line CDL1, CDL2 is sufficient. Therefore, the larger the number of first unit pixel electrodes 23a and second unit pixel electrodes 23b in the group, the capacitance detection electrode line CDL1. Therefore, the number of wires of CDL2 can be reduced.

  In the LCD with a touch panel of the present invention, the time width (pulse width) of the drive signal supplied to the capacitance detection electrode lines CDL1, CDL2˜ is the time width of the pixel electrode drive signal supplied to the first unit pixel electrode 23a. It is preferably shorter than any of the time widths of the pixel electrode drive signal supplied to the second unit pixel electrode 23b. Higher speed driving is realized and power consumption is further reduced. The time width of the pixel electrode drive signal supplied to the first unit pixel electrode 23a and the time width of the pixel electrode drive signal supplied to the second unit pixel electrode 23b hold one frame of image display on the unit pixel electrode. Therefore, since it is necessary to supply sufficient power (charge) by time-division driving, it is set to about 2 μsec (μsec) to 5 μsec. On the other hand, the drive signals supplied to the capacitance detection electrode lines CDL1, CDL2˜ are not restricted like the pixel electrode drive signals, and can be preferably about 2 μsec to 3 μsec seconds. If it is less than 2 μsec, the sensitivity of electrostatic capacitance detection tends to decrease. If it exceeds 3 μsec, high-speed driving tends to be difficult, and power consumption tends to increase.

  Further, as shown in FIG. 2, the image signal line driving circuit 4 includes capacitance detection electrodes in the first unit pixel electrode 23a, the second unit pixel electrode 23b, and the capacitance detection electrode lines CDL1, CDL2˜ constituting the group. It is preferable to supply the drive signals SigCD1, CD2 to the lines CDL1, CDL2 to the beginning or the end. In this case, the drive signals SigCD1, CD2 to be supplied to the capacitance detection electrode lines CDL1, CDL2 to the pixel electrode drive signals SigR1, B1 etc. to be supplied to the first unit pixel electrode 23a and the second unit pixel electrode 23b. Can be prevented from entering the pixel electrode drive signals SigG1, R2 and the like supplied to.

  Further, as shown in FIG. 2A, the image signal line driving circuit 4 includes the first unit pixel electrode 23a, the second unit pixel electrode 23b, and the capacitance detection electrode lines CDL1, CDL2˜ constituting the group. When a drive signal is first supplied to the capacitance detection electrode lines CDL1, CDL2˜, the drive signal is supplied to the capacitance detection electrode lines CDL1, CDL2˜ before the first unit pixel electrode 23a and the second unit pixel electrode 23b are turned on. It is preferable to supply SigCD1, CD2˜. In this case, the drive signals SigCD1, CD2 to be supplied to the capacitance detection electrode lines CDL1, CDL2 to the pixel electrode drive signals SigR1, B1 etc. to be supplied to the first unit pixel electrode 23a and the second unit pixel electrode 23b. Intrusion into the pixel electrode drive signals SigG1, R2 and the like supplied to is more reliably suppressed. For the same reason, the image signal line drive circuit 4 includes the capacitance detection electrode line CDL1 among the first unit pixel electrode 23a, the second unit pixel electrode 23b, and the capacitance detection electrode lines CDL1, CDL2˜ constituting the group. , When driving signals are finally supplied to CDL2˜, the drive signals SigCD1, CD2˜ are applied to the capacitance detection electrode lines CDL1, CDL2˜ after the first unit pixel electrode 23a and the second unit pixel electrode 23b are turned off. It is preferable to supply.

  The touch panel in the LCD with a touch panel of the present invention will be described below. As shown in FIGS. 3 and 4, the LCD with a touch panel according to the present invention has the first capacitance detection electrode line 7 formed on the surface of the liquid crystal display panel 1 of the array side substrate 1 of the liquid crystal display panel. A second capacitance detection electrode line 9 is formed on the display side surface of the substrate 2 (surface opposite to the surface on the liquid crystal 11 side). These capacitance detection electrode lines 7 and 9 constitute a projected capacitive touch panel. As shown in FIG. 3, the plurality of first capacitance detection electrode lines 7 are formed in a linear shape so as to extend in the Y direction (for example, the column direction), and the plurality of second capacitance detection electrode lines 9. Are linearly formed so as to extend in the X direction (for example, the row direction). The plurality of first capacitance detection electrode lines 7 are drive lines (in which scan pulses for detecting a change in capacitance when an electrostatic conductor such as a human finger approaches or comes into contact are sequentially input ( It functions as a drive line. The plurality of second capacitance detection electrode lines 9 function as detection lines (sensor lines) and reception lines for detecting changes in capacitance. The detection signal detected by the second capacitance detection electrode line 9 is transmitted to an external detection circuit or the like through the detection signal line of the second FPC 10 or the like. The second capacitance detection electrode line 9 includes indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), zinc oxide (ZnO), phosphorus and boron. It is formed using a conductive material such as silicon (Si) that has a light transmitting property. Although the first capacitance detection electrode line 7 is a drive line (drive line) and the second capacitance detection electrode line 9 is a detection line (sensor line) and a reception line, this relationship may be reversed. In addition, the second capacitance detection electrode line 9 is preferably formed in a line shape or a band shape with a larger area than the first capacitance detection electrode line 7, and in this case, the detection of the second capacitance detection electrode line 9 is performed. The sensitivity is improved, and when static electricity is charged, the static electricity is easily attenuated.

In FIG. 3, reference numeral 3 denotes a sealing portion that joins and seals the peripheral portion of the liquid crystal side surface of the array side substrate 1 and the peripheral portion of the liquid crystal side surface of the color filter side substrate 2. Also, as shown in FIG. 4, the second polarizing plate 13 is placed on the second capacitance detection electrode line 9 on the surface opposite to the surface on the liquid crystal 11 side of the color filter side substrate 2 (upper surface in FIG. 4). Is provided. A first polarizing plate 12 is provided on the surface of the array-side substrate 1 opposite to the surface on the liquid crystal 11 side (the lower surface in FIG. 4). On the other hand, on the surface of the array side substrate 1 on the liquid crystal 11 side, a gate signal line 21, a gate insulating film 31, an image signal line 22, a first capacitance detection electrode line 7, a planarizing film 32 made of acrylic resin, etc. An electrode 33, an interlayer insulating film 34 made of silicon nitride (SiN _x ), silicon oxide (SiO ₂ ), etc., and a pixel electrode 23 are sequentially formed. Further, a color filter 35 and a light shielding portion 36 such as a black matrix are formed on the surface of the color filter side substrate 2 on the liquid crystal 11 side.

  You may form so that the thickness of the 1st capacity | capacitance detection electrode line 7 may become thicker than the thickness of the 2nd capacity | capacitance detection electrode line 9. FIG. In this case, the resistance of the first capacitance detection electrode line 7 is reduced, and the scanning pulse input to the first capacitance detection electrode line 7 becomes smaller as it proceeds in the axial direction of the first capacitance detection electrode line 7. Can be suppressed. Note that the thickness of the first capacitance detection electrode line 7 is about 20 nm to 200 nm, and the thickness of the second capacitance detection electrode line 9 is about 20 nm to 200 nm. The first capacitance detection electrode is within these thickness ranges. It is preferable to form the wire 7 so that the thickness of the wire 7 is larger than the thickness of the second capacitance detection electrode wire 9.

  Further, both ends of the plurality of first capacitance detection electrode lines 7 may be connected in common, and in this case, the position of a detection object such as a human finger having a larger area than the pixel portion is specified two-dimensionally. Making it easier to detect.

  The second capacitance detection electrode line 9 is preferably roughened with irregularities formed on the surface thereof. In this case, the surface area of the second capacitance detection electrode wire 9 is increased, and the capacitance due to the capacitive coupling with the detection target is increased, so that the detection sensitivity is further improved.

  The width of the second capacitance detection electrode line 9 is preferably 5 times or more the width of the first capacitance detection electrode line 7. In this case, the effect of improving the detection sensitivity of the detection object is enhanced. More preferably, the width of the second capacitance detection electrode line 9 is not less than the pixel portion pitch (about 0.1 mm). In this case, the effect of improving the detection sensitivity when detecting an object to be detected such as a human finger is further increased. In addition, the influence of static electricity on the pixel portion can be suppressed by the second capacitance detection electrode line 9, and the effect of easily charging the static electricity to the second capacitance detection electrode line 9 having a large area to be attenuated is enhanced. More preferably, the width of the second capacitance detection electrode line 9 is preferably not less than the pixel portion pitch and not more than about 20 times the pixel portion pitch, and if the width exceeds about 20 times the pixel portion pitch (about 2 mm), The parasitic capacitance between the first capacitance detection electrode line 7 and the second capacitance detection electrode line 9 tends to increase, which adversely affects the detection sensitivity.

  The first capacitance detection electrode line 7 may be formed of the same transparent electrode line as the second capacitance detection electrode line 9, but the first capacitance detection electrode line 7 is preferably a metal wire. . In this case, the resistance of the first capacitance detection electrode line 7 can be reduced to further suppress the rounding of the pulse shape of the scanning pulse, that is, unnecessary collapse of the pulse shape. As a result, the detection sensitivity of the detection target can be made uniform over the entire capacitance detection region. In this case, the first capacitance detection electrode line 7 includes aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), tungsten (W), chromium (Cr), silver (Ag), Conductivity such as metal materials composed of elements selected from copper (Cu), neodymium (Nd), etc., alloy materials based on these elements, or metal nitrides such as titanium nitride, tantalum nitride, molybdenum nitride, etc. It can be formed using the material which has.

  Moreover, it is preferable that the 1st capacity | capacitance detection electrode wire 7 consists of a metal wire and the transparent electrode wire which covers it. In this case, the resistance of the first capacitance detection electrode line 7 is reduced, and the pulse shape is reduced as the scanning pulse proceeds in the axial direction of the first capacitance detection electrode line 7, that is, the pulse shape is unnecessarily broken. Can be suppressed. As a result, the detection sensitivity of the detection target can be made uniform over the entire capacitance detection region. Further, since the metal line is covered with the transparent electrode line, the formation position of the first capacitance detection electrode line 7 is shifted due to the positional shift of the mask used in the photolithography process, and the transparent electrode line is flat on the pixel portion. Even if the light enters slightly, the aperture ratio of the pixel portion can be prevented from being lowered. This transparent electrode line is made of conductive material such as ITO, indium zinc oxide (IZO), indium tin oxide added with silicon oxide (ITSO), zinc oxide (ZnO), silicon containing phosphorus and boron (Si), etc. It can be formed using a light-transmitting material and a light-transmitting material.

  Further, it is preferable that the entire first capacitance detection electrode line 7 overlaps the light shielding part 36 in plan view, and the width thereof is equal to or smaller than the width of the light shielding part 36. In this case, since the first capacitance detection electrode line 7 is not conspicuous, it is possible to suppress deterioration in display quality.

  Further, when the liquid crystal display panel is an IPS type that forms a lateral electric field applied to the liquid crystal 11 between the pixel electrode 23 and the common electrode, the second capacitance detection electrode line 9 serves as a shield electrode for the pixel electrode 23. Therefore, the configuration of the present invention is suitable for an LCD with a touch panel having an IPS liquid crystal display panel. In other words, it is possible to omit the shielding back ITO provided on the display side surface (surface opposite to the surface on the liquid crystal 11 side) of the color filter side substrate 2 of the IPS liquid crystal display panel. Similarly to the case of the IPS type liquid crystal display panel, when the liquid crystal display panel is of the FFS type that forms an end electric field (fringe electric field) applied to the liquid crystal between the pixel electrode 23 and the common electrode. However, the configuration of the present invention is suitable.

  The first capacitance detection electrode line 7 is supplied with a drive signal from the image signal line drive circuit 4 through the connection line 4, the oblique wiring portion 4 </ b> LN, and the image signal line selection circuit 20. The second capacitance detection electrode line 9 is connected to the second FPC 10 via the ACF at one end (the left end in FIG. 3) of the color filter side substrate 2 opposite to the liquid crystal 11 side. It is electrically connected to the terminal.

  Furthermore, the LCD with a touch panel of the present invention includes various suitable examples as shown below. FIG. 11 is a diagram showing an example, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. The first unit pixel electrode 212a, the second unit pixel electrode 212b, and the third unit pixel electrode 212c are arranged in the predetermined direction, and the image signal lines SL1, SL2˜ are connected to the first unit pixel electrode 212a. The first unit pixel electrode is disposed between and connected to the second unit pixel electrode 212b or between the second unit pixel electrode 212b and the third unit pixel electrode 212c. 212a, the second unit pixel electrode 212b, and the third unit pixel electrode 212c constitute one group, and the capacitance detection electrode lines CDL1˜ are between the groups where the image signal lines SL1, SL2˜ are not arranged. Has been placed. With this configuration, the number of wirings of the image signal lines SL1, SL2˜ and the capacitance detection electrode lines CDL1˜ is further reduced, and the wiring structure is further simplified. Also, the number of time division signal input lines is reduced.

  The first unit pixel electrode 212a, the second unit pixel electrode 212b, and the third unit pixel electrode 212c constituting one group are turned on by three gate signal lines GL1, GL2, and GL3. The first unit pixel electrode 212a is turned on by the gate signal line GL1 and the TFT 211a connected thereto, and the gate signal line GL2 and the TFT 211b connected thereto. The second unit pixel electrode 212b is turned on by the gate signal line GL1 and the TFT 211c connected thereto. The third unit pixel electrode 212c is turned on by the gate signal line GL1 and the TFT 211d connected thereto, and the gate signal line GL3 and the TFT 211e connected thereto. The source electrode portion of the TFT 211b that transmits the image signal to the first unit pixel electrode 212a and the source electrode portion of the TFT 211c that transmits the image signal to the second unit pixel electrode 212b are connected to the image signal line SL1 at the connection portion 210a. It is connected to the. The source electrode portion of the TFT 211d that transmits the image signal to the third unit pixel electrode 212c is connected to the image signal line SL1 at the connection portion 210b. The other groups also have the same connection structure as described above.

  Then, the image signal line drive circuit 201 outputs a signal to each of the first unit pixel electrode 212a, the second unit pixel electrode 212b, the third unit pixel electrode 212c, and the capacitance detection electrode lines CDL1, CDL2. Are supplied in a time-sharing manner. For example, for the group of unit pixel electrodes R11, G11, B11 and the capacitance detection electrode line CDL1, the image signal line drive circuit 201 sends the image signals SigR1, SigB1 to the unit pixel electrodes R11, G11, B11 and the capacitance detection electrode line CDL1. , SigG1 and drive signal SigCD1 are supplied in a time-sharing manner. With this configuration, even if the number of the first unit pixel electrode 212a, the second unit pixel electrode 212b, and the third unit pixel electrode 212c is increased in one group, at least one capacitance detection electrode line CDL is required. It will be good. As a result, the number of wirings of the capacitance detection electrode lines CDL1, CDL2 is reduced, and the wiring structure is further simplified. In addition, the first unit pixel electrode 212a, the second unit pixel electrode 212b, the third unit pixel electrode 212c, and the capacitance detection electrode lines CDL1 and CDL2 to constitute the group are the image signal line drive circuit 4 shared by them. Since the signals are respectively supplied from the capacitor detection electrode lines CDL1 and CDL2, the other drive circuits dedicated to the capacitance detection electrode lines CDL1 and CDL2 become unnecessary. As a result, the wiring structure is further simplified. The capacitance detection electrode lines CDL1, CDL2˜ receive capacitance detection signals from the image signal input terminals S1, S2 of the image signal line drive circuit 201. In the image signal line drive circuit 201, dedicated capacitance detection signals are provided. Input terminals CD1, CD2˜ may be provided, and capacitance detection signals may be input from the capacitance detection signal input terminals CD1, CD2˜. In this case, a plurality of capacitance detection electrode lines (for example, CDL1, CDL2, CDL3) may be connected in parallel to one capacitance detection signal input terminal (for example, CD1).

  In FIG. 11, the image signal line selection circuit 202 operates as follows. MUX1, XMUX1, MUX2, and XMUX2 are time-division signal input lines for driving the unit pixel electrodes R11, G11, and B11 to the capacitance detection electrode lines CDL1 to time-division. MUX1 is connected to the gate electrodes of the n-type MOS transistors of the CMOS transfer gate elements 204a and 204c, and XMUX1 is connected to the gate electrodes of the p-type MOS transistors of the CMOS transfer gate elements 204a and 204c. MUX2 is connected to the gate electrode of the n-type MOS transistor of the CMOS transfer gate element 204b, and XMUX2 is connected to the gate electrode of the p-type MOS transistor of the CMOS transfer gate element 204b. As a result, a high signal from MUX1 is input to the gate electrodes of the n-type MOS transistors of the CMOS transfer gate elements 204a and 204c, and a low signal from XMUX1 is input to the gate electrodes of the p-type MOS transistors of the CMOS transfer gate elements 204a and 204c. When the signal is input to the image signal SigR1, B1, G1, R2, B2, G2˜ are transmitted on the image signal lines SL1, SL2˜. Similarly, a high signal from MUX2 is input to the gate electrode of the n-type MOS transistor of the CMOS transfer gate element 204b, and a low signal from XMUX2 is input to the gate electrode of the p-type MOS transistor of the CMOS transfer gate element 204b. Sometimes, the capacitance detection signals SigCD1˜ are transmitted on the capacitance detection signal lines CDL1˜. In FIG. 11, reference numeral 203 denotes a connection line that connects the image signal input terminals S1 and S2 of the image signal line drive circuit 201 and the source electrode portions of the CMOS transfer gate elements 204a and 204c. FIG. 11 shows a configuration having the image signal line selection circuit 202, but the image signal line selection circuit 202 may not be provided. When the image signal line selection circuit 202 is not provided, the input of the image signals SigR1, B1, G1, R2, B2, G2˜ can be controlled by turning on / off the gate signal lines GL1, GL2, GL3˜.

  Then, as shown in the timing chart of FIG. 12, the gate signal lines GL1, GL2, and GL3 are turned on at the same timing, the on period of the gate signal line GL1 is the longest, and the on period of the gate signal line GL3 is the next. It is long and the on period of the gate signal line GL2 is the shortest. During the period when only the gate signal line GL1 is on, the image signal SigG1 is input from the CMOS transfer gate element 204a to the second unit pixel electrode 212b (for example, G11). During the period when the gate signal lines GL1 and GL2 are turned on, the image signal SigR1 is input from the CMOS transfer gate element 204a to the first unit pixel electrode 212a (for example, R11). At this time, the gate signal line GL3 may be turned on. During the period when the gate signal lines GL1 and GL3 are turned on, the image signal SigB1 is input from the CMOS transfer gate element 204a to the third unit pixel electrode 212c (for example, B11).

  Further, the gate signal line GL2 functions as a storage capacitor line (CS1) in the on period of the gate signal line GL1 and in the off period of the gate signal line GL2. That is, the storage capacitor (CS) of the first unit pixel electrode 212a (for example, R11), the storage capacitor of the second unit pixel electrode 212b (for example, G11), and the third unit pixel electrode 212c (for example, B11). Are respectively connected to a gate signal line GL2 as a storage capacitor line (CS1). With this configuration, an image signal is input to the first unit pixel electrode 212a (for example, R11), the second unit pixel electrode 212b (for example, G11), and the third unit pixel electrode 212c (for example, B11). The electric charge is held well for one frame. Further, immediately after the gate signal line GL1 is turned off, the capacitance detection signal CD1 is input from the CMOS transfer gate element 204b to the capacitance detection electrode line CDL1. Furthermore, a part of the input period of the capacitance detection signals CD1, CD2 may be set as the blanking period.

  By repeating the above time-division driving to the group of unit pixel electrodes R12, G12, and B12 in the direction in which the gate signal lines GL1, GL2, and GL3 extend, the gate signal line GL1 and the gate signal line GL3 are interposed. All of the arranged unit pixel electrodes are time-division driven.

  Next, with respect to the group of unit pixel electrodes R21, G21, B21 and the capacitance detection electrode line CDL1, by controlling on / off of the gate signal lines GL3, GL4, GL5 in the same manner as described above, the unit pixels constituting the group The electrodes R21, G21, B21 and the capacitance detection electrode line CDL1 are time-division driven. This time-division driving is repeated between the unit pixel electrodes R22, G22, and B22 in the direction in which the gate signal lines GL3, GL4, and GL5 extend to arrange them between the gate signal lines GL3 and GL5. All the unit pixel electrodes thus formed are time-division driven.

  Then, by sequentially executing the above time-division driving for all the gate signal lines, an image of one frame is displayed.

  FIG. 13 is a diagram showing another preferred example of an LCD with a touch panel, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. Common voltage lines (also referred to as common voltage branch lines) VL1 to VL1 are arranged between the unit pixel electrodes on which the image signal lines SL1, SL2, SL3, and SL4 and the capacitance detection electrode lines CDL1, CDL2 are not arranged. With this configuration, the common voltage Vcom can be separately supplied to the common electrode formed as a planar electrode (solid electrode) inside the display portion. As a result, it is possible to suppress occurrence of delay and crosstalk of the common voltage Vcom input inside the display unit far from the common voltage supply end. In this case, the common electrode formed as a planar electrode is divided into a plurality of parts at the common voltage line VL1, and a common voltage is supplied to each part from the common voltage line VL1. The LCD with a touch panel in FIG. 13 is obtained by adding a common voltage line VL1 in the configuration shown in FIG.

  FIG. 14 is a diagram showing another preferred example of an LCD with a touch panel, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. This example is a configuration in which a common voltage line VL1 is formed instead of the capacitance detection electrode line CDL2 in the configuration shown in FIG. In this case, the degree of freedom of arrangement of the common voltage line VL1 is improved.

    FIG. 15 is a diagram showing another preferred example of an LCD with a touch panel, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. This example is a configuration in which common voltage lines VL1 to VL1 are arranged between unit pixel electrodes in which the image signal lines SL1 and SL2 to the capacitance detection electrode lines CDL1 to the configuration shown in FIG.

  FIG. 16 is a diagram showing another preferred example of an LCD with a touch panel, and is a circuit diagram partially showing a unit pixel portion and an image signal line selection circuit. This example is a configuration in which a common voltage line VL1 is formed instead of the capacitance detection electrode line CDL1 in the configuration shown in FIG. In this case, the degree of freedom of arrangement of the common voltage line VL1 is improved.

  In addition, the LCD with a touch panel of the present invention has a display portion having a plurality of unit pixel portions including TFTs and unit pixel electrodes, and the common voltage lines VL1 to VL are preferably arranged in the central portion of the display portion. In this case, the occurrence of the above problem can be further suppressed in the central portion of the display portion farthest from the common voltage supply end (both end portions of the display portion) where the common voltage Vcom input delay and crosstalk are most likely to occur. .

  Moreover, as for LCD with a touchscreen of this invention, it is preferable that the said center part is the range of 1/3-2/3 of the width | variety of the said predetermined direction in a display part. In this case, the occurrence of the above problems can be further suppressed.

  Note that the LCD with a touch panel of the present invention is not limited to the above embodiment, and appropriate design changes and improvements may be made.

  The LCD with a touch panel of the present invention can be applied to various electronic devices. The electronic devices include automobile route guidance system (car navigation system), ship route guidance system, aircraft route guidance system, smartphone terminal, mobile phone, tablet terminal, personal digital assistant (PDA), video camera, digital still camera, electronic Notebook, electronic book, electronic dictionary, personal computer, copier, game device terminal, television, product display tag, price display tag, industrial programmable display, car audio, digital audio player, facsimile, printer, cash There are automatic teller machines (ATMs), vending machines, projector devices, digital display watches, smart watches, and the like.

DESCRIPTION OF SYMBOLS 1 Array side board | substrate 2 Color filter side board | substrate 4 Semiconductor integrated circuit element (image signal line drive circuit)
6 First FPC
7 First capacitance detection electrode line 9 Second capacitance detection electrode line 10 Second FPC
11 Liquid crystal 20 Image signal line selection circuit 21 Gate signal line 22 Image signal line 23 Pixel electrode 31 Gate insulating film 32 Flattening film 33 Common electrode 34 Interlayer insulating film 35 Color filter 36 Light shielding portion

Claims (7)

  A plurality of gate signal lines formed in a predetermined direction on a liquid crystal side surface of the substrate; a plurality of image signal lines formed intersecting with the gate signal lines; the gate signal lines and the image signal lines; A liquid crystal display device with a touch panel, which includes a thin film transistor and a unit pixel electrode, a capacitance detection electrode line arranged in parallel with the image signal line, and an image signal line driving circuit, which are respectively arranged corresponding to the intersections The capacitance detection electrode line is a liquid crystal display device with a touch panel arranged between the unit pixel electrodes where the image signal line is not arranged. The image signal line is disposed between and connected to the first unit pixel electrode and the second unit pixel electrode arranged in the predetermined direction, and thereby the first unit pixel. The electrode and the second unit pixel electrode constitute one unit,
Further, a plurality of the units constitute a group in the predetermined direction,
The liquid crystal display device with a touch panel according to claim 1, wherein the capacitance detection electrode line is disposed between the units in which the image signal line is not disposed in the group.   The said image signal line drive circuit supplies a signal to each of the said 1st unit pixel electrode which comprises the said group, the said 2nd unit pixel electrode, and the said capacity | capacitance detection electrode line by time division. Liquid crystal display with touch panel.   The time width of the signal supplied to the capacitance detection electrode line is greater than both the time width of the signal supplied to the first unit pixel electrode and the time width of the signal supplied to the second unit pixel electrode. The liquid crystal display device with a touch panel according to claim 3.   The image signal line driving circuit supplies a signal to the capacitance detection electrode line first or last in the first unit pixel electrode, the second unit pixel electrode, and the capacitance detection electrode line constituting the group. The liquid crystal display device with a touch panel according to claim 3 or 4.   When the image signal line drive circuit first supplies a signal to the capacitance detection electrode line in the first unit pixel electrode, the second unit pixel electrode, and the capacitance detection electrode line constituting the group, The liquid crystal display device with a touch panel according to claim 5, wherein a signal is supplied to the capacitance detection electrode line before the first unit pixel electrode and the second unit pixel electrode are turned on. A first unit pixel electrode, a second unit pixel electrode, and a third unit pixel electrode are arranged in the predetermined direction;
The image signal line is arranged between the first unit pixel electrode and the second unit pixel electrode or between the second unit pixel electrode and the third unit pixel electrode and these Thereby, the first unit pixel electrode, the second unit pixel electrode, and the third unit pixel electrode constitute one group,
The liquid crystal display device with a touch panel according to claim 1, wherein the capacitance detection electrode line is disposed between the groups where the image signal line is not disposed.