JP2017005464A - Digital filter, communication device, electronic equipment, communication system, and vehicle - Google Patents

Abstract

PROBLEM TO BE SOLVED: To appropriately remove noise while conforming to a desired communication standard.SOLUTION: A digital filter 200 comprises: an FIR filter part 210 for receiving input of an input pulse signal IN and outputting an internal pulse signal FIRO; and a window filter part 220 for receiving input of the input pulse signal IN and the internal pulse signal FIRO and outputting an output pulse signal OUT. The window filter part 220 includes: an input pulse signal monitoring part 221 for monitoring a logical switching timing of the input pulse signal IN only in an input pulse signal monitoring period set based on a logical switching timing of the internal pulse signal FIRO; and an output pulse signal generation part 222 for switching a logical level of the output pulse signal OUT with reference to the logical switching timing of each of the input pulse signal IN and the internal pulse signal FIRO.SELECTED DRAWING: Figure 9

Description

  The present invention relates to a digital filter, and a communication apparatus, electronic device, communication system, and vehicle using the same.

  In recent years, EMS (electro magnetic susceptibility) noise countermeasures have become extremely important in communication devices used in in-vehicle communication systems.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2008-078971 A

  However, with conventional EMS noise countermeasures, it has been difficult to properly remove noise while complying with a desired communication standard.

  In view of the above-mentioned problems found by the inventors of the present application, the invention disclosed in the present specification is a digital filter capable of appropriately removing noise while complying with a desired communication standard, and An object of the present invention is to provide a communication device, an electronic device, a communication system, and a vehicle using the same.

  The digital filter disclosed in the present specification includes a pre-filter unit that receives input of an input pulse signal and outputs an internal pulse signal, and receives an input of the input pulse signal and the internal pulse signal and outputs an output pulse signal. And a window filter unit for output (first configuration).

  In the digital filter having the first configuration, the window filter unit monitors the logic switching timing of the input pulse signal only during the input pulse signal monitoring period set based on the logic switching timing of the internal pulse signal. A configuration (second configuration) including: an input pulse signal monitoring unit; and an output pulse signal generation unit that switches a logic level of the output pulse signal with reference to logic switching timings of the input pulse signal and the internal pulse signal. It is good to.

  Further, in the digital filter having the second configuration, the input pulse signal monitoring unit sets the input pulse signal monitoring period in the current cycle based on the logic switching timing of the internal pulse signal in the previous cycle (third (Configuration).

  Further, in the digital filter having the second or third configuration, the output pulse signal generation unit sets a logic switching timing of the input pulse signal when the output pulse signal is switched from the first logic level to the second logic level. It is preferable to refer to the logic switching timing of the internal pulse signal when switching the output pulse signal from the second logic level to the first logic level (fourth configuration).

  In the digital filter having any one of the first to fourth configurations, the pre-filter unit and the window filter unit may be configured to operate in synchronization with a common oscillation signal (fifth configuration).

  In the digital filter having any one of the first to fifth configurations, the pre-filter unit may be configured as a FIR (finite impulse response) filter unit (sixth configuration).

  In addition, the communication device disclosed in the present specification includes a low-pass filter that receives an input of a bus signal and outputs a comparator input signal, a comparator that compares the comparator input signal with a threshold value and outputs a reception signal, A gate signal generation unit that receives a transmission signal and outputs a gate signal; an output transistor that drives the bus signal according to the gate signal; and a decoding process of the reception signal and an encoding process of the transmission signal A logic unit that performs the processing, and the logic unit includes a digital filter having any one of the first to sixth configurations that receives the received signal as the input pulse signal, and is output from the digital filter. The reception signal decoding process and the transmission signal encoding process are performed with reference to the pulse edge of the output pulse signal. There is a formation (seventh configuration).

  In addition, the electronic device disclosed in the present specification has a configuration (eighth configuration) including a communication device having the seventh configuration.

  Further, a communication system disclosed in the present specification includes an electronic device having an eighth configuration and a bus that is connected to the electronic device and serves as a transmission path for the bus signal (the ninth configuration). Composition).

  In the communication system having the ninth configuration, the bus signal may have a configuration (tenth configuration) that is a pulse width modulation signal whose pulse width is variably controlled according to the data value.

  Further, the vehicle disclosed in the present specification has a configuration (an eleventh configuration) having a communication system having the ninth or the tenth configuration.

  According to the invention disclosed in the present specification, a digital filter capable of appropriately removing noise while complying with a desired communication standard, and a communication device, electronic apparatus, communication system, and It becomes possible to provide a vehicle.

Block diagram showing overall configuration of in-vehicle communication system Block diagram showing a configuration example of a communication device Timing chart showing an example of decoding algorithm Timing chart showing an example of encoding algorithm (master) Timing chart showing an example of encoding algorithm (slave) Timing chart showing an example of signal delay Timing chart showing first example of received waveform Timing chart showing second example of received waveform Block diagram showing one configuration example of digital filter The block diagram which shows one structural example of a FIR filter part Timing chart showing noise removal effect of FIR filter section Timing chart showing one operation example of window filter Timing chart showing a modification of the decoding algorithm External view showing a configuration example of the vehicle X

<In-vehicle communication system>
FIG. 1 is a block diagram showing the overall configuration of the in-vehicle communication system. The in-vehicle communication system 1 of this configuration example includes a master device 10, a slave device 20, and a bus 30. As shown in the figure, in the in-vehicle system 1 of this configuration example, a master / slave system including a single master device 10 and one or a plurality of slave devices 20 is employed.

  Each of the master device 10 and the slave device 20 is an electronic device that constructs the in-vehicle communication system 1, and performs mutual communication of the bus signal BUS conforming to the one-wire communication format via the bus 30.

  The bus 30 is connected to the master device 10 and the slave device 20 and serves as a transmission path for the bus signal BUS. The bus signal BUS is a pulse width modulation signal whose pulse width (for example, low level width) is variably controlled according to the data value.

<Communication device>
FIG. 2 is a block diagram illustrating a configuration example of a communication device mounted on each of the master device 10 and the slave device 20. The communication device 100 of this configuration example is an interface device that mediates bidirectional communication between an ECU [electronic control unit] built in the master device 10 or the slave device 20 and the bus 30, and includes a logic unit 110 and a comparator 120. A low-pass filter 130, a gate signal generation unit 140, and an output transistor 150.

  The logic unit 110 performs a decoding process on the reception signal RX and an encoding process on the transmission signal TX when the bus signal BUS is transmitted and received.

  The comparator 120 compares the comparator input signal CMPI with a predetermined threshold voltage VTH to generate a reception signal RX and outputs it to the logic unit 110. Note that the comparator 120 may have hysteresis characteristics.

  The low-pass filter 130 receives an input of the bus signal BUS, removes a noise component (high-frequency component) superimposed thereon, generates a comparator input signal CMPI, and outputs this to the comparator 120.

  The gate signal generation unit 140 receives an input of the transmission signal TX from the logic unit 110, generates a gate signal SG, and outputs this to the gate of the output transistor 150. The gate signal generation unit 140 has a function of adjusting the rising slope / falling slope of the gate signal SG. That is, the gate signal SG is a voltage signal obtained by blunting the rising / falling slope of the transmission signal TX. By providing such a slope adjustment function, it is possible to suppress noise generation during transmission of the bus signal BUS.

  The output transistor 150 is an N channel type metal oxide semiconductor (MOS) field effect transistor that forms an open drain type output stage. The drain of the output transistor 150 is connected to the application terminal for the bus signal BUS. The source of the output transistor 150 is connected to the ground terminal. The gate of the output transistor 150 is connected to the output terminal (= application terminal of the gate signal SG) of the gate signal generator 140. Further, although not explicitly shown in the drawing, a pull-up resistor is connected to the application end of the bus signal BUS. The output transistor 150 connected in this manner is turned on when the gate signal SG is at a high level and turned off when the gate signal SG is at a low level.

  Note that when all of the communication devices 100 commonly connected to the bus 30 have the output transistor 150 turned off, the bus signal BUS is at a high level, and when at least one of the communication devices 100 has the output transistor 150 turned on. The bus signal BUS becomes low level. That is, in the plurality of communication devices 100, when high level output and low level output are performed simultaneously, the low level is given priority as the logical level of the bus signal BUS.

<Decoding / encoding algorithm>
FIG. 3 is a timing chart showing an example of a decoding algorithm (common to master / slave) in the logic unit 110. From the top, the reception signal RX, the bus edge detection signal EDGE_RX, the bus cycle count value TCNT_RX, the determination timing signal TMG, The low period count value LCNT and the internal reception signal RXD are depicted.

  The reception signal RX is a pulse width modulation signal whose pulse width (for example, the low period) is variably controlled according to the data value, similarly to the bus signal BUS (not shown in the figure). Describing according to the example of this figure, when the data value of the reception signal RX is “1”, the low period of the reception signal RX is set to “T1”. On the other hand, when the data value of the reception signal RX is “0”, the low period of the reception signal RX is set to “T0” (where T1 <T0).

  The bus edge detection signal EDGE_RX is one of internal signals in the logic unit 110. When the falling edge of the reception signal RX is detected, a one-shot pulse is generated in the bus edge detection signal EDGE_RX. However, once the falling edge of the received signal RX is detected, the falling edge is not detected again until the logical determination timing of the received signal RX (= the one-shot pulse generation timing of the determination timing signal TMG) arrives. Not done.

  The bus cycle count value TCNT_RX is one of internal parameters in the logic unit 110. The bus cycle count value TCNT_RX is reset to 0 when the falling edge of the reception signal RX is detected, and incremented one by one until the falling edge of the reception signal RX in the next cycle is detected. Therefore, the logic unit 110 can recognize the cycle T of the reception signal RX (and hence the cycle T of the bus signal BUS) from the bus cycle count value TCNT_RX immediately before the reset.

  The determination timing signal TMG is one of internal signals in the logic unit 110. A one-shot pulse is generated in the determination timing signal TMG when a predetermined waiting period has elapsed since the falling edge of the reception signal RX was detected. Note that the above-described waiting period may be set to a length obtained by storing the latest low period “T1” corresponding to the data value “1” and adding a predetermined offset period to the stored value.

  The low period count value LCNT is one of internal parameters in the logic unit 110. The low period count value LCNT is reset to 0 when the falling edge of the reception signal RX is detected, and thereafter incremented by one over the low period of the reception signal RX. Therefore, the logic unit 110 can recognize the low period (T1 or T0) of the reception signal RX from the low period count value LCNT immediately before the reset.

  The internal reception signal RXD is one of internal signals in the logic unit 110. The internal reception signal RXD is generated by latching the reception signal RX using a one-shot pulse of the determination timing signal TMG as a trigger. Therefore, the logical level of the internal reception signal RXD is high when the low period of the reception signal RX is “T1”, and is low when the low period of the reception signal RX is “T0”. That is, the internal reception signal RXD is a binary logic signal obtained by decoding the reception signal RX according to the low period (T1 or T0).

  As described above, the decoding algorithm in the logic unit 110 operates based on the falling edge of the received signal RX. Therefore, if noise (see the broken line) is superimposed on the reception signal RX and a falling edge is erroneously detected, the low period count value LCNT deviates from the original value. In this case, all the logic determination timings of the reception signal RX after the next period are also shifted, so that the decoding algorithm fails.

  FIG. 4 is a timing chart showing an example of an encoding algorithm (master) in the logic unit 110. In order from the top, the external clock signal CLK, the reception signal RX, the clock edge detection signal EDGE_CLK, the bus edge detection signal EDGE_RX, and the clock cycle count. The value TCNT_CLK, the bus cycle count value TCNT_RX, the first internal transmission signal TXD1, the second internal transmission signal TXD0, and the transmission signal TX are depicted.

  The external clock signal CLK is a clock signal for arbitrarily setting the cycle T, and is externally input to the master device 10 using a UART [universal asynchronous receiver transmitter] function. However, the input interface of the external clock signal CLK is not necessarily limited to UART. The frequency f (= 1 / T) of the external clock signal CLK can be arbitrarily set within a range of 5 to 20 kHz, for example. On the other hand, the duty of the external clock signal CLK may be fixed at 50%, for example.

  As described above, the reception signal RX is a pulse width modulation signal whose pulse width (for example, the low period) is variably controlled according to the data value.

  The clock edge detection signal EDGE_CLK is one of internal signals in the logic unit 110. When the falling edge of the external clock signal CLK is detected, a one-shot pulse is generated in the clock edge detection signal EDGE_CLK. However, once the falling edge of the external clock signal CLK is detected, the falling edge is not detected again until the logic determination timing of the external clock signal CLK arrives.

  The bus edge detection signal EDGE_RX is one of internal signals in the logic unit 110. When the falling edge of the reception signal RX is detected, a one-shot pulse is generated in the bus edge detection signal EDGE_RX. However, once the falling edge of the received signal RX is detected, the falling edge is not detected again until the logic determination timing of the received signal RX arrives.

  The clock cycle count value TCNT_CLK is one of internal parameters in the logic unit 110. The clock cycle count value TCNT_CLK is reset to 0 when the falling edge of the external clock signal CLK is detected, and is incremented by 1 until the falling edge of the external clock signal CLK in the next cycle is detected. Therefore, the logic unit 110 can recognize the cycle of the external clock signal CLK from the clock cycle count value TCNT_CLK immediately before the reset.

  The bus cycle count value TCNT_RX is one of internal parameters in the logic unit 110. The bus cycle count value TCNT_RX is reset to 0 when the falling edge of the reception signal RX is detected, and incremented one by one until the falling edge of the reception signal RX in the next cycle is detected. Therefore, the logic unit 110 can recognize the cycle of the reception signal RX (and hence the cycle of the bus signal BUS) from the bus cycle count value TCNT_RX immediately before the reset.

  The first internal transmission signal TXD1 is one of internal signals in the logic unit 110. The first internal transmission signal TXD1 is a pulse signal that is raised to a high level only for a low period T1 corresponding to the data value “1” with a one-shot pulse of the clock edge detection signal EDGE_CLK as a trigger.

  The second internal transmission signal TXD0 is one of internal signals in the logic unit 110. The second internal transmission signal TXD0 is a pulse signal that is lowered to a low level for a low period T0 corresponding to a data value “0” using a one-shot pulse of the bus edge detection signal EDGE_RX as a trigger.

  The transmission signal TX is a pulse signal generated using the first internal transmission signal TXD1 and the second internal transmission signal TXD0. More specifically, when the data value of the transmission signal TX is “1”, the low period of the transmission signal TX is set to “T1” in accordance with the high period of the first internal transmission signal TXD1. On the other hand, when the data value of the transmission signal TX is “0”, the low period of the transmission signal TX is set to “T0” in accordance with the low period of the second internal transmission signal TXD0. That is, the transmission signal TX is a pulse width modulation signal whose pulse width (for example, low period) is variably controlled according to the data value.

  The master device 10 continuously outputs the transmission signal TX having the data value “1” (low period “T1”) even when data is not transmitted, and outputs the transmission signal TX having the data value “0”. Only, it operates to extend the low period of the transmission signal TX to “T0”. With such a configuration, the slave device 20 can perform a decoding process and an encoding process in synchronization with the bus signal BUS that is periodically pulse-driven.

  As described above, the encoding algorithm in the logic unit 110 of the master device 10 operates on the basis of the falling edge of the reception signal RX as in the previous decoding algorithm. For this reason, when noise (see the broken line) is superimposed on the received signal RX and a falling edge is erroneously detected, all timings are shifted, and the encoding algorithm is broken.

  FIG. 5 is a timing chart showing an example of an encoding algorithm (slave) in the logic unit 110. In order from the top, the reception signal RX, the bus edge detection signal EDGE_RX, the bus cycle count value TCNT_RX, the second internal transmission signal TXD0, And the transmission signal TX is depicted.

  As described above, the reception signal RX is a pulse width modulation signal whose pulse width (for example, the low period) is variably controlled according to the data value.

  The bus edge detection signal EDGE_RX is one of internal signals in the logic unit 110. When the falling edge of the reception signal RX is detected, a one-shot pulse is generated in the bus edge detection signal EDGE_RX. However, once the falling edge of the received signal RX is detected, the falling edge is not detected again until the logic determination timing of the received signal RX arrives.

  The bus cycle count value TCNT_RX is one of internal parameters in the logic unit 110. The bus cycle count value TCNT_RX is reset to 0 when the falling edge of the reception signal RX is detected, and incremented one by one until the falling edge of the reception signal RX in the next cycle is detected. Therefore, the logic unit 110 can recognize the cycle of the reception signal RX (and hence the cycle of the bus signal BUS) from the bus cycle count value TCNT_RX immediately before the reset.

  The second internal transmission signal TXD0 is one of internal signals in the logic unit 110. The second internal transmission signal TXD0 is a pulse signal that is lowered to a low level for a low period T0 corresponding to a data value “0” using a one-shot pulse of the bus edge detection signal EDGE_RX as a trigger.

  The transmission signal TX is a pulse signal generated using the second internal transmission signal TXD0. More specifically, when the data value of the transmission signal TX is “1”, the transmission signal TX is fixed at a high level for one period. On the other hand, when the data value of the transmission signal TX is “0”, the low period of the transmission signal TX is set to “T0” in accordance with the low period of the second internal transmission signal TXD0.

  As described above, the slave device 20 operates so that the transmission signal TX falls to the low level for the low period “T0” only when the transmission signal TX having the data value “0” is output. As described above, the low level is prioritized as the logical level of the bus signal BUS. Accordingly, the master device 10 receives the fact that the low period of the bus signal BUS is “T0” even though the master device 10 does not transmit the data “0”, so that the slave device 20 receives the data “0”. Can be recognized.

  As described above, the encoding algorithm in the logic unit 110 of the slave device 20 operates on the basis of the falling edge of the reception signal RX as in the previous decoding algorithm. For this reason, when noise (see the broken line) is superimposed on the received signal RX and a falling edge is erroneously detected, all timings are shifted, and the encoding algorithm is broken.

<Signal delay>
FIG. 6 is a timing chart showing an example of signal delay occurring in the communication apparatus 100, in which the bus signal BUS, the reception signal RX, the transmission signal TX, and the gate signal SG are depicted in order from the top.

  As shown in this figure, the signal delay generated in the communication apparatus 100 includes a reception delay d1 generated in the comparator 120 and the low-pass filter 130, a logic delay d2 generated in the logic unit 110, and a transmission delay d3 generated in the gate signal generation unit 140. Can be mentioned. In order to make the communication device 100 conform to a predetermined communication standard, it is necessary to keep the total delay dtotal (= d1 + d2 + d3) within the standard value range.

  In order to reduce the reception delay d1, it is conceivable to increase the drive current of the comparator 120 or increase the cutoff frequency of the low-pass filter 130. In order to reduce the transmission delay d3, it is conceivable to increase the slew rate of the gate signal generation unit 140.

  Among the measures described above, an increase in the drive current of the comparator 120 and an increase in the slew rate of the gate signal generation unit 140 do not significantly affect the noise resistance. However, increasing the cut-off frequency of the low-pass filter 130 decreases noise resistance.

<EMS noise>
7 and 8 are timing charts showing examples of received waveforms, respectively, in which the bus signal BUS and the received signal RX are depicted in order from the top. FIG. 7 shows a simulation result when the noise amplitude is relatively small (= the high level of the bus signal BUS is 12V, whereas the noise amplitude is ± 8V). On the other hand, FIG. 8 shows a simulation result when the noise amplitude is relatively large (= the high level of the bus signal BUS is 12V, whereas the noise amplitude is ± 30V).

  As shown in FIG. 7, when the noise amplitude is relatively small, the noise superimposed on the bus signal BUS can be substantially eliminated by using the low-pass filter 130 and the comparator 120.

  On the other hand, as shown in FIG. 8, when the noise amplitude is relatively large, even if the low-pass filter 130 and the comparator 120 are used, the noise superimposed on the bus signal BUS cannot be sufficiently removed. However, when attention is paid to the low level period of the bus signal BUS, it is understood that noise is not easily superimposed on the reception signal RX even when the noise amplitude is relatively large.

  As described above, when noise is superimposed on the reception signal RX, the decoding process and the encoding process in the logic unit 110 are hindered. Therefore, a digital filter is mounted on the logic unit 110 as a means for removing noise superimposed on the reception signal RX.

<Digital filter>
FIG. 9 is a block diagram illustrating a configuration example of a digital filter implemented in the logic unit 110. The digital filter 200 of this configuration example includes an FIR filter unit 210 and a window filter unit 220.

  The FIR filter unit 210 operates in synchronization with an oscillation signal OSC having a predetermined oscillation frequency fosc (for example, 10 MHz), and functions as a pre-filter unit that receives an input pulse signal IN and outputs an internal pulse signal FIRO. As the input pulse signal IN, the aforementioned reception signal RX is input. The FIR filter unit 210 also has a function of initializing the logic level of the internal pulse signal FIRO in accordance with the reset signal RST.

  The window filter unit 220 operates in synchronization with the oscillation signal OSC common to the FIR filter unit 210, receives both the input pulse signal IN and the internal pulse signal FIRO, and outputs the output pulse signal OUT. Window filter unit 220 includes an input pulse signal monitoring unit 221 and an output pulse signal generation unit 222. The window filter unit 220 also has a function of initializing the logic level of the output pulse signal OUT in accordance with the reset signal RSC common to the FIR filter unit 210.

  The input pulse signal monitoring unit 221 monitors the logic switching timing of the input pulse signal IN only during the input pulse signal monitoring period set based on the logic switching timing of the internal pulse signal FIRO, and outputs the monitoring result as an output pulse signal generation unit. To 222.

  The output pulse signal generator 222 switches the logic level of the output pulse signal OUT with reference to the logic switching timings of the input pulse signal IN and the internal pulse signal FIRO. Specifically, the output pulse signal generation unit 222 determines the logic switching timing of the input pulse signal IN (= monitoring result of the input pulse signal monitoring unit 221) when the output pulse signal OUT falls from the high level to the low level. Reference is made to the logic switching timing of the internal pulse signal FIRO when the output pulse signal OUT rises from the low level to the high level.

  In this drawing, for convenience of explanation, the FIR filter unit 210 and the window filter unit 220 are depicted as if they were implemented as hardware as independent circuit blocks. The filter unit 220 may be implemented in software by digital processing in the logic unit 110.

  As described above, the logic unit 110 includes the digital filter 200 that receives the reception signal RX as the input pulse signal IN, and the reception signal RX is based on the pulse edge of the output pulse signal OUT output from the digital filter 200. The decoding process and the encoding process of the transmission signal TX are performed.

  By adopting such a configuration, it is possible to appropriately remove noise superimposed on the reception signal RX while complying with a desired communication standard. Therefore, it becomes difficult to cause a problem in the decoding process of the reception signal RX and the encoding process of the transmission signal TX in the logic unit 110, and as a result, the noise resistance of the communication device 100 can be improved.

  In the following, the technical significance of using both the FIR filter unit 210 and the window filter unit 220 together instead of using them individually will be described in detail.

<FIR filter section>
FIG. 10 is a block diagram illustrating a configuration example of the FIR filter unit 210. The FIR filter unit 210 of this configuration example includes D flip-flops 211 (1) to 211 (m) that form an m-stage (for example, 16-stage) shift register, an average value calculation unit 212, a threshold value calculation unit 213, D flip-flop 214.

  The D flip-flop 211 (1) takes in the input pulse signal IN input to the data terminal (D) in synchronization with the oscillation signal OSC, and performs latch output from the output terminal (Q). The D flip-flop 211 (k) (where k = 2, 3,..., M−1, m) is synchronized with the oscillation signal OSC and is input to the data end (D). The output of 1) is taken in and latch output is performed from the output terminal (Q). Note that each of the D flip-flops 211 (1) to 211 (m) has a function of initializing the latch output in accordance with the reset signal RST.

  The average value calculation unit 212 takes in the latch outputs of the D flip-flops 211 (1) to 211 (m) in synchronization with the oscillation signal OSC and calculates an average value S1 thereof. For example, when calculating the simple average value, if the n-stage latch output is high level among the total m-stage latch outputs, the calculation result of the average value S1 is “n / m”. The average value calculation unit 212 has a function of initializing the calculation result of the average value S1 according to the reset signal RST.

  The threshold value calculation unit 213 compares the average value S1 with the threshold value TH and generates a comparison signal S2. For example, if S1 ≧ TH, S2 = H, and if S1 <TH, S2 = L.

  The D flip-flop 214 takes in the comparison signal S2 input to the data terminal (D) in synchronization with the oscillation signal OSC, and latches and outputs it from the output terminal (Q) as the internal pulse signal FIRO. The D flip-flop 214 has a function of initializing the internal pulse signal FIRO in response to the reset signal RST.

  Regarding the number m of shift registers composed of D flip-flops 211 (1) to 211 (m) and the threshold value TH in the threshold value calculation unit 213, the characteristics of the comparator 120 and the low-pass filter 130 (see FIG. 2). It may be set as appropriate based on the above. However, when the threshold value TH is set to be shifted from the center value (= 1/2), there is a difference between the duty of the input pulse signal IN and the duty of the internal pulse signal FIRO. is necessary. If sufficient filter characteristics cannot be obtained even after adjusting the stage number m or the threshold value TH, the average value calculation unit 212 may calculate a weighted average value.

  FIG. 11 is a timing chart showing the noise removal effect in the FIR filter unit 210. From the top, the bus signal BUS, the noise signal NOISE (= corresponding to the bus signal BUS on which noise is superimposed), the input pulse signal IN (= The received signal RX) and the internal pulse signal FIRO are depicted. Here, the simulation results are shown when the number of shift register stages m is 16, the noise frequency is 1 MHz, and the frequency fosc of the oscillation signal OSC is 20 MHz.

  As shown in this figure, when the number of shift register stages m is 16, even if the frequency fosc of the oscillation signal OSC is increased to 20 MHz, noise can be substantially removed. However, noise is not completely removed in the vicinity of the essential pulse edge. In view of this fact, it can be said that the use of the FIR filter unit 210 alone as the digital filter 200 mounted on the logic unit 110 is a somewhat unsatisfactory simulation result.

  Further, in the FIR filter unit 210, a filter delay occurs due to the circuit configuration, so that the pulse edge of the internal pulse signal FIRO is delayed with respect to the pulse edge of the bus signal BUS. Therefore, when the FIR filter unit 210 is used alone as the digital filter 200, the communication device 100 may not be able to comply with a predetermined communication standard.

<Window filter part>
FIG. 12 is a timing chart showing an operation example of the window filter unit 220. From the top, the bus signal BUS (noise superposition is omitted), the input pulse signal IN (= received signal RX), and the internal pulse signal FIRO are shown. , And the output pulse signal OUT is depicted.

  In a general window filter, a detection window is opened at a predetermined timing, and a pulse edge of a detection target signal is detected while the detection window is open. However, when the timing for opening the detection window is fixed, there is a possibility that the noise tolerance varies depending on the frequency variation of the oscillation signal OSC and the frequency setting of the external clock signal CLK. Therefore, it is desirable that the timing for opening the detection window is appropriately variably controlled.

  Further, as described above, the decoding algorithm and the encoding algorithm in the logic unit 110 operate on the basis of the falling edge of the reception signal RX. Therefore, the window filter unit 220 is required to detect the falling edge of the reception signal RX as accurately and quickly as possible.

  In view of this, the window filter unit 220 of the present configuration example predicts in advance the timing at which the detection window should be opened, and has the function of always detecting the pulse edge of the input pulse signal IN at an appropriate timing. A portion 221 is provided.

  The input pulse signal monitoring unit 221 sets an input pulse signal monitoring period (corresponding to the above-described detection window, see the hatched area in the figure) in the current period based on the logic switching timing of the internal pulse signal FIRO in the previous period.

  More specifically, the input pulse signal monitoring unit 221 first determines the length of the i-th cycle (hereinafter, for the sake of convenience, the cycle T) based on the pulse edge of the internal pulse signal FIRO. (Referred to as (i)).

  Next, the input pulse signal monitoring unit 221 starts the input pulse signal monitoring period start timing (= T (i) −α in the (i + 1) th period based on the previously calculated period T (i). X Tosc, where Tosc = 1 / fosc).

  For example, by setting the shift register stage number m of the FIR filter unit 210 as the parameter α, in the (i + 1) th cycle, after the internal pulse signal FIRO falls to the low level, the cycle T (i) The pulse edge monitoring of the input pulse signal IN is started at the timing when the time (= T (i) −m × Tosc) obtained by subtracting the maximum delay time (= m × Tosc) of the FIR filter unit 210 has elapsed. .

  In setting the parameter α, not only the filter delay time generated in the FIR filter unit 210 but also the detection variation (about ± 1%) of the period T (i) may be considered.

  Further, the width W (i + 1) of the input pulse signal monitoring period may be appropriately set based on the cycle T (i) (for example, W (i + 1) = β × T (i)).

  Thereafter, after the input pulse signal monitoring period is started, the input pulse signal monitoring unit 221 sets the earliest falling edge appearing in the input pulse signal IN to be true, and sends the detection result to the output pulse signal generation unit 222. .

  The output pulse signal generator 222 switches the logic level of the output pulse signal OUT with reference to the logic switching timings of the input pulse signal IN and the internal pulse signal FIRO.

  Specifically, when the output pulse signal generation unit 222 falls the output pulse signal OUT from the high level to the low level, the output pulse signal monitoring unit 221 indicates the monitoring result of the input pulse signal monitoring unit 221 (= the falling edge of the input pulse signal IN). Reference is made to the rising edge of the internal pulse signal FIRO when the output pulse signal OUT is raised from the low level to the high level.

  That is, the falling edge of the input pulse signal IN (= received signal RX) must be detected as quickly and accurately as possible in order to meet the requirements of the communication standard. Therefore, the window filter unit 220 monitors the input pulse signal IN having a lot of noise but a small delay, and exists within the input pulse signal monitoring period set based on the internal pulse signal FIRO having a large delay but little noise. A configuration that captures a falling edge is employed.

  On the other hand, the rising edge of the input pulse signal IN (= received signal RX) is not imposed as severe as the falling edge. Therefore, the window filter unit 220 employs a configuration that directly captures the rising edge of the internal pulse signal FIRO from which noise is substantially removed.

  However, a difference occurs between the duty of the input pulse signal IN and the duty of the output pulse signal OUT due to the different detection methods of the falling edge and the rising edge, and attention must be paid to this point. .

  In the output pulse signal generation unit 222, after the falling edge and the rising edge of the output pulse signal OUT are determined, any reverse edge that does not satisfy the specification is invalidated.

<Decryption algorithm (variation)>
FIG. 13 is a timing chart showing a modified example of the decoding algorithm in the logic unit 110. The reception signal RX, the low period count value LCNT, and the internal reception signal RXD are depicted in order from the top.

  As described above, the reception signal RX is a pulse width modulation signal whose pulse width (for example, the low period) is variably controlled according to the data value. Describing according to the example of this figure, when the data value of the reception signal RX is “1”, the low period of the reception signal RX is set to “T1”. On the other hand, when the data value of the reception signal RX is “0”, the low period of the reception signal RX is set to “T0” (where T1 <T0).

  The low period count value LCNT is one of the internal parameters in the logic unit 110, and is reset to 0 when the falling edge of the reception signal RX is detected. Thereafter, the low period count value LCNT is one for the low period of the reception signal RX. It is incremented by one.

  The internal reception signal RXD is one of internal signals in the logic unit 110, and is high when the low period of the reception signal RX is “T1”, and when the low period of the reception signal RX is “T0”. Become low level.

  In FIG. 3, the logical level of the internal reception signal RXD is determined by latching the reception signal RX at a predetermined logic determination timing after the falling edge of the reception signal RX is detected. However, it is known that noise is likely to be superimposed during the high level period of the reception signal RX in which the logic determination timing is set (see FIG. 8 above). For this reason, there is a great concern that the logical level of the internal reception signal RXD is erroneously determined.

  Therefore, in the decoding algorithm of this modification, the low period count value LNCT (= the length of the low period) and a predetermined threshold at the logic determination timing (for example, (15/16) × T) indicated by the broken line in the figure. A configuration for performing comparison determination with LCNTth is employed. The threshold LCNTth may be calculated by storing the latest low period “T1” corresponding to the data value “1” and adding a predetermined offset value to the stored value.

  Referring to the example of this figure, at the above logic determination timing, if LCNT ≦ LCNTth, the internal reception signal RXD is set to the high level, and if LCNT> LCNTth, the internal reception signal RXD is set to the low level. .

  As described above, it is known that noise is difficult to be superimposed during the low level period of the reception signal RX (see FIGS. 7 and 8 above). Therefore, it is considered that the decoding accuracy of the reception signal RX can be improved if the logic level of the internal reception signal RXD is determined based on the comparison result between the low period count value LCNT and the threshold value LCNTth.

<Application to vehicles>
FIG. 14 is an external view showing a configuration example of the vehicle X. The vehicle X of this configuration example includes various electronic devices X11 to X18 that operate by receiving power supply from a battery. In addition, about the mounting position of the electronic devices X11-X18, it may differ from the actual for convenience of illustration.

  The electronic device X11 is an engine control unit that performs control related to the engine (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto cruise control, and the like).

  The electronic device X12 is a lamp control unit that performs on / off control such as HID [high intensity discharged lamp] and DRL [daytime running lamp].

  The electronic device X13 is a transmission control unit that performs control related to the transmission.

  The electronic device X14 is a body control unit that performs control (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.) related to the motion of the vehicle X.

  The electronic device X15 is a security control unit that performs drive control such as a door lock and a security alarm.

  The electronic device X16 is an electronic device that is built into the vehicle X at the factory shipment stage as a standard equipment item or manufacturer's option product, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat. It is.

  The electronic device X17 is an electronic device that is optionally mounted on the vehicle X as a user option product such as an in-vehicle A / V [audio / visual] device, a car navigation system, and an ETC [electronic toll collection system].

  The electronic device X18 is an electronic device that includes a high-voltage motor such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

  The above-described in-vehicle communication system 1 can be incorporated in the vehicle X as a communication means between the electronic devices X11 to X18.

<Other variations>
In the above embodiment, the detailed explanation has been given by taking the EMS noise countermeasure of the in-vehicle communication system as an example. However, the application target of the present invention is not limited to this, and is used for other purposes. The present invention can be widely applied to improve noise resistance performance (and hence communication accuracy) of the entire communication system.

  In the above embodiment, the description has been given of the configuration that handles the reception signal RX (see FIG. 7 and FIG. 8) in which noise is difficult to be superimposed during the low level period of the bus signal BUS. By appropriately adjusting, it is possible to cope with an input signal whose noise tolerance during the low level period is not so high.

  In the above embodiment, the configuration using the FIR filter unit 210 as an example of the pre-filter unit that roughly removes noise superimposed on the input pulse signal IN has been exemplified. An IIR [infinite impulse response] filter unit or the like may be applied.

  As described above, various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  The present invention can be applied to, for example, an in-vehicle communication system mounted on a vehicle.

1 In-vehicle communication system 10 Master device (electronic device)
20 Slave equipment (electronic equipment)
30 bus 100 communication device 110 logic unit 120 comparator 130 low-pass filter 140 gate signal generation unit 150 output transistor 200 digital filter 210 FIR filter unit (pre-filter unit)
211 (1) to 211 (m) D flip-flop 212 average value calculation unit 213 threshold value calculation unit 214 D flip-flop 220 window filter unit 221 input pulse signal monitoring unit 222 output pulse signal generation unit X vehicle X11 to X18 electronic device

Claims (11)

A pre-filter unit for receiving an input pulse signal and outputting an internal pulse signal;
A window filter unit that receives an input of the input pulse signal and the internal pulse signal and outputs an output pulse signal;
A digital filter characterized by comprising: The window filter unit includes:
An input pulse signal monitoring unit that monitors the logic switching timing of the input pulse signal only during an input pulse signal monitoring period set based on the logic switching timing of the internal pulse signal;
An output pulse signal generator that switches the logic level of the output pulse signal with reference to the logic switching timing of each of the input pulse signal and the internal pulse signal;
The digital filter according to claim 1, comprising:   3. The digital filter according to claim 2, wherein the input pulse signal monitoring unit sets the input pulse signal monitoring period in a current cycle based on a logic switching timing of the internal pulse signal in a previous cycle.   The output pulse signal generation unit refers to a logic switching timing of the input pulse signal when the output pulse signal is switched from a first logic level to a second logic level, and the output pulse signal is changed from the second logic level to the second logic level. The digital filter according to claim 2 or 3, wherein the logic switching timing of the internal pulse signal is referred to when switching to the first logic level.   The digital filter according to any one of claims 1 to 4, wherein the pre-filter unit and the window filter unit operate in synchronization with a common oscillation signal.   The digital filter according to claim 1, wherein the pre-filter unit is an FIR [finite impulse response] filter unit. A low-pass filter that accepts a bus signal input and outputs a comparator input signal;
A comparator that compares the comparator input signal with a threshold value and outputs a received signal;
A gate signal generator for receiving a transmission signal and outputting a gate signal;
An output transistor for driving the bus signal in response to the gate signal;
A logic unit that performs decoding processing of the received signal and encoding processing of the transmission signal;
Have
The logic unit is mounted with the digital filter according to any one of claims 1 to 6 that receives the received signal as the input pulse signal, and the logic unit outputs the output pulse signal output from the digital filter. A communication apparatus that performs decoding processing of the received signal and encoding processing of the transmission signal on the basis of a pulse edge.   An electronic apparatus comprising the communication device according to claim 7. An electronic device according to claim 8,
A bus connected to the electronic device and serving as a transmission path for the bus signal;
A communication system comprising:   The communication system according to claim 9, wherein the bus signal is a pulse width modulation signal whose pulse width is variably controlled according to the data value.   A vehicle comprising the communication system according to claim 9 or 10.

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