JP2016540300A - 低電圧セキュアデジタル（ｓｄ）インターフェースのためのシステムおよび方法 - Google Patents

低電圧セキュアデジタル（ｓｄ）インターフェースのためのシステムおよび方法 Download PDF

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JP2016540300A
JP2016540300A JP2016530857A JP2016530857A JP2016540300A JP 2016540300 A JP2016540300 A JP 2016540300A JP 2016530857 A JP2016530857 A JP 2016530857A JP 2016530857 A JP2016530857 A JP 2016530857A JP 2016540300 A JP2016540300 A JP 2016540300A
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compliant
signal
volts
devices
voltage level
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JP2016540300A5 (https=
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ニール・ガーバー
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クアルコム，インコーポレイテッド
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Publication of JP2016540300A publication Critical patent/JP2016540300A/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Sources (AREA)
  • Information Transfer Systems (AREA)
  • Telephone Function (AREA)
  • Mobile Radio Communication Systems (AREA)
JP2016530857A 2013-11-22 2014-11-20 低電圧セキュアデジタル（ｓｄ）インターフェースのためのシステムおよび方法 Pending JP2016540300A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/087,047 US9899105B2 (en) 2013-11-22 2013-11-22 Systems and methods for low voltage secure digital (SD) interfaces
US14/087,047 2013-11-22
PCT/US2014/066567 WO2015077426A1 (en) 2013-11-22 2014-11-20 Systems and methods for low voltage secure digital (sd) interfaces

Related Child Applications (1)

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JP2019151909A Division JP2019197598A (ja) 2013-11-22 2019-08-22 低電圧セキュアデジタル（ｓｄ）インターフェースのためのシステムおよび方法

Publications (2)

Publication Number Publication Date
JP2016540300A true JP2016540300A (ja) 2016-12-22
JP2016540300A5 JP2016540300A5 (https=) 2017-12-14

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Family Applications (2)

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JP2016530857A Pending JP2016540300A (ja) 2013-11-22 2014-11-20 低電圧セキュアデジタル（ｓｄ）インターフェースのためのシステムおよび方法
JP2019151909A Pending JP2019197598A (ja) 2013-11-22 2019-08-22 低電圧セキュアデジタル（ｓｄ）インターフェースのためのシステムおよび方法

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JP2019151909A Pending JP2019197598A (ja) 2013-11-22 2019-08-22 低電圧セキュアデジタル（ｓｄ）インターフェースのためのシステムおよび方法

Country Status (6)

Country Link
US (1) US9899105B2 (https=)
EP (1) EP3072056B1 (https=)
JP (2) JP2016540300A (https=)
KR (1) KR20160087819A (https=)
CN (1) CN105745633A (https=)
WO (1) WO2015077426A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10235312B2 (en) 2016-10-07 2019-03-19 Samsung Electronics Co., Ltd. Memory system and host device that maintain compatibility with memory devices under previous standards and/or versions of standards
CN109428587B (zh) * 2017-08-31 2023-10-27 恩智浦美国有限公司 电平移位器备用单元
CN111370052B (zh) * 2018-12-25 2022-03-29 北京兆易创新科技股份有限公司 一种非易失存储器验证系统及方法
US12197264B2 (en) * 2020-11-10 2025-01-14 Micron Technology, Inc. Power management for a memory device

Citations (1)

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US20090006022A1 (en) * 2007-06-30 2009-01-01 Kathy Tian Link transmitter swing compensation

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US7483329B2 (en) * 2000-01-06 2009-01-27 Super Talent Electronics, Inc. Flash card and controller with integrated voltage converter for attachment to a bus that can operate at either of two power-supply voltages
CN2886681Y (zh) * 2006-01-20 2007-04-04 骆建军 集成电压转换器的存储控制器
US6438638B1 (en) * 2000-07-06 2002-08-20 Onspec Electronic, Inc. Flashtoaster for reading several types of flash-memory cards with or without a PC
JP2003281485A (ja) 2002-03-26 2003-10-03 Toshiba Corp メモリカード及びメモリカードのデータ記録方法
JP2004241995A (ja) * 2003-02-05 2004-08-26 Yazaki Corp 車両用電源重畳多重通信システム
US6944028B1 (en) 2004-06-19 2005-09-13 C-One Technology Corporation Storage memory device
JP4799417B2 (ja) 2004-09-28 2011-10-26 ｄブロード株式会社 ホストコントローラ
US7587544B2 (en) 2006-09-26 2009-09-08 Intel Corporation Extending secure digital input output capability on a controller bus
CN201134901Y (zh) 2007-12-24 2008-10-15 深圳市三木通信技术有限公司 一种通信终端
US8233551B2 (en) * 2008-07-07 2012-07-31 Intel Corporation Adjustable transmitter power for high speed links with constant bit error rate
US8019923B2 (en) * 2008-12-01 2011-09-13 Sandisk Il Ltd. Memory card adapter
KR101626528B1 (ko) * 2009-06-19 2016-06-01 삼성전자주식회사 플래시 메모리 장치 및 이의 데이터 독출 방법
US9135109B2 (en) * 2013-03-11 2015-09-15 Seagate Technology Llc Determination of optimum threshold voltage to read data values in memory cells

Patent Citations (1)

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US20090006022A1 (en) * 2007-06-30 2009-01-01 Kathy Tian Link transmitter swing compensation

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PRODUCT SPECIFICATION INDUSTRIAL SD & SDHC MEMORY CARDS - HERCULES SERIES -, JPN7019003890, 16 August 2010 (2010-08-16), pages 1 - 37, ISSN: 0004165729 *
SAMSUNG SD & MICRO SD CARD PRODUCT FAMILY SDA 3.0 SPECIFICATION COMPLIANT-UP TO UHS-I MODE, JPN7019003887, 4 November 2013 (2013-11-04), pages 1 - 37, ISSN: 0004165728 *
SD GROUP, SD SPECIFICATIONS PART 1 PHYSICAL LAYER SIMPLIFIED SPECIFICATION VERSION 4.10, vol. Version 4.10, JPN7018004043, 22 January 2013 (2013-01-22), pages 1 - 186, ISSN: 0004165726 *
武藤 佳恭, 超低コスト インターネット・ガジェット設計, vol. 第１版, JPN6018046411, 15 May 2008 (2008-05-15), JP, pages 132 - 133, ISSN: 0004165727 *

Also Published As

Publication number Publication date
WO2015077426A1 (en) 2015-05-28
JP2019197598A (ja) 2019-11-14
US20150149841A1 (en) 2015-05-28
US9899105B2 (en) 2018-02-20
EP3072056A1 (en) 2016-09-28
EP3072056B1 (en) 2018-05-02
KR20160087819A (ko) 2016-07-22
CN105745633A (zh) 2016-07-06

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