JP2016530631A - ベクトルの算術的削減 - Google Patents
ベクトルの算術的削減 Download PDFInfo
- Publication number
- JP2016530631A JP2016530631A JP2016534602A JP2016534602A JP2016530631A JP 2016530631 A JP2016530631 A JP 2016530631A JP 2016534602 A JP2016534602 A JP 2016534602A JP 2016534602 A JP2016534602 A JP 2016534602A JP 2016530631 A JP2016530631 A JP 2016530631A
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- Prior art keywords
- output
- vector
- elements
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- arithmetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Advance Control (AREA)
- Complex Calculations (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/967,191 | 2013-08-14 | ||
| US13/967,191 US20150052330A1 (en) | 2013-08-14 | 2013-08-14 | Vector arithmetic reduction |
| PCT/US2014/049604 WO2015023465A1 (en) | 2013-08-14 | 2014-08-04 | Vector accumulation method and apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2016530631A true JP2016530631A (ja) | 2016-09-29 |
| JP2016530631A5 JP2016530631A5 (enExample) | 2017-08-31 |
Family
ID=51492424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016534602A Pending JP2016530631A (ja) | 2013-08-14 | 2014-08-04 | ベクトルの算術的削減 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20150052330A1 (enExample) |
| EP (1) | EP3033670B1 (enExample) |
| JP (1) | JP2016530631A (enExample) |
| CN (1) | CN105453028B (enExample) |
| TW (1) | TWI507982B (enExample) |
| WO (1) | WO2015023465A1 (enExample) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020513120A (ja) * | 2017-04-03 | 2020-04-30 | グーグル エルエルシー | ベクトル縮小プロセッサ |
| JP2023515348A (ja) * | 2020-02-10 | 2023-04-13 | エックスモス リミテッド | ベクトル演算の回転累算器 |
| US12499081B2 (en) | 2024-01-31 | 2025-12-16 | Google Llc | Vector reduction processor |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9678715B2 (en) | 2014-10-30 | 2017-06-13 | Arm Limited | Multi-element comparison and multi-element addition |
| US20160179530A1 (en) * | 2014-12-23 | 2016-06-23 | Elmoustapha Ould-Ahmed-Vall | Instruction and logic to perform a vector saturated doubleword/quadword add |
| US10296342B2 (en) | 2016-07-02 | 2019-05-21 | Intel Corporation | Systems, apparatuses, and methods for cumulative summation |
| US10466967B2 (en) | 2016-07-29 | 2019-11-05 | Qualcomm Incorporated | System and method for piecewise linear approximation |
| US10331445B2 (en) * | 2017-05-24 | 2019-06-25 | Microsoft Technology Licensing, Llc | Multifunction vector processor circuits |
| GB2574817B (en) * | 2018-06-18 | 2021-01-06 | Advanced Risc Mach Ltd | Data processing systems |
| US11294670B2 (en) * | 2019-03-27 | 2022-04-05 | Intel Corporation | Method and apparatus for performing reduction operations on a plurality of associated data element values |
| CN110807521B (zh) * | 2019-10-29 | 2022-06-24 | 中昊芯英(杭州)科技有限公司 | 支持向量运算的处理装置、芯片、电子设备和方法 |
| US20240004647A1 (en) * | 2022-07-01 | 2024-01-04 | Andes Technology Corporation | Vector processor with vector and element reduction method |
| US20250208878A1 (en) * | 2023-12-20 | 2025-06-26 | Advanced Micro Devices, Inc. | Accumulation apertures |
Citations (8)
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| JPH02210538A (ja) * | 1988-10-05 | 1990-08-21 | United Technol Corp <Utc> | 集積回路と演算処理システム |
| JPH0773149A (ja) * | 1993-03-31 | 1995-03-17 | Motorola Inc | データ処理システムとその方法 |
| JPH07271969A (ja) * | 1993-11-30 | 1995-10-20 | Texas Instr Inc <Ti> | レジスタ対から条件付きでメモリへ記憶させる装置 |
| JP2006529043A (ja) * | 2003-05-09 | 2006-12-28 | サンドブリッジ テクノロジーズ インコーポレーテッド | 飽和あり、または飽和なしで、オペランドの積和を実行するプロセッサ簡約ユニット |
| JP2011509476A (ja) * | 2008-01-11 | 2011-03-24 | インターナショナル・ビジネス・マシーンズ・コーポレーション | コンピュータ・システム、その動作方法、及び、コンピュータ・プログラム |
| WO2013095634A1 (en) * | 2011-12-23 | 2013-06-27 | Intel Corporation | Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction |
| JP2014229133A (ja) * | 2013-05-23 | 2014-12-08 | 富士通株式会社 | 移動平均処理プログラム、及びプロセッサ |
| JP2016510461A (ja) * | 2013-01-23 | 2016-04-07 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | Vectorelementrotateandinsertundermask命令を処理するためのコンピュータ・プログラム、コンピュータ・システム及び方法 |
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| US5542074A (en) * | 1992-10-22 | 1996-07-30 | Maspar Computer Corporation | Parallel processor system with highly flexible local control capability, including selective inversion of instruction signal and control of bit shift amount |
| US5727229A (en) * | 1996-02-05 | 1998-03-10 | Motorola, Inc. | Method and apparatus for moving data in a parallel processor |
| US6542918B1 (en) * | 1996-06-21 | 2003-04-01 | Ramot At Tel Aviv University Ltd. | Prefix sums and an application thereof |
| US5845112A (en) * | 1997-03-06 | 1998-12-01 | Samsung Electronics Co., Ltd. | Method for performing dead-zone quantization in a single processor instruction |
| US5864703A (en) * | 1997-10-09 | 1999-01-26 | Mips Technologies, Inc. | Method for providing extended precision in SIMD vector arithmetic operations |
| US6418529B1 (en) * | 1998-03-31 | 2002-07-09 | Intel Corporation | Apparatus and method for performing intra-add operation |
| US7395302B2 (en) * | 1998-03-31 | 2008-07-01 | Intel Corporation | Method and apparatus for performing horizontal addition and subtraction |
| US6295597B1 (en) * | 1998-08-11 | 2001-09-25 | Cray, Inc. | Apparatus and method for improved vector processing to support extended-length integer arithmetic |
| US6192384B1 (en) * | 1998-09-14 | 2001-02-20 | The Board Of Trustees Of The Leland Stanford Junior University | System and method for performing compound vector operations |
| US6324638B1 (en) * | 1999-03-31 | 2001-11-27 | International Business Machines Corporation | Processor having vector processing capability and method for executing a vector instruction in a processor |
| US7624138B2 (en) * | 2001-10-29 | 2009-11-24 | Intel Corporation | Method and apparatus for efficient integer transform |
| US6920545B2 (en) * | 2002-01-17 | 2005-07-19 | Raytheon Company | Reconfigurable processor with alternately interconnected arithmetic and memory nodes of crossbar switched cluster |
| US7376812B1 (en) * | 2002-05-13 | 2008-05-20 | Tensilica, Inc. | Vector co-processor for configurable and extensible processor architecture |
| US7159099B2 (en) * | 2002-06-28 | 2007-01-02 | Motorola, Inc. | Streaming vector processor with reconfigurable interconnection switch |
| US7051186B2 (en) * | 2002-08-29 | 2006-05-23 | International Business Machines Corporation | Selective bypassing of a multi-port register file |
| TWI221562B (en) * | 2002-12-12 | 2004-10-01 | Chung Shan Inst Of Science | C6x_VSP-C6x vector signal processor |
| US7293056B2 (en) * | 2002-12-18 | 2007-11-06 | Intel Corporation | Variable width, at least six-way addition/accumulation instructions |
| US20040193847A1 (en) * | 2003-03-31 | 2004-09-30 | Lee Ruby B. | Intra-register subword-add instructions |
| TW200504592A (en) * | 2003-07-24 | 2005-02-01 | Ind Tech Res Inst | Reconfigurable apparatus with high hardware efficiency |
| US7797363B2 (en) * | 2004-04-07 | 2010-09-14 | Sandbridge Technologies, Inc. | Processor having parallel vector multiply and reduce operations with sequential semantics |
| DE102006027181B4 (de) * | 2006-06-12 | 2010-10-14 | Universität Augsburg | Prozessor mit internem Raster von Ausführungseinheiten |
| US8429384B2 (en) * | 2006-07-11 | 2013-04-23 | Harman International Industries, Incorporated | Interleaved hardware multithreading processor architecture |
| US7725518B1 (en) * | 2007-08-08 | 2010-05-25 | Nvidia Corporation | Work-efficient parallel prefix sum algorithm for graphics processing units |
| US8996846B2 (en) * | 2007-09-27 | 2015-03-31 | Nvidia Corporation | System, method and computer program product for performing a scan operation |
| US8661226B2 (en) * | 2007-11-15 | 2014-02-25 | Nvidia Corporation | System, method, and computer program product for performing a scan operation on a sequence of single-bit values using a parallel processor architecture |
| US8856492B2 (en) * | 2008-05-30 | 2014-10-07 | Nxp B.V. | Method for vector processing |
| US8131979B2 (en) * | 2008-08-15 | 2012-03-06 | Apple Inc. | Check-hazard instructions for processing vectors |
| US9176735B2 (en) * | 2008-11-28 | 2015-11-03 | Intel Corporation | Digital signal processor having instruction set with one or more non-linear complex functions |
| US8595467B2 (en) * | 2009-12-29 | 2013-11-26 | International Business Machines Corporation | Floating point collect and operate |
| US8667042B2 (en) * | 2010-09-24 | 2014-03-04 | Intel Corporation | Functional unit for vector integer multiply add instruction |
| US8868885B2 (en) * | 2010-11-18 | 2014-10-21 | Ceva D.S.P. Ltd. | On-the-fly permutation of vector elements for executing successive elemental instructions |
| WO2012134532A1 (en) * | 2011-04-01 | 2012-10-04 | Intel Corporation | Vector friendly instruction format and execution thereof |
| US9760372B2 (en) * | 2011-09-01 | 2017-09-12 | Hewlett Packard Enterprise Development Lp | Parallel processing in plural processors with result register each performing associative operation on respective column data |
| US9411583B2 (en) * | 2011-12-22 | 2016-08-09 | Intel Corporation | Vector instruction for presenting complex conjugates of respective complex numbers |
| WO2013095631A1 (en) * | 2011-12-23 | 2013-06-27 | Intel Corporation | Systems, apparatuses, and methods for performing a butterfly horizontal and cross add or substract in response to a single instruction |
-
2013
- 2013-08-14 US US13/967,191 patent/US20150052330A1/en not_active Abandoned
-
2014
- 2014-08-04 CN CN201480043504.XA patent/CN105453028B/zh active Active
- 2014-08-04 WO PCT/US2014/049604 patent/WO2015023465A1/en not_active Ceased
- 2014-08-04 EP EP14759362.8A patent/EP3033670B1/en active Active
- 2014-08-04 JP JP2016534602A patent/JP2016530631A/ja active Pending
- 2014-08-07 TW TW103127139A patent/TWI507982B/zh not_active IP Right Cessation
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02210538A (ja) * | 1988-10-05 | 1990-08-21 | United Technol Corp <Utc> | 集積回路と演算処理システム |
| JPH0773149A (ja) * | 1993-03-31 | 1995-03-17 | Motorola Inc | データ処理システムとその方法 |
| JPH07271969A (ja) * | 1993-11-30 | 1995-10-20 | Texas Instr Inc <Ti> | レジスタ対から条件付きでメモリへ記憶させる装置 |
| JP2006529043A (ja) * | 2003-05-09 | 2006-12-28 | サンドブリッジ テクノロジーズ インコーポレーテッド | 飽和あり、または飽和なしで、オペランドの積和を実行するプロセッサ簡約ユニット |
| JP2011509476A (ja) * | 2008-01-11 | 2011-03-24 | インターナショナル・ビジネス・マシーンズ・コーポレーション | コンピュータ・システム、その動作方法、及び、コンピュータ・プログラム |
| WO2013095634A1 (en) * | 2011-12-23 | 2013-06-27 | Intel Corporation | Systems, apparatuses, and methods for performing a horizontal partial sum in response to a single instruction |
| JP2016510461A (ja) * | 2013-01-23 | 2016-04-07 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | Vectorelementrotateandinsertundermask命令を処理するためのコンピュータ・プログラム、コンピュータ・システム及び方法 |
| JP2014229133A (ja) * | 2013-05-23 | 2014-12-08 | 富士通株式会社 | 移動平均処理プログラム、及びプロセッサ |
Non-Patent Citations (1)
| Title |
|---|
| 五月女哲夫,小林達也,織田篤史: "徹底解説! ARMプロセッサ", INTERFACE, vol. 第29巻,第8号, JPN6019000555, 1 August 2003 (2003-08-01), JP, pages 76 - 80, ISSN: 0003958144 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020513120A (ja) * | 2017-04-03 | 2020-04-30 | グーグル エルエルシー | ベクトル縮小プロセッサ |
| JP7055809B2 (ja) | 2017-04-03 | 2022-04-18 | グーグル エルエルシー | ベクトル縮小プロセッサ |
| JP2022095817A (ja) * | 2017-04-03 | 2022-06-28 | グーグル エルエルシー | ベクトル縮小プロセッサ |
| JP7256914B2 (ja) | 2017-04-03 | 2023-04-12 | グーグル エルエルシー | ベクトル縮小プロセッサ |
| US11940946B2 (en) | 2017-04-03 | 2024-03-26 | Google Llc | Vector reduction processor |
| JP2023515348A (ja) * | 2020-02-10 | 2023-04-13 | エックスモス リミテッド | ベクトル演算の回転累算器 |
| JP7439276B2 (ja) | 2020-02-10 | 2024-02-27 | エックスモス リミテッド | ベクトル演算の回転累算器 |
| US12499081B2 (en) | 2024-01-31 | 2025-12-16 | Google Llc | Vector reduction processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105453028A (zh) | 2016-03-30 |
| TWI507982B (zh) | 2015-11-11 |
| CN105453028B (zh) | 2019-04-09 |
| EP3033670B1 (en) | 2019-11-06 |
| WO2015023465A1 (en) | 2015-02-19 |
| US20150052330A1 (en) | 2015-02-19 |
| TW201519090A (zh) | 2015-05-16 |
| EP3033670A1 (en) | 2016-06-22 |
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