JP2016514882A5 - - Google Patents

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Publication number
JP2016514882A5
JP2016514882A5 JP2016507630A JP2016507630A JP2016514882A5 JP 2016514882 A5 JP2016514882 A5 JP 2016514882A5 JP 2016507630 A JP2016507630 A JP 2016507630A JP 2016507630 A JP2016507630 A JP 2016507630A JP 2016514882 A5 JP2016514882 A5 JP 2016514882A5
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Japan
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state
response
processor
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JP2016507630A
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Japanese (ja)
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JP5996828B2 (ja
JP2016514882A (ja
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Priority claimed from US13/933,337 external-priority patent/US9292442B2/en
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JP2016507630A 2013-04-11 2014-04-09 コヒーレントバスを介したセマフォ管理シーケンスのパフォーマンスを改善するための方法および装置 Expired - Fee Related JP5996828B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361810889P 2013-04-11 2013-04-11
US61/810,889 2013-04-11
US13/933,337 US9292442B2 (en) 2013-04-11 2013-07-02 Methods and apparatus for improving performance of semaphore management sequences across a coherent bus
US13/933,337 2013-07-02
PCT/US2014/033474 WO2014169025A1 (en) 2013-04-11 2014-04-09 Methods and apparatus for improving performance of semaphore management sequences across a coherent bus

Publications (3)

Publication Number Publication Date
JP2016514882A JP2016514882A (ja) 2016-05-23
JP2016514882A5 true JP2016514882A5 (enExample) 2016-07-21
JP5996828B2 JP5996828B2 (ja) 2016-09-21

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016507630A Expired - Fee Related JP5996828B2 (ja) 2013-04-11 2014-04-09 コヒーレントバスを介したセマフォ管理シーケンスのパフォーマンスを改善するための方法および装置

Country Status (6)

Country Link
US (1) US9292442B2 (enExample)
EP (1) EP2984571A1 (enExample)
JP (1) JP5996828B2 (enExample)
KR (1) KR101651192B1 (enExample)
CN (1) CN105103139B (enExample)
WO (1) WO2014169025A1 (enExample)

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* Cited by examiner, † Cited by third party
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TWI507991B (zh) * 2013-02-27 2015-11-11 Rdc Semiconductor Co Ltd 多核心處理器及其相關控制方法與電腦系統
US11269773B2 (en) 2019-10-08 2022-03-08 Arm Limited Exclusivity in circuitry having a home node providing coherency control
US11467964B1 (en) 2020-03-09 2022-10-11 Marvell Asia Pte Ltd Mergeable counter system and method
US11379370B1 (en) * 2020-04-08 2022-07-05 Marvell Asia Pte Ltd System and methods for reducing global coherence unit snoop filter lookup via local memories
US12020028B2 (en) * 2020-12-26 2024-06-25 Intel Corporation Apparatuses, methods, and systems for 8-bit floating-point matrix dot product instructions

Family Cites Families (20)

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US5440752A (en) * 1991-07-08 1995-08-08 Seiko Epson Corporation Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
US6073211A (en) * 1994-12-13 2000-06-06 International Business Machines Corporation Method and system for memory updates within a multiprocessor data processing system
US6138218A (en) * 1998-02-17 2000-10-24 International Business Machines Corporation Forward progress on retried snoop hits by altering the coherency state of a local cache
US6279085B1 (en) * 1999-02-26 2001-08-21 International Business Machines Corporation Method and system for avoiding livelocks due to colliding writebacks within a non-uniform memory access system
US6269428B1 (en) * 1999-02-26 2001-07-31 International Business Machines Corporation Method and system for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system
US6629209B1 (en) 1999-11-09 2003-09-30 International Business Machines Corporation Cache coherency protocol permitting sharing of a locked data granule
US6594736B1 (en) 2000-08-15 2003-07-15 Src Computers, Inc. System and method for semaphore and atomic operation management in a multiprocessor
US20030131201A1 (en) * 2000-12-29 2003-07-10 Manoj Khare Mechanism for efficiently supporting the full MESI (modified, exclusive, shared, invalid) protocol in a cache coherent multi-node shared memory system
US6745294B1 (en) 2001-06-08 2004-06-01 Hewlett-Packard Development Company, L.P. Multi-processor computer system with lock driven cache-flushing system
US6892258B1 (en) * 2001-10-26 2005-05-10 Lsi Logic Corporation Hardware semaphores for a multi-processor system within a shared memory architecture
US6986013B2 (en) * 2002-12-05 2006-01-10 International Business Machines Corporation Imprecise cache line protection mechanism during a memory clone operation
US20050102457A1 (en) * 2003-11-12 2005-05-12 Dell Products L.P. System and method for interrupt processing in a multiple processor system
US7991966B2 (en) * 2004-12-29 2011-08-02 Intel Corporation Efficient usage of last level caches in a MCMP system using application level configuration
US20060271717A1 (en) * 2005-05-27 2006-11-30 Raja Koduri Frame synchronization in multiple video processing unit (VPU) systems
US8209492B2 (en) * 2005-06-14 2012-06-26 Hewlett-Packard Development Company, L.P. Systems and methods of accessing common registers in a multi-core processor
US7421529B2 (en) * 2005-10-20 2008-09-02 Qualcomm Incorporated Method and apparatus to clear semaphore reservation for exclusive access to shared memory
US7769958B2 (en) 2007-06-22 2010-08-03 Mips Technologies, Inc. Avoiding livelock using intervention messages in multiple core processors
US7984244B2 (en) 2007-12-28 2011-07-19 Intel Corporation Method and apparatus for supporting scalable coherence on many-core products through restricted exposure
US9547596B2 (en) 2009-12-24 2017-01-17 Arm Limited Handling of a wait for event operation within a data processing apparatus
GB2491350B (en) * 2011-05-27 2020-02-12 Advanced Risc Mach Ltd Store-exclusive instruction conflict resolution

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