JP2016502206A - Hierarchical power map for low power design - Google Patents

Abstract

The power information associated with the IC design is displayed graphically and hierarchically using a power map, thereby distributing power among the various power domains of the IC and the multiple parents within those power domains. -Provide an intuitive way to express child relationships. Each power domain is associated with power control for controlling the power domain. The power control status of each power domain is displayed on the power map. The power map may include a token for setting and displaying the current operating mode of the IC design to allow the IC design to be debugged under a plurality of different operating modes.

Description

[Cross-reference of related applications]
This application is the priority of US Patent Provisional Application No. 61 / 358,002, filed June 24, 2010, entitled “Method and system for displaying IC design intent with power domain intent”. 12/2012, part of continuation of US application 13 / 158,471, entitled “Hierarchical power map for low power design”, filed June 13, 2011, claiming benefit Claiming priority to US patent application Ser. No. 13 / 718,979, entitled “Hierarchical power map for low power design” filed on Jan. 18, All contents in their entirety by reference are incorporated herein.

  The present invention relates to a computer-implemented method for debugging a low power integrated circuit (IC) design, and more particularly to creating an integrated graphic user interface to debug an IC design and provide a map of its power usage. Regarding the method.

  A number of mobile and consumer electronic devices are widely used, such as personal mobile computers, MP3 audio players, notebooks, and digital cameras. The trend toward lower power consumption in increasingly thinner and lighter products requires the integration of multiple components on the IC. For example, as more circuitry is integrated on a system-on-chip (SoC) IC to perform increasingly complex functions at low power, the IC becomes more difficult to debug. In many low power designs, the circuit is divided into a number of parts called power domains, each of which can be associated with a power source. A power domain is a collection of instances, pins, and ports that can share the same power distribution network (voltage). Some of the plurality of power domains can be turned on or off by a power switch. The plurality of power switches are used to turn off a plurality of unused parts in the design in order to save power consumption.

  Isolation cells are used to isolate multiple signals between two power domains, one switched on and one switched off. A plurality of such cells are used to isolate a plurality of signals generated in a power domain that has been switched off. An isolation cell has its output having a predetermined or latched value when the power domain is turned off, thereby leaving other active domains unaffected Make sure.

  A level shifter is generally required to change one voltage level to another voltage level between different power domains. Therefore, low power SoC ICs often include power network circuits having multiple power components in addition to multiple digital circuits.

  Referring to FIG. 1, in a conventional manner, digital circuit design is implemented in a hardware description language (HDL), such as Verilog code 1. The term “power supply specification” is defined herein as a description of the power intent (intended power supply behavior) of a circuit design. In order to implement a low power network, Cadence Common Power Format to capture the power information to allow designers to implement a low power network design in a separate file without changing Verilog code 1. A power supply description 2 described in a power supply format such as (CPF) or Unified Power Format (UPF) is usually used. The power format describes a low power intent for design implementation, analysis, and verification.

  A power network is designated to control power distribution in order to specify multiple constraints of the low power design to minimize energy consumption. Using UPF, a network can be specified at an abstract level. Such a network includes multiple supply ports, multiple supply nets, multiple power switches, and is a high level abstraction of the electrical circuit network on the power supply side of the chip. Multiple supply ports provide multiple supply interfaces to multiple power domains and multiple power switches, while multiple supply nets connect multiple supply ports. Since the supply network is specified separately from the logic design, the logic design specification remains independent of multiple power supply network specifications.

  Since conventional hardware description language (HDL) is not sufficient to specify power design information, power supply formats such as UPF provide a format without changing existing HDL code. For example, the UPF provides a create_power_domain command for creating a power domain and grouping multiple design instances associated with the power domain. Other multiple power components, such as multiple power switches, multiple isolation cells, and multiple level shifters, can be created using corresponding multiple commands defined by multiple power supply formats.

  Given Verilog design and power design based on the power supply format, the IC design can be analyzed and debugged. However, as long as the conventional circuit design file is separate from the power network design, to debug the circuit, the designer needs to establish a relationship between these two files.

  In addition, circuit designers are focused on multiple functions of the circuit design and are focused on creating multiple hierarchies based on the functional and logical aspects of the design. However, power designers prefer to have multiple design hierarchies in physical form that can be defined by a power supply format having multiple power domains within a power network design. As a result, if the low power network design does not appear at the top level and does not interact with the power designer, it is inefficient and error prone for designers to debug the entire chip. There continues to be a need for more efficient and reliable techniques for designing multiple low power circuits.

  According to embodiments of the present invention, power supply information called a power map is displayed in a graphic window to enable easy debugging, and the power structure and the relationship between power network design and circuit design. , Help multiple users to quickly understand. The power map includes a plurality of power domains, a plurality of isolation cells, a plurality of level shifters, a plurality of power switches, and a plurality of power supplies.

  One embodiment of the present invention provides a computer-implemented method for generating and displaying a power map. The power map is a top-level low power network design based on the low power information defined in the power format to allow designers to debug the low power network design and its associated circuit design. And in those designs, the power map comprises a plurality of power domain symbols that represent a plurality of power domains and that are linked to a plurality of associated portions of the circuit design.

  In one embodiment of the present invention, a method is provided for generating and displaying a power map according to the following steps: First, a plurality of original circuit design HDL codes, which are several text files, are converted into an internal structure that is a hierarchical structure, usually called a circuit design hierarchy, and stored in a knowledge database generated by an HDL parser. The multiple original circuit design hierarchies of the knowledge database are regrouped into new hierarchies defined by the power supply specifications. In multiple new hierarchies, multiple instances sharing the same power domain are grouped together. Thereafter, a plurality of new hierarchies called a plurality of power domain circuit design hierarchies are stored in the power supply database. Finally, a power map is created from the power database. It may also indicate multiple discrepancies or multiple errors between power supply specifications and circuit design for those improperly processed signals connecting multiple power domains.

  The present invention discloses that the power map comprises a plurality of low power symbols such as a plurality of power domain symbols, a plurality of isolation cells, a plurality of level shifter cells, and a plurality of power switch cells. Furthermore, to provide designers with debugging information, the power map can display multiple current values of simulation results for multiple signals in the power map at a particular simulation time, or By dragging and dropping the selected signal to the waveform window, it is used together with the simulation result such as displaying a plurality of waveforms of the simulation result in the simulation period on the waveform window. In addition, the power map also provides a methodology for detecting which multiple HDL signals are not covered by the isolation and level shifter connections and automatically activate this function when the power map is created To do.

  A feature of the power map displayed in the graphics window is that it provides some active annotation to facilitate communication and interaction with multiple users. Thus, it is more user-friendly to have multiple users debug the power network along with the digital circuit design in the interactive interface.

  Another object of the present invention is to display low power information with a hierarchical representation of multiple power domains in a graphic window to provide an intuitive way to view multiple parent-child relationships between multiple power domains. Is to provide a solution for this.

  One embodiment of the present invention provides a method for generating and displaying a power map in a hierarchical representation. The power map includes a plurality of power domains, and each of the plurality of power domains is associated with a part of a circuit design belonging to the power domain, and the plurality of power domains includes a plurality of boundaries between the power domains. Grouped into a plurality of sets of power domains with expressions representing a plurality of parent-child relationships. To present a hierarchical power map, the at least one set of power domains includes at least two power domains in which a parent power domain and at least one child power domain within the parent power domain exist. Each of the plurality of power domains is associated with a corresponding power control for controlling the power domain, and the status of the power control is displayed on the power map.

  One embodiment of the power map is generated to debug an IC design having a plurality of different operating modes, the power map comprising a token for setting and displaying the current mode of the IC design. When the current mode is changed to a new mode, the multiple power domains of the power map are redrawn under the new mode of IC design as specified in the low power specification.

  The detailed technology implemented for the present invention and the preferred embodiments described above are described in the following paragraphs with the accompanying drawings in order to enable those skilled in the art to better understand the features of the claimed invention. Described in.

  Many of the foregoing aspects and attendant advantages of the present invention will become easier as they become better understood by reference to the following detailed description, taken in conjunction with the accompanying drawings, in which: Will be understood.

1 illustrates a conventional low power digital circuit design methodology.

4 is a flowchart of multiple steps performed to create a power map, in accordance with one embodiment of the present invention.

Fig. 4 illustrates a hierarchical circuit design defined by a power supply specification after regrouping the original circuit design hierarchy, according to one embodiment of the present invention.

FIG. 3 is a schematic diagram showing a power map according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating an isolation rule according to an embodiment of the present invention.

It is the schematic which shows the level shifter rule by one Embodiment of this invention.

FIG. 3 is a schematic diagram illustrating a power switch rule according to an embodiment of the present invention.

4 is a signal value list window according to an embodiment of the present invention.

4 is a waveform window according to an embodiment of the present invention.

FIG. 6 illustrates a hierarchical representation of a power map by grouping multiple power domains in a circuit design according to power control and multiple parent-child relationships between multiple power domains, according to one embodiment of the present invention. .

FIG. 6 is a flowchart of multiple steps performed in creating a hierarchical representation of a power map, in accordance with one embodiment of the present invention.

  FIG. 2 is a flowchart for creating a power map of an integrated circuit (IC) according to an embodiment of the present invention. 3, the original text-based circuit design HDL code is parsed, converted to an internal structure, and stored in a knowledge database. A knowledge database that can be generated by an HDL parser is an internal computer readable data structure (which can have a hierarchical or flat structure) of a circuit design and can be manipulated or controlled by software. 4, a plurality of power designs described in CPF or UPF is parsed by CPF or UPF parser and converted into an internal structure. The original circuit design hierarchy in the knowledge database is then regrouped into a plurality of new design hierarchies defined by a power supply specification having multiple power domains. In multiple new hierarchies, multiple instances sharing the same power domain are grouped together. It should be understood that the original design is not limited to a hierarchical or flat design. If the original circuit design is flattened and stored in the knowledge database, it can be divided into multiple power domains. At 5, a plurality of new design hierarchies are stored in the power supply database and converted to an internal structure that is a computer readable data structure for circuit design and power design. The power database can be manipulated, controlled, or modified by software.

  At 6, a power map is created based on the power database and displayed by a user friendly GUI (Graphical User Interface) window. The power map may include a number of objects such as multiple power domain symbols and multiple isolation cells, as described in detail below. When a power domain in the power map is activated in a user-friendly GUI window, for example, when the user clicks, the circuit design associated with the power domain is activated. Therefore, whole-chip debugging with power network design and associated HDL code is more efficient and simpler than conventional technologies.

  At 7, static checks can be performed to identify multiple discrepancies or errors between power supply specifications and circuit design for improperly processed signals connecting multiple power domains. As shown at 8, such mismatches or errors may be indicated to multiple users by multiple annotations, such as multiple dotted lines, multiple symbols, or multiple colored highlights.

  Referring to FIG. 3, frame 9 shows a power map, in which the HDL original circuit design hierarchy 11 is defined by the power specifications and regrouped into a new hierarchy 10 having multiple power domains. Is done. Each power domain includes multiple instances from the circuit design that share the same power domain. The original design hierarchy 11 has a top level that includes multiple instances including module power supply_control with three instances, PD_control_1, PD_control_2, and PD_control_3. After regrouping in the power map, a top level called PM_Top is created. The instance PD_control_1 is associated with the power domain PD1 and disposed under the power domain PD1, the instance PD_control_2 is associated with the power domain PD2 and disposed under the power domain PD2, and the instance PD_control_3 is associated with the power domain It is associated with PD3 and placed under power domain PD3.

  After multiple new hierarchies are defined by a power specification with multiple power domains, they can be stored in a power database, which is an internal computer readable data structure that integrates circuit design and power network design information. The power database can be manipulated or controlled by software.

  After the power database is generated, the power map can be used to display the power network design, as shown in FIG. 4A. The power map 12 includes a number of power domain symbols 13, 14, and 15, connected to a plurality of grounds 19b, at least one isolation cell 16, at least one level shifter cell 17, at least one power switch cell 18, and at least one. Two power supplies 19a are shown to be included.

  The isolation cell 16 representing an isolation command includes a number of isolation nets 20 for connection to a plurality of power supply domains and an isolation state net 21 for presenting an isolation state expression. The isolation cell 16 is shown to display a trigger status symbol located at the upper left of the isolation cell 16. If the associated state value is “1”, the trigger status is successful, the trigger status symbol displays the up arrow 22a, otherwise the trigger status symbol displays the down arrow 22b.

  A level shifter cell 17 representing a level shifter command may include a number of level shifter nets 23 for connection to a plurality of power supply domains.

  A power switch cell 18 representing a power switch may include a number of power switch nets 24 for connection to a power source 19a, or one or more power domains, or other power switch cells. In addition, the power switch cell 18 also includes a status pin 26. When the user turns on active annotation, state value 25 is annotated on state pin 26. Active annotation provides interaction with the power map and easy communication. Active annotation can be turned on by an “active annotation mechanism”. For example, it can be turned on by clicking on the highlighted icon or symbol to annotate the state value 25 on the state pin 26, or by selecting an item using a mouse button.

  In addition, in one embodiment, the power map shows a red dotted line with a mark of “iso” 27 to display a signal without proper isolation, and a “lvs” 28 to display a signal without a level shifter. Use a red dotted line with a mark.

The rules for each power component used in the power map are as follows.
Isolation rules (CPF / UPF).

Referring to FIG. 4B, the power map uses isolation cells 16 that represent isolation commands in the power specifications. The isolation cell 16 includes an isolation state net 21 to present an isolation state representation. The isolation cell 16 displays an isolation trigger status symbol on the upper left of the isolation cell. If the associated state value is “1”, the trigger status is successful and the trigger status symbol displays an up arrow, otherwise the trigger status displays a down arrow 22b.
Level shifter rule (CPF / UPF).

Referring to FIG. 4C, the power map uses level shifter cells 17 to represent level shifter commands.
Power switch (CPF / UPF).
Referring to FIG. 4D, the power map uses the power switch cell 18 to represent the power switch, so that if the user turns on the active annotation (such as by clicking on the power switch cell 18), the status pin 26 The power switch state value 25 is shown above.
Connections not covered.

  Signal connections that connect to multiple power domains but are not specified by multiple isolation rules and / or level shifter rules in the power specification are called non-exhaustive connections. Referring to FIG. 4A, power map 12 provides a methodology for detecting which multiple HDL signals are not properly covered by multiple isolation rules or multiple level shifter rules, thereby providing a power map. This function is automatically activated when 12 is created. In one embodiment, the power map 12 displays a red dotted line with an “iso” 27 mark to display a signal without proper isolation, and an “lvs” 28 mark to display a signal without a level shifter. Use a red dotted line with

  After the power map is generated, static checks are performed to detect multiple mismatches or multiple errors between the power supply specification and the circuit design, where the user encounters such multiple mismatches or multiple errors. You can tell if you are. There can be many ways for multiple mismatches or multiple errors to occur. For example, the connection may be wrong in the cell connection of the isolation / level shifter, and the control signal may be lost or mismatched in the power control signal connected to the power switch. Mismatch, or lost control signals, or wasted due to lost isolation cells and / or level shifter cells for multiple nets connected to multiple power domains There may be multiple isolation connections that are properly covered, or level shifter connections that are inappropriately covered. In addition, to ensure that there are both isolation connections and level shifter connections between two power domains with multiple HDL signals, the power map has a multiple between them to alert the designers. Virtual nets (alternatively referred to herein as a plurality of virtual power rule nets). For example, if two power domains do not have an isolation connection and / or level shifter connection between them, the power map creates a virtual level shifter power rule net and / or a virtual isolation power rule net between them . Each of the plurality of overcrowded signals of the two virtual power rule nets is an HDL signal between the two power domains.

  Referring to FIG. 4A, each power domain symbol can be activated to link to a portion of the circuit design associated with the power domain. In one embodiment, when the user activates the power domain symbol 13 by clicking on it, the portion of the circuit design associated with that power domain debugs the entire chip including the power network design and the original HDL code. Thus, it can be activated to allow the user to view the circuit design.

  The power map is further adapted to display a plurality of current values of a plurality of simulated signals at any simulation time. In one embodiment, the power map includes a signal value list window 29, as shown in FIG. 5, to make debugging easier. When the user turns on active annotation, such as by clicking on a highlighted icon or symbol, or selecting an item with the mouse, the signal value list window 29 is for that particular simulation time. Display a plurality of values of a corresponding plurality of simulated signals in the power map. Further, in one embodiment, as shown in FIG. 6, the power map using the waveform window 30 can include a plurality of simulation waveforms (arbitrary) when the user drags and drops a plurality of selected signals in the power map. Display the simulation period). For example, if a user drags an isolation cell and drops it on the waveform window 30, that isolation level is connected—and multiple variables (VBs) —multiple nets automatically in the waveform window 30. As a result, automatically resulting in the display of those waveforms during the simulation period, as shown in FIG. Similarly, waveforms of multiple signals of a power component (eg, power domain, PD) can also be displayed in the waveform window 30. In yet another embodiment, when the user moves the cursor in the waveform window 30 to a simulation time, multiple nets in the power map are annotated with their associated signal values at that particular time. Therefore, according to embodiments of the present invention, the process of debugging power network and digital circuit design is made easier and more efficient than conventional techniques.

  FIG. 7 shows a hierarchical power map in which multiple power domains of a circuit design are grouped according to a specification that includes multiple boundaries of the power domains, as well as representations of multiple parent-child relationships within the multiple power domains. Each power map is associated with a power control for controlling that power domain. As can be seen from FIG. 7, the top level of the power map called PD_TOP 700 is shown to include three sets of parent power domains: PD_CPU 710, PD_FSM 721, and PD_RAM 731. The power domain PD_CPU 710 is shown to include three child power domains, namely PD_ALUB 711, PD_PCU 712, and PD_CCU 713, inside the rectangle representing the parent power domain PD_CPU 700. One power domain PD_alu 714 is shown in PD_ALUB 711, indicating that there is a parent-child relationship between the parent power domain PD_ALUB 711 and the child power domain PD_alu 714. Although FIG. 7 shows a power map of a three level hierarchy, it should be understood that the hierarchy of the power map may include more levels. The top level hierarchy is also shown to include a second power domain set PD_FSM 721 and a third power domain set PD_RAM 731. The child power domain is not shown in the power domain PD_FSM 721 or the PD_RAM 731. To present a hierarchical power map, the at least one set of power domains includes at least two power domains: a parent power domain and at least one child power domain within the parent power domain. Each of the plurality of power domains is associated with a corresponding power control for controlling the power domain. The power control status is displayed on the power map. Power control of the parent power domain can be used to control its child power domains as well. For example, in one embodiment, when a parent power domain is powered off, all of the child domains within the parent power domain are similarly turned off. However, when the parent power domain is powered on, each of the multiple child power domains can be automatically turned on or, if necessary, subject to additional local power control associated with that child power domain. It's okay.

  The status 701 of the first power control of the first set of power domain PD_CPU 710 is displayed along the shape of the first rectangle. For example, the status 701 of the first power supply control PD_CPU indicates that the power domain of the first set is ON at a voltage level of 1.2V. Similarly, the power control statuses of the power domains PD_ALUB 711, PD_PCU 712, PD_CCU 713, PD_FSM 721, and PD_RAM 731 are displayed as 702, 704, 703, 705, and 706, respectively. In another example, the power control status 705 of the power domain PD_FSM 721 indicates that the power of the PD_FSM 721 is changed from ON to OFF. The status of the power control 706 of the power domain PD_RAM 731 indicates that the power of the PD_RAM 731 is ON at a voltage level of 0.8V. To aid in circuit debugging, static checks also identify multiple discrepancies or multiple errors between power specifications and circuit design for improperly processed signals that connect multiple power domains. Can be executed to As shown in FIG. 7, such mismatches or errors may be indicated to multiple users by one or more annotations such as dotted lines, symbols, or colored highlights. . Connection 731 between power domain PD_CPU 710 and PD_FSM 721, which is a plurality of connections between power domains or between hierarchical blocks of power domains without an isolation cell or level shifter cell, power supply A connection 732 between the domain PD_ALUB 711 and the PD_FSM 721, a connection 734 between the power domain PD_alu 714 and the PD_CCU 713, a connection 733 between the power domain PD_PCU 712 and the PD_CCU 713, and the like can be highlighted with a plurality of dotted lines.

  Isolation cell 754 is shown as connecting power domain PD_ALUB 711 to PD_FSM 721 and having a logic “high” clamp value. Similarly, isolation cell 755 is shown connecting power domain PD_alu 714 to PD_FSM 721 and having a logic “high” clamp value. Isolation cell 756 is shown to connect power domain PD_ALUB 711 to PD_RAM 731. However, the clamp value of the isolation cell 756 is not defined and is not shown in the power map. Similarly, clamp values for isolation cells 751, 752 and 753 are not defined and are not shown in FIG. Therefore, multiple states or multiple errors between multiple power domains can be seen in the hierarchical power map to assist in debugging IC designs.

  For multiple circuits with multiple modes of operation, each mode of operation is its own to avoid complex display and difficult debugging by merging all modes of operation into a single power map. Can have a power map. As a result, a corresponding hierarchical power map can be generated and displayed independently for each mode. For example, as shown in FIG. 7, the current mode of operation is displayed as mode_1 708 on the top level of the power map.

  In one embodiment, a computer-implemented method for creating a power map according to the present invention is as follows. As shown in FIG. 8, at 760, a plurality of original text-based circuit design HDL codes are parsed and converted into internal structures and stored in a knowledge database. A knowledge database that can be generated by an HDL parser is a computer readable data structure within a circuit design that can be easily manipulated or controlled by software. A knowledge database is generally hierarchical, but may have a flat structure. At 761, a plurality of power designs described in CPF or UPF are parsed and converted to internal structure by a CPF or UPF parser. Thereafter, the original circuit design hierarchy in the knowledge database is regrouped into a plurality of power domain hierarchies defined by the power supply specifications having a number of power domains. At 762, a plurality of power domain hierarchies are stored in a power database and converted to an internal structure that is a computer readable data structure for circuit design and power design and can be controlled by software. At 763, a power map is created according to the power domain hierarchy of the power database and displayed in the GUI window. The power map includes a number of power domains, each of which is associated with a portion of the circuit. The power map includes a first representation that indicates a plurality of boundaries and a plurality of parent-child relationships between the plurality of power domains, wherein at least one of the plurality of power domains includes at least one child power domain. Each power domain has power control for controlling the power domain, and the status of power control is displayed on the power map. Power control of the parent power domain can be used to control its child power domains as well. For example, in one embodiment, when the parent power domain is powered off, all of the child domains within the parent power domain can be similarly turned off. However, when the parent power domain is powered on, each of the multiple child power domains can be automatically turned on or, if necessary, subject to additional local power control associated with that child power domain. Can be done.

  At 764, a static check can be performed to detect multiple discrepancies or multiple errors between the power specification and the circuit design for improperly processed signals connecting multiple power domains. As shown at 765, multiple inconsistencies or multiple errors may be displayed to multiple users by one or more annotations such as multiple dotted lines, multiple symbols, or multiple colored highlights.

  The above embodiments of the present invention are illustrative and not limiting. Numerous other additions, deletions or modifications are apparent in light of the present disclosure and are intended to be included within the scope of the appended claims.

The above embodiments of the present invention are illustrative and not limiting. Numerous other additions, deletions or modifications are apparent in light of the present disclosure and are intended to be included within the scope of the appended claims.
(Item 1)
A computer-implemented method for debugging the power supply side of a circuit design described in a power supply specification format by displaying a power supply map that integrates the power supply specification and the circuit design.
Generating a knowledge database from the circuit design when the computer is started to debug the circuit design;
Generating a power supply database according to the power supply specification and the knowledge database;
Generating and displaying the power map according to the power database using the computer, the power map including a plurality of power domains each associated with a different part of the circuit design;
Checking and displaying a plurality of mismatches or errors between the power supply specifications and the circuit design for a plurality of signals connecting the plurality of power supply domains,
The power map includes a first representation indicating a plurality of boundaries and a plurality of parent-child relationships between the plurality of power domains, wherein at least one of the plurality of power domains is at least one child power domain. And at least one of the plurality of power domains is associated with power control for controlling the power domain, and the status of the power control is displayed on the power map
Computer mounting method.
(Item 2)
At least one subset of the plurality of power domains has an associated parent power domain and an associated child power domain
The computer-implemented method of claim 1.
(Item 3)
The above check and display steps are:
If there are a plurality of hardware description language (HDL) signals between at least two power domains and there is no isolation connection between the at least two power domains, the virtual between the at least two power domains Displaying the isolation connection net; and
If there is a plurality of hardware description language (HDL) signals between the at least two power domains and there is no level shifter connection between the at least two power domains, the virtual between the at least two power domains Displaying a level shifter connection net
The computer-implemented method according to claim 2.
(Item 4)
The power map is used with simulation results,
The above computer mounting method is:
Displaying a plurality of current simulation values of a plurality of signals in the power map;
In order to indicate whether the associated power domain is currently powered on or powered off, the status of each power control is displayed using an ON or OFF symbol. The status further comprises: including a voltage level if the associated power domain is powered on
The computer-implemented method according to claim 2.
(Item 5)
The power map further includes at least one isolation cell representing an isolation command, and the at least one isolation cell includes a plurality of isolation nets for connection to the plurality of power domains.
The computer-implemented method of claim 1.
(Item 6)
The power map further includes at least one level shifter cell representing a level shifter command, and the at least one level shifter cell includes a plurality of level shifter nets for connection to the plurality of power supply domains.
The computer-implemented method of claim 1.
(Item 7)
The power map further includes at least one power switch cell representing a power switch, the at least one power switch cell for power supply, or a plurality of power domains, or connection to at least one power switch cell. Includes multiple power switch nets
The computer-implemented method of claim 1.
(Item 8)
The virtual isolation connection net or the virtual level shifter connection net is represented by either a dotted line or a colored line.
The computer-implemented method according to claim 5.
(Item 9)
A computer system adapted to debug the power supply side of a circuit design described in a power supply specification format by displaying a power supply map that integrates the power supply specification and its corresponding circuit design, the computer The system comprises a processor and a computer readable storage medium adapted to store instructions, the instructions being executed by the processor upon the processor,
Generate a knowledge database from the above circuit design,
Generate a power supply database according to the power supply specification and the knowledge database,
Generating and displaying the power map including a plurality of power domains each associated with a different part of the circuit design according to the power database;
Check and display multiple mismatches or multiple errors between the power supply specifications and the circuit design for multiple signals connecting the multiple power domains,
The power map includes a first representation indicating a plurality of boundaries and a plurality of parent-child relationships between at least one subset of the plurality of power domains, wherein at least one of the plurality of power domains is at least Including one child power domain, wherein at least one of the plurality of power domains is associated with power control for controlling the at least one power domain, and the status of the power control is indicated on the power map. Is displayed
Computer system.
(Item 10)
At least one subset of the plurality of power domains has an associated parent power domain and an associated child power domain
The computer system according to claim 9.
(Item 11)
The above checks and indications
If there are a plurality of hardware description language (HDL) signals between at least two power domains and there is no isolation connection between the at least two power domains, the virtual between the at least two power domains Displaying an isolation connection net;
If there is a plurality of hardware description language (HDL) signals between the at least two power domains and there is no level shifter connection between the at least two power domains, the virtual between the at least two power domains Further displaying a level shifter connection net
The computer system according to claim 10.
(Item 12)
The power map is used with simulation results,
When the plurality of instructions are executed by the processor, the processor further includes:
Display multiple current simulation values for multiple signals in the power map,
In order to indicate whether the associated power domain is currently powered on or powered off, the status of each power control is displayed using an ON or OFF symbol. , Including the voltage level if the associated power domain is powered on
The computer system according to claim 10.
(Item 13)
The power map further includes at least one isolation cell representing an isolation command, and the at least one isolation cell includes a plurality of isolation nets for connection to the plurality of power domains.
The computer system according to claim 9.
(Item 14)
The power map further includes at least one level shifter cell representing a level shifter command, and the at least one level shifter cell includes a plurality of level shifter nets for connection to the plurality of power supply domains.
The computer system according to claim 9.
(Item 15)
The power map further includes at least one power switch cell representing a power switch, the at least one power switch cell for connection to a power source, the plurality of power domains, or at least one power switch cell. Includes multiple power switch nets
The computer system according to claim 9.
(Item 16)
The virtual isolation connection net or the virtual level shifter connection net is represented by either a dotted line or a colored line.
The computer system according to claim 13.
(Item 17)
Multiple instructions that, when executed by a processor, cause the processor to debug the power side of the circuit design described in the power specification format by displaying a power map integrating the power specification and its corresponding circuit design. A computer readable storage medium comprising: when executed by the processor, the computer readable storage medium further comprising:
Generate a knowledge database from the above circuit design,
Generate a power supply database according to the power supply specification and the knowledge database,
Generating and displaying the power map including a plurality of power domains each associated with a different part of the circuit design according to the power database;
A plurality of instructions for checking and displaying a plurality of mismatches or errors between the power supply specifications and the circuit design for a plurality of signals connecting the plurality of power supply domains;
The power map includes a first representation indicating a plurality of boundaries and a plurality of parent-child relationships between at least one subset of the plurality of power domains, wherein at least one of the plurality of power domains is at least Including one child power domain, wherein at least one of the plurality of power domains is associated with power control for controlling the at least one power domain, and the status of the power control is indicated on the power map. Is displayed
Computer-readable storage medium.
(Item 18)
At least one subset of the plurality of power domains has an associated parent power domain and an associated child power domain
The computer-readable storage medium according to claim 17.
(Item 19)
The above checks and indications
If there are a plurality of hardware description language (HDL) signals between at least two power domains and there is no isolation connection between the at least two power domains, the virtual between the at least two power domains Displaying an isolation connection net;
If there is a plurality of hardware description language (HDL) signals between the at least two power domains and there is no level shifter connection between the at least two power domains, the virtual between the at least two power domains Further displaying a level shifter connection net
The computer-readable storage medium according to claim 18.
(Item 20)
The power map is used with simulation results,
When the plurality of instructions are executed by the processor, the processor further includes:
Display multiple current simulation values for multiple signals in the power map,
In order to indicate whether the associated power domain is currently powered on or powered off, the status of each power control is displayed using an ON or OFF symbol. , Including the voltage level if the associated power domain is powered on
The computer-readable storage medium according to claim 18.
(Item 21)
The power map further includes at least one isolation cell representing an isolation command, and the at least one isolation cell includes a plurality of isolation nets for connection to the plurality of power domains.
The computer-readable storage medium according to claim 17.
(Item 22)
The power map further includes at least one level shifter cell representing a level shifter command, and the at least one level shifter cell includes a plurality of level shifter nets for connection to the plurality of power supply domains.
The computer-readable storage medium according to claim 17.
(Item 23)
The power map further includes at least one power switch cell representing a power switch, the at least one power switch cell for connection to a power source, the plurality of power domains, or at least one power switch cell. Includes multiple power switch nets
The computer-readable storage medium according to claim 17.
(Item 24)
The virtual isolation connection net or the named virtual level shifter connection net is represented by either a dotted line or a colored line.
The computer-readable storage medium according to claim 21.

Claims (24)

A computer-implemented method for debugging the power supply side of a circuit design described in a power supply specification format by displaying a power supply map that integrates the power supply specification and the circuit design, the method comprising:
Generating a knowledge database from the circuit design when the computer is started to debug the circuit design;
Generating a power database according to the power specifications and the knowledge database;
Generating and displaying the power map according to the power database using the computer, the power map including a plurality of power domains each associated with a different part of the circuit design;
Checking and displaying a plurality of mismatches or errors between the power supply specifications and the circuit design for a plurality of signals connecting the plurality of power domains,
The power map includes a first representation indicating a plurality of boundaries and a plurality of parent-child relationships between the plurality of power domains, wherein at least one of the plurality of power domains is at least one child power domain. And at least one of the plurality of power domains is associated with power control for controlling the power domain, and the status of the power control is displayed on the power map. The computer-implemented method of claim 1, wherein at least one subset of the plurality of power domains has an associated parent power domain and an associated child power domain. The checking and displaying step includes:
If there is a plurality of hardware description language (HDL) signals between at least two power domains and there is no isolation connection between the at least two power domains, the virtual between the at least two power domains Displaying the isolation connection net; and
If there is a plurality of hardware description language (HDL) signals between the at least two power domains and there is no level shifter connection between the at least two power domains, a virtual between the at least two power domains The computer-implemented method according to claim 2, further comprising: displaying a level shifter connection net. The power map is used with simulation results,
The computer-implemented method is:
Displaying a plurality of current simulation values of a plurality of signals in the power map;
Displaying the status of each power control using an ON or OFF symbol to indicate whether the associated power domain is currently powered on or powered off. The computer-implemented method of claim 2, wherein the status further comprises a voltage level if the associated power domain is powered on. The power map further includes at least one isolation cell representing an isolation command, the at least one isolation cell including a plurality of isolation nets for connection to the plurality of power domains. The computer-implemented method according to 1. The power supply map further includes at least one level shifter cell representing a level shifter command, and the at least one level shifter cell includes a plurality of level shifter nets for connection to the plurality of power supply domains. Computer mounting method. The power map further includes at least one power switch cell representing a power switch, the at least one power switch cell for power supply, or a plurality of power domains, or connection to at least one power switch cell. The computer-implemented method according to claim 1, comprising a plurality of power switch nets. The computer-implemented method according to claim 5, wherein the virtual isolation connection net or the virtual level shifter connection net is represented by either a dotted line or a colored line. A computer system adapted to debug the power supply side of a circuit design described in a power supply specification format by displaying a power supply map that integrates the power supply specification and its corresponding circuit design, the computer The system comprises a processor and a computer readable storage medium adapted to store instructions, wherein when the instructions are executed by the processor, the processor
Generating a knowledge database from the circuit design;
Generating a power supply database according to the power supply specification and the knowledge database;
Generating and displaying the power map according to the power database, including a plurality of power domains each associated with a different part of the circuit design;
Checking and displaying a plurality of mismatches or errors between the power specification and the circuit design for a plurality of signals connecting the plurality of power domains;
The power map includes a first representation indicating a plurality of boundaries and a plurality of parent-child relationships between at least a subset of the plurality of power domains, wherein at least one of the plurality of power domains is at least Including one child power domain, wherein at least one of the plurality of power domains is associated with power control for controlling the at least one power domain, and the status of the power control is indicated on the power map Displayed computer system. The computer system according to claim 9, wherein at least one subset of the plurality of power domains has an associated parent power domain and an associated child power domain. The check and display
If there is a plurality of hardware description language (HDL) signals between at least two power domains and there is no isolation connection between the at least two power domains, the virtual between the at least two power domains Displaying an isolation connection net;
If there is a plurality of hardware description language (HDL) signals between the at least two power domains and there is no level shifter connection between the at least two power domains, a virtual between the at least two power domains The computer system according to claim 10, further comprising: displaying a level shifter connection net. The power map is used with simulation results,
When the plurality of instructions are executed by the processor, the processor further includes:
Displaying a plurality of current simulation values of a plurality of signals in the power map;
In order to indicate whether the associated power domain is currently powered on or powered off, the status of each power control is displayed using an ON or OFF symbol, and the status of power control is The computer system of claim 10, comprising a voltage level if the associated power domain is powered on. The power map further includes at least one isolation cell representing an isolation command, the at least one isolation cell including a plurality of isolation nets for connection to the plurality of power domains. 10. The computer system according to 9. The power supply map further includes at least one level shifter cell representing a level shifter command, and the at least one level shifter cell includes a plurality of level shifter nets for connection to the plurality of power supply domains. Computer system. The power map further includes at least one power switch cell representing a power switch, the at least one power switch cell for connection to a power source, the plurality of power domains, or at least one power switch cell. The computer system according to claim 9, comprising a plurality of power switch nets. The computer system according to claim 13, wherein the virtual isolation connection net or the virtual level shifter connection net is represented by either a dotted line or a colored line. A plurality of instructions that, when executed by a processor, cause the processor to debug the power side of the circuit design described in a power specification format by displaying a power map integrating the power specification and its corresponding circuit design A computer readable storage medium comprising: when executed by the processor, the computer readable storage medium further comprising:
Generating a knowledge database from the circuit design;
Generating a power supply database according to the power supply specification and the knowledge database;
Generating and displaying the power map according to the power database, including a plurality of power domains each associated with a different part of the circuit design;
A plurality of instructions for checking and displaying a plurality of mismatches or errors between the power supply specification and the circuit design for a plurality of signals connecting the plurality of power supply domains;
The power map includes a first representation indicating a plurality of boundaries and a plurality of parent-child relationships between at least a subset of the plurality of power domains, wherein at least one of the plurality of power domains is at least Including one child power domain, wherein at least one of the plurality of power domains is associated with power control for controlling the at least one power domain, and the status of the power control is indicated on the power map Computer readable storage medium to be displayed. The computer-readable storage medium of claim 17, wherein at least one subset of the plurality of power domains has an associated parent power domain and an associated child power domain. The check and display
If there is a plurality of hardware description language (HDL) signals between at least two power domains and there is no isolation connection between the at least two power domains, the virtual between the at least two power domains Displaying an isolation connection net;
If there is a plurality of hardware description language (HDL) signals between the at least two power domains and there is no level shifter connection between the at least two power domains, a virtual between the at least two power domains The computer-readable storage medium according to claim 18, further comprising: displaying a level shifter connection net. The power map is used with simulation results,
When the plurality of instructions are executed by the processor, the processor further includes:
Displaying a plurality of current simulation values of a plurality of signals in the power map;
In order to indicate whether the associated power domain is currently powered on or powered off, the status of each power control is displayed using an ON or OFF symbol, and the status of power control is The computer-readable storage medium of claim 18, comprising a voltage level if the associated power domain is powered on. The power map further includes at least one isolation cell representing an isolation command, the at least one isolation cell including a plurality of isolation nets for connection to the plurality of power domains. The computer-readable storage medium according to 17. The power supply map further includes at least one level shifter cell representing a level shifter command, and the at least one level shifter cell includes a plurality of level shifter nets for connection to the plurality of power supply domains. Computer-readable storage medium. The power map further includes at least one power switch cell representing a power switch, the at least one power switch cell for connection to a power source, the plurality of power domains, or at least one power switch cell. The computer-readable storage medium according to claim 17, comprising a plurality of power switch nets. The computer-readable storage medium according to claim 21, wherein the virtual isolation connection net or the named virtual level shifter connection net is represented by either a dotted line or a colored line.

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