JP2016223783A - Circuit device, electronic apparatus and movable body - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit device capable of reducing noise generated in association with gain control of a driving signal, and an electronic apparatus, a movable body and the like.SOLUTION: A circuit device outputs a driving signal DQ driving a physical quantity transducer 12. The circuit device includes: an amplifier circuit 32 amplifying a feedback signal DI from the physical quantity transducer 12; a gain control circuit 40 having an n-th low-pass filter circuit 46 input with a signal DV after amplification by the amplifier circuit 32 where n is defined as an integer of 2 or more and outputting a control voltage VCTL on the basis of output of the n-th low-pass filter circuit 46; and a driving signal output circuit 50 generating the driving signal DQ with an amplitude controlled by the control voltage VCTL on the basis of the signal DV after the amplification by the amplifier circuit 32 and outputting the driving signal DQ.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a circuit device, an electronic device, a moving object, and the like.

  Conventionally, a circuit device that detects a physical quantity based on a detection signal from a physical quantity transducer is known. Taking a gyro sensor as an example, the circuit device detects an angular velocity or the like as a physical quantity. For example, the gyro sensor is incorporated in an electronic device such as a digital camera or a smartphone, or a moving body such as a car or an airplane, and performs camera shake correction, posture control, GPS autonomous navigation, and the like using a detected physical quantity such as an angular velocity.

  Such a physical quantity transducer is driven by application of a drive signal. At this time, the drive circuit performs gain control of the drive signal based on a feedback signal from the physical quantity transducer. For example, Patent Document 1 includes an AGC circuit and a comparator, and the AGC circuit includes a full-wave rectifier circuit that full-wave rectifies the feedback signal, and an integrator that integrates a signal from the full-wave rectifier circuit, As the comparator, there is disclosed a drive circuit that changes the amplitude of the drive signal by a signal from an integrator.

JP 2009-168588 A

  In the drive circuit as described above, there is a problem that noise is generated with gain control of the drive signal. For example, when a full-wave rectifier circuit is used in the AGC circuit, the signal after full-wave rectification includes noise having a frequency twice that of the drive signal (hereinafter referred to as a double frequency), and gain control is performed by the signal. The drive signal includes noise having a frequency twice that of the drive signal. That is, if noise is included in a signal for changing the amplitude of the drive signal, the drive signal whose gain is controlled by the signal includes noise. Then, the noise may affect the detection circuit via electrostatic leakage (electrostatic coupling) or the like, and the detection accuracy may be reduced.

  According to some aspects of the present invention, it is possible to provide a circuit device, an electronic device, a moving body, and the like that can reduce noise generated in response to gain control of a drive signal.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or modes.

  One aspect of the present invention is a circuit device that outputs a drive signal for driving a physical quantity transducer, and when an amplification circuit that amplifies a feedback signal from the physical quantity transducer and n is an integer of 2 or more, A gain control circuit that has an n-order low-pass filter circuit to which the signal amplified by the amplifier circuit is input, and that outputs a control voltage based on the output of the n-order low-pass filter circuit; and the amplitude is controlled by the control voltage And a drive signal output circuit that generates and outputs the drive signal generated based on the signal amplified by the amplifier circuit.

  According to one aspect of the present invention, a control voltage is output based on the output of the nth-order low-pass filter circuit, and the amplitude of the drive signal that drives the physical quantity transducer is controlled based on the control voltage. By using the nth-order low-pass filter circuit, it is possible to reduce the gain while securing the band of the AGC loop, and therefore it is possible to reduce noise generated due to the gain control of the drive signal.

  In one aspect of the present invention, the gain control circuit includes a rectifier circuit that rectifies the signal after amplification by the amplifier circuit, and the signal after rectification by the rectifier circuit is transmitted to the n-th order low-pass filter circuit. It may be entered.

  The signal obtained by rectifying the signal amplified by the amplifier circuit includes noise having a frequency twice that of the drive signal. According to one embodiment of the present invention, noise having a double frequency of the drive signal can be reduced by the n-th order low-pass filter circuit, and therefore, noise of the double frequency of the drive signal included in the control voltage can be suppressed. Thereby, the influence on a detection system by double frequency noise can be reduced.

  In one aspect of the present invention, the cutoff frequency of the n-th order low-pass filter circuit may be less than twice the frequency of the drive signal.

  By setting the cut-off frequency to a frequency smaller than twice the drive frequency in this way, the double component of the drive frequency can be reduced by the steep cutoff characteristic of the nth-order low-pass filter circuit.

  In the aspect of the invention, the cutoff frequency of the n-th order low-pass filter circuit may be higher than a frequency band of physical quantity information output based on a detection signal from the physical quantity transducer.

  Thus, by setting the cutoff frequency of the nth-order low-pass filter circuit to a frequency higher than the frequency band of the physical quantity information, the band of the AGC loop extends to the high band side, and the gain characteristic does not have a peak. As a result, the occurrence of noise of a specific frequency (the peak of the gain characteristic of the AGC loop) in the physical quantity detected by the detection circuit is suppressed, and the noise characteristic of the physical quantity information can be improved.

  In the aspect of the invention, the n-order low-pass filter circuit may be a multiple feedback low-pass filter circuit.

  In the aspect of the invention, the n-order low-pass filter circuit includes an operational amplifier, a first resistance element provided between an input node and a feedback node of the n-order low-pass filter circuit, and an output node of the operational amplifier. And a second resistance element provided between the feedback node and the second feedback element.

  In one aspect of the present invention, a gain of the nth-order low-pass filter circuit may be set according to a resistance ratio between the first resistance element and the second resistance element.

  In the aspect of the invention, the n-th order low-pass filter circuit may include a third resistance element provided between the feedback node and a first input node of the operational amplifier.

  In the aspect of the invention, the n-order low-pass filter circuit includes an operational amplifier, a first capacitor provided between a feedback node of the n-order low-pass filter and a first power supply node, and an output node of the operational amplifier. And a second capacitor provided between the first input node and the first input node.

  In such a multiple feedback low-pass filter, the gain is set by the resistance ratio of the first resistance element and the second resistance element, and the frequency is determined by the resistance values of the first to third resistance elements and the capacitance values of the first and second capacitors. A characteristic (for example, a cutoff frequency) is set. That is, the gain and the pass band can be adjusted independently, and the gain can be lowered while securing the pass band, so that both the securing of the AGC loop band and the gain reduction can be achieved.

  In one embodiment of the present invention, the capacity of the second capacitor may be smaller than the capacity of the first capacitor.

  In the aspect of the invention, the first capacitor may be a metal-oxide-semiconductor (MOS) capacitor.

  As described above, since one end of the first capacitor is connected to the first power supply node, a MOS capacitor whose one end is the substrate potential of the semiconductor substrate can be used. Since the first capacitor having a larger capacity than the second capacitor can be configured by a MOS capacitor having a large capacity density, the layout area can be suppressed.

  In the aspect of the invention, the second capacitor may be a MIM (Metal-Insulator-Metal) capacitor.

  Since the second capacitor has a smaller capacity than the first capacitor, the influence on the layout area is small even when the MIM capacitor is used as the second capacitor.

  In one aspect of the present invention, a detection circuit that outputs physical quantity information corresponding to the physical quantity based on a detection signal corresponding to the physical quantity output from the physical quantity transducer may be included.

  Another aspect of the invention relates to an electronic device including the circuit device described in any of the above.

  Still another embodiment of the present invention relates to a moving body including any of the circuit devices described above.

The comparative example of the circuit apparatus of this embodiment. The signal waveform figure of the circuit apparatus of a comparative example. FIG. 3A is a schematic diagram of gain characteristics of the AGC loop in the comparative example. FIG. 3B shows a configuration example of a complete integrator. 1 is a configuration example of a circuit device according to the present embodiment. 3 is a detailed configuration example of an n-order low-pass filter circuit. 6A and 6B are diagrams illustrating characteristics of an n-order low-pass filter circuit. Setting example of each parameter of secondary low-pass filter. The schematic diagram of the gain characteristic of an AGC loop. 3 shows a detailed configuration example of a drive circuit. The modification structural example of the circuit apparatus of this embodiment. The signal waveform diagram of the circuit device of a modification example of composition. Gain characteristics of AGC loop. 13A and 13B show detailed configuration examples of the sample and hold circuit. The voltage waveform figure of each node of a sample hold circuit. 1 is a first detailed configuration example of a phase adjustment circuit. The 2nd detailed structural example of a phase adjustment circuit, and the detailed structural example of a synchronizing signal output circuit. 1 is a configuration example of a circuit device, an electronic device, and a gyro sensor (physical quantity detection device) of the present embodiment. 3 shows detailed configuration examples of a drive circuit and a detection circuit. 19A to 19D are examples of a moving body and an electronic device in which the circuit device of this embodiment is incorporated.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Comparative Example FIG. 1 shows a comparative example of the circuit device of this embodiment. The circuit device includes a drive circuit 30 that drives the physical quantity transducer 12. The drive circuit 30 includes an amplification circuit 32 that amplifies the feedback signal DI from the physical quantity transducer 12, a drive signal output circuit 50 that outputs a drive signal DQ based on the signal from the amplification circuit 32, and a drive signal output circuit 50. And a gain control circuit 40 that controls the amplitude of the drive signal DQ by controlling the gain. The gain control circuit 40 integrates the full-wave rectified circuit 48 that sine-waves the signal DV of the sine wave voltage from the amplifier circuit 32 and the full-wave rectified signal WRQ to drive the control voltage VCTL (control signal). And an integrator 44 that outputs to the output circuit 50.

  The amplitude of the drive signal DQ is controlled by the control voltage VCTL. That is, when the amplitude of the feedback signal DI from the physical quantity transducer 12 decreases, the amplitude of the signal DV from the amplifier circuit 32 decreases, and the signal level of the signal WRQ from the full-wave rectifier circuit 48 decreases. The integrator 44 inverts and integrates the signal WRQ with respect to the reference signal to increase the signal level of the control voltage VCTL, and the drive signal output circuit 50 increases the amplitude of the drive signal DQ accordingly. Hereinafter, such a negative feedback loop for the gain of the drive signal DQ is also referred to as an AGC (Auto Gain Control) loop.

  FIG. 2 is a signal waveform diagram of the circuit device of the comparative example. Here, an example of a waveform when the physical quantity transducer 12 is a vibrating piece (for example, a quartz vibrating piece) is shown.

  As shown in FIG. 2, the physical quantity transducer 12 is driven by a drive signal DQ having a rectangular wave voltage, for example. The feedback signal DI is a sine wave current signal and is converted into a sine wave voltage signal DV by the amplifier circuit 32. A signal WRQ (voltage signal) obtained by full-wave rectifying the signal DV is integrated with reference to the reference voltage VR3 in the vicinity of the amplitude center, and a control voltage VCTL (voltage signal) is output. The drive signal output circuit 50 decreases or increases the upper voltage of the rectangular-wave drive signal DQ in accordance with the decrease or increase of the control voltage VCTL.

  Since the full-wave rectified signal WRQ has a waveform obtained by folding the lower side of the sine wave signal DV upward, the full-wave rectified signal WRQ includes a component having a frequency twice that of the signal DV (ie, the frequency of the drive signal DQ). That is, the control voltage VCTL obtained by integrating the full-wave rectified signal WRQ also includes a double frequency component of the drive signal DQ. The gain is controlled by the control voltage VCTL, so that the drive signal DQ has a double frequency. As a result, these components are included. The double frequency component included in the drive signal DQ is propagated as noise to the surrounding circuits and may adversely affect the circuits. For example, when the detection system is affected, the physical quantity detection accuracy decreases.

  Specifically, as will be described later with reference to FIG. 18, the detection signals IQ 1 and IQ 2 from the physical quantity transducer 12 are detected by a detection circuit 60 including a synchronous detection circuit 81. When electrostatic coupling exists between the input terminals of the detection signals IQ1 and IQ2 and the output terminal of the drive signal DQ (for example, the drive circuit 30 and the detection circuit 60 are integrated on one IC chip). If). In this case, double frequency noise included in the drive signal DQ propagates (electrostatic leakage) to the detection signals IQ1 and IQ2 via electrostatic coupling. The synchronous detection circuit 81 synchronously detects the detection signals IQ1 and IQ2 amplified by the amplifier circuit 61 in synchronization with the frequency of the drive signal DQ. At this time, noise twice the frequency of the drive signal DQ propagated to the detection signals IQ1 and IQ2 is synchronously detected, and the physical quantity detection accuracy is lowered.

  For example, a gyro sensor using a resonator element detects an angular velocity proportional to the output voltage of the synchronous detection circuit 81. Since noise having a frequency twice that of the drive signal DQ is turned back to the vicinity of DC by synchronous detection, the noise causes an error in the angular velocity (for example, the angular velocity that is not zero when the vibration piece is not actually rotated). Observed).

  Further, the integrator 44 is a so-called perfect integrator. However, when the perfect integrator is used, there is a problem in that the AGC loop bandwidth, layout area and noise are traded off as follows.

  That is, FIG. 3A shows the gain characteristics of the AGC loop. As shown in FIG. 3A, for example, the frequency characteristic of the gain of the AGC loop is a characteristic that rises near the frequency f1. In this case, noise near the frequency f1 is amplified by the AGC loop. When this noise propagates to the detection circuit 60 due to electrostatic leakage, there is a possibility that the noise is placed near the frequency f1 of the detected physical quantity. In order to reduce the influence on the detection circuit 60, it is necessary to lower the gain of the AGC loop. The gain of the AGC loop can be adjusted by the gain of the integrator 44 as follows, but the above trade-off occurs.

  FIG. 3B shows a configuration example of the integrator 44 which is a complete integrator. The integrator 44 includes an operational amplifier OPB2, an input resistor RB2, and a feedback capacitor CB2. The reference voltage VR3 is an integration reference voltage as shown in FIG. 2, and is set to a level at which the target amplitude of the drive signal DQ can be obtained. When the resistance value of the resistance element RB2 of the complete integrator is R and the capacitance value of the capacitor CB2 is C, the gain of the complete integrator is expressed as 1 / (ωRC). ω is the angular frequency of the signal. In order to reduce the gain, it is necessary to increase the resistance value R or the capacitance value C. However, the increase in the resistance value R and the capacitance value C is limited from the viewpoint of the layout area of the resistance elements and capacitors.

  Further, as shown in FIG. 3A, there is a problem that when the gain of the complete integrator is lowered, the band of the AGC loop is lowered. For example, when the gain characteristic GCD changes to the gain characteristic GCE, the peak position of the frequency characteristic moves to the low frequency side. In FIG. 3A, the frequency axis is a logarithmic axis, and when viewed on the logarithmic axis, 1 / (ωRC) is a straight line to the right, but when this gain is lowered, it appears that the straight line has moved to the low frequency side. The band of the AGC loop is lowered. When the drive circuit 30 is started (when the oscillation of the resonator element starts), the transient response of the AGC loop converges to a steady oscillation state, and this convergence time is related to the frequency characteristics of the AGC loop that is a negative feedback loop. doing. For this reason, if the AGC loop bandwidth is reduced, the convergence time at the time of startup becomes longer.

2. Circuit Device FIG. 4 shows a configuration example of the circuit device of the present embodiment that can solve the noise problem generated by the AGC loop as described above. This circuit device includes a drive circuit 30 that receives a feedback signal DI from the physical quantity transducer 12 and outputs a drive signal DQ that drives the physical quantity transducer 12.

  The drive circuit 30 includes an amplifier circuit 32, a gain control circuit 40, and a drive signal output circuit 50. The amplifier circuit 32 amplifies the feedback signal DI from the physical quantity transducer 12. The gain control circuit 40 has an n-order low-pass filter circuit 46 (incomplete integrator) to which a signal (here, the signal WRQ) amplified by the amplifier circuit 32 is input when n is an integer of 2 or more. The control voltage VCTL is output based on the output of the n-order low-pass filter circuit 46. The drive signal output circuit 50 generates and outputs a drive signal DQ whose amplitude is controlled by the control voltage VCTL based on the signal DV amplified by the amplifier circuit 32.

  Here, the “signal after amplification by the amplification circuit 32” input to the n-order low-pass filter circuit 46 is a signal based on the output signal DV of the amplification circuit 32, and after being amplified by the amplification circuit 32, Any signal may be used. That is, not only the signal DV itself output from the amplifier circuit 32 but also a signal that is amplified by the amplifier circuit 32 and then processed by another circuit.

  The drive signal output circuit 50 compares the signal DV with a reference voltage using, for example, a comparator, and generates a rectangular wave drive signal DQ. At this time, the comparator controls the amplitude of the drive signal DQ based on the control voltage VCTL. However, the method for generating the drive signal DQ is not limited to this. For example, the sine wave signal DV may be amplified by an amplifier circuit to generate the drive signal DQ, and at that time, the amplifier circuit may output the drive signal DQ with an amplitude corresponding to the control voltage VCTL.

  The gain control circuit 40 includes a rectifier circuit that rectifies the signal DV amplified by the amplifier circuit 32. The n-order low-pass filter circuit 46 receives the signal WRQ after rectification by the rectifier circuit. Specifically, the gain control circuit 40 includes a full-wave rectifier circuit 48 as a rectifier circuit.

  Thus, by integrating the output of the full-wave rectifier circuit 48 by the n-order low-pass filter circuit 46 as an incomplete integrator, the problem of noise generated by the AGC loop can be solved.

  That is, since the gain of the nth-order low-pass filter circuit 46 is determined by the ratio of the feedback resistance and the input resistance, the gain can be lowered without increasing the resistance value of the resistance element or the capacitance value of the capacitor. As a result, the gain of the AGC loop can be lowered while suppressing an increase in layout area, and noise at twice the frequency of the drive signal DQ can be reduced.

  The n-order low-pass filter circuit 46 can independently adjust the gain determined by the resistance ratio and the pass band determined by the resistance value and the capacitance value. Therefore, it is possible to reduce the gain of the pass band while maintaining the band (cutoff frequency). Thereby, even if the gain of the AGC loop is lowered, the band can be secured, so that the convergence time at the start-up does not become long.

  FIG. 5 shows a detailed configuration example of the n-order low-pass filter circuit 46. Here, a case where n = 2 is described as an example, but it is only necessary that n ≧ 2.

  The secondary (n = 2) low-pass filter circuit 46 is a multiple feedback low-pass filter circuit. The multiple feedback low-pass filter circuit is an active low-pass filter circuit having a plurality of feedback nodes (the same number as the filter order). The feedback node is a node where a signal is negatively fed back from the output of the filter circuit. For example, in FIG. 5, the nodes ND1 and ND2 are feedback nodes, the node ND1 is a node to which the output signal VCTL is negatively fed back via the capacitor C2, and the node ND2 is a node to which the output signal VCTL is negatively fed back via the resistor element R2. Node

  Specifically, the secondary low-pass filter circuit 46 includes an operational amplifier OPD, a first resistance element R1 provided between the input node NDI and the feedback node ND2 of the secondary low-pass filter circuit 46, and the output of the operational amplifier OPD. A second resistance element R2 provided between the node NDQ and the feedback node ND2. Then, the gain of the secondary low-pass filter circuit is set by the resistance ratio of the first resistance element R1 and the second resistance element R2. The gain of the secondary low-pass filter circuit 46 is desirably 20 times or more and 500 times or less.

  Thus, since the secondary multiple feedback low-pass filter has the input resistor R1 and the feedback resistor R2, the gain can be set by the resistance ratio (R2 / R1). Also, if the resistance ratio is the same, each resistance value (R1, R2) can be changed, so that the frequency characteristics can be adjusted independently of the gain. Thereby, it is possible to secure a band while lowering the gain of the AGC loop.

  The secondary low-pass filter circuit 46 includes a third resistance element R3 provided between the feedback node ND2 and the first input node ND1 (negative terminal, first input terminal) of the operational amplifier OPD. The secondary low-pass filter circuit 46 includes a first capacitor C1 provided between the feedback node ND2 and the first power supply node, and a second capacitor C2 provided between the output node NDQ and the first input node ND1. And having.

  Here, the first power source node is a node to which the first power source is supplied. For example, the first power source is a low potential side power source of the circuit device. In the above description, the node ND2 is called a feedback node. However, there are two feedback nodes ND1 and ND2 in the secondary multiple feedback low-pass filter. The feedback node ND1 is a first input node of the operational amplifier OPD. The reference voltage VR1 is supplied to the second input node (positive electrode terminal, second input terminal) of the operational amplifier OPD.

  The transfer function H (s) of the multiple feedback low-pass filter having such a configuration is shown in the formula FA of FIG. 6A, and the cutoff frequency fc is shown in the formula FB. FIG. 6B shows frequency characteristics of the amplitude of the transfer function H (s) as an example. Here, s = iω, where i is an imaginary unit and ω is the angular frequency of the signal. In FIG. 6B, the vertical axis is a logarithmic axis (decibel), the horizontal axis is a logarithmic axis, and fd is the drive frequency of the physical quantity transducer 12.

  It can be seen from the formula FA that H (0) = − R2 / R1 and the DC gain is determined by the resistance ratio of the resistance elements R1 and R2. It can also be seen from the equation FB that the cutoff frequency can be adjusted independently of the DC gain by adjusting the resistance values of the resistance elements R2 and R3 and the capacitance values of the capacitors C1 and C2.

  FIG. 7 shows an example of setting each parameter of the secondary low-pass filter.

  For example, when setting 1 and setting 4 are compared, the resistance ratio R2 / R1 of setting 4 is about ½ of setting 1, thereby reducing the gain by about 6 dB. At this time, the cutoff frequency is higher in setting 4, and it can be seen that the AGC loop band does not decrease even when the gain is decreased. In the complete integrator, the gain reduction and the band reduction are linked, but the imperfect integrator has a very high degree of design freedom, and the frequency characteristics of the AGC loop can be designed appropriately.

  As shown in FIG. 6B, the cutoff frequency fc is smaller than twice (2fd) the frequency fd of the drive signal DQ of the physical quantity transducer 12 (drive frequency fd of the physical quantity transducer 12).

  In this embodiment, since the preceding stage of the integrator is the full-wave rectifier circuit 48, the input signal of the integrator includes many components twice the drive frequency. In the present embodiment, since the secondary low-pass filter circuit 46 is used as an integrator, the double component of the drive frequency can be reduced by the steep cutoff characteristic. Thereby, the influence on a detection system by double frequency noise can be reduced.

  The cut-off frequency fc is higher than the frequency band of physical quantity information output based on the detection signal from the physical quantity transducer 12. Specifically, the frequency band of the physical quantity information is the frequency band of the physical quantity represented by the physical quantity information with time (frequency band of the desired signal). More specifically, the DSP unit 110 (FIG. 18) of the detection circuit 60 performs digital filter processing (low-pass filter processing) on the physical quantity information, but it is more secondary than the pass band (for example, cutoff frequency) of the digital filter processing. The cut-off frequency fc of the low-pass filter circuit 46 is high. For example, the gyro sensor detects the angular velocity as a physical quantity, but the cutoff frequency fc of the secondary low-pass filter circuit 46 is higher than the frequency band of the change in angular velocity output from the detection circuit 60.

  FIG. 8 shows a schematic diagram of the gain characteristics of the AGC loop. GCD is a gain characteristic when a perfect integrator is used, and GCF is a gain characteristic when the secondary low-pass filter circuit 46 of the present embodiment is used. As shown in FIG. 8, by using a secondary low-pass filter, the maximum gain value can be lowered, and the band can be widened to eliminate the peak of the frequency characteristic.

  Specifically, the peak of the gain characteristic GCD is the frequency f1, but when this peak falls within the physical quantity information band, noise near the frequency f1 appears in the frequency characteristic of the physical quantity information, thereby reducing the signal quality. There is a possibility to make it. On the other hand, in this embodiment, since the cutoff frequency of the secondary low-pass filter is higher than the frequency band of the physical quantity information, the band of the AGC loop extends to the high band side and has no peak. Thereby, the noise of specific frequencies, such as frequency f1, is reduced and the noise characteristic of physical quantity information can be improved.

  In the present embodiment, as shown in FIG. 7, the capacity of the second capacitor C2 is smaller than the capacity of the first capacitor C1. The first capacitor C1 is a MOS (Metal-Oxide-Semiconductor) capacitor, and the second capacitor C2 is a MIM (Metal-Insulator-Metal) capacitor.

  As shown in FIG. 5, since one end of the first capacitor C1 is connected to the first power supply node, a MOS capacitor whose one end is the substrate potential of the semiconductor substrate can be used. The MOS capacitor is a capacitor having a MOS transistor substrate (for example, an NMOS P substrate) as one electrode and a MOS transistor gate as the other electrode. Of the capacitors C1 and C2 of the secondary low-pass filter, the capacitor C1 having a large capacity is formed of a MOS capacitor having a large capacity density, so that the layout area can be suppressed.

  Since the second capacitor C2 is connected between the output node NDQ and the first input node ND1 of the operational amplifier OPD, the second capacitor C2 is composed of, for example, an MIM capacitor. An MIM capacitor is a capacitor composed of two metal layers and a dielectric layer between them. For example, a metal wiring layer of a semiconductor integrated circuit is a first electrode, an insulating layer on the metal wiring layer is a dielectric layer, and a metal layer formed on the insulating layer is a second electrode. The MIM capacitor has a smaller capacity density than the MOS transistor, but since it is used for the capacitor C2 having a smaller capacity, the influence on the layout area is small.

  When a perfect integrator is used, it is necessary to configure the capacitor with, for example, an MIM capacitor, and it is necessary to increase the capacitance value in order to reduce the gain of the AGC loop. On the other hand, in the present embodiment, the first capacitor C1 having a large capacity can be constituted by a MOS capacitor, and the gain is determined by the resistance ratio, so that the capacitance value does not increase even if the gain is lowered.

3. Drive Circuit FIG. 9 shows a detailed configuration example of the drive circuit 30. The drive circuit 30 includes an amplifier circuit 32, a gain control circuit 40, and a drive signal output circuit 50. The gain control circuit 40 includes a full-wave rectifier circuit 48 and an n-order low-pass filter circuit 46.

  The amplifier circuit 32 is a current-voltage (I / V) conversion circuit, and includes an operational amplifier OPB1, a feedback resistance element RB1, and a capacitor CB1.

  The drive signal output circuit 50 includes a low-pass filter 51, a high-pass filter 53, a comparator CPB1 (comparison circuit), and an amplifier circuit 55.

  The low-pass filter 51 is a passive type and includes a resistance element RB3 and a capacitor CB3. The high pass filter 53 is a passive type and includes a capacitor CB4 and a resistance element RB4. The low pass filter 51 and the high pass filter 53 pass the band component of the drive signal DQ of the signal DV and attenuate the unnecessary component of the signal DV.

  The comparator CPB1 compares the voltage signal HQ from the high pass filter 53 with the reference voltage VR1, and outputs a rectangular wave voltage signal PQ. Since the signal HQ from the high pass filter 53 is a sine wave with the reference voltage VR1 as a reference, the output signal PQ of the comparator CPB1 is at a low level above the sine wave. Since the phase of the signal DV is shifted by 180 degrees with respect to the drive signal DQ as described in FIG. 2, the output of the comparator CPB1 has the same phase as that of the drive signal DQ.

  The amplifier circuit 55 is a non-inverting amplifier circuit that buffers the signal PQ, and includes an operational amplifier OPB3 and feedback (gain setting) resistance elements RB5 and RB6.

  The full-wave rectifier circuit 48 includes an inverting amplifier circuit (including an operational amplifier OPB4, an input resistance element RB7, and a feedback resistance element RB7), switch elements SB1 and SB2, a comparator CPB2, and an inverter IVB1. Including.

  The comparator CPB2 compares the voltage of the signal DV from the amplifier circuit 32 with the reference voltage VR1. When the voltage of the signal DV is higher than the reference voltage VR1, the comparator CPB2 outputs a low level. Therefore, the switch element SB1 is turned off, the switch element SB2 is turned on, and the signal DV is output as it is as the signal WRQ. . On the other hand, when the voltage of the signal DV is smaller than the reference voltage VR1, the comparator CPB2 outputs a high level, so that the switch element SB1 is turned on, the switch element SB2 is turned off, and the signal inverted by the inverting amplifier circuit DV is output as signal WRQ. In this way, the lower side of the sine wave signal DV with the reference voltage VR1 as a reference is folded back above the reference voltage VR1, and the rectified signal WRQ is output.

  The rectified signal WRQ is integrated with reference to the target voltage (reference voltage VR3) of the control voltage VCTL, but when viewed with reference to the target voltage, the rectified signal WRQ is a signal having a frequency twice that of the signal DV (drive signal DQ). ing. In the present embodiment, since the cutoff frequency of the nth-order low-pass filter circuit 46 is smaller than the double frequency of the drive signal DQ, the double frequency component of the drive signal DQ is effectively cut off.

4). Modified Example FIG. 10 shows a modified configuration example of the circuit device of this embodiment. This circuit device includes a drive circuit 30 that receives the feedback signal DI from the physical quantity transducer 12 and drives the physical quantity transducer 12. In the following description, the same components as those already described are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The drive circuit 30 includes an amplifier circuit 32, a gain control circuit 40, and a drive signal output circuit 50. The amplifier circuit 32 amplifies the feedback signal DI from the physical quantity transducer 12. The gain control circuit 40 includes a sample hold circuit 42 that samples and holds the signal DV amplified by the amplifier circuit 32, and outputs a control voltage VCTL based on the output (signal SHQ) of the sample hold circuit 42. The gain control circuit 40 includes an n-order low-pass filter circuit 46 that receives the output of the sample hold circuit 42 and outputs a control voltage VCTL. The drive signal output circuit 50 generates and outputs a drive signal DQ whose amplitude is controlled by the control voltage VCTL based on the signal DV amplified by the amplifier circuit 32. In addition, the drive circuit 30 can include a phase adjustment circuit 54.

  The sample hold circuit 42 is a circuit that repeatedly performs the sampling operation and the hold operation at the same frequency as the drive signal DQ, samples the signal DV in the first period (determines the sampling value at the end timing of the first period), and The sampled signal is held in the second period.

  By using such a sample-and-hold circuit 42, it is possible to generate the control voltage VCTL in which the double frequency component of the drive signal DQ is reduced, and noise generated by the AGC loop can be reduced. This will be specifically described below with reference to waveform diagrams and the like.

  FIG. 11 is a signal waveform diagram of the circuit device of this embodiment. Here, an example of a waveform when the physical quantity transducer 12 is a vibrating piece is shown.

  The sample hold circuit 42 operates with a sample hold signal CKS (clock signal) having the same frequency as that of the drive signal DQ. The sample hold circuit 42 operates like a peak hold circuit, holds the peak voltage from the peak of the signal DV to the next peak, and outputs it. Specifically, the sample hold circuit 42 samples the signal DV during the period in which the sample hold signal CKS is at the low level (first period), and determines the voltage level of the signal DV at the timing when the sample hold signal CKS changes to the high level. Hold. Then, the held voltage level is continuously output in a period during which the sample hold signal CKS is at a high level (second period) and the next period during which the low level is low (first period).

  Since the voltage of the output signal SHQ of the sample and hold circuit 42 changes at every peak of the signal DV, the double frequency component of the drive signal DQ is suppressed. Even if the signal SHQ includes a component having a double frequency of the drive signal DQ, the signal SHQ is further reduced by the n-order low-pass filter circuit 46. As a result, the control voltage VCTL does not include noise having a frequency twice that of the drive signal DQ, and adverse effects on the detection circuit as described in the comparative example (physical quantity detection error, for example, angular velocity detection error in the gyro sensor) are reduced. be able to.

  As described above, the sample hold circuit 42 is a circuit that samples and holds the peak of the signal DV amplified by the amplifier circuit 32.

  When the signal DV is full-wave rectified as in the comparative example, the level of the signal WRQ obtained is 2 / π of the amplitude of the signal DV. On the other hand, in the present embodiment, when the sample hold circuit 42 holds the peak of the signal DV, the signal SHQ having a level corresponding to the amplitude of the signal DV can be output. As a result, the gain of the AGC loop can be lowered (for example, the gain of the integrator 44 can be lowered), and the noise generated by the AGC loop can be further reduced.

  FIG. 12 shows the gain characteristics of the AGC loop. Here, the gain characteristic when a perfect integrator is used as an integrator is shown.

  As shown in FIG. 12, GCA is the gain characteristic in the comparative example using the full-wave rectifier circuit 48, and GCB is the gain characteristic in the present embodiment using the sample hold circuit 42. Since the level of the signal SHQ is π / 2 times that of the comparative example, the gain of the AGC loop can be increased to 2 / π times. That is, the gain of the AGC loop can be lowered by about 3.9 dB. This reduces the noise generated by the AGC loop by about 3.9 dB. Even when the n-order low-pass filter circuit 46 is used as an integrator, the gain characteristic of the AGC loop can be lowered as a whole by about 3.9 dB by applying the sample hold circuit 42.

  As shown in FIG. 12, since the gain characteristic of the AGC loop is increased near the frequency f1, it is considered that the frequency characteristic of the noise level is also increased near the frequency f1. In this case, noise near the frequency f1 may ride on the detection signal due to electrostatic leakage, and the noise may reduce the detection accuracy of the physical quantity. For example, when the upper limit of the angular velocity detection band in the gyro sensor is higher than the frequency f1, if noise near the frequency f1 is on the detection signal, the noise cannot be cut by the band-limited low-pass filter, and the angular velocity signal is converted. Noise near the frequency f1 is mixed.

  In this regard, according to the present embodiment, the gain of the AGC loop can be reduced, so that it is possible to reduce the noise caused by the AGC loop included in the physical quantity detection band as described above.

  As shown in FIG. 11, the sample hold circuit 42 performs sampling and holding based on the sample hold signal CKS having the same frequency as the drive signal DQ and the phase of the drive signal DQ being shifted.

  The signal DV from the amplifier circuit 32 is out of phase with the drive signal DQ. Therefore, the peak of the signal DV can be sampled by performing sampling and holding based on the sample hold signal CKS having the same frequency as the drive signal DQ and the phase of the drive signal DQ being shifted.

  Specifically, the signal DV is sampled and held by the sample hold signal CKS whose phase is shifted by 270 degrees (or -90 degrees) with respect to the drive signal DQ. When the physical quantity transducer 12 is a vibrating piece, the phase of the feedback signal DI is shifted by 90 degrees with respect to the drive signal DQ, and the phase is further shifted by 90 degrees when the amplification circuit 32 converts the feedback signal DI into a current voltage. That is, the signal DV is 180 degrees out of phase with the drive signal DQ. Therefore, the peak of the sine wave of the signal DV is shifted by 270 degrees from the rising edge of the drive signal DQ, and the phase is shifted by 270 degrees (or -90 degrees) with respect to the drive signal DQ in order to determine the peak as the hold value. The sample hold signal CKS is used.

  Note that it is not necessary to sample and hold at the peak of the signal DV because it is only necessary to sample and hold a higher signal level than when a full-wave rectifier circuit is used. That is, when the amplitude of the signal DV amplified by the amplifier circuit 32 is 2 × VP, the sample hold circuit 42 determines that the amplified signal DV is VP × (2 / π) based on the sample hold signal CKS. Sampling and holding are performed at a larger timing.

  Specifically, the timing may be any timing when the absolute value of the signal DV is larger than VP × (2 / π). The reference of the magnitude of the signal DV is the center level of the sine wave (the signal level when the phase of the sin wave is zero). The signal DV is larger than VP × (2 / π) in the range of 40 to 140 degrees (−220 degrees to −320 degrees) in the phase of the signal DV. In the phase based on the rising edge of the drive signal DQ, the range is 220 degrees to 320 degrees (-40 degrees to -140 degrees).

  In this way, by sampling and holding at timing when the signal DV is larger than VP × (2 / π), a larger signal level can be output than when the full-wave rectifier circuit is used. Then, the gain of the AGC loop can be lowered by an amount corresponding to the increase in the signal level, and the noise near the frequency f1 can be reduced.

  Next, the phase adjustment circuit 54 will be described. The phase adjustment circuit 54 outputs a sample hold signal CKS in which the phase with respect to the drive signal DQ is adjusted. The sample hold circuit 42 performs sampling and holding based on the sample hold signal CKS.

  As will be described later with reference to FIG. 18, the phase adjustment circuit 54 is included in a synchronization signal output circuit 52 that outputs a synchronization signal SYC based on the drive signal DQ to the detection circuit 60. The detection circuit 60 is a circuit that outputs physical quantity information corresponding to the physical quantity based on a detection signal corresponding to the physical quantity output from the physical quantity transducer 12. The physical quantity is, for example, angular velocity, and the physical quantity information corresponding to the physical quantity is angular velocity information. For example, the detection circuit 60 amplifies the input detection signals IQ1 and IQ2, and performs synchronous detection on the amplified signal using the synchronization signal SYC from the drive circuit 30. And A / D conversion of the signal after synchronous detection is performed, and physical quantity information is output. In this case, it is preferable that the detection circuit 60 performs signal processing such as filter processing and correction processing on the information after A / D conversion, and outputs the physical quantity information after the signal processing. This physical quantity information is, for example, physical quantity digital data (eg, angular velocity digital data).

  Here, the synchronization signal SYC is a signal whose frequency is synchronized with the drive signal DQ and whose phase is the same (or 180 degrees different), and is used for detection in the synchronous detection circuit 81. As described with reference to FIG. 11, the sample hold signal CKS is a signal whose frequency is synchronized with the drive signal DQ and whose phase is shifted by 90 degrees (or 270 degrees).

  As described above, the phase adjustment circuit 54 adjusts the phase of the sample hold signal CKS with respect to the drive signal DQ, so that the sample hold circuit 42 can sample and hold the signal DV at a phase where the signal DV becomes a peak voltage.

5. Sample Hold Circuit FIGS. 13A and 13B show a detailed configuration example of the sample hold circuit 42. FIG. 13A shows an operation state in the sampling period (first period), and FIG. 13B shows an operation state in the hold period (second period).

  The sample hold circuit 42 includes an operational amplifier OPA (amplifier circuit), a first circuit CCT1, a second circuit CCT2, and a third circuit CCT3.

  The first circuit CCT1 is provided between the input node NI of the sample hold circuit 42 and the first input node N3 (negative terminal, first input terminal) of the operational amplifier OPA, and the signal DV of the input node NI in the first period. Is sampled. The second circuit CCT2 is provided between the output node NQ of the operational amplifier OPA and the first input node N3, and connects the output node NQ and the first input node N3 via the capacitor CA2 in the second period. The third circuit CCT3 is provided between the output node NQ and the first input node N3, samples the signal of the output node NQ in the second period, and performs a hold operation in the first period.

  Thus, by connecting the output node NQ and the first input node N3 via the capacitor CA2 in the second period, the voltage (charge) sampled by the first circuit CCT1 in the first period is transferred to the capacitor CA2. It can be held in the second period.

  Specifically, the first circuit CCT1 includes a first capacitor CA1 provided between the input node NI and the first input node N3. The second circuit CCT2 has a second capacitor CA2 provided between the output node NQ and the first input node N3. The third circuit CCT3 includes a third capacitor CA3 provided between the output node NQ and the first input node N3.

  In the first period, the first circuit CCT1 connects the first capacitor CA1 between the input node NI and the node of the reference voltage VR1, so that the charge according to the voltage of the signal DV is transferred to the first capacitor CA1. And is sampled. In addition, the second circuit CCT2 connects both ends of the second capacitor CA2 to the node of the reference voltage VR1, thereby resetting the charge of the second capacitor CA2. In the second period, the first circuit CCT1 connects the first capacitor CA1 between the node of the reference voltage VR1 and the first input node N3, and the second circuit CCT2 connects the second capacitor CA2 with the output node NQ. By connecting to the 1 input node N3, the electric charge accumulated in the first capacitor CA1 is transferred to the second capacitor CA2 and held. The gain of the sample hold circuit 42 is determined by the capacitance ratio of the capacitors CA1 and CA2. For example, when the capacitance ratio is 1, the same voltage as the voltage sampled in the first period is output as the signal SHQ in the second period. .

  In the second period, the third circuit CCT3 connects the third capacitor CA3 between the output node NQ and the first input node N3, so that the charge according to the signal SHQ in the second period is changed to the third capacitor. Accumulated in CA3. In the first period, the third circuit CCT3 connects the third capacitor CA3 between the output node NQ and the node of the reference voltage VR1, so that the same voltage as the signal SHQ in the second period is output in the first period. Is done. That is, as described in FIG. 2, the sampling voltage determined at the end timing of the first period is output until the end timing of the next first period.

  More specifically, the first circuit CCT1 includes switch elements SA1 to SA4, the second circuit CCT2 includes switch elements SA5 to SA8, and the third circuit CCT3 includes switch elements SA9 and SA10. These switch elements SA1 to SA10 are transistors, for example, and are turned on and off by a sample hold signal CKS. The operation of switching the connection between the first to third capacitors CA1 to CA3 and each node in the first period and the second period is realized by switching control of the switch elements SA1 to SA10.

  The second input node (positive terminal, second input terminal) of the operational amplifier OPA is connected to the node of the reference voltage VR1. That is, the output signal SHQ of the sample hold circuit 42 is a voltage based on the reference voltage VR1. In the waveform diagram of FIG. 11, the center of the sine wave of the signal DV (the voltage at the phase of the sin wave of zero) corresponds to the reference voltage VR1, and the signal SHQ is output with the center of the sine wave as a reference. That is, the voltage from the reference voltage VR1 that is the center of the sine wave to the peak of the sine wave (which may be above or below) is the voltage level of the signal SHQ.

  FIG. 14 shows a voltage waveform diagram of each node of the sample hold circuit 42.

  In the first period, the sample hold signal CKS is at a low level, and the switch elements SA1, SA3, SA5, SA7, and SA9 are turned on. Therefore, the node N1 at one end of the first capacitor CA1 becomes the voltage of the input signal DV, and the node N2 at the other end becomes the reference voltage VR1. The node N5 at one end and the node N4 at the other end of the second capacitor CA2 become the reference voltage VR1. At this time, since the node N6 at one end of the third capacitor CA3 is connected to the summing node N3, the output signal SHQ continues to output the hold voltage in the previous second period.

  In the second period, the sample hold signal CKS is at a high level, and the switch elements SA2, SA4, SA6, SA8, and SA10 are turned on. Therefore, the node N1 at one end of the first capacitor CA1 becomes the reference voltage VR1, and the node N2 at the other end is connected to the summing node N3. Since the node N5 at one end of the second capacitor CA2 is connected to the output node NQ and the node N4 at the other end is connected to the summing node N3, the output signal SHQ becomes a sampling voltage (= hold voltage). Since the node N6 at one end of the third capacitor CA3 becomes the reference voltage VR1, the third capacitor CA3 is charged by the output signal SHQ.

6). Phase Adjustment Circuit FIG. 15 shows a first detailed configuration example of the phase adjustment circuit 54. The phase adjustment circuit 54 includes a low-pass filter 162, a high-pass filter 164, and a comparator CPC1 (comparison circuit).

  The low-pass filter 162 is a passive type and includes a resistance element RC1 and a capacitor CC1. The high pass filter 164 is a passive type and includes a capacitor CC2 and a resistance element RC2. The low-pass filter 162 shifts the phase of the input signal DV by about 90 degrees. That is, the cutoff frequency determined by the resistance value of the resistance element RC1 and the capacitance value of the capacitor CC1 is set to the same frequency (including substantially the same) as the drive signal DQ. The high pass filter 164 performs fine adjustment of the phase that cannot be adjusted by the low pass filter 162. The cutoff frequency is set higher than the frequency of the drive signal DQ. The comparator CPC1 compares the output signal of the high-pass filter 164 with the reference voltage VR1 as a reference with the reference voltage VR1, and outputs the comparison result as a sample hold signal CKS.

  FIG. 16 shows a second detailed configuration example of the phase adjustment circuit 54 and a detailed configuration example of the synchronization signal output circuit 52.

  The synchronization signal output circuit 52 includes a binarization circuit 210 and a phase adjustment circuit 54. The phase adjustment circuit 54 includes an adjustment circuit 220, a DLL (Delay Locked Loop) circuit 230, and an output circuit 240.

  The binarization circuit 54 (waveform shaping circuit) receives the sine wave output signal DV from the drive circuit 30, performs binarization processing (waveform shaping) of the output signal DV, and converts, for example, a rectangular wave signal IN. Output. The binarization circuit 210 can be realized by, for example, a comparator that compares the output signal DV with the reference voltage VR1 and outputs a signal IN.

  The phase adjustment circuit 54 adjusts the phase of the input signal IN and outputs the phase-adjusted signal as a synchronization signal SYC and a sample hold signal CKS.

  Specifically, the DLL circuit 230 includes a delay control circuit 232 and a delay circuit 234. The delay control circuit 232 outputs a delay control signal PNB. For example, the delay control circuit 232 performs a phase comparison process based on the feedback signal from the DLL circuit 230 to generate the delay control signal PNB. As this phase comparison process, various processes can be assumed as will be described later.

  The delay circuit 234 includes a plurality of delay units D0 to Dn-1 (first to nth delay units). These delay units D0 to Dn-1 are connected in series. For example, the output of the kth (1 ≦ k <n) delay unit Dk is input to the next k + 1th delay unit Dk + 1, and the output of the k + 1th delay unit Dk + 1 is the next k + 2th delay unit Dk + 2. Is input.

  Delay times of the delay units D0 to Dn-1 are controlled by a delay control signal PNB from the delay control circuit 232. For example, when the delay units D0 to Dn-1 are current control type inverter circuits, the delay control signal PNB is a signal for controlling the current (bias current) flowing through the inverter circuit. When the current flowing through the inverter circuit becomes large, the delay time becomes short, and when the current becomes small, the delay time becomes long. The signal from the delay circuit 234 is fed back to the delay control circuit 232, whereby a loop of the DLL circuit 230 is formed, and a DLL operation is performed in which the delay time of each delay unit D0 to Dn-1 is locked. Specifically, the delay times of the delay units D0 to Dn−1 are locked so that the phase difference from the delay unit D0 to the delay unit Dn−1 is, for example, 360 degrees.

  The output circuit 240 outputs a synchronization signal SYC and a sample hold signal CKS based on the multiphase clock signal from the DLL circuit 230. That is, a clock signal whose phase is shifted by zero degrees and 90 degrees with respect to the drive signal DQ is selected from the multiphase clock signals and output as the synchronization signal SYC and the sample hold signal CKS, respectively. The multiphase clock signal is a clock signal whose phase is sequentially shifted. For example, the first clock signal of the multiphase clock signal is the output signal of the delay unit D0. The second and third clock signals of the multiphase clock signal are output signals of the delay units D1 and D2. The phase of the second clock signal is shifted by the delay time of the delay unit D1 with respect to the first clock signal, and the third clock signal is delayed by the delay unit D2 with respect to the second clock signal. The phase is shifted by the delay time.

  The adjustment circuit 220 includes at least one delay unit whose delay time is controlled by the delay control signal PNB. Then, a signal DLI obtained by delaying an input signal IN (for example, a signal obtained by binarizing the output signal DV) based on the output signal DV from the drive circuit 30 is output to the DLL circuit 230. That is, the signal IN is delayed by the delay unit included in the adjustment circuit 220, and the delayed signal DLI is input to the DLL circuit 230.

  Specifically, the adjustment circuit 220 includes a delay unit having the same configuration as the delay units D0 to Dn-1 of the delay circuit 234. The delay time of the adjustment circuit 220 is controlled based on the delay control signal PNB, similarly to the delay units D0 to Dn-1 of the DLL circuit 230. For example, when the delay units D0 to Dn-1 are configured by a current control type inverter circuit, the adjustment circuit 220 is also configured by a current control type inverter circuit having the same configuration. In the inverter circuit, the delay time is controlled based on the delay control signal PNB, similarly to the inverter circuit constituting the delay units D0 to Dn-1 of the DLL circuit 230. Note that the delay time of the delay unit of the adjustment circuit 220 may be set to be shorter or longer than the delay time of the delay units D0 to Dn-1 of the delay circuit 234.

  According to the synchronization signal output circuit 52 of the present embodiment described above, the delay time of the delay unit of the adjustment circuit 220 is controlled using the delay control signal PNB used in the delay circuit 234 of the DLL circuit 230. A signal DLI obtained by delaying the input signal IN is input to the DLL circuit 230 by the delay unit of the adjustment circuit 170.

  For example, the number of delay units D0 to Dn−1 of the delay circuit 234 is n = 360, and the DDO 0 to Dn− are controlled by the DLL circuit 230 so that the phase delay (phase change amount) of one delay unit becomes 1 degree. Assume that the delay time of each delay unit is locked.

  In this case, for example, if a delay unit whose delay time is half that of each of the delay units D0 to Dn-1 of the delay circuit 234 is provided in the adjustment circuit 220, fine adjustment of the phase in 0.5 degree steps can be performed. This can be realized by the circuit 220. Further, for example, if 30 delay units controlled by the delay control signal PNB are provided in the adjustment circuit 220, the adjustment circuit 220 can realize rough adjustment of the phase in steps of 30 degrees. Therefore, according to the present embodiment, fine adjustment and coarse adjustment of the phase can be realized by a simple method of adding the adjustment circuit 220 whose delay time is controlled by the delay control signal PNB.

  In particular, the present embodiment is characterized in that the adjustment circuit 220 does not enter the loop of the DLL circuit 230 (delay time lock loop). In this way, the phase adjustment amount (delay time) set by the delay control signal PNB is locked and fixed by the loop of the DLL circuit 230. For example, if the number of delay units of the delay circuit 234 is 360, the phase adjustment amount set by the delay control signal PNB is fixed to 1 degree (degree), and if 180 is set, it is fixed to 2 degrees. Since the adjustment circuit 220 is not in the loop of the DLL circuit 230, even if the number of delay units in the adjustment circuit 220 is increased or decreased, the phase adjustment amount set by the delay control signal PNB is not affected and changes. do not do. Therefore, there is an advantage that accurate fine adjustment and coarse adjustment of the phase can be realized by setting the number of stages of the delay unit in the adjustment circuit 220 and setting the delay time of the delay unit.

7). Detailed Configuration of Electronic Device, Gyro Sensor, and Circuit Device FIG. 17 shows a circuit device 20 of the present embodiment, a gyro sensor 510 (physical quantity detection device in a broad sense) including the circuit device 20, and an electronic device including the gyro sensor 510. 500 detailed configuration examples are shown.

  Note that the circuit device 20, the electronic device 500, and the gyro sensor 510 are not limited to the configuration shown in FIG. 17, and various modifications such as omitting some of the components or adding other components are possible. . In addition, as the electronic device 500 of the present embodiment, various devices such as a digital camera, a video camera, a smartphone, a mobile phone, a car navigation system, a robot, a biological information detection device, a game machine, a watch, a health appliance, or a portable information terminal are used. Equipment can be assumed. In the following description, the physical quantity transducer (angular velocity sensor element) is a piezoelectric vibrating piece (vibrating gyro) and the sensor is a gyro sensor. However, the present invention is not limited to this. For example, the present invention can be applied to a capacitance detection type vibration gyro formed from a silicon substrate or the like, a physical quantity equivalent to angular velocity information, or a physical quantity transducer that detects a physical quantity other than angular velocity information.

  Electronic device 500 includes a gyro sensor 510 and a processing unit 520. Further, a memory 530, an operation unit 540, and a display unit 550 can be included. A processing unit 520 (external processing device) realized by a CPU, MPU, or the like performs control of the gyro sensor 510 and the like and overall control of the electronic device 500. The processing unit 520 performs processing based on angular velocity information (physical quantity in a broad sense) detected by the gyro sensor 510. For example, processing for camera shake correction, posture control, GPS autonomous navigation, and the like is performed based on the angular velocity information. The memory 530 (ROM, RAM, etc.) stores control programs and various data, and functions as a work area and a data storage area. The operation unit 540 is for the user to operate the electronic device 500, and the display unit 550 displays various information to the user.

  The gyro sensor 510 (physical quantity detection device) includes the resonator element 10 and the circuit device 20. The vibrating piece 10 (physical quantity transducer or angular velocity sensor element in a broad sense) is a piezoelectric vibrating piece formed from a thin plate of a piezoelectric material such as quartz. Specifically, the vibrating piece 10 is a double T-shaped vibrating piece formed of a Z-cut quartz substrate.

  The circuit device 20 includes a drive circuit 30, a detection circuit 60, a control unit 140, a register unit 142, an output unit 144 (interface unit), and a nonvolatile memory 146. Various modifications such as omitting some of these components or adding other components are possible.

  The drive circuit 30 outputs a drive signal DQ to drive the resonator element 10. For example, the vibration piece 10 is excited by receiving the feedback signal DI from the vibration piece 10 and outputting the corresponding drive signal DQ. The drive circuit 30 includes a sample hold circuit 42, an n-th order low-pass filter circuit 46, and a phase adjustment circuit 54, and performs gain control of the AGC loop as described above. The detection circuit 60 receives the detection signals IQ1 and IQ2 (detection current and charge) from the vibration piece 10 driven by the drive signal DQ, and receives a desired signal corresponding to the physical quantity applied to the vibration piece 10 from the detection signals IQ1 and IQ2. (Coriolis force signal, physical quantity information in a broad sense) is detected (extracted).

  The resonator element 10 includes a base 1, connecting arms 2 and 3, driving arms 4, 5, 6 and 7, and detection arms 8 and 9. The detection arms 8 and 9 extend in the + Y axis direction and the −Y axis direction with respect to the rectangular base 1. Further, the connecting arms 2 and 3 extend in the −X axis direction and the + X axis direction with respect to the base portion 1. The drive arms 4 and 5 extend in the + Y-axis direction and the −Y-axis direction with respect to the connection arm 2, and the drive arms 6 and 7 extend in the + Y-axis direction and the −Y-axis direction with respect to the connection arm 3. ing. The X axis, the Y axis, and the Z axis indicate crystal axes, and are also referred to as an electric axis, a mechanical axis, and an optical axis, respectively.

  The drive signal DQ from the drive circuit 30 is input to the drive electrodes provided on the upper surfaces of the drive arms 4 and 5 and the drive electrodes provided on the side surfaces of the drive arms 6 and 7. In addition, signals from the drive electrodes provided on the side surfaces of the drive arms 4 and 5 and the drive electrodes provided on the upper surfaces of the drive arms 6 and 7 are input to the drive circuit 30 as feedback signals DI. Further, signals from detection electrodes provided on the upper surfaces of the detection arms 8 and 9 are input to the detection circuit 60 as detection signals IQ1 and IQ2. The common electrode provided on the side surfaces of the detection arms 8 and 9 is grounded, for example.

  When an AC drive signal DQ is applied by the drive circuit 30, the drive arms 4, 5, 6, and 7 perform bending vibration (excitation vibration) as indicated by an arrow A due to the inverse piezoelectric effect. That is, the distal ends of the driving arms 4 and 6 repeatedly approach and separate from each other, and the distal ends of the driving arms 5 and 7 also perform bending vibrations that repeatedly approach and separate from each other. At this time, since the driving arms 4 and 5 and the driving arms 6 and 7 are oscillating line-symmetrically with respect to the Y axis passing through the center of gravity of the base 1, the base 1, the connecting arms 2 and 3, and the detection arm 8. , 9 hardly vibrate.

  In this state, when an angular velocity with the Z axis as the rotation axis is applied to the vibrating piece 10 (when the vibrating piece 10 rotates around the Z axis), the drive arms 4, 5, 6, and 7 are moved to the arrow B by Coriolis force. Vibrate as shown. That is, the Coriolis force in the direction of the arrow B perpendicular to the direction of the arrow A and the direction of the Z-axis acts on the drive arms 4, 5, 6, and 7, thereby generating a vibration component in the direction of the arrow B. The vibration of the arrow B is transmitted to the base 1 via the connecting arms 2 and 3, and the detection arms 8 and 9 perform bending vibration in the direction of the arrow C. Charge signals generated by the piezoelectric effect due to the bending vibration of the detection arms 8 and 9 are input to the detection circuit 60 as detection signals IQ1 and IQ2. Here, the vibration of the arrow B of the drive arms 4, 5, 6, and 7 is the vibration in the circumferential direction with respect to the center of gravity of the base portion 1, and the vibration of the detection arms 8 and 9 is It is the vibration in the direction of the arrow C in the opposite direction. The detection signals IQ1 and IQ2 are signals whose phases are shifted by 90 degrees with respect to the drive signal DQ.

  For example, when the angular velocity of the vibrating piece 10 (gyro sensor) around the Z axis is ω, the mass is m, and the vibration velocity is v, the Coriolis force is expressed as Fc = 2 m · v · ω. Therefore, the detection circuit 60 can obtain the angular velocity ω by detecting a desired signal that is a signal corresponding to the Coriolis force. By using the obtained angular velocity ω, the processing unit 520 can perform various processes for camera shake correction, posture control, GPS autonomous navigation, and the like.

  FIG. 17 shows an example in which the resonator element 10 is a double T-shape, but the resonator element 10 of the present embodiment is not limited to such a structure. For example, a tuning fork type, an H type, or the like may be used. In addition, the piezoelectric material of the resonator element 10 may be a material such as ceramics or silicon other than quartz.

  The control unit 140 performs various control processes. For example, the control unit 140 performs control processing for the drive circuit 30 and the detection circuit 60. Further, access control to the register unit 142, control of the output unit 144, read control of the nonvolatile memory 146, and the like are performed. The control unit 140 can be realized by a logic circuit generated by an automatic placement and routing method such as a gate array, or a processor that operates based on firmware or the like.

  The register unit 142 includes a register in which various types of information are set. The register unit 142 can be realized by a memory such as an SRAM, a flip-flop circuit, or the like.

  The output unit 144 outputs various information. The output unit 144 functions as an interface unit (I / F unit) with an external device, and outputs post-computation physical quantity information from the detection circuit 60 by a given communication method, for example. For example, as described later, post-computation physical quantity information such as rotation speed information is output as serial data (serial communication method).

  The nonvolatile memory 146 is a nonvolatile memory that stores various types of information. As the nonvolatile memory 146, for example, an EEPROM or an EPROM can be used. Various types of non-volatile memory 146 may be used. For example, a memory using a fuse or a memory other than a semiconductor may be used. Further, the nonvolatile memory 146 may be provided outside the circuit device without being provided inside.

  FIG. 18 shows a detailed configuration example of the drive circuit 30 and the detection circuit 60 of the circuit device.

  The drive circuit 30 includes an amplifier circuit 32 to which the feedback signal DI from the vibration piece 10 is input, a gain control circuit 40 that performs automatic gain control, and a drive signal output circuit 50 that outputs the drive signal DQ to the vibration piece 10. . A synchronization signal output circuit 52 that outputs the synchronization signal SYC to the detection circuit 60 is also included. The configuration of the drive circuit 30 is not limited to that shown in FIG. 18, and various modifications such as omitting some of these components or adding other components are possible.

  The amplification circuit 32 (I / V conversion circuit) amplifies the feedback signal DI from the vibration piece 10. For example, a current signal DI from the vibrating piece 10 is converted into a voltage signal DV and output. The amplifier circuit 32 can be realized by an operational amplifier, a feedback resistor element, a feedback capacitor, or the like.

  The drive signal output circuit 50 outputs a drive signal DQ based on the signal DV amplified by the amplifier circuit 32. For example, when the drive signal output circuit 50 outputs a rectangular wave (or sine wave) drive signal, the drive signal output circuit 50 can be realized by a comparator or the like.

  The gain control circuit 40 (AGC) outputs a control voltage VCTL to the drive signal output circuit 50 to control the amplitude of the drive signal DQ. Specifically, the gain control circuit 40 monitors the signal DV and controls the gain of the oscillation loop. For example, in the drive circuit 30, in order to keep the sensitivity of the gyro sensor constant, it is necessary to keep the amplitude of the drive voltage supplied to the vibration piece 10 (drive vibration piece) constant. Therefore, a gain control circuit 40 for automatically adjusting the gain is provided in the oscillation loop of the drive vibration system. The gain control circuit 40 automatically variably adjusts the gain so that the amplitude of the feedback signal DI from the vibrating piece 10 (vibration speed v of the vibrating piece) is constant. The gain control circuit 40 can be realized by a sample-and-hold circuit that samples and holds the output signal DV of the amplifier circuit 32, an integrator that performs integration processing of the output signal of the full-wave rectifier circuit, or the like.

  The synchronization signal output circuit 52 includes a phase adjustment circuit 54. Then, the signal DV amplified by the amplifier circuit 32 is received, the synchronization signal SYC (reference signal) is output to the detection circuit 60, and the sample hold signal CKS is output to the gain control circuit 40. The synchronization signal output circuit 52 performs a binarization process on the sine wave (alternating current) signal DV to generate a rectangular wave synchronization signal SYC, and a phase adjustment circuit 54 (which adjusts the phase of the synchronization signal SYC). It can be realized by a phase shifter).

  The detection circuit 60 includes an amplification circuit 61, a synchronous detection circuit 81, a filter unit 90, an A / D conversion circuit 100, and a DSP unit 110. The amplifier circuit 61 receives the first and second detection signals IQ1 and IQ2 from the resonator element 10, and performs charge-voltage conversion, differential signal amplification, gain adjustment, and the like. The synchronous detection circuit 81 performs synchronous detection based on the synchronous signal SYC from the drive circuit 30. The filter unit 90 (low-pass filter) functions as a pre-filter for the A / D conversion circuit 100. The filter unit 90 also functions as a circuit that attenuates unnecessary signals that could not be removed by synchronous detection. The A / D conversion circuit 100 performs A / D conversion of the signal after synchronous detection. The DSP unit 110 performs digital signal processing such as digital filter processing and digital correction processing on the digital signal from the A / D conversion circuit 100. Examples of digital correction processing include zero point correction processing, sensitivity correction processing, integration processing, and posture calculation processing. The DSP unit 110 can be realized by a logic circuit generated by an automatic placement and routing method such as a gate array, or a processor that operates based on firmware or the like. When the automatic placement and routing method is used, for example, the DSP unit 110 and the control unit 140 can be integrally formed by an automatic placement and routing method such as a gate array.

  For example, the detection signals IQ1 and IQ2 that are charge signals (current signals) from the vibrating piece 10 are delayed in phase by 90 degrees with respect to the drive signal DQ that is a voltage signal. Further, the phase is delayed by 90 degrees in the Q / V conversion circuit of the amplifier circuit 61 and the like. For this reason, the phase of the output signal of the amplifier circuit 61 is delayed by 180 degrees with respect to the drive signal DQ. Therefore, for example, by performing synchronous detection using the synchronization signal SYC in phase with the drive signal DQ (DV), an unnecessary signal whose phase is delayed by 90 degrees with respect to the drive signal DQ can be removed.

8). Mobile Object, Electronic Device FIG. 19A shows an example of a mobile object including the circuit device 20 of this embodiment. The circuit device 20 of the present embodiment can be incorporated into various moving bodies such as cars, airplanes, motorcycles, bicycles, and ships. The moving body is, for example, a device or apparatus that moves on the ground, in the sky, or on the sea, including a driving mechanism such as an engine or motor, a steering mechanism such as a steering wheel or rudder, and various electronic devices. FIG. 19A schematically shows an automobile 206 as a specific example of the moving object. The automobile 206 incorporates a gyro sensor 510 (sensor) having the resonator element 10 and the circuit device 20. The gyro sensor 510 can detect the posture of the vehicle body 207. A detection signal of the gyro sensor 510 is supplied to the vehicle body posture control device 208. The vehicle body posture control device 208 can control the hardness of the suspension and the brakes of the individual wheels 209 according to the posture of the vehicle body 207, for example. In addition, such posture control can be used in various mobile objects such as a biped robot, an aircraft, and a helicopter. The gyro sensor 510 can be incorporated in realizing the attitude control.

  As shown in FIGS. 19B and 19C, the circuit device of this embodiment is a digital still camera, a biological information detection device (wearable health device such as a pulse meter, a pedometer, an activity meter, etc.). It can be applied to various electronic devices. For example, camera shake correction using a gyro sensor or an acceleration sensor can be performed in a digital still camera. Further, in the biological information detection apparatus, it is possible to detect a user's body movement or an exercise state using a gyro sensor or an acceleration sensor. As shown in FIG. 19D, the circuit device of this embodiment can also be applied to a movable part (arm, joint) or main body part of a robot. As the robot, any of a moving body (traveling robot, walking robot) and an electronic device (non-traveling robot, non-walking robot) can be assumed. In the case of a traveling robot or a walking robot, for example, the circuit device of this embodiment can be used for autonomous traveling.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described at least once together with a different term having a broader meaning or the same meaning in the specification or the drawings can be replaced with the different term in any part of the specification or the drawings. All combinations of the present embodiment and the modified examples are also included in the scope of the present invention. In addition, the configuration and operation of the gain control circuit, the drive circuit, the detection circuit, the circuit device, and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

1 base, 2, 3 connecting arm, 4-7 driving arm, 8, 9 detecting arm, 10 vibrating piece,
12 physical quantity transducers, 20 circuit devices, 30 drive circuits,
32 amplifier circuit, 40 gain control circuit, 42 sample hold circuit,
44 integrator, 46 n-order low-pass filter circuit, 48 full-wave rectifier circuit,
50 drive signal output circuit, 51 low-pass filter,
52 synchronization signal output circuit, 53 high-pass filter, 54 phase adjustment circuit,
55 amplification circuit, 60 detection circuit, 61 amplification circuit, 81 synchronous detection circuit,
90 filter section, 100 A / D conversion circuit, 110 DSP section,
140 control unit, 142 register unit, 144 output unit,
146 Non-volatile memory, 162 Low pass filter,
164 high pass filter, 170 adjustment circuit, 206 automobile,
207 body, 208 body posture control device, 209 wheel, 220 adjustment circuit,
230 DLL circuit, 232 delay control circuit, 234 delay circuit,
240 output circuit, 500 electronics, 510 gyro sensor,
520 processing unit, 530 memory, 540 operation unit, 550 display unit,
C1, C2, CA1 to CA3 capacitors, CCT1 first circuit,
CCT2 second circuit, CCT3 third circuit, CKS sample hold signal,
DI feedback signal, DQ drive signal, VCTL control voltage,
IQ1, IQ2 detection signal, OPA, OPD operational amplifier,
R1-R3 resistance elements, SA1-SA10 switch elements, SYC synchronization signal,
VR1, VR3 reference voltage

Claims (15)

A circuit device for outputting a drive signal for driving a physical quantity transducer,
An amplification circuit for amplifying a feedback signal from the physical quantity transducer;
a gain having an n-order low-pass filter circuit to which the signal amplified by the amplifier circuit is input when n is an integer of 2 or more, and outputting a control voltage based on the output of the n-order low-pass filter circuit A control circuit;
A drive signal output circuit for generating and outputting the drive signal, the amplitude of which is controlled by the control voltage, based on the signal amplified by the amplifier circuit;
A circuit device comprising: The circuit device according to claim 1,
The gain control circuit includes:
A rectifier circuit for rectifying the amplified signal by the amplifier circuit;
The circuit device, wherein the signal after rectification by the rectifier circuit is input to the n-order low-pass filter circuit. The circuit device according to claim 1 or 2,
The circuit device according to claim 1, wherein a cutoff frequency of the n-th order low-pass filter circuit is smaller than twice the frequency of the drive signal. The circuit device according to any one of claims 1 to 3,
A circuit device, wherein a cutoff frequency of the n-th order low-pass filter circuit is higher than a frequency band of physical quantity information output based on a detection signal from the physical quantity transducer. In the circuit device according to any one of claims 1 to 4,
The nth-order low-pass filter circuit is
A circuit device comprising a multiple feedback low-pass filter circuit. The circuit device according to claim 5,
The nth-order low-pass filter circuit is
An operational amplifier;
A first resistance element provided between an input node and a feedback node of the nth-order low-pass filter circuit;
A second resistance element provided between an output node of the operational amplifier and the feedback node;
A circuit device comprising: The circuit device according to claim 6,
A circuit device characterized in that a gain of the n-th order low-pass filter circuit is set by a resistance ratio of the first resistance element and the second resistance element. The circuit device according to claim 6 or 7,
The nth-order low-pass filter circuit is
A circuit device comprising a third resistance element provided between the feedback node and a first input node of the operational amplifier. The circuit device according to any one of claims 5 to 8,
The nth-order low-pass filter circuit is
An operational amplifier;
A first capacitor provided between a feedback node of the nth-order low-pass filter circuit and a first power supply node;
A second capacitor provided between an output node and a first input node of the operational amplifier;
A circuit device comprising: The circuit device according to claim 9, wherein
The circuit device according to claim 1, wherein a capacity of the second capacitor is smaller than a capacity of the first capacitor. The circuit device according to claim 9 or 10,
The circuit device according to claim 1, wherein the first capacitor is a metal-oxide-semiconductor (MOS) capacitor. The circuit device according to any one of claims 9 to 11,
The circuit device according to claim 1, wherein the second capacitor is an MIM (Metal-Insulator-Metal) capacitor. The circuit device according to any one of claims 1 to 12,
A circuit device comprising: a detection circuit that outputs physical quantity information corresponding to the physical quantity based on a detection signal corresponding to the physical quantity output from the physical quantity transducer.   An electronic apparatus comprising the circuit device according to claim 1.   A moving body comprising the circuit device according to claim 1.

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