JP2016221714A - Power supply device, printer and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power supply circuit and a control method which can accurately specify an abnormality when the abnormality occurs in the power supply circuit and a load while reducing the charging time of an electrolytic capacitor.SOLUTION: After completion of changing of an electrolytic capacitor 105, a current value of a charging circuit 106 is switched to a first current value smaller than a current value before completion of charging of the electrolytic capacitor 105. Whether a voltage value detected by a voltage detection circuit 121 is equal to or greater than a prescribed threshold, when the voltage value detected after completion of charging of the electrolytic capacitor 105 is less than the prescribed threshold, the current value supplied by the charging circuit 106 is switched to a current value higher than the first current value. The number of times of rising the current value supplied by the charging circuit 106 after completion of charging of the electrolytic capacitor 105 and before operation termination of a recording head 3 is specified, and error processing is executed on the basis of the specified number of times.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a power supply device, a printer, and a control method, and more particularly, to a power supply device, a printer, and a control method including a unit that controls power supply to a load.

  In recent inkjet recording apparatuses (hereinafter also referred to as recording apparatuses), the number of nozzles for ejecting ink has been increasing in order to improve printing speed and print resolution. For example, in the case of a thermal recording apparatus, a heater is provided in the vicinity of the ink discharge port, and by supplying power to the heater, the ink is instantly foamed and the ink is ejected by the kinetic energy of the foaming.

  In such a recording apparatus, the power consumed at the time of image formation varies depending on the density of the image. When an image having a high density is formed, a large number of nozzle driving heaters are instantaneously turned on in order to eject a large amount of ink onto the paper surface, and a large current is passed through a head including the nozzles in a short time.

  When an instantaneous large current is passed, it is necessary to lower the impedance of the power supply, and a printer is known in which an electrolytic capacitor having a small equivalent series resistance value and a large capacity is connected to a power supply line near the recording head ( Patent Document 1). In Patent Document 1, a push-pull circuit is provided in which a current is limited in order to prevent an inrush current from being generated when charging or discharging an electric charge with respect to an electrolytic capacitor.

JP 2009-286096 A

  By the way, when an electrolytic capacitor having a large capacity is connected to the power supply circuit, the charging time of the electrolytic capacitor becomes long. Therefore, if the value of the current passed through the power supply circuit is increased in order to shorten the charging time of the electrolytic capacitor, it becomes difficult to detect when an abnormality occurs due to a short circuit or the like in the device including the power supply circuit or the head.

  In view of the circumstances described above, the present invention provides a power supply device, a printer, and a control method capable of specifying an abnormality more accurately when an abnormality occurs in a power supply circuit or a load while shortening the charging time of an electrolytic capacitor. It is an issue to provide.

  In order to achieve the above object, a power supply apparatus of the present invention is connected to a power supply unit that supplies power to a power load via a power supply line, and to the power supply line that connects the power supply unit and the power load. A capacitor, a charging circuit that limits the current value of power supplied from the power supply unit and charges the capacitor, a detection unit that detects a voltage value of the capacitor, and a voltage value detected by the detection unit Determining means for determining whether or not the capacitor is equal to or greater than a predetermined threshold; and switching the current value of the charging circuit after completion of charging of the capacitor to a first current value smaller than the current value before completion of charging of the capacitor; If the voltage value detected by the detection means after completion of charging is less than a predetermined voltage value, the current value supplied by the charging circuit is higher than the first current value. Control means for controlling switching, specifying means for specifying the number of times the current value supplied by the charging circuit is increased after the charging of the capacitor is completed and before the operation of the power load is completed, and the specifying Execution means for executing error processing based on the number of times specified by the means.

  According to the present invention, it is possible to more accurately identify an abnormality when an abnormality occurs in the power supply circuit or the load while shortening the charging time of the electrolytic capacitor.

FIG. 2 is a block diagram illustrating a control circuit configuration of the printer according to the first embodiment. 3 is a flowchart illustrating an operation of supplying power to the recording head according to the first embodiment. It is a timing chart which shows charge and discharge to an electrolytic capacitor. It is a timing chart which shows the electrolytic capacitor voltage, head charging current, and leakage current when abnormality occurs in the leakage current according to the reference example. 3 is a timing chart showing an electrolytic capacitor voltage, a head charging current, and a leakage current when an abnormality occurs in the leakage current according to the first embodiment. It is a timing chart which shows the voltage and electric current value when a momentary interruption occurs. It is a timing chart which shows a voltage and electric current value when a leak abnormality occurs. It is a timing chart which shows a voltage and electric current value when a comparatively small leak abnormality occurs. FIG. 3 is a state transition diagram illustrating a control flow according to the first embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram illustrating a main configuration of a printer control circuit which is an example of a power supply apparatus according to the first embodiment. In FIG. 1, a printer having a printing function will be described as an example. However, the printer is not limited to this, and may be, for example, a composite printer having a printing function and a reading function. The power supply device is not limited to a printer, and may not have a printing function as long as it is a device that supplies power to a load.

  1 includes a power supply circuit 101, a head power supply control block 102, a printer control CPU 123, a RAM 125, a ROM 124, a charging circuit 106, a discharging circuit 107, the print head 3, an electrolytic capacitor 105, and the like. Have. In addition, a field effect transistor (FET) 103 and a transistor 104 are included. In the present embodiment, “power supply power” refers to power supplied from the power supply circuit 101 to the print head 3.

  The power supply circuit 101 is a so-called power supply unit, and is an AC / DC converter that generates a DC voltage for driving the head from an AC power supply (not shown). In FIG. 1, the output of the DC voltage for driving the head power supply is denoted by VM.

  The printer control CPU 123 is a central processing unit that controls the entire recording apparatus, and controls the operation of the entire printer by executing a program or starting up hardware.

  The ROM 124 stores programs and setting parameters for controlling the entire printer. The RAM 125 is used as a work area for converting a print job received from the outside into print data, developing a program, and temporarily storing parameters and image data.

  The head power supply control block 102 includes a head power supply control sequencer 122, a circuit 121 for detecting the power supply voltage of the head, and a counter 131, and controls the power supplied to the head.

  The voltage detection circuit 121 detects a voltage value (head power supply voltage value) of a power supply line that supplies power to the print head. Hereinafter, the head power supply voltage is also referred to as “electrolytic capacitor voltage”. This is because the voltage of the electrolytic capacitor 105 is the same as the head power supply voltage. The voltage detection circuit 121 may be an AD converter or a circuit in which a plurality of comparators are arranged to have a plurality of threshold values. The head power supply voltage is divided by the resistors 111 and 112 and input to the voltage detection circuit 121 from the input terminal PI1. The head power supply control sequencer 122 controls on / off of the transistor 104 by outputting a signal from PO1. Further, the current values of the charging circuit 106 and the discharging circuit 107 are controlled. The head power supply control sequencer 122 controls the current value supplied by the charging circuit 106 by outputting a signal from PO2, and controls the current value discharged by the charging circuit 107 by outputting a signal from PO3. . The counter 131 is a counter that counts the number of times the current value supplied by the charging circuit 106 is switched before the electrolytic capacitor 105 is completely charged and before the electrolytic capacitor 105 starts discharging.

  The CPU 123 and the head power supply control block 102 may be mounted on the LSI as the same integrated circuit, or may be mounted as separate LSIs.

  The print head 3 is a part that performs a printing operation as a power load. In the present embodiment, the print head 3 has ink tanks for each color, and performs recording by ejecting ink droplets onto a recording medium (for example, paper). The print head 3 may eject ink while moving in a direction orthogonal to the transport direction along the shaft that supports the head carriage, or a line head having nozzle rows of each color along the transport direction. It may have. The printer according to the present embodiment performs printing by a thermal method, and a plurality of heaters are provided in the vicinity of the ink discharge ports. When ink is ejected, the ink is instantly foamed by supplying power to the heater, and the ink is ejected by the kinetic energy of the foaming.

  The electrolytic capacitor 105 is an electrolytic capacitor that supplies power to the print head 3, and also serves to absorb load fluctuations that change depending on the ink discharge status. The electrolytic capacitor 105 is connected in parallel with the recording head 3 with respect to a power supply line (power supply line). In the present embodiment, the electrolytic capacitor 105 is a capacitor having a small equivalent series resistance value and a large capacity. By using the electrolytic capacitor 105 having a large capacity, a large charge accumulated in the electrolytic capacitor 105 is supplied as instantaneous power when an image having a high density is formed. As a result, even in a situation where a large current flows instantaneously, a drop in the heater driving voltage can be prevented and stable ink ejection can be realized.

  The FET 103 is turned on when the print head 3 requires a large amount of power to perform a printing operation. In this embodiment, the gate is opened and closed by turning on and off the transistor 104 with a PMOS. The transistor 104 is connected to the output terminal PO1 of the head power supply control block 102, and is turned on / off by a signal High / Low output from the head power supply control sequencer 122. In this embodiment, when the electrolytic capacitor 105 is charged by the charging circuit 106, the FET 103 is turned off.

  The charging circuit 106 is a circuit for charging the electrolytic capacitor 105, and the discharging circuit 107 is a circuit for discharging the electrolytic capacitor 105.

  The charging circuit 106 limits the current value of the power supplied from the power supply circuit 101 and charges the electrolytic capacitor 105. The charging circuit 106 is a constant current circuit having a current mirror configuration, includes an FET and a constant current source 108, and generates a reference current by the constant current source 108. The constant current source 108 is controlled by the output terminal PO2 of the head power supply control block 102, and the current value can be switched in a plurality of stages. In the present embodiment, the charging time can be shortened by switching the current supplied by the charging circuit 106. More specifically, when the electrolytic capacitor 105 is charged, the current supplied by the charging circuit 106 is set to a high current value, and after the request for charging the electrolytic capacitor 105 is completed, the current supplied by the charging circuit 106 is low. Value. The details of switching the current value of the constant current source 108 will be described later.

  Similarly to the charging circuit 106, the discharge circuit 107 is a constant current circuit having a current mirror configuration, includes an FET and a constant current source 109, and the constant current source 109 generates a reference current. In addition, the constant current source 109 is connected to the output terminal PO3 of the head power supply control block 102, and the current value can be switched in a plurality of stages in the same manner as the constant current source 108.

  A head power supply control sequence according to the present embodiment will be described with reference to FIGS. The flowchart in FIG. 2 is a flowchart showing an operation of supplying power to the print head. FIG. 3 is a timing chart showing charging and discharging of the electrolytic capacitor, and a part of the flow of FIG. 2 is shown in the timing chart.

  The flowchart shown in FIG. 2 is realized, for example, when the CPU 123 reads a program stored in the ROM 124 into the RAM 125 and executes it. Specifically, a flow is shown in which the printer receives a print command and the head 3 is turned on from the state where the head 3 is not turned on to perform the printing operation.

  When the printer receives a print command, control of the power supply voltage is started (S201), and the electrolytic capacitor 105 is charged (S202 to S207). Here, Ichg1, Ichg2, and Ichg3 shown in FIGS. 2 and 3 are charging currents output from the charging circuit 106, respectively, and are switched according to the voltage state of the electrolytic capacitor. Specifically, when the voltage of the electrolytic capacitor monitored by the voltage detection circuit 121 exceeds preset voltage threshold values (Vth1, Vth2), the charging current value is increased to a predetermined value (Ichg2, Ichg3). Thus, in the present embodiment, by switching the charging current value, charging can be completed as quickly as possible while satisfying the thermal limitation of the FET of the charging circuit 106. In the present embodiment, the heat calculated by the product of the potential difference between the source and drain of the FET of the charging circuit 106 and the current output from the charging circuit 106 is set so as to satisfy the allowable loss of the FET of the charging circuit 106. . For example, when the potential difference between the source and the drain is VM−Vth1 and the current is Ichg1, the amount of heat generated in the charging circuit 106 is expressed as (VM−Vth1) × Ichg1. Similarly, when the potential difference between the source and the drain is VM−Vth2 and the current value is Ichg2, the amount of heat generated in the charging circuit 106 is expressed as (VM−Vth2) × Ichg2. When the potential difference between the source and the drain is VM−Vth3 and the current value is Ichg3, the amount of heat generated in the charging circuit 106 is expressed as (VM−Vth3) × Ichg3. All of (VM−Vth1) × Ichg1, (VM−Vth2) × Ichg2, and (VM−Vth3) × Ichg3 are set to be equal to or less than a certain allowable loss. Therefore, the current value Ichg1 when the potential difference with VM is less than Vth1 is relatively small, and Ichg3 when the potential difference with VM is less than Vth3 is relatively large. In the present embodiment, the switching of the current value is shown in three stages, but the present invention is not limited to this, and the number of switching of the current value may be more than three or less than three. First, the head power supply control sequencer 122 outputs a signal from the output terminal PO2 so as to select Ichg1 as the charging current value of the charging circuit 106 (S202). Then, it is determined whether the voltage of the electrolytic capacitor detected by the voltage detection circuit 121 is Vth1 or higher (first threshold or higher) (S203). If it is determined that the voltage of the electrolytic capacitor is equal to or higher than Vht1 (Yes in S203), the head power supply control sequencer 122 outputs a signal from the output terminal PO2 so as to select Ichg2 as the charging current value of the charging circuit 106 (S204). That is, the charging current value of the charging circuit 106 is switched from Ichg1 to Ichg2. Then, it is determined whether the voltage of the electrolytic capacitor detected by the voltage detection circuit 121 is Vth2 or higher (second threshold or higher) (S205).

  If it is determined that the voltage of the electrolytic capacitor is equal to or higher than Vht2 (Yes in S205), Tcnt is reset (S206), and the current setting value is set to Ichg3 (S207). Note that the order of S206 and S207 may be reversed. In S206, the counter Tcnt counted up every time Ichg3 is switched is reset and the counter value becomes zero. Although details will be described later in this embodiment, an error is determined when the counter Tcnt reaches a preset number of times. In S207, the head power supply control sequencer 122 outputs a signal from the output terminal PO2 so as to select Ichg3 as the charging current value of the charging circuit 106. That is, the charging current value of the charging circuit 106 is switched from Ichg2 to Ichg3. FIG. 3A is a timing chart of the voltage of the electrolytic capacitor 105 monitored by the voltage detection circuit 121. FIG. 3B is a timing chart showing the charging current and discharging current to the electrolytic capacitor, and FIG. 3C is a timing chart showing the voltage level of PO1.

  During the period 310 during which the electrolytic capacitor 105 is charged, the voltage rise curve becomes steep. This is because, as shown in FIG. 3B, the charging current value is switched from Ichg1 to Ichg2 at timing 301 when the electrolytic capacitor voltage becomes equal to or higher than the threshold value of Vth1.

  After Ichg3 is selected, it is determined whether the voltage of the electrolytic capacitor detected by the voltage detection circuit 121 is Vth3 or more (third threshold or more) (S208). If it is determined that the voltage of the electrolytic capacitor is equal to or higher than Vht3 (Yes in S208), the head power supply control sequencer 122 outputs a signal from the output terminal PO2 so as to select the voltage holding current value Ikeep as the charging current value of the charging circuit 106. (S209). That is, the charging current value of the charging circuit 106 is switched from Ichg1 to Ikeep. The current value Ikeep is a current value that can detect an increase in leakage while maintaining the voltage of the electrolytic capacitor 105. Therefore, the Ikeep current value is set to a value lower than the value when the charging current value is increased (for example, Ichg3). In the present embodiment, the Ikeep current value is set to a value lower than Ichg1, that is, a value lower than the current value supplied by the charging circuit 106 during charging.

  After switching to Ikeep, a value is set in a counter Toff that determines an error detection invalid period (S210), and it is determined whether the voltage of the electrolytic capacitor is less than Vth_error (less than the error voltage value) (S211). The counter Toff is a down counter. The set value of the Toff counter is set to a time longer than a time during which the voltage can be recovered from a voltage drop due to an instantaneous interruption to a value higher than Vth_error. Here, the instantaneous interruption means that a voltage is not temporarily applied by the power supply circuit 101 for a very short time due to an external factor.

  If the voltage of the electrolytic capacitor is equal to or higher than Vth_error (Yes in S211), the charging of the electrolytic capacitor 105 is completed, and the printing data is ready, the printing operation is started (S212). First, in S213, PO1 of the head power supply control sequencer 122 is set to High (see timing 304 in FIG. 3C). Thereby, the FET 103 is turned on. If the FET 103 is not turned on, the current supplied by the charging circuit 106 to the power supply line is in an Ikeep state, so that the power consumed by the head for printing cannot be secured sufficiently. The printing operation by the recording head 3 in S212 is executed (S214). When the printing operation is completed, the voltage level of PO1 is set to Low in S215 (see timing 305 in FIG. 3C). As a result, the FET 103 in FIG. 1 is turned off. The completion of the printing operation here includes, for example, completion of one scan of the serial printer. The serial printer prints on the paper as the recording medium while moving the head 3 in the first direction, and then prints on the paper while moving in the second direction opposite to the first direction. In the present embodiment, the printing operation is completed when printing in one line or a plurality of lines is completed by moving in any one direction.

  Then, the head power supply control sequencer 122 outputs a signal from the output terminal PO2 so as to select Ikeep as the charging current value of the charging circuit 106 (S216). That is, the supply current to the head returns to Ikeep.

  In step S217, it is determined whether printing is completed. If it is determined that printing has been completed (Yes in S217), the control proceeds to discharging the head power supply capacitor (S226 to S231). The electrolytic capacitor 105 uses the discharge circuit 107 to discharge while limiting the current. Here, the electrolytic capacitor 105 is set to satisfy the thermal restriction of the FET of the discharge circuit 107 when discharging, similarly to the charging.

  First, the head power supply control sequencer 122 outputs a signal from the output terminal PO3 so as to select Idis3 as the discharge current value of the discharge circuit 107 (S226). Here, since the potential difference between the source and drain of the FET of the discharge circuit 107 becomes a difference between GND and the head power supply voltage, the higher the head power supply potential, the larger the potential difference. Therefore, at timings 306 to 307 in FIG. 3B, the discharge current Idis3 is set to a small value.

  Then, it is determined whether the voltage of the electrolytic capacitor detected by the voltage detection circuit 121 is less than Vth2 (S227). When the voltage of the electrolytic capacitor detected by the voltage detection circuit 121 becomes less than Vth2 (Yes in S227), the head power supply control sequencer 122 sends a signal from the output terminal PO3 so as to select Idis2 as the discharge current value of the discharge circuit 107. It outputs (S228). That is, from timing 307, the discharge current is switched from Idis3 to Idis2. Here, Idis2 is set to a value slightly larger than Idis3. Then, it is determined whether the voltage of the electrolytic capacitor detected by the voltage detection circuit 121 is less than Vth1 (S229). When the voltage of the electrolytic capacitor detected by the voltage detection circuit 121 becomes less than Vth1 (Yes in S229), the head power supply control sequencer 122 sends a signal from the output terminal PO3 so as to select Idis1 as the discharge current value of the discharge circuit 107. Output (S230). That is, from timing 308, the discharge current is switched from Idis2 to Idis1. Then, the discharge is completed at the timing 309 in FIG.

  Here, a case where the capacitor voltage becomes less than Vth_error in S211 will be described. When the electrolytic capacitor voltage becomes equal to or lower than the error threshold Vth error (Yes in S221), the Toff counter starts a down-count operation (S218). Then, it is determined whether the capacitor voltage is less than Vth4 (S219).

  When the capacitor voltage is less than Vth4 (No in S219), it is determined whether the capacitor voltage is equal to or higher than Vth3 (S220). If the capacitor voltage is not equal to or higher than Vth3 (No in S220), the process returns to S219. If the capacitor voltage is equal to or higher than Vth3 (Yes in S220), the process returns to S210.

  If the capacitor voltage is less than Vth4 (Yes in S219), Ichg3 is set as the current value (S221). Specifically, the head power supply control sequencer 122 outputs a signal from the output terminal PO2 so as to select Ichrg3 as the charging current value of the charging circuit 106 (S221). At this time, by switching to Ichg3, Tcnt is incremented by one step (S222), and it is determined whether Tcnt is a set value (S223). In the present embodiment, the set value is 5.

  If Tcnt is not the set value (No in S223), it is determined whether the Toff counter is 0 (S224). When the Toff counter becomes 0 (Yes in S224), it is determined whether the capacitor voltage is less than Vth error (S225).

  If it is determined that the capacitor voltage is not less than Vth error, that is, not less than Vth error (No in S225), the process returns to S208. Here, as described above, the Toff set value is set longer than the time required to recover from the momentary interruption. Therefore, in the case of the momentary interruption, the capacitor voltage before the downcount becomes zero. Exceeds Vth error. In S208, if the capacitor voltage is equal to or higher than Vth3, the current is switched to the Ikeep current (S209).

  If Tcnt is a set value (Yes in S223), an error process is performed and the process ends. Thus, in this embodiment, if the number of times of switching is equal to or greater than a predetermined number set in advance, error processing is executed. The error process is a process for terminating the power supply to the head 3 via the power supply line. Specifically, the FET 103 in FIG. 1 is turned off and the charging circuit 106 is turned off. Further, the power supply of the power supply circuit 101 is turned off. Further, it may be controlled such that the discharge circuit 107 is turned on to positively discharge.

  As described above, in this embodiment, it is determined whether or not to execute error processing based on the determination result whether the voltage value of the capacitor voltage is less than Vth error and the number of times of switching to increase the current value of the charging circuit 106. .

  Here, the head power supply control block 102 will be described. FIG. 9 is a state management diagram in the head power supply control sequencer 122. In FIG. 9A, a state in which the power supply of the head 3 is turned off is defined as a standby 701. When a print job is input, the state transitions to the charging state 702 in order to turn on the power of the head 3. FIG. 9B is a state transition diagram showing the charging state 702 in detail. As shown in FIG. 9B, the state of the charging state transitions by switching the charging current based on the voltage of the electrolytic capacitor in the charging state 702. When the voltage of the electrolytic capacitor becomes equal to or higher than Vth1, the charging 1 state 702_1 transitions to the charging 2 state 702_2. At this time, the charging current is switched from Ichg1 to Ichg2. Similarly, when the voltage of the electrolytic capacitor becomes Vth2 or higher, the charging current is switched from Ichg2 to Ichg3 when the charging 2 state 702_2 transitions to the charging 3 state 702_3.

  When the voltage of the electrolytic capacitor becomes Vth3 or more and charging is completed, the state shifts to the holding state 703 in FIG. Along with this, the charging current is switched to Ikeep. When the printing operation starts, the state transits to the printing operation state 704. Until the print job is completed, it moves back and forth between the holding state 703 and the state of the printing operation 704. In the present embodiment, the state transitions to the holding state 703 after the charging state 702. However, when the printing operation is rushed, the state may directly transition to the printing operation state 704 after the charging state 702.

  When the printing operation is finished, the state transits to the discharge state 705. Also, when an abnormality is detected by the head power supply voltage monitor, the state is changed to the discharge state 1005. Abnormality detection by monitoring the head power supply voltage is particularly easy to detect in the holding state 1003, but if it is detected in the printing operation state 704, it may be immediately shifted to the discharge state 705. In the printing operation state 704, when an abnormality is detected by the head power supply voltage monitor, the state may be changed to the holding state 703 and then changed to the discharge state 705.

  FIG. 9C is a state transition diagram showing the discharge state 705 in detail. As shown in FIG. 9C, when the discharge state is changed, the state of the discharge state is changed by switching the current value based on the voltage of the electrolytic capacitor. Specifically, a transition is made from the discharge 1 state 705_1 to the discharge 2 state 705_2 and the discharge 3 state 705_3, and the discharge current and Idis3, Idis2, and Idis1 are also switched each time. When the discharge is completed, the state transitions to standby 701. When the threshold value is lowered during the holding state 703, the state shifts to the charging state 702, and the current supplied by the charging circuit 106 is switched to Ichg1, Ichg2, or Ichg3 according to the voltage, and the charging operation is started again.

  As shown below, the CPU 123 manages the entire print control and manages that the head power supply is operating normally.

When the CPU 123 receives a print command from an external device connected to the printer or an instruction unit of the printer, the head power on command is sent to the head power control block 102 in parallel with the start of preparation of print data from the print job data. Put out. Upon receiving the head power on command, the head power control block 102 starts the flow of FIG. 2 (S201).
(1) The CPU 123 monitors the state of the head power supply control sequencer 122 in parallel with the preparation of print data from the print job data, and determines whether the charging state or the holding state has been reached. In this embodiment, the state of the head power supply control sequencer is monitored, but the present invention is not limited to this. For example, it may be determined whether or not the head power supply voltage is equal to or higher than Vth3 from the output value of the voltage detection circuit 121 and the value obtained by AD input by directly inputting the divided voltage between the resistor 111 and the resistor 112. . If it is determined that the state is the three charging state or the holding state, the CPU 123 periodically monitors the output value of the voltage detection circuit 121 and the value obtained by AD conversion by directly inputting the divided voltage between the resistor 111 and the resistor 112. to continue. That is, the voltage value during the stop of the print head operation is continuously monitored. When the value becomes a value corresponding to “a state where the head power supply voltage is equal to or lower than Vth_error”, it is determined that the state is abnormal and error processing is performed.
(2) When printing data is ready in a state that is not in an error state, it is determined that printing can be started, and a print operation start command is issued to the head power supply control block 102. Upon receiving the print operation start command, the head power supply control block 102 performs the process of S213. Thereafter, the CPU 123 transmits print data to the head and performs a printing operation.
(3) When the printing operation is completed, the CPU 123 issues a printing operation end command to the head power supply control block 102. In response to the print operation end command, the head power supply control block 102 performs the process of S215.
(4) If there is print job data, repeat (2) → (3).
(5) When there is no print job data, the CPU 123 issues a head power off command to the head power control block 102. In response to the head power off command, the head power control block 102 performs the process of S226.

  Next, the operation when a voltage drop due to a momentary interruption occurs will be described with reference to FIG. First, when charging is started and the head power supply voltage becomes Vth3 or higher, the current set value is set to Ichg3. The counter Tcnt that is counted up every time the Ichg3 is switched is reset and the counter value becomes zero. In the present embodiment, an error is determined when the counter Tcnt reaches a preset number of times. The head voltage further rises and the charging is completed (see 401 in the timing chart of FIG. 6A). When charging is completed, the current value is switched to lkeep smaller than Ichg3, and a value is set in a counter Toff that determines an error detection invalid period. The counter Toff is a down counter, and even if the head power supply voltage becomes equal to or lower than the error threshold value (Vth_error) until the counter value becomes 0 after the set time elapses, it is not determined as an error. As shown in FIG. 6A, the set value of the Toff counter is set to a time longer than a time during which the voltage can be recovered from a voltage drop due to a momentary interruption to a value higher than Vth_error. Thereby, it can suppress that the fall of the voltage by instantaneous interruption is erroneously detected as the error by leak. As shown in FIG. 6A, when an instantaneous interruption occurs (see 402 in FIG. 6A), the VM voltage output from the power supply circuit 101 decreases, and the electrolytic capacitor voltage also decreases at the same time. When the electrolytic capacitor voltage becomes equal to or lower than the error threshold Vth error (see 403 in FIG. 6A), the Toff counter starts a down-count operation. Further, when the voltage drop due to the instantaneous interruption continues and the capacitor voltage becomes Vth4 or less (see 404 in FIG. 6A), Ichg3 is set as the current value (see 404 in FIG. 6B). At this time, switching to Ichg3 increments Tcnt by one step, but switching to Ichg3 is the first time and does not cause an error. During this time, the Toff counter continues the down-counting operation. When the count reaches 0, the head voltage monitor is enabled and it is determined whether or not it is less than the Vth error threshold value. As described above, the Toff set value is set longer than the time required to recover from the momentary interruption. Therefore, in the case of the momentary interruption, the capacitor voltage becomes Vth error before the downcount becomes zero. That's it. Charging is completed when the capacitor voltage becomes higher than Vth3 (see 405 in FIG. 6A).

  Next, a case where a leak occurs will be described with reference to FIG. The leak here is not a leak due to natural discharge but a leak caused by a short circuit or the like occurring on the power supply circuit or the power load side. As shown at 406 in FIG. 7, when a leak occurs, the capacitor voltage starts dropping and becomes less than Vth error (see 407 in FIG. 7A). Here, since it is the Toff period, no error determination is made. Further, the capacitor voltage continues to drop, and the voltage does not rise even if the current supplied by the charging circuit 106 is returned to Ichg3 when it becomes less than Vth4, as in the case of FIG. Therefore, even when the Toff counter becomes 0, the capacitor voltage is less than Vth error (see 408 in FIG. 7A), so that it is detected as an error.

  Further, the operation when the leakage current is smaller than Ichg3 will be described with reference to FIG. The leak here is not a leak due to natural discharge but a leak caused by a short circuit or the like occurring on the power supply circuit or the power load side. After the capacitor voltage is fully charged and switched to the Ikeep current, the leakage current increases at timing 409 in FIG. 8A, and when a leakage current higher than the lkeep current occurs, the electrolytic capacitor voltage starts to decrease. . Then, it becomes less than Vth error (see timing 410 in FIG. 8A) and eventually becomes less than Vth4 (see timing 411 in FIG. 8A). When the capacitor voltage becomes less than Vth4, the current value supplied by the charging circuit 106 is controlled to be switched to Ichg3. Since the current value Ichg3 supplied by the charging circuit 106 is larger than the leakage current, the electrolytic capacitor voltage starts to rise (timing 411 to 412 in FIG. 8A). At the same time as the current value supplied by the charging circuit 106 is switched to Ichg3, a counter Tcnt that counts the switching to Ichg3 is incremented by one step as shown in FIG. 8B. When the current value supplied by the charging circuit 106 is switched to Ichg3, the electrolytic capacitor voltage continues to rise, and when the Toff becomes 0, the electrolytic capacitor voltage is already equal to or higher than Vth error. Therefore, charging is completed when the electrolytic capacitor becomes Vth3 or higher without being recognized as an error. After the charging of the electrolytic capacitor 105 is completed, lkeep is selected as the current value supplied by the charging circuit 106, but the leakage current exceeds the current supplied from the charging circuit 106 (Ikeep current). Therefore, the electrolytic capacitor voltage starts to fall again (see timing 412 and thereafter in FIG. 8). However, as shown in FIG. 8, when a leak current higher than Ichg3 continues to be generated, the above-described operation is repeated while incrementing the Tcnt counter. Each time these operations are repeated, the counter value Tcnt for switching to Ichg3 is counted up. When the counter value is equal to or greater than a preset value, it is determined that the error is due to an increase in leakage current.

  Further, the current value of the Ikeep current that is the charging current after the timing 303 in FIG. 3B will be described. The head power supply circuit discharges naturally due to various reasons even when no abnormality has occurred in the power supply circuit or the device having the power load after the electrolytic capacitor 105 of the head is completely charged. Sometimes. The reason for the spontaneous discharge is, for example, a current flowing through the voltage detection resistors 111 and 112 in FIG. 1 or a leak current that naturally occurs because the head itself is manufactured by a semiconductor process. By preventing the head power supply voltage from decreasing due to these phenomena, the printing operation can be started immediately even after a while has elapsed since the charging operation. Therefore, the Ikeep current value is set to a value larger than these natural discharge currents. Note that a natural discharge current can be assumed in advance by the configuration of the power supply circuit and the configuration of the device including the load. The Ikeep current value may be a value larger than the assumed natural discharge current. The lower limit value of the Ikeep current will be described in more detail using FIG. FIG. 4 is a timing chart showing the head power supply voltage, the head charging current, and the leakage current when the current value set for voltage holding is lower than the natural discharge current. More specifically, a timing chart in the case where the value is set smaller than the natural discharge current is shown. FIG. 4A shows the state of the voltage of the electrolytic capacitor 105. FIG. 4B is a timing chart of the current value during charging and the current value of natural discharge, and ILeak indicated by a broken line is the current value of natural discharge of the head power supply circuit. In FIG. 4B, Ikeep is a smaller value than ILeak. Therefore, as shown in FIG. 4A, the voltage of the electrolytic capacitor 105 is maintained gradually from the timing 603 when the current value of the charging circuit 106 is switched to the Ikeep current, and the voltage gradually decreases, and the Vth_error threshold is reached after a certain period of time. The value is reached. Here, Vth_error is a threshold value for monitoring the head power supply voltage after completion of charging of the electrolytic capacitor 105 and determining an abnormality. The voltage of the power supply line is monitored by monitoring the voltage of PI1 in FIG. As described above, if Ikeep is set to be equal to or less than the current value of natural discharge, it becomes impossible to accurately determine the abnormality of the head. Therefore, a value larger than ILeak at the time of natural discharge is set as Ikeep.

  As described above, the voltage of the electrolytic capacitor is monitored during a period when the printing operation is not performed. Specifically, the voltage of the electrolytic capacitor is looped between S209 and S210 in FIG. 2, and the voltage of the electrolytic capacitor is always monitored after the completion of charging and before the start of the printing operation. In the flowchart of FIG. 2, the voltage of the electrolytic capacitor is constantly monitored until the printing operation is completed. In S216, the current value is selected again as Ikeep. However, if the charging circuit in 106 of FIG. 1 is not turned off, the current value may not be selected again in S216.

  Next, the upper limit value of Ikeep will be described with reference to FIG. FIG. 5A shows the state of the voltage when charging the electrolytic capacitor. FIG. 5B shows the current value supplied by the charging circuit 106 that is charging the electrolytic capacitor and the discharge current value of the head power supply circuit, and ILeak indicated by a broken line is the discharge current value. In FIG. 5B, ILeak up to timing 504 is a current value of normal natural discharge. This ILeak is smaller than any of the current values of Ichg1, Ichg2, Ichg3, and Ikeep, and the phenomenon that the voltage drops does not occur as described with reference to FIG.

  Here, if a leak other than the spontaneous discharge occurs, that is, if the head terminal is short-circuited for some reason or the head leak increases, ILeak increases as indicated by timing 504 in FIG. 5B. . As shown in FIG. 5A, the voltage of the electrolytic capacitor gradually decreases from the timing 505 at which ILeak exceeds the value of Ikeep, and at timing 506, it is detected that an abnormality has occurred because the voltage falls below Vth_error. In the printer that detects the abnormality, it is possible to perform control such as turning off the FET 103 in FIG. 1, turning off the charging circuit 106, and turning on the discharging circuit 107 to positively discharge.

  Therefore, in the present embodiment, Ikeep is set to a specific value or less so that an abnormality can be detected at an appropriate timing for ILeak at the time of abnormality. For example, when the behavior of ILeak can be predicted, Ikeep is set so that the result of integrating ∫ {ILeak (t) × V (t)} dt in the period 508 is equal to or less than a desired amount of heat. Further, since it is difficult to detect an abnormality due to a voltage drop when it is equal to or lower than Ikeep, Ikeep may be set so that the amount of heat of VM × Ikeep falls within an allowable range.

  As described above, the present embodiment has a charging circuit that can switch the current value and a voltage detection circuit that identifies the voltage of the power supply circuit, and maintains sensitivity to detect an abnormality after charging is completed. Therefore, the current value is set small. And when the capacitor voltage falls below a predetermined threshold value for the purpose of suppressing erroneous error determination based on voltage drop due to instantaneous interruption or shortening the recovery time of voltage drop due to instantaneous interruption. Increase the current value. At this time, if the number of times the current value is increased exceeds a predetermined number, it is determined that an error has occurred. As a result, when an abnormality occurs in the power supply circuit or the head, it can be determined that the error is more accurate. Therefore, the power supply to the recording head can be stopped to ensure the safety of the printer. A leak current value generated due to an abnormality is not constant and may be lower than an assumed value assumed in advance. In this case, if the current value is switched higher each time the voltage drops, the error threshold may be exceeded and restored every time the voltage is switched. On the other hand, in the present embodiment, when an error other than spontaneous discharge, specifically, when an abnormality occurs in the power supply circuit or the head, the error can be detected with higher accuracy.

  Further, in the present embodiment, by making the current value after completion of charging lower than the current value at the time of charging, it is possible to appropriately specify the occurrence of an abnormality in the power supply circuit or the head. That is, when an abnormal leak current flows through the recording head, it is possible to immediately detect the leak current and stop power supply to the recording head.

  Therefore, it is possible to quickly detect an abnormality in the leakage current of the head while shortening the charging time of the electrolytic capacitor. Moreover, even when the voltage drop of the electrolytic capacitor occurs due to the instantaneous interruption of the power supply circuit, the desired voltage can be quickly recovered. Furthermore, an error can be detected when a leak occurs with a relatively small value. That is, according to the present embodiment, both the performance and safety of the printer can be achieved.

  Further, when increasing the value of Ichg in order to shorten the charging time of a large-capacity electrolytic capacitor, it is necessary to select a FET with a large allowable loss, which may lead to an increase in cost. On the other hand, in the present embodiment, by switching the current according to the allowable loss of the FET of the charging circuit 106, the charging time of the electrolytic capacitor is shortened to the extent that the target performance of the recording apparatus is reached, and the cost of the FET 103 is reduced. An increase can be prevented.

(Other embodiments)
The present invention is not limited to the embodiment described above. For example, in the above-described embodiment, the error determination is performed based on the number of times the current value is switched. However, the error determination method is not limited to this. For example, the number of times the capacitor voltage has repeatedly decreased or increased may be counted. In this case, the counter 131 may count the number of times that the capacitor voltage exceeds a predetermined threshold from the output of the voltage detection circuit 121.

  In the above-described embodiment, the power supply device includes the head as the power load. However, the power supply device is not limited to this and may not include the power load. That is, it may be connectable to a power load and supply power to the power load.

  In the embodiment described above, the current value supplied by the charging circuit 106 is switched when the electrolytic capacitor 105 is charged. However, the present invention is not limited to this, and the current value supplied by the charging circuit 106 is constant. It may be a current value.

  In the above-described embodiment, the current value supplied by the charging circuit 106 is switched when the electrolytic capacitor 105 is charged. However, the current value may be gradually increased.

  Further, a state machine that represents a transition state of a circuit in which the current limit value is switched may be provided, and a circuit abnormality may be detected by monitoring the state of the state machine.

Claims (12)

A power supply for supplying power to the power load via the power supply line;
A capacitor connected to the power supply line connecting the power supply unit and the power load;
A charging circuit that limits the current value of power supplied from the power supply unit and charges the capacitor;
Detecting means for detecting a voltage value of the capacitor;
Determining means for determining whether the voltage value detected by the detecting means is equal to or greater than a predetermined threshold;
The voltage detected by the detecting means after completion of charging of the capacitor is switched to a first current value smaller than the current value before completion of charging of the capacitor after completion of charging of the capacitor. Control means for controlling to switch the current value supplied by the charging circuit to a current value higher than the first current value when the value is less than a predetermined voltage value;
A specifying means for specifying the number of times the current value supplied by the charging circuit is increased after the charging of the capacitor is completed and before the operation of the power load is completed;
Execution means for executing error processing based on the number of times specified by the specifying means;
A power supply apparatus comprising:   The power supply apparatus according to claim 1, wherein the error processing is executed when the number of times specified by the specifying unit is a predetermined number or more.   3. The power supply according to claim 1, wherein the specifying unit specifies the number of times of increasing the current value supplied by the charging circuit based on the number of times the current value supplied by the charging circuit is switched. apparatus.   3. The power supply according to claim 1, wherein the specifying unit specifies the number of times the current value supplied by the charging circuit is increased based on the number of times the voltage value detected by the detection unit is increased. apparatus.   5. The power supply apparatus according to claim 1, wherein the error process is a process of terminating power supply to the power load via the power supply line. 6.   The power supply apparatus according to claim 5, wherein the execution unit turns off the power supply of the power supply unit.   The power supply apparatus according to claim 1, wherein the determination unit is executed while the operation of the power load is stopped.   The power supply device according to any one of claims 1 to 7, wherein the first current value is larger than a current value of natural discharge.   The power supply apparatus according to claim 1, wherein the power load is a print head.   The power supply device according to claim 1, comprising the power load. A power supply for supplying power to the print head via a power supply line;
A capacitor connected to the power supply line connecting the power supply unit and the print head;
A charging circuit that limits the current value of power supplied from the power supply unit and charges the capacitor;
Detecting means for detecting a voltage value of the capacitor;
Determining means for determining whether the voltage value detected by the detecting means is equal to or greater than a predetermined threshold;
The voltage detected by the detecting means after completion of charging of the capacitor is switched to a first current value smaller than the current value before completion of charging of the capacitor after completion of charging of the capacitor. Control means for controlling to switch the current value supplied by the charging circuit to a current value higher than the first current value when the value is less than a predetermined voltage value;
Specifying means for specifying the number of times of increasing the current value supplied by the charging circuit after the charging of the capacitor is completed and before the operation of the print head is completed;
Execution means for executing error processing based on the number of times specified by the specifying means;
A printer comprising: A power supply for supplying power to the power load via the power supply line;
A capacitor connected to the power supply line connecting the power supply unit and the power load;
A charging circuit that limits the current value of power supplied from the power supply unit and charges the capacitor;
A method for controlling a power supply apparatus comprising:
A first switching step of switching a current value of the charging circuit to a first current value smaller than a current value before completion of charging of the capacitor after completion of charging of the capacitor;
A detection step of detecting a voltage value of the capacitor;
A determination step of determining whether the voltage value detected by the detection step is equal to or greater than a predetermined threshold;
When the voltage value detected in the detection step after completion of charging of the capacitor is less than a predetermined voltage value, a second current value supplied from the charging circuit is switched to a current value higher than the first current value. Switching process;
A specifying step of specifying the number of times that the current value supplied by the charging circuit is increased after the charging of the capacitor is completed and before the operation of the power load is completed;
An execution step of executing error processing based on the number of times specified in the specific step;
A control method characterized by comprising:

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