JP2016218855A5 - - Google Patents
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- JP2016218855A5 JP2016218855A5 JP2015104724A JP2015104724A JP2016218855A5 JP 2016218855 A5 JP2016218855 A5 JP 2016218855A5 JP 2015104724 A JP2015104724 A JP 2015104724A JP 2015104724 A JP2015104724 A JP 2015104724A JP 2016218855 A5 JP2016218855 A5 JP 2016218855A5
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- PIGFYZPCRLYGLF-UHFFFAOYSA-N aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
Description
ここで、図７（Ａ）のように、複雑な演算命令は、演算器ＦＬＡによる演算命令の実行サイクル数Ｅ１〜ＥＮが閾値以上である演算命令である。これに対し、図７（Ｂ）のように、簡単な演算命令（後続の演算命令）は、演算器ＦＬＡによる演算命令の実行サイクル数Ｅが閾値未満である演算命令である。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015104724A JP6477248B2 (ja) | 2015-05-22 | 2015-05-22 | 演算処理装置及び演算処理装置の処理方法 |
| US15/068,692 US9965283B2 (en) | 2015-05-22 | 2016-03-14 | Multi-threaded processor interrupting and saving execution states of complex instructions of a first thread to allow execution of an oldest ready instruction of a second thread |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015104724A JP6477248B2 (ja) | 2015-05-22 | 2015-05-22 | 演算処理装置及び演算処理装置の処理方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2016218855A JP2016218855A (ja) | 2016-12-22 |
| JP2016218855A5 true JP2016218855A5 (ja) | 2018-02-15 |
| JP6477248B2 JP6477248B2 (ja) | 2019-03-06 |
Family
ID=57324564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015104724A Active JP6477248B2 (ja) | 2015-05-22 | 2015-05-22 | 演算処理装置及び演算処理装置の処理方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US9965283B2 (ja) |
| JP (1) | JP6477248B2 (ja) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2023135511A (ja) | 2022-03-15 | 2023-09-28 | 富士通株式会社 | 演算処理装置及び演算処理方法 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6567839B1 (en) | 1997-10-23 | 2003-05-20 | International Business Machines Corporation | Thread switch control in a multithreaded processor system |
| US6237081B1 (en) * | 1998-12-16 | 2001-05-22 | International Business Machines Corporation | Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor |
| JP5104862B2 (ja) * | 2007-06-20 | 2012-12-19 | 富士通株式会社 | 命令実行制御装置及び命令実行制御方法 |
| CN101681261B (zh) * | 2007-06-20 | 2014-07-16 | 富士通株式会社 | 运算处理装置及其控制方法 |
| US20130297910A1 (en) * | 2012-05-03 | 2013-11-07 | Jared C. Smolens | Mitigation of thread hogs on a threaded processor using a general load/store timeout counter |
| US20140181484A1 (en) * | 2012-12-21 | 2014-06-26 | James Callister | Mechanism to provide high performance and fairness in a multi-threading computer system |
| US20160011874A1 (en) * | 2014-07-09 | 2016-01-14 | Doron Orenstein | Silent memory instructions and miss-rate tracking to optimize switching policy on threads in a processing device |
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2015
- 2015-05-22 JP JP2015104724A patent/JP6477248B2/ja active Active
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2016
- 2016-03-14 US US15/068,692 patent/US9965283B2/en active Active