JP2016218503A - Parallelizing compile method, parallelizing compiler, and car onboard device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parallelizing compile method with which it is possible to optimize performance improvement effects when a sequential program has a plurality of processes, in which some of the processes is made a sequential operation and the rest is made a parallel operation.SOLUTION: The parallelizing compile method comprises: a classification procedure for classifying a process group constituting a sequential program into a sequential process that runs sequentially on a single core constituting a multi-core processor and parallel processes that run in parallel on a plurality of cores constituting the multi-core processor; an assignment procedure for executing an uneven assignment process that assigns the processes classified into parallel processes by the classification procedure unevenly to the plurality of cores; and a generation procedure for generating parallel programs on the basis of the classification result of the classification procedure and the assignment result of the assignment procedure.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a parallel compilation method, a parallel compiler, and an in-vehicle device that generate a parallel program parallelized for a multicore processor from a sequential program described for a single core processor.

  For the advancement and integration of control systems and information systems in automobiles, it is important to increase the capacity of processors to realize them. For example, in order to upgrade the engine control system, which is important for the development of safe, comfortable and fuel-efficient vehicles, it is inevitable that the calculation load will increase due to the advancement of control algorithms and the realization of new control functions. In order to solve such a problem, it is essential to increase the speed of a processor that realizes real-time control.

  However, it is difficult to improve the operating frequency of the processor as in the prior art because power consumption increases in proportion to the cube of the frequency. For this reason, multiple processor cores with low operating frequencies are integrated on a single chip, and processor cores with low frequency and low voltage are operated in parallel to reduce power consumption, thereby simultaneously increasing processing speed and reducing power consumption. The transition to a feasible multi-core processor is taking place at a rapid pace.

  In order to perform processing at a higher speed than a single core processor in a multi-core processor, the processing of the sequential program for the single core processor is divided, and each processing is performed on each processor core in a form that minimizes communication between the processor cores. Must be assigned. Conventionally, it has been necessary to manually perform such parallelization of sequential programs, but such operations are very difficult and require a long period of time, increasing development costs, reliability of parallelized programs, etc. Many challenges have arisen.

  Patent Document 1 below proposes a parallel compilation method that can create a parallel program for an embedded system for an in-vehicle device that can perform high-speed processing with high reliability while suppressing the development period and development cost. ing.

Japanese Patent Laid-Open No. 2015-1807

  In the conventional technique, when a sequential program has a plurality of processes, all the plurality of processes are parallelized and a parallelized program assigned to a plurality of cores is generated. In this case, in order to equalize the processing load of each of the plurality of cores, the processing time is apportioned by the number of cores. For example, the processing time in the case of two cores is approximately half that of the sequential program. However, if the processing included in the sequential program includes something with a short execution time, the time increase in overhead such as the communication processing time between cores by parallelizing the processing is ignored compared to the original processing execution time. It may become impossible. In such a case, a parallelized program is generated in which the processing with a short execution time is performed as it is and the other processing is performed in parallel.

  Furthermore, the processing included in the sequential program may include processing that is desired to be executed by a specific core made redundant in order to cope with functional safety. However, in general, since all the cores of a multi-core processor are not made redundant, it is necessary to execute the above-described processing by a specific redundant core, and such processing should be left in sequential operation. Is required. As described above, when the parallelized program includes processes that are not parallelized but remain in sequential operation, there is a problem in that the performance cannot be improved by equalizing the originally intended processing load.

  The present invention has been made in view of such a problem, and the purpose thereof is when a sequential program has a plurality of processes, a part of the processes is a sequential operation, and the remaining processes are a parallel operation. The present invention relates to a parallelization compiling method, a parallelizing compiler, and an in-vehicle device that can optimize the performance improvement effect.

  In order to solve the above-mentioned problem, a parallel compilation method according to the present invention includes a parallel program parallelized so that it can be processed by a multi-core processor (21) from a sequential program described so that it can be processed by a single-core processor. A parallelized compiling method to be generated, wherein a processing group constituting the sequential program is sequentially operated on a single core constituting the multi-core processor and parallel operation on a plurality of cores constituting the multi-core processor. A classification procedure for classifying the parallel processing to be performed, an allocation procedure for performing non-uniform allocation processing for non-uniformly allocating the processing classified as the parallel processing by the classification procedure to the plurality of cores, and classification of the classification procedure A generation procedure for generating the parallel program based on a result and an allocation result of the allocation procedure; .

  The parallelizing compiler according to the present invention is a parallelizing compiler that generates a parallel program parallelized so that it can be processed by a multicore processor (21) from a sequential program described so that it can be processed by a single core processor. Thus, the classification procedure, the allocation procedure, and the generation procedure of the parallel compilation method can be executed.

  Moreover, the vehicle-mounted device according to the present invention includes a multi-core processor that operates by a parallel program that is parallelized so that it can be processed by a multi-core processor (21) from a sequential program described so as to be processed by a single-core processor. (20) It is configured to be able to execute a classification procedure, an allocation procedure, and a generation procedure of the parallel compilation method.

  According to these aspects of the present invention, the non-uniform allocation process that non-uniformly allocates the processes classified as the parallel process by the classification procedure to the plurality of cores is executed, so that the performance improvement when the sequential process is included is optimized. be able to.

  According to the present invention, when a sequential program has a plurality of processes, a parallel process capable of optimizing the performance improvement effect when a part of the processes is a sequential operation and the remaining processes are a parallel operation. A compiling method, a parallelizing compiler, and an in-vehicle device can be provided.

FIG. 1 is a diagram for explaining a parallel compiling method according to an embodiment of the present invention. FIG. 2 is a diagram for explaining a parallel compilation method according to the embodiment of the present invention. FIG. 3 is a block diagram showing the in-vehicle device according to the embodiment of the present invention. FIG. 4 is a diagram for explaining a parallel compilation method according to the embodiment of the present invention. FIG. 5 is a diagram for explaining a parallel compilation method according to the embodiment of the present invention. FIG. 6 is a diagram for explaining the parallel compilation method according to the embodiment of the present invention. FIG. 7 is a view for explaining a parallel compiling method according to the embodiment of the present invention. FIG. 8 is a diagram for explaining a parallel compiling method according to the embodiment of the present invention. FIG. 9 is a diagram for explaining a parallel compiling method according to the embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In order to facilitate the understanding of the description, the same constituent elements in the drawings will be denoted by the same reference numerals as much as possible, and redundant description will be omitted.

  The parallel compilation method of this embodiment will be described with reference to the flowchart shown in FIG.

  In step S01, a sequential program to be automatically parallelized is input. In step S02 following step S01, the execution time and execution cycle of each process constituting the sequential program are input.

  Step S03 following step S02 is processing corresponding to the classification procedure in the present invention. In step S03, each process constituting the sequential program is classified as a sequential process or a parallel process. More specifically, a sequential program that operates on a single core composed of a plurality of processing groups is input, and each processing is classified as either sequential processing or parallel processing. For example, the execution time of each process is set as a judgment value, and if it is equal to or greater than a certain value, it is set as a parallel process, and if it is less than a certain value, it is classified as a sequential process.

  Step S04 following step S03 is processing corresponding to the allocation procedure in the present invention. In step S04, a core that executes sequential processing is determined. When selecting a core for executing sequential processing, it may be based on designation from the user side or may be automatically selected from structural analysis of the program.

  In step S05 following step S04, a non-uniformization guideline is determined. As will be described in detail later, the program generation guideline is set so that parallel operation is performed with uneven processing load by using the execution time, execution cycle, and execution cycle of parallel processing executed in each core of the multi-core processor. decide. As an example, the ratio of the execution cycle of sequential processing to the execution cycle of parallel processing is set as a weight value (if the ratio exceeds 1, 1 is set as a weight value), and the value obtained by multiplying the execution time of sequential processing by the weight value Making a difference is a guideline for non-uniformity.

  Step S06 following step S05 is processing corresponding to the generation procedure in the present invention. In step S06 following step S05, parallel processing based on the non-uniformization guideline is executed for each processing classified as parallel processing in step S03 (details will be described later). In step S07 following step S06, the parallel program after parallelization processing is output.

  Next, the parallel processing based on the non-uniformization guideline in step S06 of the parallel compilation method will be described with reference to the flowchart shown in FIG.

  In step S061, parallel processing is divided. In the parallel processing division, the parallel processing is divided into fine processing blocks. The processing block is a unit for performing parallelization, and is, for example, various arithmetic processing, assignment processing, loop processing, branch processing, program language statements such as function calls, or a combination of these. A processing block can be composed of a single statement in a programming language, but if parallelized in such a fine unit, synchronization between cores and communication overhead become larger. Therefore, the processing block is preferably composed of a plurality of statements, and the execution time of the processing block can be used as the criterion. The execution time of the processing block may be determined by analyzing the architecture of a multi-core processor in which parallel processing is executed, or may be determined by feedback from an actual operation result.

  In step S062, dependency analysis is executed. For all the processing blocks obtained in step S061, which is a division step of parallel processing, the data dependency between the processing blocks and the control dependency are analyzed. The data dependence between processing blocks means, for example, a case where another processing block refers to data updated in a certain processing block. The term “dependence of control between processing blocks” refers to a case where, for example, whether or not another processing block is executed is determined based on a result of a condition determination performed in a certain processing block.

  In step S063, parallelism is extracted. Based on the data dependency between the processing blocks analyzed in step S062, which is the dependency relationship analysis step, and the control dependency, the parallelism in units of processing blocks is extracted. In this case, since processing blocks having neither data dependency nor control dependency can be executed in parallel, it is determined that there is parallelism.

  In step S064, scheduling based on the non-uniformization guideline is executed. In scheduling based on the non-uniformization guideline, processing blocks are executed based on parallelism extracted in step S063, which is a parallelism extraction step, and constraint information such as the number of cores included in a multicore processor on which parallel processing is executed. Determine cores and their execution order. At that time, in accordance with the non-uniformization guideline, the core on which the processing block is executed is determined so that the processing load of each core becomes non-uniform. The non-uniform processing load means that the total execution time of the processing blocks executed in each core is non-uniform depending on the core. To determine this non-uniformity, the execution time of each processing block can be used. Finally, a parallelized program is generated according to the execution core and effective order of the determined processing block. In addition, as long as “parallelization based on the non-uniformization guideline” can be performed, the parallelization method is not limited to that described above.

  Next, the configuration of the in-vehicle device 20 that operates according to the parallelized program generated by the automatic parallelizing compiling method of the present embodiment will be described with reference to FIG. Of course, the automatic parallel compilation method is not limited to the in-vehicle device 20, and can generate parallel programs for operating various electronic devices having the same configuration. An automatic parallelizing compiler based on the automatic parallelizing compiling method of this embodiment can also be provided.

  The in-vehicle device 20 includes a multi-core processor 21, a communication unit 22, a sensor unit 23, an input / output port 24, and the like.

  The multi-core processor 21 includes a ROM 21a, a RAM 21b, a plurality of cores 21c, 21d, 21e,.

  The ROM 21a stores a parallelized program 21a-1 (binary data) generated by the automatic parallel compilation method. The multi-core processor 21 operates according to the parallelized program 21a-1 and performs overall control of the in-vehicle device 20.

  The RAM 21b is a part accessed by the cores 21c, 21d, 21e, etc. The communication unit 22 is a part that communicates with other ECUs connected via an in-vehicle LAN or the like.

  The sensor unit 23 is a part composed of various sensors for detecting the state of a control target or the like. The input / output port 24 is a part that transmits and receives various signals for controlling the control target.

  Next, a specific example of processing for generating a parallelized program by the automatic parallelizing compilation method of this embodiment will be described. In the following description, “processing” is described, which means a description of a series of processes including various operations, assignments, branch processes, function calls, and the like. More specifically, it is a task managed by an OS operating on the multi-core processor 21 or an interrupt handler.

  FIG. 4 is a diagram showing a concept of converting a single-core program into a multi-core program by the parallel compilation method according to the present embodiment. In the example shown in FIG. 4, “time synchronization processing A” is parallelized so as to be processed by the cores 21c, 21d, and 21e, and “time synchronization processing B” is parallelized so as to be processed by the cores 21c, 21d. Further, the “angle synchronization processing A” is processed in the core 21c while being sequentially processed, and the “angle synchronization processing B” is processed in parallel so as to be processed by the cores 21d and 21e. In the present embodiment, this non-uniform processing of parallelization is performed. Therefore, in FIG. 5 and subsequent figures, the processing cores are limited to the core 21c and the core 21d, and the simplified notation such as “processing A” and “processing B” is used. explain.

  FIG. 5A shows a sequential program processed by the core 21c, and is configured to execute the process A and the process B in one system cycle. In the parallelization shown in FIG. 5B, the processing A and the processing B are evenly parallelized. In the parallelization shown in FIG. 5B for the sequential program, the performance improvement effect is the “performance improvement effect (B)” shown in the figure.

  Considering only the performance improvement effect, it can be said that the parallelization shown in FIG. 5B is suitable, but it is also assumed that the process B is a process not suitable for parallelization. For example, when the process B is a process with a short execution time or a process that is desired to be executed by a specific redundant core in order to cope with functional safety, these processes should be left in sequential operation. Is required.

  Therefore, a parallelization technique as shown in FIG. In the parallelization technique shown in FIG. 5C, the parallelized program is configured so that the processing A is uniformly parallelized and the processing B is sequentially processed in the core 21c. The performance improvement effect in this case is the “performance improvement effect (C)” shown in the figure.

  Although not as high as the “performance improvement effect (B)”, a parallelization method that is more effective than the “performance improvement effect (C)” is the parallelization method shown in FIG. In the parallelization technique shown in FIG. 5D, the parallelized program is configured so that the processing A is unevenly parallelized and the processing B is sequentially processed in the core 21c. More specifically, parallelization is performed so that the execution time required for a part of the process A assigned to the core 21d is longer than the execution time required for the part of the process A assigned to the core 21c on the side that sequentially processes the process B. ing. The performance improvement effect in this case is the “performance improvement effect (D)” shown in the figure, and the performance improvement effect is higher than the “performance improvement effect (C)”.

  As shown in FIG. 6, the non-uniform allocation process can be executed based on the length of execution time of process B, which is a sequential process. More specifically, the execution time of process A assigned to the core 21c, which is a single core that executes sequential processing, and the execution time of process A assigned to the core 21d, which is a plurality of cores other than a single core, are as follows: The execution time of the process A assigned to the core 21d is increased by the execution time of the process B (see (A) in FIG. 6). By paralleling in this way, the execution times of the core 21c and the core 21d become substantially the same as shown in FIG. 6B.

  The length of execution time of the process B which is a sequential process can be determined statically by analyzing in advance the architecture of the multi-core processor 21 including the core 21c in which the process B operates. More specifically, the length of execution time can be determined when processing B is described in assembly language using information on the number of execution cycles in assembly language included in the core 21c. Furthermore, it is possible to determine the execution time of the process B with higher accuracy by using information on the time taken to access the ROM 21a and the RAM 21b from the core 21c. By doing so, the length of the execution time of the process B can be more accurately determined by reflecting the structure of the multi-core processor 21 including the core 21c. This method is effective when it is difficult or difficult to prepare an environment for actually operating the process B, such as when the in-vehicle device 20 is under development.

  The length of execution time of the process B, which is a sequential process, can be determined by feedback from the actual operation result of the process B. In this way, it is possible to reflect the execution speed including the fluctuation factors in the actual operating environment. Specifically, the fluctuation factor in the operating environment depends on the determination result of the condition determination part included in the process B, the fluctuation of the execution time due to the change of the contents to be executed, or the core 21c and the core 21d are simultaneously read into the ROM 21a or For example, there is a delay in execution time accompanying access arbitration that occurs when the RAM 21b is accessed. When it is desired to improve the performance improvement effect on the average regardless of the operating conditions, the operation results of the process B under a plurality of operating conditions may be averaged to determine the length of execution time of the process B. Further, when it is desired to maximize the performance improvement effect under a specific operation condition, for example, when obtaining the maximum performance improvement effect when the processing load of the entire multi-core processor 21 is highest, the processing B under the specific operation condition It is preferable to determine the length of execution time of the process B by feeding back the operation result. This method is effective when it is desired to enhance the performance improvement effect even if it takes time and effort, such as when the processing capacity of the multi-core processor 21 is not sufficient for the processing load of the parallelized program 21a-1.

  The parallelization method described with reference to FIG. 6 is more suitable for the execution cycle as shown in FIG. In the execution cycle shown in FIG. 7, the execution cycle of the process A and the execution cycle of the process B are synchronized, and the process A and the process B are always executed in the same execution cycle. Therefore, a parallel method for minimizing the execution time for the entire process A and process B is suitable.

  On the other hand, as shown in FIG. 8, the difference between the core 21c in which the sequential process B is executed and the core 21d is multiplied by the weighting value smaller than 1 by the length of the execution time of the process B. It is also possible to perform non-uniform allocation processing. In the example shown in FIG. 8, the weighting value is set to 0.5, and the execution time of process A assigned to the core 21c is assigned to the core 21d by an execution time that is 0.5 times the execution time of process B. The execution time of process A is increased (see FIG. 8A). By paralleling in this way, as shown in FIG. 8B, the execution time of the core 21c is longer than the execution time of the core 21d.

  The parallelization method described with reference to FIG. 8 is more suitable for the execution cycle as shown in FIG. The execution cycle shown in FIG. 9 is twice the execution cycle of the process B with respect to the execution cycle of the process A. Since the weighting value is set to 0.5, the weighting value is determined using the ratio between the execution cycle of process A, which is parallel processing, and the execution cycle of process B, which is sequential processing. When processing A is used as a reference, processing B is executed once every two times. Therefore, in the parallelization method described with reference to FIG. The overall efficiency will be reduced. Therefore, in order to balance the cycle in which the process B is executed and the cycle in which the process B is not executed, a parallelization method as shown in FIG. 8 is used.

  It is possible to accept designation of the execution cycle of process A, which is parallel processing, and the execution cycle of process B, which is sequential processing, and to statically determine the execution cycle based on this designation. The user can realize parallel processing according to each execution cycle by inputting the execution cycle of process A, which is parallel processing, and the execution cycle of process B, which is sequential processing.

  The execution cycle of process A, which is a parallel process, and the execution cycle of process B, which is a sequential process, can be determined by feedback from the actual operation results of process A and process B. By feeding back the execution cycle of the process A, which is a parallel process, and the execution cycle of the process B, which is a sequential process, it is possible to realize a parallel process according to the actual execution cycle.

Whether or not the process B is a sequential process may be specified by user designation. As an example when the user does not intentionally perform parallel processing,
・ When there is no dependency on the data structure of the program and parallelization is possible, but when the execution order is specified sequentially in the control specification, you want to maintain the correspondence between the program and the control specification and make it easier to understand.
When it is necessary to execute on a redundant core (for example, a lockstep core) for functional safety.
-When control is based on a special CPU architecture. For example, software that runs on the accelerator side of a heterogeneous architecture, such as vector processing.
Is mentioned.

  In the parallelization method of the present embodiment, a system in which a core to be executed statically is determined instead of a core that is dynamically executed by the OS is considered as a particularly suitable application system. In particular, it is suitable for use in a control system in which real-time characteristics are more important, particularly in a vehicle-mounted control program related to running, turning, and stopping.

  Although a description has been given of generating a parallel program by inputting a sequential program, a parallel program that operates on a multi-core may be used to be further subdivided.

20: In-vehicle device 21: Multi-core processor

Claims (27)

A parallel compilation method for generating a parallel program parallelized so as to be processed by a multi-core processor (21) from a sequential program described so as to be processed by a single core processor,
Classification procedure for classifying the processing group constituting the sequential program into sequential processing that sequentially operates on a single core that constitutes the multi-core processor and parallel processing that operates in parallel on a plurality of cores that constitute the multi-core processor; ,
An allocation procedure for performing a non-uniform allocation process that non-uniformly allocates the processing classified into the parallel processing by the classification procedure to the plurality of cores;
A parallel compilation method comprising: a generation procedure for generating the parallel program based on a classification result of the classification procedure and an allocation result of the allocation procedure.   2. The parallel compilation method according to claim 1, wherein in the allocation procedure, the non-uniform allocation processing is executed based on a length of execution time of the sequential processing.   3. The parallel compiling method according to claim 2, wherein, in the allocation procedure, the execution time length of the sequential processing is statically determined by analyzing an architecture of the multi-core processor.   3. The parallelized compiling method according to claim 2, wherein in the allocation procedure, the length of execution time of the sequential processing is determined by feedback from an actual operation result of the sequential processing.   In the allocation procedure, the non-uniform allocation process is executed by making a difference by the length of the execution time of the sequential process between the single core and the multiple cores other than the single core. The parallel compilation method according to any one of claims 2 to 4, wherein:   In the allocation procedure, the single core and the plurality of cores other than the single core are given a difference by multiplying the length of the execution time of the sequential processing by a weight value smaller than 1. The parallel compilation method according to claim 2, wherein non-uniform allocation processing is executed.   The parallelization compiling method according to claim 6, wherein in the allocation procedure, the weighting value is determined using a ratio between an execution cycle of the parallel processing and an execution cycle of the sequential processing.   8. The parallel processing according to claim 7, wherein in the allocation procedure, designation of an execution cycle of the parallel processing and an execution cycle of the sequential processing is received, and the execution cycle is statically determined based on the designation. Compilation method.   8. The allocation procedure according to claim 7, wherein the execution cycle of the parallel processing and the execution cycle of the sequential processing are determined by feedback from actual operation results of the parallel processing and the sequential processing. Parallel compilation method. A parallelizing compiler that generates a parallel program parallelized so as to be processed by a multicore processor (21) from a sequential program described so as to be processed by a single core processor,
Classification procedure for classifying the processing group constituting the sequential program into sequential processing that sequentially operates on a single core that constitutes the multi-core processor and parallel processing that operates in parallel on a plurality of cores that constitute the multi-core processor; ,
An allocation procedure for performing a non-uniform allocation process that non-uniformly allocates the processing classified into the parallel processing by the classification procedure to the plurality of cores;
A parallelizing compiler configured to be able to execute a generation procedure for generating the parallel program based on a classification result of the classification procedure and an allocation result of the allocation procedure.   The parallelizing compiler according to claim 10, wherein in the allocation procedure, the non-uniform allocation processing is executed based on a length of execution time of the sequential processing.   12. The parallelizing compiler according to claim 11, wherein in the allocation procedure, the length of execution time of the sequential processing is statically determined by analyzing an architecture of the multi-core processor.   12. The parallelizing compiler according to claim 11, wherein in the allocation procedure, the length of execution time of the sequential processing is determined by feedback from an actual operation result of the sequential processing.   In the allocation procedure, the non-uniform allocation process is executed by making a difference by the length of the execution time of the sequential process between the single core and the multiple cores other than the single core. The parallelizing compiler according to claim 11, wherein:   In the allocation procedure, the single core and the plurality of cores other than the single core are given a difference by multiplying the length of the execution time of the sequential processing by a weight value smaller than 1. 14. The parallelizing compiler according to claim 11, wherein non-uniform allocation processing is executed.   The parallelizing compiler according to claim 15, wherein in the allocation procedure, the weighting value is determined using a ratio between an execution cycle of the parallel processing and an execution cycle of the sequential processing.   The parallel processing according to claim 16, wherein in the allocation procedure, designation of an execution cycle of the parallel processing and an execution cycle of the sequential processing is received, and the execution cycle is statically determined based on the designation. Compiler.   17. The allocation procedure according to claim 16, wherein the execution cycle of the parallel processing and the execution cycle of the sequential processing are determined by feedback from actual operation results of the parallel processing and the sequential processing. Parallelizing compiler. An in-vehicle device (20) comprising a multi-core processor that operates by a parallel program that is parallelized so that it can be processed by a multi-core processor (21) from a sequential program that is described so that it can be processed by a single-core processor,
Classification procedure for classifying the processing group constituting the sequential program into sequential processing that sequentially operates on a single core that constitutes the multi-core processor and parallel processing that operates in parallel on a plurality of cores that constitute the multi-core processor; ,
An allocation procedure for performing a non-uniform allocation process that non-uniformly allocates the processing classified into the parallel processing by the classification procedure to the plurality of cores;
An in-vehicle device configured to execute a generation procedure for generating the parallel program based on a classification result of the classification procedure and an allocation result of the allocation procedure.   The in-vehicle device according to claim 19, wherein in the allocation procedure, the non-uniform allocation processing is executed based on a length of execution time of the sequential processing.   21. The in-vehicle apparatus according to claim 20, wherein in the allocation procedure, the length of execution time of the sequential processing is statically determined by analyzing an architecture of the multi-core processor.   21. The in-vehicle apparatus according to claim 20, wherein, in the allocation procedure, the length of execution time of the sequential processing is determined by feedback from an actual operation result of the sequential processing.   In the allocation procedure, the non-uniform allocation process is executed by making a difference by the length of the execution time of the sequential process between the single core and the multiple cores other than the single core. The in-vehicle device according to any one of claims 20 to 22.   In the allocation procedure, the single core and the plurality of cores other than the single core are given a difference by multiplying the length of the execution time of the sequential processing by a weight value smaller than 1. The in-vehicle device according to any one of claims 20 to 22, wherein non-uniform allocation processing is executed.   25. The in-vehicle apparatus according to claim 24, wherein, in the allocation procedure, the weighting value is determined using a ratio between an execution cycle of the parallel processing and an execution cycle of the sequential processing.   The in-vehicle system according to claim 25, wherein in the allocation procedure, designation of an execution cycle of the parallel processing and an execution cycle of the sequential processing is received, and the execution cycle is statically determined based on the designation. apparatus.   26. The allocation procedure according to claim 25, wherein the execution cycle of the parallel processing and the execution cycle of the sequential processing are determined by feedback from actual operation results of the parallel processing and the sequential processing. In-vehicle device.

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