JP2009151645A - Parallel processor and program parallelizing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a parallel processor for improving execution efficiency of a program and reducing a maximum execution time. <P>SOLUTION: A command execution part 9(13) notifies other process elements of a synchronous event corresponding to its own task when the execution result of the own task is synchronous with the tasks of the other process elements, and notifies the other process elements of the truth value of a predicate register 7(12) when carrying out a task of notifying the tasks executed by the other process elements, of the execution condition determined result of the task. The command execution part further carries out the own task based on the truth value of a predicate receiving register 8(11) when carrying out the task executed based on the execution condition determined result of the tasks executed by the other process elements. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a parallel processing device that executes a parallelized program and a program parallelizing device that automatically divides a program into a plurality of tasks that can be executed in parallel.

  In a program parallelization device, one program is generally divided into a plurality of tasks and executed in parallel on a plurality of process elements. Therefore, the flow dependence, reverse dependence, and output dependence regarding the reading and writing of variables that are the operation target of the program. Analyzing data dependence from each dependency, extracting precedence constraints between tasks, and incorporating synchronization instructions into the divided program, so that precedence constraints between tasks assigned to process elements are protected, and operation results are consistent Guarantee sex.

  In such a program parallelization apparatus, the conventional apparatus treats one virtual machine code as one task, divides the program into tasks that can be executed in parallel, schedules tasks for a plurality of processors, In some cases, by combining tasks and re-scheduling tasks, the overhead due to synchronization processing is reduced (see, for example, Patent Document 1).

  In addition, there are the following devices as conventional program parallelization devices. In other words, in a static task scheduling system that performs task scheduling for each task before the execution of each task based on a task graph indicating the dependency relationship of each task including the task for which the execution processor is specified, the task is terminated from each task. High priority is given to tasks with a long path length to the next task, a forward direction list registered in descending order of priority, and high priority to tasks with a long path length from the last task to each task There is one that has a reverse direction list in which the degree is given and is registered in the order of low priority (see, for example, Patent Document 2). In such a program parallelization apparatus, when scheduling, either the forward list or the backward list is selected, and the execution time of each task is determined based on the selected list. Such a program parallelization apparatus appropriately performs task scheduling in the forward direction and the reverse direction depending on the state of the highest priority task of each processor, so that it is possible to reduce the waiting state of the task and improve the use efficiency of the processor. it can.

Japanese Patent No. 3039953 JP 2003-29988 A

  However, when performing task scheduling in which a program is divided into a plurality of tasks and allocated to a plurality of process elements, it cannot be said that the conventional program parallelization apparatus performs allocation with high execution efficiency.

  That is, the overall execution time of the program after parallelization is determined by the processing time of the process element having the longest processing time. In the case of a program that is installed in a device and controls the device, when the program finishes execution, the data needs to be updated by external input / output, so the processing of the program allocated after the division ends quickly Only the processed element cannot be advanced to the next processing cycle ahead of other process elements. A process element that has finished processing earlier needs to wait until processing in the process element that requires the most processing time is finished. As a result, the process element that has finished processing will have idle time until it starts processing in the next cycle. As a result of task scheduling, it suffices if processing is assigned to each process element so that all process elements finish processing at the same time, but only one process element takes longer than other process elements. When such a scheduling result is obtained, the other process elements wait until the one process element finishes processing, and there is a problem that the execution efficiency of a plurality of process elements is lowered. .

  The above problem is a problem concerning the last part of the process assigned to the process element, but the same problem may occur at a point in the middle of the process assigned to the process element. If a task assigned to a process element has a data-dependent relationship with a variable included in a task assigned to another process element (referred to as a preceding task), the completion of the preceding task assigned to the other process element is I need to wait. Therefore, there is a problem that idle time occurs even while waiting for the completion of the preceding task. It is possible to eliminate the idle time by assigning a task that does not depend on data and is not restricted in terms of control flow to the idle time among the subsequent tasks. However, this is a case where there is a task that satisfies such a condition in the succeeding task, and when there is no task that satisfies the condition, free time is generated in processing of the process element as described above. However, the problem that the execution efficiency of the process element decreases similarly occurs.

  For example, like the device described in Patent Document 1, one virtual machine code is handled as one task, a program is divided into tasks that can be executed in parallel, and a task schedule is performed on a plurality of processors, and then combined. In the method of scheduling again after combining tasks that can be performed, the execution efficiency of the process element is improved because scheduling is performed so that the idle time is reduced, but the number of times of scheduling is increased and the amount of calculation is reduced. There was a problem of increasing.

  In addition, in the control program for an embedded device, the program can be configured by a continuous combination of execution conditions and processing under those conditions. If one machine code of such a program is handled as one task based on the handling of the task in the apparatus described in Patent Document 1, the task combination is considered in consideration of the execution condition for each machine code. It is necessary to judge whether it is possible. This is because tasks with different execution conditions cannot be combined as one task. As a result, in the case of such a control program, there is a problem that the amount of calculation increases because execution conditions are taken into consideration when tasks are combined.

  Further, in the apparatus described in Patent Document 2, in a static task scheduling system that performs scheduling before execution based on a task graph indicating the dependency of each task, the order in which tasks are registered in descending order of priority. Using a direction list and a reverse list in which tasks are registered in order of priority, task scheduling is performed by selecting the forward list and the reverse list according to the status of the highest priority task of each processor. As a result, it is possible to reduce the idle time in which tasks are waiting. However, there is a problem that idle time still cannot be solved by this method between tasks having data dependency.

  The present invention has been made to solve the above-described problems. A parallel processing apparatus and a program parallel capable of improving the execution efficiency of a program by reducing the idle time of a process element and reducing the maximum execution time. An object is to obtain a device.

  In the parallel processing device according to the present invention, each of the plurality of process elements includes a predicate register for storing a true / false value for determining whether or not to execute the next instruction, and the next process element received from another process element. A predicate reception register that stores a synchronization event with a predicate with a true / false value to determine whether or not to execute the instruction, and a task execution condition determination result is notified to a task executed by another process element When a task to be executed is executed, a synchronization event with a predicate with a true / false value of the predicate register is notified to other process elements and executed based on the execution condition determination result of the task executed in the other process element. When the task is executed, the prefetched synchronization event receive register is true. Those having an instruction execution unit for executing the own tasks on the basis of the value.

  The parallel processing device according to the present invention includes a predicate register for storing a true / false value for determining whether or not each of a plurality of process elements executes the next instruction, and a next instruction received from another process element. Since the task is executed synchronously based on the value of the predicate reception register that stores the truth value for determining whether to execute or not, the execution efficiency of the program is improved, and the maximum execution time Can be shortened.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a parallel processing apparatus according to Embodiment 1 of the present invention.
In the figure, the parallel processing device comprises a processor 1, an external memory 5, and a bus 6 for connecting them together. The processor 1 includes two or more process elements (in the first embodiment, two process elements (PE) # 0 (2) and # 1 (3)) and a built-in memory 4. These process elements # 0 (2) and # 1 (3) include predicate registers 7 and 12, predicate reception registers 8 and 11, instruction execution units 9 and 13, and synchronization mechanisms 10 and 14, respectively.

The predicate registers 7 and 12 are registers that store true / false values for determining whether or not to execute the next instruction in each of the process elements # 0 (2) and # 1 (3). The values of these predicate registers 7 and 12 are changed by calculation on the process elements # 0 (2) and # 1 (3). For example, the value of this register becomes false when the result of the comparison instruction between the variables does not match or when the result of the magnitude comparison instruction is not established. On the other hand, when the result of the comparison instruction between the variables matches or the result of the magnitude comparison instruction is established, the value of this register becomes true.
The predicate reception registers 8 and 11 are registers for receiving the result (true / false value) of an instruction executed by another process element. That is, the predicate reception register 8 receives the instruction execution result by the process element # 1 (3), and the predicate reception register 11 receives the instruction execution result by the process element # 0 (2).

  When the execution result of the task assigned to itself is synchronized with the task assigned to another process element, the instruction execution units 9 and 13 send a synchronization event corresponding to the own task to the other process element. When executing a task that is executed based on a synchronization event of a task that is executed in another process element, the task is executed based on the reception of the synchronization event, and the execution condition of the task When executing a task for notifying the determination result to a task executed in another process element, the truth value of the predicate registers 7 and 12 is notified to the other process element and executed in the other process element. When executing a task that is executed based on the execution condition judgment result of the It is configured to perform its tasks on the basis of the truth value of the reception register 8, 11.

  That is, these instruction execution units 9 and 13 support conditional execution instructions. Execution of the conditional execution instruction depends on the values of the predicate registers 7 and 12. The predicate registers 7 and 12 store either true or false values. If the values of the predicate registers 7 and 12 are true, the read conditional execution instruction is executed and the operation result is obtained. Write to the built-in memory 4. On the other hand, when the values of the predicate registers 7 and 12 are false, the next instruction is read without executing the read conditional execution instruction.

The synchronization mechanisms 10 and 14 are mechanisms for synchronizing the plurality of process elements # 0 (2) and # 1 (3) on the processor 1, and the synchronization events notified from their own process elements. Synchronization between these process elements is performed by an instruction to wait and an instruction of a synchronization event notified from another process element.
That is, each process element # 0 (2), # 1 (3) has a command for notifying other process elements of a synchronization event. This synchronization event is given a unique number. The unique number of the synchronization event is statically determined when the program parallelization apparatus 20 described later divides the program 30, and the corresponding instruction is incorporated into the machine code 31. The program 30 and the machine code 31 will also be described later.

  For example, when the process element # 1 (3) waits for a synchronization event from the process element # 0 (2), the synchronization mechanism 14 of the process element # 1 (3) waits with an instruction “WAITEV 0”, for example. The process element # 0 (2) notifies the synchronization mechanism 14 of a synchronization event by, for example, an instruction “SENDEV 0”. When the waiting process element # 1 (3) receives the corresponding synchronization event, the synchronization mechanism 14 of the waiting process element # 1 (3) recognizes this, and in this case, the process element # 1 The execution process of 1 (3) is resumed. Processing of the process element waits until a corresponding synchronization event is issued by an external process element on the system when “WAITEV n” (n is an integer) is called.

The built-in memory 4 in the processor 1 is a memory that holds a program and data stored in the external memory 5 and in which execution results are written by the instruction execution units 9 and 13. That is, each process element # 0 (2), # 1 (3) on the processor 1 reads the machine code 31 from the corresponding program area on the external memory 5, reads the value from the built-in memory 4, performs an operation, and performs the built-in The result is written to a variable on the memory 4. The built-in memory 4 has an arbitration function, and access to one variable from the process elements # 0 (2) and # 1 (3) is performed exclusively.
In this example, the machine code 31 is arranged on the external memory 5, but it may be arranged on the internal memory 4 existing inside the processor 1. Further, the variables arranged on the built-in memory 4 can be arranged on the external memory 5. The external memory 5 also has an arbitration function and is accessed exclusively. The bus 6 is a bus for connecting the processor 1 and the external memory 5 to each other.

  Further, FIG. 1 shows a case where the processor 1 includes two process elements, but three or more process elements may exist. In this case, the synchronization mechanism and predicate register possessed by each process element are connected to all process elements other than its own process element.

Next, the program parallelization apparatus will be described.
FIG. 2 is a configuration diagram of the program parallelization apparatus.
The illustrated program parallelization apparatus 20 includes an analysis unit 21, a task division unit 22, a scheduling unit 23, and a code generation unit 24.

  The analysis unit 21 performs lexical analysis and syntax analysis on the input program 30 and converts it into an intermediate code. As the intermediate code, for example, a quadruplet is cited. The analysis unit 21 is configured to analyze the dependency between variables based on the calculation contents expressed in the program 30 and the order thereof. The task dividing unit 22 divides the program expressed by the intermediate code into a plurality of tasks. As a unit of a task, a basic block or a group of execution conditions and processing under those conditions may be mentioned. A basic block is a unit of a program that is continuously executed in the order in which the program is described without a branch in the middle. For tasks based on these units, the task division unit 22 obtains execution order constraints between tasks based on the analysis result of the dependency between variables.

  The scheduling unit 23 is a functional unit that allocates the program divided into tasks by the task dividing unit 22 to a plurality of process elements. As a scheduling method, a critical path method can be mentioned, but any scheduling algorithm can be adopted. However, in the first embodiment, scheduling based on the critical path method using the processing time of each task as an evaluation function will be described. Scheduling is performed based on execution order constraints between previous tasks. The code generation unit 24 is a functional unit that generates a machine code 31 of a process element to be executed for each task assigned to a plurality of process elements by the scheduling unit 23. In this code generation, if the dependency of variables between tasks extends between process elements, it is necessary to keep the execution order between different process elements. Therefore, the code generation unit 24 adds a synchronous instruction to that place. It is configured to

Note that the program parallelization apparatus 20 is realized by a computer, and includes software corresponding to the analysis unit 21 to the code generation unit 24, and hardware such as a CPU and a memory for executing the software. Alternatively, the analysis unit 21 to the code generation unit 24 are configured from dedicated hardware.
Further, the program parallel processing device 20 and the parallel execution device shown in FIG. 1 are connected by, for example, a network cable or a USB cable, and store the program parallelized by the program parallelization device 20 and the program of the parallel execution device. Is transferred to the external memory 5.

Next, operations of the program parallelization apparatus and the parallel processing apparatus according to the first embodiment will be described.
For example, the dependency relationship between tasks when a program is treated as an execution condition and a group of processes under the condition will be described with reference to a program represented in FIG. FIG. 3 shows a part of the program, and other tasks may exist before and after the program.
Each node in FIG. 3 represents a task, and the numbers in the circles are task numbers. The numerical value on the right side of the circle expresses the processing time of the task as a numerical value. Furthermore, the arrows between the nodes represent the precedence constraints between tasks. For example, task 2 cannot start processing until task 1 ends, and task 4 cannot start processing until task 2 and task 3 end.

  In the following, each task is expressed as a pair of an execution condition and a processing content under the condition, and it is assumed that a determination of the execution condition always exists at the head of each task. As a language for describing the program, any language can be used as long as it can describe execution conditions and processing under the conditions, and the target language is not limited.

Hereinafter, the flow of processing when the program having the task configuration shown in FIG. 3 is input as the program 30 to the program parallelizing apparatus 20 will be described with reference to FIG.
When receiving the program 30 as input, the program parallelizing apparatus 20 performs lexical analysis / syntactic analysis in the analysis unit 21 to generate an intermediate code (step ST1). At this time, the task division unit 22 obtains the dependency relationship between tasks shown in FIG. 3 (step ST2). Next, the scheduling unit 23 assigns tasks to process elements from the task dependency analysis results shown in FIG. 3 and the processing time of each task using, for example, a critical path method (step ST3). FIG. 5 shows an example in which the task configuration of FIG. 3 is assigned to two process elements.

  In FIG. 5, task 1, task 2, and task 4 are allocated to process element # 0 (2), and task 3 is allocated to process element # 1 (3). Since execution of task 3 needs to wait for task 1 to end, an instruction for transferring a synchronous event is added between these tasks. That is, an instruction for waiting for a synchronization event from task 1 is added to the beginning of task 3, and an instruction for notifying a synchronization event to task 3 is added to the end of task 1. Here, the time required for synchronization is set to 1. For this reason, 65, which is obtained by adding the synchronous event delivery time 1 from task 1 to task 3 to the total processing time of task 1, task 2 and task 4, is the processing time by this scheduling. The processing time when all tasks are processed in sequence on one process element is 84, which is the sum of the processing times of all tasks, so the processing time is reduced by parallelization.

The synchronous event is expressed by a synchronous event notification instruction “SENDEV n” and a synchronous event standby instruction “WAITEV n”. In addition, n is an integer and means an event number. That is, the side that waits for an event with the WAITEV instruction waits for processing until a synchronization event of the designated event number is notified. On the other hand, the side that notifies the synchronization event specifies the other party to whom the synchronization event is to be notified by the event number.
In the synchronization event notification, one synchronization event notification command may broadcast one synchronization event to a plurality of synchronization event standby commands.
The synchronization event with predicate is expressed by, for example, a synchronization event notification command “SENDEV_PD n” and a synchronization event wait command with predicate “WAITEV_PD n”.

When the scheduling unit 23 finishes assigning the tasks to the process elements, the task is not assigned for a longer time than the time required for the communication overhead between the process elements, and the free time is obtained. It is confirmed whether it exists (step ST4). The free time is confirmed by scanning the scheduling result in order from the top and extracting the time when no task is assigned.
In the example of FIG. 5, while process element # 1 (3) is executing task 4, no task is assigned to process element # 0 (2) and there is a free time. Therefore, the process branches to task re-division (step ST5) by the task division unit 22 to re-divide the task.

FIG. 6 is a flowchart showing a process flow of the task re-division (step ST5) in FIG.
First, for process elements having free time, the time from the start of processing of free time and the number of process elements having free time at that time are obtained (step ST11). Next, it is confirmed whether there is a task that can divide the process at that time (step ST12). At this time, if the processing time of the task is short and the overhead of passing the synchronous event due to the parallelization becomes larger than the division and parallelization, it is determined that there is no task that can be divided and the processing is terminated. On the other hand, when there is a task with a long processing time for the overhead of passing the synchronous event as in task 4 in FIG. 5, the process moves to step ST13 and the process of the task that can be divided has a free time. Divide by the number of elements. In the example of FIG. 5, since there are two process elements, the process of task 4 is divided into two. As described above, when dividing a task process into a plurality of processes, it is necessary to check the dependency of the data in the process and avoid dividing the process between the processes. The reason is that, when a process having a dependency is assigned to a plurality of process elements, it is necessary to newly add a synchronization event passing instruction in order to guarantee the dependency. Therefore, when dividing into different process elements, a process having no dependency is assigned. If there is a dependency, processes having a dependency relationship are collectively arranged in one process element, and the remaining processes are arranged in another process element.

  In accordance with the processing flow shown in FIG. 6, task 4 in FIG. 5 is divided into two to generate task 4-1 and task 4-2. Task 4-1 is the first half of task 4 and task 4-2 is the second half of task 4. The task 4 execution condition determination process is included in task 4-1. Therefore, the predicate value, which is the execution condition obtained in task 4-1, is notified to task 4-2.

When the task is subdivided in this way, a synchronization instruction with a predicate is added to the position where the synchronization event of the task that started the divided task is issued (step ST14). Further, a command for waiting for a synchronization event with a predicate is added to the standby position of the synchronization event at the activation destination (step ST15).
The above is the process of the task dividing unit 22 when re-dividing a task.

After the task is subdivided, the scheduling unit 23 performs scheduling for the new task configuration (step ST3 in FIG. 4). Then, it is confirmed whether there is a free time of the process element in the scheduling result (step ST4). In this step ST4, if there is a free time, a task re-division process (step ST5) is performed again.
If there is no free time, the code generator 24 generates the machine code 31 (step ST6). The code generation unit 24 adds a synchronization event notification command and a synchronization event standby command for delivering a synchronization event based on the dependency relationship between tasks. For a task to which a synchronization instruction with a predicate added when the task is subdivided is added, the instruction is incorporated in the machine code 31 when the machine code 31 is generated.

In addition, with regard to the delivery of redundant synchronization events, such as repeated notification processing of synchronization events from a certain process element to a specific process element, the synchronization events are deleted to the minimum necessary when the machine code 31 is generated. Also good.
For the purpose of shortening the free time of the scheduling result shown in FIG. 5, the scheduling result shown in FIG. 7 is obtained as a result of executing the processing shown in FIGS. 4 and 6.
FIG. 7 divides the processing of task 4 in FIG. 5 into two process elements, thereby reducing the idle time and the processing time of the entire program. If the time for the condition determination process of task 4 is 2, this time cannot be divided, so the process is performed on process element # 1 (3). The predicate value obtained by this condition determination process is notified to the task 4-2 assigned to the process element # 0 (2). As described above, as a result of dividing the task, the total processing time is equal to the time 2 of the condition determination and the time of the two synchronous instructions with respect to the time of task 1 and task 2 and the time of task 4-2 (= 19). The total is 47.

Next, the operation of the parallel processing device when the parallelized program (program in the state shown in FIG. 7) generated by the program parallelizing device 20 is stored in the external memory 5 will be described.
Process element # 0 (2) of the parallel processing device executes the programs of task 1, task 2, and task 4-2, which are tasks on the left side of FIG. Further, the process element # 1 (3) sequentially executes the programs of the task 3 and the task 4-1, which are the tasks on the right side of FIG.
First, the process element # 0 (2) reads the task 1 program from the memory (the built-in memory 4 or the external memory 5) and starts processing. At this time, the process element # 1 (3) also reads the task 3 program and starts processing, but the first instruction is issued from the process element # 0 (2) when the task 1 ends at the beginning of the task 3. Since this is an instruction to wait for a synchronized event, the synchronization mechanism 14 of the process element # 1 (3) is set to wait for an event from the process element # 0 (2), and the event enters a standby state. . This synchronization event is assigned a unique number, and the system waits until an event having that number is issued. As for the unique number of the synchronization event, when the code generation unit 24 of the program parallelizing apparatus 20 adds a synchronization event transmission / reception command to the location where the synchronization event needs to be transferred, a unique number is assigned to each location. It has been.

When the process of task 1 is completed, the instruction execution unit 9 of process element # 0 (2) notifies the synchronization mechanism 14 of the synchronization event that task 3 of process element # 1 (3) is waiting for. Next, the instruction execution unit 9 of the process element # 0 (2) reads the task 2 program and starts its execution.
The process element # 1 (3) that has received the synchronization event from the process element # 0 (2) determines whether the synchronization event received by the synchronization mechanism 14 is a synchronization event that is a condition for exiting the standby state. In this case, since this is a synchronous event for exiting the standby state, the standby state is exited, the processing in the instruction execution unit 13 is resumed, and the processing of the program 3 is started. When the process of task 2 is completed, the instruction execution unit 9 of process element # 0 (2) reads the program of task 4-2. The head of the program 4-2 is an instruction for waiting for a synchronization event with a predicate from the process element # 1 (3). For this reason, the instruction execution unit 9 of the process element # 0 (2) registers a synchronization event to wait in the synchronization mechanism 10, and shifts to a standby state.

  When the instruction execution unit 13 of the process element # 1 (3) finishes the process of the task 3, the process proceeds to the process of the task 4-1. When the instruction execution unit 13 finishes executing the execution condition determination process at the head part of the task 4-1, the program parallelization apparatus 20 executes the synchronization instruction with a predicate added to the next position on the program. This synchronization instruction with predicate is an instruction for notifying the target process element of the true / false value of the predicate register 12 at the time when the instruction is executed, together with the synchronization event. In this case, since the synchronization instruction with a predicate is issued when the execution condition determination process of task 4-1 is completed, the value of the predicate register 12 at the end of the execution condition determination process of task 4-1 is processed. The element # 0 (2) is notified together with the synchronization event. Here, the value of the predicate register 12 is notified to the predicate reception register 8. This is a process of instructing execution start of the task 4-2 and notifying execution / non-execution of the conditional execution instruction included in the task 4-2. The process element # 0 (2) that has received the synchronization event and the predicate value from the process element # 1 (3) causes the instruction execution unit 9 to start processing of the task 4-2 based on the received predicate value.

  In this way, after assigning a task to a process element, if there is a free time in the process element and there is a task that can divide the processing after executing the execution condition determination at that time, the task's A process for allocating processing parts to process elements having free time, adding a synchronous event delivery instruction for notifying the execution start timing of the assigned program, and providing a mechanism for notifying the result of execution condition determination As a result, the processing time of the entire program can be shortened.

  As described above, according to the parallel processing device of the first embodiment, in a parallel processing device that includes a plurality of process elements and performs parallel processing of tasks with the plurality of process elements, each process element outputs the following instruction: Predicate register that stores a Boolean value for determining whether to execute, and synchronization with a predicate with a Boolean value for determining whether to execute the next instruction received from another process element When a predicate reception register that stores events and a task that notifies task execution condition determination results to tasks executed by other process elements are executed, a synchronization event with a predicate with a true / false value of the predicate register To other process elements and When executing a task that is executed based on the execution condition determination result of the program, the instruction execution unit that executes the task based on the true / false value of the reception register of the synchronization event with predicate is provided. A parallel processing device capable of improving execution efficiency and reducing the maximum execution time can be realized.

  Further, according to the program parallelizing apparatus of the first embodiment, a program parallelizing apparatus that divides a program into tasks that are executed in parallel on a plurality of process elements in the parallel processing apparatus of the first embodiment. An analysis unit that analyzes the dependency of the data contained in the task, a task division unit that divides the program into tasks corresponding to a plurality of process elements based on the analysis result of the analysis unit, and a plurality of process elements A scheduling unit that performs scheduling for execution in the system, and a code generation unit that generates a task for each scheduled process element as a code of an execution format of each process element by adding a synchronization instruction according to data dependency And scheduled by the scheduling unit As a result, when the scheduling unit determines that there is a free time for task execution in any process element, the task division unit divides the task processing corresponding to a plurality of process elements, and the code generation unit Since an instruction for passing a synchronization event with a predicate for synchronizing the processing of the divided tasks is added, the execution efficiency of the program in the parallel processing device can be improved and the maximum execution time can be shortened.

Embodiment 2. FIG.
Since the configurations of the parallel processing device and the program parallelizing device in the second embodiment are the same as those in the first embodiment, they will be described with reference to the drawings of the first embodiment.

The program parallelizing apparatus 20 according to the second embodiment takes an example of a program in which the dependency relationship between tasks when an execution condition and a group of processing contents under the condition are handled as one task is shown in FIG. The flow of processing and the operation of the parallel processing device will be described.
FIG. 8 shows a part of the program, and other tasks may exist before and after the program.
In FIG. 8, as in the first embodiment, each node represents a task, and a numerical value in a circle represents a task number. The numerical value on the right side of the circle is the task processing time. Furthermore, the arrows between the nodes represent the precedence constraints between tasks. In this example, in order to execute the task 3 with the processing time 4, both the task 1 with the processing time 40 and the task 2 with the processing time 20 must complete the processing.

  When a program having the task configuration shown in FIG. 8 is input to the program parallelization apparatus 20, the program is analyzed and an intermediate code is generated. Then, the program is divided into task units as shown in FIG. 8, and tasks are assigned to process elements. When the scheduling for performing is completed, a scheduling result as shown in FIG. 9 is obtained. Task 1 and task 3 are executed on process element # 0 (2), and task 2 is executed on process element # 1 (3). At this time, the processing time of the entire program is the processing time in the process element # 0 (2), which is 44, which is the sum of the processing time of task 1 and the processing time of task 3.

  When the scheduling is finished, it is confirmed whether there is a free time exceeding the communication overhead between the process elements on any of the process elements (step ST4 in FIG. 4). In this example, in process element # 1 (3), the time after execution of task 2 is idle time. For this reason, the program parallelization apparatus 20 enters into the task re-division process.

  In task re-division (see FIG. 6), the time of free time and the number of PEs having free time at that time are obtained (step ST11). Thereafter, it is confirmed whether there is a task capable of dividing the process at the same time (step ST12). In this example, processing of task 1 is performed on process element # 0 (2) in the time after execution of task 2 is completed in process element # 1 (3). Since this process is performed for 20 hours after the completion of the process of task 2, it is a process of a separable task. Therefore, the divisional task processing is divided by the number of assignable PEs (step ST13). In this example, task 1 is divided into task 1-1 and task 1-2.

Then, a synchronization instruction with a predicate is added to the position where the execution condition determination process included in the task 1-1 which is the synchronization event issuing position of the activation source task is completed (step ST14). Next, a command to wait for a synchronization event with a predicate is added to the head position of the task 1-2 that is the notification destination of the synchronization event (step ST15). In this way, scheduling is performed again in a state where task 1 is divided into two parts.
As a result, the program is allocated to the process element as shown in FIG. Here, the divided task 1-2 is scheduled after the task 2. In this example, since there is no dependency between task 1 and task 2, it does not matter which task is executed first. However, since the task 1-2 requires a predicate value that is the processing result of the execution condition determination performed in the task 1-1, the process element is preferably started after the predicate value is determined. The occurrence of free time can be suppressed. Therefore, in parallel with the time during which execution condition determination processing is performed on process element # 0 (2), a task is assigned so that processing of task 2 is performed on process element # 1 (3).

  In the scheduling result of FIG. 10, by dividing the processing of task 1 of FIG. 9 into two process elements, the free time is reduced and the processing time of the entire program is shortened. If the processing time of task 1 execution condition determination is 4, the processing time of the entire program in the scheduling result of FIG. 9 is 44, whereas the processing portion of task 1 is divided as shown in FIG. By parallelizing the processing, the processing time of the whole program can be shortened to 35.

Next, the operation of the parallel processing device in this embodiment will be described.
Process element # 0 (2) of the parallel processing device executes the program of task 1-1 in FIG. Further, the process element # 1 (3) starts execution from the task 2 program of FIG.
When the process element # 0 (2) completes the execution condition determination process of the task 1-1, the process element # 0 (2) notifies the process element # 1 (3) of a synchronization event with a predicate. Thereafter, the process element # 0 (2) continues the subsequent processing of the task 1-1.
Process element # 1 (3) starts execution from the program of task 2 at the start, but receives a predicated synchronization event from process element # 0 (2) during the execution of task 2. At this time, the reception command corresponding to the synchronous event notification has not been executed yet. This is because the instruction for receiving this synchronization event is present at the head of the task 1-2 that is executed after the processing of the task 2 is completed. In such a case, the process element # 1 (3) that has received the synchronization event with a predicate holds the number of the synchronization event in the synchronization mechanism 14 and holds the value of the received predicate in the predicate reception register 11.

  When the process of task 2 in process element # 1 (3) is completed, the process of task 1-2 is continuously started. At this time, the head of the task 1-2 is an instruction for receiving the synchronization event with predicate transmitted from the process element # 0 (2) first. Therefore, the instruction execution unit 13 of the process element # 1 (3) confirms whether the event has already been received by the synchronization mechanism 14. In this example, since the target predicate synchronization command has already been received, the subsequent processing is continued as it is. When the process element # 1 (3) finishes the process of the task 1-2, the process element # 1 (3) continues the process to the end while continuing to read the program of the task 3.

  As described above, in the second embodiment, after assigning a task to a process element, there is a free time in the process element, and there is a task that can divide the processing after performing conditional execution determination at that time. If this is the case, the processing part of the task is allocated to a process element having a free time, and a synchronous event delivery instruction is sent to notify the execution start timing of the allocated program. By providing a mechanism for notifying together, the processing time of the entire program can be shortened.

Embodiment 3 FIG.
In the third embodiment, a task having a large number of subsequent tasks is divided under the preceding constraint of tasks.
Since the configuration of the program parallelizing apparatus and the parallel processing apparatus in the third embodiment is the same as that in the first embodiment, these drawings will be used for explanation.

  In the program parallelization apparatus 20 according to the third embodiment, the task dividing unit 22 divides the program into tasks corresponding to a plurality of process elements based on the analysis result of the analyzing unit 21 and the subsequent data dependency relationship. When there are more than a predetermined number of target tasks, the target task is divided. As a result of scheduling by the scheduling unit 23, when the processing time is shortened, the target task is divided and the machine code 31 is generated. Other configurations are the same as those of the program parallelization apparatus 20 of the first embodiment. Further, since the configuration of the parallel processing device is the same as that of the first embodiment, description thereof is omitted here.

Hereinafter, the program parallelizing apparatus according to the third embodiment will be described with reference to an example of a program in which the dependency relationship between tasks when the execution conditions and the processing contents under the conditions are treated as one task is shown in FIG. The process flow 20 will be described.
In FIG. 11, as in the first embodiment, each node represents a task, and a numerical value in a circle represents a task number. The numerical value on the right side of the circle is the task processing time. Furthermore, the arrows between the nodes represent the precedence constraints between tasks. In this example, after task 1 having a processing time of 18 is executed, tasks 3 to 6 can be executed. Task 2 can always be executed.

After scheduling, as shown in the first and second embodiments, even if any task in the program is divided and there is no improvement in the scheduling result, there is no free time on the process element. May exist. Due to the overhead due to synchronization, it is determined that the processing time of the entire program is shorter when the idle time is left as it is than when the task is divided and the synchronization instruction is added.
However, when such small free times exist at multiple locations in the scheduling result, there is a possibility that the scheduling conditions can be improved by dividing a task having many subsequent tasks and the processing time of the entire program can be shortened. is there.

  If a task with many subsequent tasks is divided and the end time of processing is advanced, tasks that were not subject to scheduling until the preceding task is completed can be scheduled earlier than before due to task precedence constraints As a result, the number of candidate tasks to be scheduled increases. As a result, in the past, due to the task's precedence constraint, a task that has become free time is assigned a task that can be scheduled again, thereby reducing the free time and shortening the processing time of the entire program. Can do.

  For example, if there are four or more subsequent tasks and the task whose processing time can be shortened by dividing is detected, the processing time of the program is compared before and after dividing the task in order, and it is effective. There is a method of adopting the division only for the task. In this case, the corresponding task is detected in order from the beginning of the program, and the process is terminated when the program proceeds to the end of the program.

  When a program having a task configuration as shown in FIG. 11 is assigned to two process elements, the result is as shown in FIG. The numerical value on the right side of the arrow indicating the task in FIG. 12 represents the processing time of the task. At this time, the execution condition determination time for task 1 is set to 1. Since the time difference between task 1 and task 2 is 3, considering the synchronization processing overhead, there is no effect of dividing task 1. For this reason, task 1 is not divided. The processing time of the program at this time is 26.

On the other hand, in the third embodiment, a task having a large number of subsequent tasks is forcibly divided. In this example, since there are four tasks following task 1, task 1 is divided into two. Then, in order to activate the latter half of the task 1 process, a synchronization event transmission / reception process with a predicate is added.
FIG. 13 shows a scheduling result when task 1 is divided. When the scheduling as shown in FIG. 13 is performed, the processing time of the program is 25, which can be shortened compared to the case where task 1 is handled as one task. The numerical value on the right side of the arrow indicating the task in FIG. 13 represents the processing time of the task.

The flow of the above processing is shown in FIG.
First, the task dividing unit 22 divides a task in order from the top task in the program for tasks having three or more subsequent tasks among all tasks (steps ST21 and ST22), and scheduling is performed by the scheduling unit 23. Is performed (step ST23). As a result, if there is an effect of reducing the processing time in step ST24, the scheduling result is adopted and the task is divided. On the other hand, if there is no effect due to the division in step ST24, the task is returned to the state before the division (step ST25).
Next, the task dividing unit 22 confirms whether or not the task is the last task of the program (step ST26). In step ST21, when there are not three or more subsequent tasks, the process proceeds to step ST26. In step ST26, if the task is the last task, the process ends. On the other hand, if the task is not the last task, the process returns to step ST21 and moves to the next task. At this time, the task moves to a task having three or more subsequent tasks.
In this example, the number of subsequent tasks is three or more, but the number of tasks is not limited to three or more, and may be two or four or more.

Note that the operation of the parallel processing apparatus is the same as in the first and second embodiments, and a description thereof will be omitted here.
In addition, after the implementation of the first or second embodiment, further application of the task division of the third embodiment can further reduce the processing time of the program.

  As described above, the program parallelizing apparatus according to the third embodiment is a program parallelizing apparatus that divides a program into tasks that are executed in parallel on a plurality of process elements in the parallel processing apparatus according to the third embodiment. Then, based on the analysis result of the data dependency included in the program and the analysis result of the analysis unit, the program is divided into tasks corresponding to a plurality of process elements, and the subsequent task in the data dependency relationship A task dividing unit that divides the target task when there are more than a predetermined number of target tasks, a scheduling unit that schedules the tasks divided by the task dividing unit to be executed by a plurality of process elements, Synchronize instructions for each process element according to data dependency And a code generator that generates each process element as an executable code, and if the scheduling unit determines that the processing time can be reduced as a result of scheduling by the scheduling unit, the task division unit is the target Since the task is divided, the number of tasks that can be assigned at that time increases with respect to the time that is free due to the preceding constraints of the data, so that it can be assigned to that free time. If a complicated task appears, the processing time of the entire program can be shortened.

Embodiment 4 FIG.
In the fourth embodiment, the task execution condition determination process is divided corresponding to a plurality of process elements.
The configuration of the program parallelizing apparatus in the drawing is the same as that in FIG. 2 and will be described with reference to FIG.
The task dividing unit 22 in the program parallelizing apparatus 20 according to the fourth embodiment divides the program into tasks corresponding to a plurality of process elements based on the analysis result of the analyzing unit 21 and performs scheduling by the scheduling unit 23. As a result, when there is an idle time for task execution in any process element, the task execution condition determination process is divided into a plurality of process elements. The code generation unit 24 is configured to add a synchronization instruction for synchronizing the divided task execution condition determination process when the task division unit 22 divides the task execution condition determination process. Yes. Other configurations are the same as those in the first embodiment.

FIG. 15 is a configuration diagram of process elements in the parallel processing device according to the fourth embodiment.
The processor according to the fourth embodiment includes N (N is an arbitrary integer) process elements (PE), and FIG. 15 illustrates an Nth (#N) process element 50.
The illustrated process element 50 includes a predicate register 51, N−1 predicate reception registers 52, an instruction execution unit 53, and a synchronization mechanism 54. The predicate register 51 is a register for holding a predicate value for a program to be processed by the process element (stores the true / false value of the processing result of the own process element), and the N−1 predicate reception registers 52 are These are registers for storing predicate values of connection destinations received from other process elements by synchronization events with predicates. The instruction execution unit 53 executes the task based on the value of the predicate register 51 and the value of the predicate reception register 52. Furthermore, the synchronization mechanism 54 is for synchronizing with other process elements, like the synchronization mechanisms 10 and 14 in the first embodiment.

In the fourth embodiment, the process for determining the task execution condition that can be divided is divided by the number of PEs having free time. Then, in order to combine the results of execution condition determinations that are calculated in parallel, a synchronization event with a predicate is passed between a plurality of process elements.
Hereinafter, the program parallelizing apparatus according to the fourth embodiment will be described with reference to an example of a program whose dependency relationship between tasks when an execution condition and a group of processing contents under the condition are treated as one task is shown in FIG. The flow of 20 processes and the operation of the parallel processing device will be described.

  In FIG. 16, as in the first embodiment, each node represents a task, and a numerical value in a circle represents a task number. The numerical value on the right side of the circle is the task processing time. Furthermore, the arrows between the nodes represent the precedence constraints between tasks. In this example, task 2 and task 3 can be executed after task 1 having a processing time of 40 is executed.

  When a program having the task configuration shown in FIG. 16 is input to the program parallelization apparatus 20, the program is analyzed and an intermediate code is generated. Then, the program is divided into task units shown in FIG. A scheduling result like 17 is obtained. The numerical value on the right side of the arrow indicating the task operation in FIG. 17 represents the processing time of the task. Task 1 and task 2 are executed on process element # 0 (2), and task 3 is executed on process element # 1 (3). At this time, the processing time of the entire program is the processing time in process element # 0 (2), which is 61, which is the sum of the processing time of task 1 and the processing time of task 2.

  When the scheduling is completed, the scheduling unit 23 confirms whether there is a free time exceeding the communication overhead between the process elements on any of the process elements. In this example, while task 1 is being executed in process element # 0 (2), there is a free time in process element # 1 (3). For this reason, the program parallelization apparatus 20 enters into the task re-division process.

FIG. 18 is a flowchart showing task re-division processing.
In the task re-division, the time of free time and the number of PEs having free time at that time are obtained (step ST31). Thereafter, it is confirmed whether there is a task capable of dividing the process at the same time (step ST32). Here, task 1 is a task with a processing time of 40, and it is assumed that the processing time 40 requires 30 hours for execution condition determination processing.
In this example, while task 1 having a processing time of 40 is being executed in process element # 0 (2), no process is assigned to process element # 1 (3) and there is free time. Therefore, it is possible to divide the execution condition determination of task 1 that requires 30 hours. Further, the process element # 0 (2) and the process element # 1 (3) that can be allocated to the divided task 1 are two. Therefore, the task 1 execution condition determination process executed on process element # 0 (2) is divided into two, and each is assigned to process element # 0 (2) and process element # 1 (3). (Step ST33).

The execution condition determination process is constituted by a combination of values, a logical operation, and a process for obtaining execution conditions, and a combination of logical sums and logical products of various execution conditions. When a long time is required for execution condition determination processing, a logical product or a logical sum may be obtained for these execution conditions after calculation of individual execution conditions. In such a case, processing time can be shortened by performing processing in parallel by assigning processing for obtaining individual execution conditions to a plurality of process elements.
Then, the calculation result of the execution condition obtained in each process element is transmitted as a predicate value to other process elements using a synchronization instruction with a predicate together with a synchronization event. An instruction for receiving a synchronization event with a predicate is added to a process element that receives a synchronization event with a predicate from another process element. Then, the logical operation in the original program is replaced with an operation instruction between predicate registers.

  That is, the task dividing unit 22 adds a synchronization instruction with a predicate to the synchronization event issuing position of the activation source task (step ST34), and adds a synchronization waiting instruction to the synchronization event standby position of the activation destination (step ST35). Then, a logical calculation instruction using the predicate value received after waiting for the synchronization event and the value of the predicate register is added (step ST36). FIG. 19 shows a scheduling result obtained by dividing the task in this way.

  An operation instruction between predicate registers is a predicate register that holds a predicate value for a program to be processed by the process element, and a predicate register that stores a predicate value of a connection destination received from a sync event with a predicate from another process element. It is an instruction that performs a logical operation between them. This calculation result is put in a predicate register for storing the predicate value of the self-process element.

  With the above configuration, conditional execution determination processing is divided into a plurality of process elements, assigned and executed in parallel, and the assigned execution condition determination operation results are aggregated by a synchronized instruction with a predicate, and logical operations are performed between predicate registers. By doing so, it is possible to shorten the processing time required to obtain the execution condition in the execution condition determination process.

Next, the operation of the parallel processing apparatus according to the fourth embodiment will be described using the scheduling result program shown in FIG. 19 as an example.
Process element # 0 (2) of the parallel processing device executes the divided task 1-1. Here, task 1-1 is the first half of task 1 execution condition determination processing. Further, the process element # 1 (3) executes the divided task 1-2. Task 1-2 is the latter half of the task 1 execution condition determination process. In the last part of the task 1-1 program, an instruction for receiving an event with a predicate and an instruction for performing a logical operation between the notified predicate value and the predicate value of the own process element are added. In addition, a transmission command for a synchronization event with a predicate is added to the last part of the task 1-2 program.

  When the task 1-1 on the process element # 0 (2) ends before the task 1-2 on the process element # 1 (3), the task enters a standby state for a synchronization event with a predicate from the task 1-2. That is, the standby instruction is stored in the synchronization mechanism 54 of the process element # 0 (2). Then, when the processing of the task 1-2 on the process element # 1 (3) is completed, the instruction execution unit 53 transmits a synchronization event with a predicate to the synchronization mechanism 54 of the process element # 0 (2). . By receiving the predicate synchronization event from the task 1-2, the instruction execution unit 53 of the process element # 0 (2) performs an operation between predicates.

  On the other hand, if the task 1-2 of the process element # 1 (3) ends before the task 1-1 of the process element # 0 (2), the predicate value of the process element # 1 (3) at the end time Is notified to the predicate reception register 52 of the process element # 0 (2) by a synchronization event with a predicate. Then, the instruction execution unit 53 of the process element # 1 (3) reads the task 3 program and starts execution. Here, at the head of task 3, since there is a command for receiving a synchronization event from process element # 0 (2), the task waits for a synchronization event from process element # 0 (2).

  In the process element # 0 (2), at the end of the processing of the task 1-1, the reception instruction for the synchronization event with predicate is executed. At this time, the target synchronization event has already been received from the process element # 1 (3). Therefore, the instruction execution unit 53 of the process element # 0 (2) receives the predicate register 51 of its own process element # 0 (2) and the process element # 1 (3) received together with the synchronization event and stored in the predicate reception register 52. ), The overall predicate value for the task 1 execution condition determination is obtained by calculation.

In the instruction execution unit 53 of the process element # 0 (2), the execution condition determination results calculated in parallel on a plurality of process elements are aggregated by a synchronous instruction with a predicate, and the calculation is performed between the predicate reception register 52 and the predicate register 51. To obtain the predicate value of the execution condition determination part. Based on the true / false value of the predicate register, the process of task 1-3 is performed.
The instruction execution unit 53 of the process element # 0 (2) issues a synchronization event to the task 3 on the process element # 1 (3) after completing the execution of the task 1-3. Also, the process of task 2 is started. At this time, the process element # 1 (3) that has received the synchronization event starts the processing of task 3, and performs the processing of task 2 and task 3 in parallel.

The above flow will be described with reference to FIGS.
FIG. 20 is an explanatory diagram showing an outline of a program before the division of task 1 in the fourth embodiment. In the execution condition determination process of process E in FIG. 20, what is divided at the logical sum is FIG. 21 and FIG. In this example, the process of FIG. 21 is assigned to process element # 0 (2), and the process of FIG. 22 is assigned to process element # 1 (3).
The program shown in FIG. 21 indicates that the logical product of the condition A and the condition B is stored in the predicate register 51 and the reception of the predicate value from the process element # 1 (3) is awaited. When the process element # 0 (2) receives the predicate synchronization event, the process element # 0 (2) takes the logical sum of the value stored in the predicate reception register 52 and its own predicate register 51 and stores it in the predicate register 51. Then, the process E executes the process based on the true / false value of the predicate register 51. Thereafter, a synchronization event is transmitted to the process element # 1 (3) in order to start the task 3 based on the prior relationship of the tasks shown in FIG. Thereafter, the process proceeds to task 2.

On the other hand, the program shown in FIG. 22 indicates that the logical product of the condition C and the condition D is stored in the predicate register 51, and the predicate value is transmitted to the process element # 0 (2) together with the synchronization event. Thereafter, it waits for a synchronization event for starting execution of task 3 assigned to process element # 1 (3).
By performing such processing, the processing time of the program, which took 61 hours in the scheduling shown in FIG. 17 before the division of task 1, is changed as shown in FIG. 48.

  As described above, the program parallelizing apparatus according to the fourth embodiment is a program parallelizing apparatus that divides a program into tasks that are executed in parallel on a plurality of process elements in the parallel processing apparatus according to the fourth embodiment. An analysis unit that analyzes the dependency of data included in the program, a task division unit that divides the program into tasks corresponding to a plurality of process elements based on the analysis result of the analysis unit, and a plurality of divided tasks A scheduling unit that performs scheduling for execution in each process element and a task for each scheduled process element are generated as a code in an execution format of each process element by adding a synchronization instruction according to data dependency A code generator, and scheduling by the scheduling unit As a result, if the scheduling unit determines that there is an idle time for task execution in any process element, the task division unit divides the task execution condition determination processing corresponding to a plurality of process elements. At the same time, the code generation unit adds an instruction for passing a synchronization event with a predicate for synchronizing the determination processing of the execution conditions of the divided tasks, so that the execution efficiency of the program in the parallel processing device is improved, Maximum execution time can be reduced.

It is a block diagram which shows the parallel processing apparatus by Embodiment 1 of this invention. BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the program parallelization apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the precedence relationship of the task in Embodiment 1 of this invention. It is a flowchart which shows operation | movement of the program parallelization apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the state which allocated the task structure in Embodiment 1 of this invention to the process element. It is a flowchart which shows the re-division process of the task of the program parallelization apparatus by Embodiment 1 of this invention. It is explanatory drawing which shows the state which allocated the task structure after the task re-division in Embodiment 1 of this invention to the process element. It is explanatory drawing which shows the precedence relationship of the task in Embodiment 2 of this invention. It is explanatory drawing which shows the state which allocated the task structure in Embodiment 2 of this invention to the process element. It is explanatory drawing which shows the state which allocated the task structure after the task re-division in Embodiment 2 of this invention to the process element. It is explanatory drawing which shows the precedence relationship of the task in Embodiment 3 of this invention. It is explanatory drawing which shows the state which allocated the task structure in Embodiment 3 of this invention to the process element. It is explanatory drawing which shows the state which allocated the task structure after the task re-division in Embodiment 3 of this invention to the process element. It is a flowchart which shows the division | segmentation process of the task of the program parallelization apparatus by Embodiment 3 of this invention. It is a block diagram which shows the process element of the parallel processing apparatus by Embodiment 4 of this invention. It is explanatory drawing which shows the precedence relationship of the task in Embodiment 4 of this invention. It is explanatory drawing which shows the state which allocated the task structure in Embodiment 4 of this invention to the process element. It is a flowchart which shows the re-division process of the task of the program parallelization apparatus by Embodiment 4 of this invention. It is explanatory drawing which shows the state which allocated the task structure after the task re-division in Embodiment 4 of this invention to the process element. It is explanatory drawing which shows the program before the division | segmentation in Embodiment 4 of this invention. It is explanatory drawing which shows the program at the time of allocating the program after the division | segmentation in Embodiment 4 of this invention to one process element. It is explanatory drawing which shows the program at the time of allocating the program after the division | segmentation in Embodiment 4 of this invention to the other process element.

Explanation of symbols

  1 processor, 2, 3, 50 process element, 4 internal memory, 5 external memory, 6 bus, 7, 12, 51 predicate register, 8, 11, 52 predicate reception register, 9, 13, 53 instruction execution unit, 10, 14, 54 synchronization mechanism, 20 program parallelization device, 21 analysis unit, 22 task division unit, 23 scheduling unit, 24 code generation unit, 30 program, 31 machine code.

Claims (4)

In a parallel processing device that includes a plurality of process elements and performs parallel processing of tasks with the plurality of process elements,
Each of the process elements is
A predicate register for storing a Boolean value for determining whether or not to execute the next instruction;
A predicate receive register that stores a predicate synchronization event with a Boolean value for determining whether to execute the next instruction received from another process element;
When executing a task that notifies the task execution condition determination result to a task executed by another process element, the predicate synchronization event with the true / false value of the predicate register is notified to the other process element. When executing a task that is executed based on the execution condition determination result of a task executed by another process element, the task is executed based on the true / false value of the reception register of the synchronization event with predicate. A parallel processing device comprising an instruction execution unit for performing the processing. A program parallelizing device for dividing a program into tasks to be executed in parallel on a plurality of process elements in the parallel processing device according to claim 1,
An analysis unit for analyzing the dependency of data included in the program;
A task dividing unit that divides the program into tasks corresponding to the plurality of process elements based on the analysis result of the analyzing unit;
A scheduling unit that performs scheduling for executing the divided tasks in the plurality of process elements;
A code generation unit that generates a scheduled task for each process element as a code of an execution format of each process element by adding a synchronization instruction according to data dependency;
As a result of scheduling performed by the scheduling unit, if the scheduling unit determines that there is a free time for task execution in any process element, the task division unit handles task processing for the plurality of process elements. A program parallelizing apparatus to which the code generation unit adds an instruction for passing a synchronization event with a predicate for synchronizing the processing of the divided task. A program parallelizing device for dividing a program into tasks to be executed in parallel on a plurality of process elements in the parallel processing device according to claim 1,
An analysis unit for analyzing the dependency of data included in the program;
Based on the analysis result of the analysis unit, the program is divided into tasks corresponding to the plurality of process elements, and if there are more than a predetermined number of target tasks in the data dependency relationship, the target A task division unit for dividing the task;
A scheduling unit that performs scheduling for executing the tasks divided by the task dividing unit by the plurality of process elements;
A code generation unit that generates a scheduled task for each process element as a code of an execution format of each process element by adding a synchronization instruction according to data dependency;
As a result of scheduling by the scheduling unit, a program parallelizing apparatus in which the task dividing unit divides the target task when the scheduling unit determines that the processing time can be shortened. A program parallelizing device for dividing a program into tasks to be executed in parallel on a plurality of process elements in the parallel processing device according to claim 1,
An analysis unit for analyzing the dependency of data included in the program;
A task dividing unit that divides the program into tasks corresponding to the plurality of process elements based on the analysis result of the analyzing unit;
A scheduling unit that performs scheduling for executing the divided tasks in the plurality of process elements;
A code generation unit that generates a scheduled task for each process element as a code of an execution format of each process element by adding a synchronization instruction according to data dependency;
As a result of scheduling performed by the scheduling unit, if the scheduling unit determines that there is an idle time for task execution in any one of the process elements, the task division unit performs the task execution condition determination process. The program parallelizing apparatus adds a command for delivering a synchronization event with a predicate for synchronizing the determination processing of the execution condition of the divided task.

Images