JP2016208589A - Internal power circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power-voltage dependency of a current flowing in the load during a load short circuit.SOLUTION: A control switch s0 is connected to a power supply voltage VCC, and outputs current after turning on a switch on a basis of a control signal Sin. A clamp circuit 1a is connected to a load 2, and applies a clamp control on an output voltage of the control switch s0. A current control element 1b conducts or disconnects the current on a basis of the output voltage on which the clamp control is applied. A changeover switch group 1c switches between paths L1, L2 for generating an internal power supply based on the voltage applied on switches s1-s3, which change depending on a conduction or non-conduction state of the current. A current control element 1d conducts the current outputted from the current control element 1b when the load short circuit is generated and the clamp circuit 1a applies a clamp control.SELECTED DRAWING: Figure 1

Description

  The present technology relates to an internal power supply circuit and a semiconductor device.

  2. Description of the Related Art In recent years, development of a semiconductor device called IPS (Intelligent Power Switch) in which a switch element using a power semiconductor element, a drive circuit for the switch element, a peripheral control circuit, a protection circuit, and the like are integrated on one chip has been progressing.

  IPS is widely used in vehicle electrical systems such as transmissions, engines, and brakes, for example, and products that meet the demands for miniaturization, high performance, and high reliability are demanded.

  As a conventional technology, when a voltage drop of the power supply voltage or internal power supply voltage occurs by starting up the booster circuit with a low magnification setting and then boosting with a high magnification setting to suppress the charge / discharge amount of the capacitor Has been proposed (Patent Document 1).

  In addition, a technique has been proposed in which the gate voltage of a pumping transistor is controlled in accordance with a voltage obtained by feeding back the boosted voltage to control the boosted voltage (Patent Document 2).

JP 2007-318967 A JP 2007-089242 A

As the IPS, a high-side IPS having a configuration in which a semiconductor device is arranged on the power supply side and a load is arranged between the output terminal of the semiconductor device and the ground has been developed.
In such a high-side type IPS, the output terminal voltage is turned on when it rises from the ground to the power supply voltage. In addition, when a load short circuit occurs in which the output terminal and the ground are short-circuited, it is desirable that a current with a peak value limited flows from the output terminal to the load.

  However, since the current output from the output terminal when the load is short-circuited depends on the power supply voltage, if the dependent voltage range is wide, when the load short-circuit occurs, the current flowing through the load as the power supply voltage increases Will rise significantly. Further, when such a state occurs, there is a possibility of causing element destruction.

  In view of the above, an object of the present invention is to provide an internal power supply circuit and a semiconductor device in which the power supply voltage dependency of a current flowing through a load when a load is short-circuited is reduced.

  In order to solve the above problems, in one proposal, an internal power supply circuit is provided. The internal power supply circuit has a control switch, a clamp circuit, a first current control element, a changeover switch group, and a second current control switch.

  The control switch is connected to the power supply voltage and is turned on based on the control signal to output a current. The clamp circuit is connected to a load and clamps the output voltage of the control switch. The first current control element makes the current conductive or non-conductive depending on the output voltage to be clamped. The changeover switch group switches a path for generating an internal power supply based on application of a voltage that changes in accordance with current conduction or non-conduction. The second current control element conducts the current output from the first current control element when a load short-circuit occurs and clamping by the clamp circuit is performed.

  In one scheme, a semiconductor device is provided. The semiconductor device has a charge pump and an internal power supply circuit. The internal power supply circuit includes a control switch, a clamp circuit, a first current control element, a changeover switch group, and a second current control element.

  The charge pump performs a boosting operation for driving a load using an internal power source generated from the power source voltage as an operating power source. The control switch is connected to the power supply voltage and is turned on based on the control signal to output a current. The clamp circuit is connected to a load and clamps the output voltage of the control switch. The first current control element makes the current conductive or non-conductive depending on the output voltage to be clamped. The changeover switch group switches a path for generating an internal power supply based on application of a voltage that changes in accordance with current conduction or non-conduction. The second current control element conducts the current output from the first current control element when a load short-circuit occurs and clamping by the clamp circuit is performed.

  It becomes possible to reduce the power supply voltage dependency of the current flowing through the load when the load is short-circuited.

(A) It is a figure which shows the structural example of an internal power supply circuit. (B) It is a figure for demonstrating operation | movement. It is a figure which shows the structural example of a semiconductor device. It is a figure which shows one path | route when an internal power supply circuit produces | generates a power supply. It is a figure which shows the other path | route at the time of an internal power supply circuit producing | generating a power supply. It is a figure which shows the ON / OFF state of each transistor for every path | route. It is a figure which shows the structural example of a semiconductor device. It is a figure which shows the electric current path which flows into the added depletion MOS transistor. It is a figure which shows the power supply voltage dependence of an electric current. It is a figure which shows the power supply voltage dependence of an electric current. It is a figure which shows the structural example of high side type IPS.

  Hereinafter, embodiments will be described with reference to the drawings. In the present specification and drawings, elements having substantially the same function may be denoted by the same reference numerals and redundant description may be omitted.

  FIG. 1A is a diagram illustrating a configuration example of the internal power supply circuit. The internal power supply circuit 1 includes a control switch s0, a clamp circuit 1a, a current control element 1b (first current control element), a changeover switch group 1c, and a current control element 1d (second current control element). The changeover switch group 1c includes switches s1 (first switch), s2 (second switch), and s3 (third switch) as three-terminal switches.

  An input terminal IN for receiving a control signal Sin is connected to the input terminal of the control switch s0. The current output terminal of the control switch s0 is connected to one input terminal of the switches s1, s2, and s3 and the input terminal of the current control element 1b.

  The output terminal of the current control element 1b is connected to the other input terminal of the switches s1 and s3, one input terminal of the current control element 1d, and one input terminal of the clamp circuit 1a. The output terminal of the switch s1 is connected to the other input terminal of the switch s2 and the internal ground GND1.

  The output ends of the switches s2 and s3 are connected to the internal power supply output terminal VDDout. The other output terminal of the current control element 1d is connected to the internal ground GND1, the output terminal of the clamp circuit 1a is connected to one end of the load 2, and the other end of the load 2 is connected to the external ground GND0.

  Here, the control switch s0 is connected to the power supply voltage VCC which is the driving power supply of this circuit, and is turned on based on the control signal Sin to output a current. The clamp circuit 1a is connected to the load 2 and performs clamp control of the output voltage of the control switch s0.

  The current control element 1b makes the current conductive or non-conductive based on the output voltage subjected to clamp control. The changeover switch group 1c is configured to generate a path L1 (first path) and L2 (second path) for generating an internal power source based on application of a voltage that changes according to current conduction or non-conduction to the switches s1 to s3. Switch. The current control element 1d is turned on when a load short-circuit occurs and clamping by the clamp circuit 1a is performed, and the current output from the current control element 1b flows to the internal ground GND1.

  FIG. 1B is a diagram for explaining the operation. The vertical axis represents current, and the horizontal axis represents power supply voltage VCC. The graph ga shows the waveform of the peak value of the current output from the output terminal OUT of the internal power supply circuit 1.

  The voltage range V1 is a range in which the internal power supply by the path L1 is generated. The voltage range V2 is a range in which an internal power supply is generated through the path L2. Note that the voltage value of the internal power supply generated by the path L1 changes according to the fluctuation of the power supply voltage VCC. Further, the internal power supply generated by the path L2 has a constant voltage value regardless of the fluctuation of the power supply voltage VCC.

  In the internal power supply circuit 1, when the load is short-circuited, the current control element 1d is turned on, and the inflection point P0 where the voltage range V1 and the voltage range V2 are switched is positioned on the low voltage side (the internal power supply is generated in the path L2). Wide voltage range).

  For this reason, it becomes possible to reduce the power supply voltage dependence of the electric current which flows into the load 2 at the time of load short circuit. Since a current whose peak value is limited flows to the load 2 when the load is short-circuited, it is possible to suppress an increase in current flowing to the load 2 and to suppress element destruction.

  Next, before describing the details of the technology of the present invention, the configuration and problems of an internal power supply circuit that does not have the function of the present invention will be described. Hereinafter, the external ground is simply referred to as GND0, and the internal ground is simply referred to as GND1.

FIG. 2 is a diagram illustrating a configuration example of a semiconductor device. The semiconductor device 100 includes an internal power supply circuit 10 and a charge pump 101 and is connected to the load 2.
The internal power supply circuit 10 includes PMOS transistors M1 to M3 that are P-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), an NMOS transistor M4 that is an N-channel MOSFET, a depletion MOS transistor Md1 that is a depletion type MOSFET, a Zener diode Dz, and a resistor R1. Is provided.

  The depletion MOS transistor Md1 is a depletion type MOSFET and is a transistor in which a gate voltage is 0 V and a current flows between a drain and a source, and is used as a current source. The PMOS transistors M1 to M3 and the NMOS transistor M4 are enhancement type MOSFETs.

  Regarding the connection relationship of the circuit elements, the source of the PMOS transistor M1 is connected to the power supply voltage VCC, and the gate of the PMOS transistor M1 is connected to the input terminal IN. The drain of the PMOS transistor M1 is connected to the drain of the depletion MOS transistor Md1, the drain of the NMOS transistor M4, the source of the PMOS transistor M2, and the source of the PMOS transistor M3.

  The gate of the depletion MOS transistor Md1 is connected to the source of the depletion MOS transistor Md1, the gate of the NMOS transistor M4, the cathode of the Zener diode Dz, and the gate of the PMOS transistor M2.

  The drain of the PMOS transistor M2 is connected to the gate of the PMOS transistor M3 and GND1. The back gate of the PMOS transistor M2 is connected to the power supply voltage VCC, and the back gate of the PMOS transistor M3 is connected to the power supply voltage VCC.

  When the PMOS transistor M1 is off, the voltage at the node n1 is in a floating state. Therefore, by connecting the back gates of the PMOS transistors M2 and M3 to the power supply voltage VCC, the PMOS transistors M2 and M3 The operation is stabilized.

  The drain of the PMOS transistor M3 is connected to the source of the NMOS transistor M4, the internal power supply output terminal VDDout, and one power supply terminal of the charge pump 101. The anode of the Zener diode Dz is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to one end of the load 2 via the output terminal OUT.

  The other power supply terminal of the charge pump 101 is connected to GND1, and the other end of the load 2 is connected to GND0. A boosted voltage signal is output from the output terminal of the charge pump 101 toward a predetermined circuit. For example, this voltage signal becomes a gate control signal applied to the gate when a main switch (not shown) for driving the load 2 is turned on / off.

  Here, VCC in the figure is an external power supply voltage, for example, 13V. GND0 is a normal 0V ground. Further, unlike GND0, GND1 is 0V when the semiconductor device 100 is not operating, and is a voltage that is a value obtained by subtracting a predetermined value (for example, 5V) from VCC when the semiconductor device 100 is operating.

  Further, the input terminal IN is a terminal to which a control signal Sin for turning on / off the driving of the internal power supply circuit 10 is input. The internal power supply circuit 10 is driven when the control signal Sin is at the L level and is not driven when the control signal Sin is at the H level. The output terminal OUT is an output terminal to which the load 2 is connected.

  The internal power supply output terminal VDDout is a terminal for outputting the internal power supply VDD generated by the internal power supply circuit 10 from the external power supply VCC. The internal power supplies VDD and GND1 are supplied as operation power supplies for peripheral circuits.

Next, the normal operation of the internal power supply circuit 10 will be described. The internal power supply circuit 10 is configured to generate the internal power supply VDD from the power supply voltage VCC through two paths.
Thus, for example, in the initial operation, the internal power supply VDD having a voltage value lower than the power supply voltage is supplied, and the internal power supply VDD having the same level as the power supply voltage is supplied after a predetermined time has passed. The circuit is stabilized and started by stabilizing the circuit by supplying power.

  FIG. 3 is a diagram showing one path when generating the internal power supply. The path L1 is a path through the PMOS transistor M3, and is a path for generating the internal power supply VDD from the power supply voltage VCC with almost no voltage drop.

  An operation of generating the internal power supply VDD in the path L1 will be described. First, the control signal Sin shifts from the H level to the L level, and the PMOS transistor M1 is turned on. Therefore, the voltage of the node n1 (Vn1) increases.

  On the other hand, the Zener diode Dz is connected in the opposite direction to the current flowing through the PMOS transistor M1, and the voltage Vn1 is lower than the breakdown voltage (Vz) of the Zener diode Dz.

  Therefore, the diode is clamped, the depletion MOS transistor Md1 is not energized (non-conducting), and the voltage at the node n2 (referred to as Vn2) is equal to the voltage Vn1.

  Therefore, since the source of the PMOS transistor M2 connected to the node n1 and the gate of the PMOS transistor M2 connected to the node n2 have the same potential, the PMOS transistor M2 is off.

  When the PMOS transistor M2 is turned off, the potential of GND1 is applied to the gate of the PMOS transistor M3. Therefore, since the gate potential of the PMOS transistor M3 is lower than the source potential of the PMOS transistor M3, the PMOS transistor M3 is turned on.

  On the other hand, the source of the NMOS transistor M4 is electrically connected to the node n1 because the PMOS transistor M3 is turned on. Therefore, the source potential of the NMOS transistor M4 is substantially the same as the voltage Vn1 (that is, the same potential as the voltage Vn2 of the node n2).

Accordingly, since the gate of the NMOS transistor M4 and the source of the NMOS transistor M4 are at the same potential, the NMOS transistor M4 is turned off.
Therefore, the current output from the PMOS transistor M1 flows through the path L1 shown in FIG. 3, and the internal power supply VDD is generated. The internal power supply VDD is output from the internal power supply output terminal VDDout.

  Note that the output voltage of the PMOS transistor M1 (the voltage Vn1 of the node n1) gradually approaches the power supply voltage VCC from the start of the on-state of the PMOS transistor M1, and the internal power supply VDD is the power supply voltage VCC when the PMOS transistor M1 is fully on. Is equal to

FIG. 4 is a diagram showing the other path when generating the internal power supply. The path L2 is a path through the NMOS transistor M4 that functions as a source follower.
In the path L2, a voltage value lower than the power supply voltage VCC by the threshold voltage of the NMOS transistor M4 is generated as the internal power supply VDD. This prevents the high power supply voltage VCC from being applied directly to the peripheral circuit during initial operation.

  An operation for generating the internal power supply VDD in the path L2 will be described. Assume that the internal power supply VDD rises and reaches the value of the breakdown voltage Vz of the Zener diode Dz. This means that the voltage Vn2 of the node n2 on the cathode side of the Zener diode Dz reaches the breakdown voltage Vz, so that the Zener diode Dz causes breakdown (release of the diode clamp occurs).

  When the Zener diode Dz breaks down, the depletion MOS transistor Md1 is energized (conducted), and a current flows from the cathode of the Zener diode Dz toward the anode.

That is, the current output from the PMOS transistor M1 flows through the depletion MOS transistor Md1 and the Zener diode Dz.
At this time, a potential difference is generated between the voltage Vn1 at the node n1 and the voltage Vn2 at the node n2, and the voltage Vn1 is higher than the voltage Vn2 (Vn2 <Vn1). Accordingly, since the gate potential of the PMOS transistor M2 is lower than the source potential of the PMOS transistor M2, the PMOS transistor M2 is turned on.

When the PMOS transistor M2 is turned on, a high potential is applied to the gate of the PMOS transistor M3, so that the PMOS transistor M3 is turned off.
On the other hand, although the voltage Vn2 is applied to the gate potential of the NMOS transistor M4, it is higher than the source potential of the NMOS transistor M4, so that the NMOS transistor M4 is turned on.

  Therefore, the current output from the PMOS transistor M1 flows through the path L2 shown in FIG. 4, and the internal power supply VDD is generated. The internal power supply VDD is output from the internal power supply output terminal VDDout.

  In the path L2, the internal power supply VDD is maintained at a certain voltage (voltage Vd) value until the breakdown of the Zener diode Dz is eliminated. This voltage Vd is a voltage value obtained by subtracting the threshold voltage of the NMOS transistor M4 from the power supply voltage VCC.

Next, the operation of switching from the path L2 to the path L1 and generating the internal power supply VDD again in the path L1 will be described.
Since the internal power supply VDD is an operation power supply for the charge pump 101, the charge pump 101 operates when the internal power supply VDD is supplied. When the charge pump 101 operates, a gate control signal (a gate voltage of the power MOSFET) for turning on and off the power MOSFET for driving the load 2 is output.

  In this way, when the charge pump 101 operates, the voltage at the output terminal OUT connected to the load 2 also rises, so the voltage on the anode side of the Zener diode Dz rises, and the Zener diode Dz breaks. Down will be eliminated.

When the breakdown of the Zener diode Dz is resolved, diode clamping occurs again, and the generation path of the internal power supply VDD is the path L1.
That is, when the breakdown of the Zener diode Dz is eliminated, the depletion MOS transistor Md1 is de-energized, so that the voltage Vn1 at the node n1 is equal to the voltage Vn2 at the node n2.

Therefore, the transistor switching operation described above with reference to FIG. 3 is performed, and the internal power supply VDD is generated by the path L1.
The table 20 in FIG. 5 collectively shows the ON / OFF state of each transistor for each of the paths L1 and L2.

  Next, problems to be solved will be described. In the internal power supply circuit 10, when a load short-circuit occurs in which the output terminal OUT and GND0 are short-circuited, the transistor switching operation as described above with reference to FIG. 3 is performed, and the internal power supply VDD is generated by the path L1. .

  The internal power supply VDD generated by the path L2 has a constant value, but the voltage value of the internal power supply VDD generated by the path L1 changes according to the fluctuation of the power supply voltage VCC. Therefore, when the internal power supply VDD rises to the same high potential as the power supply voltage VCC, the voltage value of the gate control signal output from the charge pump 101 also increases.

  That is, since the charge pump 101 performs a boosting operation with the internal power supply VDD, if the internal power supply VDD rises, the boosted voltage value by the charge pump 101 also increases. Therefore, the output level of the charge pump 101 (the voltage value of the gate control signal) ) Also increases.

  Then, since the gate voltage applied to the power MOSFET for driving the load 2 increases, the drain current flowing through the power MOSFET increases. Since this drain current is an oscillation current that drives the load 2, the current flowing through the load 2 increases.

  However, if the current flowing through the load 2 increases in a state where a load short-circuit occurs, problems such as element breakdown may occur, and the quality and reliability of the device are impaired.

  Next, an internal power supply circuit according to the technique of the present invention will be described. FIG. 6 is a diagram illustrating a configuration example of a semiconductor device. The semiconductor device 100a includes an internal power supply circuit 10a and a charge pump 101.

  The internal power supply circuit 10a includes PMOS transistors M1 to M3, NMOS transistor M4, depletion MOS transistors Md1 and Md2, a Zener diode Dz, and a resistor R1.

The semiconductor device 100a newly includes a depletion MOS transistor Md2 with respect to the configuration of FIG. 2, and the other components are the same as those of FIG.
As shown in FIG. 1, the control switch s0 corresponds to the PMOS transistor M1, the switch s1 corresponds to the PMOS transistor M2, the switch s2 corresponds to the PMOS transistor M3, and the switch s3 This corresponds to the NMOS transistor M4.

  Current control element 1b corresponds to depletion MOS transistor Md1, and current control element 1d corresponds to depletion MOS transistor Md2. The clamp circuit 1a is realized by a Zener diode Dz and a resistor R1.

  The connection relationship of the depletion MOS transistor Md2 will be described. The drain of the depletion MOS transistor Md2 is the gate of the PMOS transistor M2, the gate of the depletion MOS transistor Md1, the source of the depletion MOS transistor Md1, the gate of the NMOS transistor M4, and the cathode of the Zener diode Dz. Connect to.

  The gate of the depletion MOS transistor Md2 is connected to the source of the depletion MOS transistor Md2 and GND1. The connection relationship of the other elements is the same as in FIG.

  The operation will be described. When a load short circuit occurs, in the configuration of the internal power supply circuit 10 in FIG. 2, the internal power supply VDD by the path L1 is generated by the diode clamp of the Zener diode Dz as described above.

  On the other hand, in the internal power supply circuit 10a shown in FIG. 6, by adding the depletion MOS transistor Md2, the current blocked by the Zener diode Dz flows through the depletion MOS transistor Md2.

  FIG. 7 is a diagram showing a current path flowing through the added depletion MOS transistor. In the internal power supply circuit 10a, immediately after the load short circuit occurs, the current flowing from the PMOS transistor M1 flows through the path L3 through the depletion MOS transistor Md1 and the depletion MOS transistor Md2.

  Then, since the voltage Vn2 at the node n2 becomes lower than the voltage Vn1 at the node n1 (Vn2 <Vn1), the source-gate voltage of the PMOS transistor M2 increases and the PMOS transistor M2 is turned on.

  Therefore, when the PMOS transistor M2 is turned on, as described above, the PMOS transistor M3 is turned off and the NMOS transistor M4 is turned on, so that the generation path of the internal power supply VDD by the path L2 is established.

  The internal power supply VDD generated by the path L2 is a constant voltage and is not affected by fluctuations in the power supply voltage VCC. For this reason, since the constant internal power supply VDD is supplied to the charge pump 101, the output level of the charge pump 101 is also constant.

  Therefore, since the gate voltage of the power MOSFET for driving the load 2 is constant, an increase in the current flowing through the power MOSFET is suppressed. Therefore, the peak current value output from the output terminal OUT when the load is short-circuited can be suppressed.

  Next, a simulation result of the power supply voltage dependency of current will be described. FIG. 8 is a diagram showing the power supply voltage dependency of the current. The vertical axis represents current (A), and the horizontal axis represents power supply voltage VCC (V). A waveform g1 is a current peak value output from the output terminal OUT, and shows a simulation result of the power supply voltage dependency of the current in the internal power supply circuit 10 before improvement.

An inflection point P1 indicates a switching point in the internal power supply circuit 10 at which the internal power supply VDD generated through the path L1 switches to the internal power supply VDD generated through the path L2.
The voltage range Va in the vicinity of the power supply voltage VCC = 6 to 14V indicates the generation of the internal power supply VDD by the path L1, and is switched to the generation of the internal power supply VDD by the path L2 with the inflection point P1 as a boundary. The voltage range Va is a range where the power supply voltage dependency of the current appears, and the current value increases as the power supply voltage VCC increases.

  FIG. 9 is a diagram showing the power supply voltage dependence of current. The vertical axis represents current (A), and the horizontal axis represents power supply voltage VCC (V). A waveform g2 is a current peak value output from the output terminal OUT, and shows a simulation result of the power supply voltage dependency of the current in the improved internal power supply circuit 10a.

  The inflection point P2 indicates a switching point in the internal power supply circuit 10a where the internal power supply VDD generated through the path L1 is switched to the internal power supply VDD generated through the path L2.

  A voltage range Vb in the vicinity of the power supply voltage VCC = 6 to 10V indicates generation of the internal power supply VDD by the path L1, and is switched to generation of the internal power supply VDD by the path L2 with the inflection point P2 as a boundary. The voltage range Vb is a range in which the dependency of the current on the power supply voltage appears, and the current value increases as the power supply voltage VCC increases.

  Here, when comparing the waveforms g1 and g2, the inflection point P1 of the waveform g1 is near the power supply voltage VCC = 13V, and the inflection point P2 of the waveform g2 is near the power supply voltage VCC = 10V. Thus, in the improved internal power supply circuit 10a, the inflection point can be shifted to the low voltage side of the power supply voltage VCC.

  For this reason, the voltage range Vb is narrower than the voltage range Va, and the voltage range in which the power supply voltage dependency appears is narrow. That is, when the load is short-circuited, the voltage range in which the internal power supply VDD is generated in the path L1 is narrowed, and the voltage range in which the internal power supply VDD is generated in the path L2 is widened.

  As described above, the internal power supply circuit 10a reduces the dependency of the current flowing in the load on the power supply voltage when the load is short-circuited. Therefore, when the load is short-circuited, the internal power supply VDD having a constant voltage is supplied to the charge pump 101, so that the peak current flowing through the load 2 can be reduced.

Next, the configuration of the IPS to which the semiconductor device 100a of the present invention is applied will be described. FIG. 10 is a diagram illustrating a configuration example of the high-side IPS.
The IPS 30 is connected to the load 2, the microcomputer 4, and the battery 5. The IPS 30 includes a logic circuit 31, a level shift driver 32, an internal power supply circuit 33, an ST (status) circuit 34, a low voltage detection circuit 35, a short circuit detection circuit 36, a load release detection circuit 37, an overcurrent detection circuit 38, and an overheat. A detection circuit 39 is provided.

  Further, the IPS 30 has a switch element M0 that is a power MOSFET for driving the load 2, and a diode D0 (FWD: Free Wheel Diode) is connected to the switch element M0.

  At the moment when the switch element M0 is turned off, a counter electromotive force is generated from the inductive load 2 such as a motor. For this reason, the diode D0 is connected in antiparallel to the switch element M0, and the load current at this time is circulated.

  Here, the logic circuit 31 collectively recognizes a control signal from the microcomputer 4 input from the terminal In and a state detection signal of each protection circuit, and controls ONBH (ON By H) for controlling the switch element M0. Output a signal.

  The level shift driver 32 generates a GS signal obtained by boosting the ONBH signal output from the logic circuit 31 to a level required to fully turn on the switch element M0, and applies it to the gate of the switch element M0. The level shift driver 32 includes the function of the charge pump 101 described above.

  The internal power supply circuit 33 generates an internal power supply that is a power supply voltage that is gradually increased from a value lower than the power supply voltage VCC, and supplies the internal power supply to a circuit that needs to be controlled by the internal power supply. The internal power supply circuit 33 includes the function of the internal power supply circuit 10a shown in FIG.

The ST circuit 34 transmits the operating state of the switch element M0 to the microcomputer 4 via the ST terminal.
The low voltage detection circuit 35 transmits an abnormal signal to the logic circuit 31 when the power supply voltage VCC is lower than the rated voltage. The logic circuit 31 that has received the abnormal signal transmitted from the low voltage detection circuit 35 outputs the ONBH signal that controls the switch element M0 as an OFF signal.

  The short circuit detection circuit 36 transmits an abnormal signal to the logic circuit 31 when the output terminal OUT connected to the source of the switch element M0 is short-circuited to GND. The logic circuit 31 that has received the abnormal signal transmitted from the short circuit detection circuit 36 outputs the ONBH signal that controls the switch element M0 as an OFF signal.

  The load release detection circuit 37 transmits an abnormal signal to the logic circuit 31 when the output terminal OUT connected to the source of the switch element M0 is opened. The logic circuit 31 that has received the abnormal signal transmitted from the load release detection circuit 37 outputs an ONBH signal for controlling the switch element M0 as an OFF signal.

  The overcurrent detection circuit 38 receives the same current as the current flowing through the switch element M0 from the transistor Mc that forms a current mirror circuit with the switch element M0. Then, when it is detected that an abnormally large current flows from the rating, an abnormal signal is transmitted to the logic circuit 31. The logic circuit 31 that has received the abnormal signal transmitted from the overcurrent detection circuit 38 outputs an ONBH signal for controlling the switch element M0 as an off signal.

  The overheat detection circuit 39 transmits an abnormal signal to the logic circuit 31 when the switch element M0 becomes an abnormally high temperature than the rating. The logic circuit 31 that has received the abnormal signal transmitted from the overheat detection circuit 39 outputs an ONBH signal for controlling the switch element M0 as an OFF signal.

  As described above, according to the present invention, the source-gate voltage of the PMOS transistor M2 when generating the internal power supply VDD through the path L1 can be increased. For this reason, the PMOS transistor M2 is easily turned on at a lower power supply voltage, so that the power generation range in the path 2 where flat current characteristics can be obtained is widened, and the dependency of the current on the power supply voltage can be reduced. .

  This also reduces the oscillation peak current when the load is short-circuited, so that it is possible to suppress the occurrence of element destruction and improve the device quality and reliability. Furthermore, since a current having a low peak value is continuously output from the output terminal OUT even when the load is short-circuited, it is possible to restart immediately without performing a reset operation if the load short-circuit is eliminated.

  Furthermore, since the current flowing when the load is short-circuited can be reduced, for example, a margin can be provided for the fusing current of the wire connecting the load and the device, and the number of wire bondings can be reduced.

  Further, if the wire is an Au (gold) wire, a cost reduction effect can be expected. Furthermore, since the current flowing through the printed board can also be reduced, the printed board line can be made thinner, which can contribute to a reduction in the board area.

  As mentioned above, although embodiment was illustrated, the structure of each part shown by embodiment can be substituted by the other thing which has the same function. Moreover, other arbitrary structures and processes may be added.

DESCRIPTION OF SYMBOLS 1 Internal power supply circuit 1a Clamp circuit 1b 1st current control element 1c Changeover switch group 1d 2nd current control element 2 Load s0 Control switch s1 1st switch s2 2nd switch s3 3rd switch Sin Control signal L1 1st path L2 Second path IN input terminal OUT output terminal VDDout Internal power output terminal GND0 External ground GND1 Internal ground ga Peak current waveform V1 Range of power supply voltage generated by the first path V2 Internal power generated by the second path Power supply voltage range P0 Inflection point

Claims (6)

In the internal power supply circuit that generates the internal power supply from the power supply voltage,
A control switch connected to the power supply voltage and turned on based on a control signal to output a current;
A clamp circuit that connects to a load and clamps the output voltage of the control switch;
A first current control element that makes the current conductive or non-conductive depending on the output voltage to be clamped;
A selector switch group for switching a path for generating the internal power supply based on application of a voltage that changes according to conduction or non-conduction of the current;
A second current control element that conducts the current output from the first current control element when a load short circuit occurs and clamping by the clamp circuit is performed;
An internal power supply circuit comprising: The changeover switch group switches between a first path for generating the internal power supply whose voltage value changes in accordance with fluctuations in the power supply voltage and a second path for generating the internal power supply at a constant level from the power supply voltage. Done
The changeover switch group switches the generation path of the internal power source to the second path when the second current control element is conducted.
The internal power supply circuit according to claim 1.   The inflection point at which the first voltage range in which the internal power source is generated by the first path and the second voltage range in which the internal power source is generated by the second path is switched is the second current control. 3. The internal power supply circuit according to claim 2, wherein the element is shifted to a low voltage side when the element is conducted. The changeover switch group includes a first switch, a second switch, and a third switch, which are three-terminal switches,
An input terminal to which the control signal is input is connected to an input terminal of the control switch,
The current output terminal of the control switch is connected to one input terminal of the first, second and third switches and the input terminal of the first current control element,
The output terminal of the first current control element is connected to the other input terminal of the first and third switches, one input terminal of the second current control element, and one input terminal of the clamp circuit. And
The output terminal of the first switch is connected to the other input terminal of the second switch and the internal ground,
The output terminals of the second and third switches are connected to an internal power output terminal,
The other output terminal of the second current control element is connected to the internal ground, the output terminal of the clamp circuit is connected to one end of the load, and the other end of the load is connected to an external ground;
The internal power supply circuit according to claim 2. When the output voltage is less than a predetermined voltage, the output voltage is clamped by the clamp circuit and the first current control element becomes non-conductive, the first switch is turned off, and the second switch is turned on. And the third switch is turned off, the first path from the control switch to the internal power output terminal is generated via the second switch, and the internal power is output.
When the output voltage is equal to or higher than a predetermined voltage, the clamp circuit releases the clamp of the output voltage and the first current control element is turned on, the first switch is turned on, and the second switch is turned off. And the third switch is turned on, the second path from the control switch to the internal power supply output terminal is generated via the third switch, and the internal power supply is output.
When the output voltage is clamped by the clamp circuit when the load is short-circuited, the second current control element is turned on, and the current output from the first current control element is caused to flow to the internal ground. The first switch is turned on, the second switch is turned off, and the third switch is turned on, and the second path is generated to output the internal power supply.
The internal power supply circuit according to claim 4. A charge pump that performs a boosting operation for driving a load using an internal power supply generated from a power supply voltage as an operation power supply;
A control switch that is connected to the power supply voltage and is turned on based on a control signal to output current, a clamp circuit that is connected to the load and clamps the output voltage of the control switch, and the output voltage that is clamped Switching for switching a path for generating the internal power supply based on application of a voltage that changes according to conduction or non-conduction of the current and a first current control element that conducts or non-conducts the current. An internal power supply circuit including a switch group and a second current control element that conducts the current output from the first current control element when a load short-circuit occurs and clamping by the clamp circuit is performed;
A semiconductor device comprising:

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