JP2016184721A5

JP2016184721A5 -

Info

Publication number: JP2016184721A5
Application number: JP2016017827A
Authority: JP
Filing date: 2016-02-02
Publication date: 2018-11-08
Anticipated expiration: 2036-02-02

Description

メモリトランジスタ４０Ｃ（９０ａ等）を用いた不揮発性メモリの構成及び製造方法の別例を図６６〜図７１を参照して更に説明する。
図６６〜図７１は不揮発性メモリの製造方法の別例を示す図である。ここで、図６６は第１製造工程の一例の要部断面模式図、図６７は第２製造工程の一例の要部断面模式図、図６８は第３製造工程の一例の要部断面模式図、図６９は第４製造工程の一例の要部断面模式図、図７０は第５製造工程の一例の要部断面模式図、図７１は第６製造工程の一例の要部断面模式図である。以下、図６６〜図７１を参照し、不揮発性メモリの製造工程の一例について、順に説明する。 Another example of the configuration and manufacturing method of the nonvolatile memory using the memory transistor 40C (90a, etc.) will be further described with reference to FIGS.
66 to 71 are views showing another example of a method for manufacturing a nonvolatile memory. Here, FIG. 66 is a schematic cross-sectional view of the main part of an example of the first manufacturing process, FIG. 67 is a schematic cross-sectional view of the main part of an example of the second manufacturing process, and FIG. 69 is a schematic cross-sectional view of an essential part of an example of a fourth manufacturing process, FIG. 70 is a schematic cross-sectional view of an essential part of an example of a fifth manufacturing process, and FIG. 71 is a schematic cross-sectional view of an essential part of an example of a sixth manufacturing process. . Hereinafter, an example of a manufacturing process of the nonvolatile memory will be described in order with reference to FIGS. 66 to 71.

Claims

The concentration distribution of impurities contained in the first source region and the first drain region in the semiconductor substrate is steeper than the concentration distribution of impurities contained in the second source region and the second drain region. the semiconductor device according to claim 16 or 17, characterized in.