JP2016178551A - Communication device and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a data amount to be stored beforehand in a storage device in a communication device which transmits and verifies a check code, while processing the check code at high speed.SOLUTION: A communication device 100 includes: a storage unit 110 which sets a plurality of groups composed of a plurality of values each having a part of digits in predetermined digits to be effective digits while digits other than the effective digits set to be 0, and retains a plurality of surplus values obtained by dividing the plurality of values included in each group by a predetermined value respectively, on a group-by-group basis; a generation unit 130 which divides transmission data into the plurality of groups, acquires each surplus value by referring to the storage unit for each of the plurality of groups, and generates a transmission check code on the basis of the total sum of acquired surplus values; and a verification unit 160 which divides a value based on the reception data into a plurality of groups, acquires each surplus value by referring to the storage unit for each of the plurality of groups, and verifies the reception data and the reception check code on the basis of the total sum of acquired surplus values. The storage unit can be referred to simultaneously from the generation unit and the verification unit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a communication apparatus and a control method, and more particularly to a communication apparatus that transmits and verifies a check code and a control method for the communication apparatus.

  In order to detect errors in communication data, an error detection method using CRC (Cyclic Redundancy Check) is used. In recent years, the amount of communication data processed per unit time has increased as the capacity of storage devices has increased and the speed of communication interfaces and bus interfaces has increased, making it necessary to calculate a large number of CRCs. Yes.

  Normally, the remainder value obtained by dividing the target data into a polynomial and dividing by a predetermined generator polynomial is used as the CRC. In general, in order to calculate the CRC, a method of calculating a remainder value of the target data by executing a predetermined comparison / subtraction process while shifting the target data bit by bit. However, in this method, since it is necessary to execute the comparison / subtraction processing bit by bit, it takes a lot of time to calculate the remainder value.

  In order to shorten the calculation time of the remainder value, the remainder value obtained by dividing all the possible values of the target data by the generator polynomial is calculated in advance and stored in a table, and the target data is referred to by referring to the table. A method of obtaining the remainder value of can also be considered. However, as the size of the target data increases, the required table size increases exponentially, and there is a problem that the size and cost of the storage device increase.

  There is known a residue calculation device that calculates a residue when a polynomial corresponding to an input information sequence is divided by a generator polynomial (see Patent Document 1). The remainder calculation apparatus stores a plurality of remainder tables each holding the values of the corresponding remainder information strings, using the values of the plurality of unit information strings as indexes. The remainder calculation apparatus divides the target information string into a plurality of unit information strings, obtains values of the plurality of remainder information strings by referring to the plurality of remainder tables using the values of the respective unit information strings as indexes. The remainder is calculated based on the exclusive OR of the plurality of remainder information strings.

  Also, a division device that divides an input information bit string by a generator polynomial is known (see Patent Document 2). This division device divides an input information bit string into a plurality of sub-bit strings. The division device holds a remainder value obtained by dividing a bit string in which the bit position in the input information bit string corresponding to the least significant bit of each sub-bit string is 1 and the other bits are 0 by the generator polynomial. . Then, the division device modulo-2 adds each remainder value and the multiplication result of the corresponding sub-bit sequence, and divides by the generator polynomial.

JP 2008-11025 A JP 2008-160663 A

  In the remainder calculation apparatus described in Patent Document 1 and the division apparatus described in Patent Document 2, an input information sequence can be efficiently divided by a generator polynomial.

  However, a communication device that transmits and verifies a check code is required to further reduce the amount of data stored in a storage device while processing the check code at high speed.

  An object of the present invention is to provide a communication device and a control method capable of further reducing the amount of data stored in a storage device while processing the check code at high speed in a communication device that transmits and verifies a check code. It is to provide.

  A communication apparatus according to an aspect of the present invention is a communication apparatus that communicates transmission data and reception data having a predetermined digit, wherein a part of the predetermined digit is a valid digit and a digit other than the valid digit is set to 0. A plurality of groups composed of a plurality of values are set, a storage unit that holds a plurality of residue values for each group obtained by dividing a plurality of values included in each group by a predetermined value, and transmission data into a plurality of groups A generation unit that divides and acquires a remainder value by referring to a storage unit for each of a plurality of groups, generates a transmission check code based on the sum of the obtained remainder values, and a transmission unit that transmits transmission data together with the transmission check code A reception unit that receives the reception data and a reception check code for the reception data, and divides the value based on the reception data into a plurality of groups, and refers to the storage unit for each of the plurality of groups, Tokushi includes a verification unit for verifying the received data and the reception check code based on the sum of the obtained residue values to, the storage unit can be simultaneously referred to from the generation unit and the verification unit.

  A communication device according to another aspect of the present invention is a communication device that communicates transmission data and reception data having a predetermined digit, wherein a part of the predetermined digit is a valid digit and a digit other than the valid digit is set. A plurality of groups each composed of a plurality of values set to 0 are set, a first storage unit that holds a remainder value obtained by dividing a minimum value in each group by a predetermined value for each group, and a predetermined plurality of values respectively. A second storage unit that holds a plurality of residue values divided by a value, and divides transmission data into a plurality of groups, acquires a residue value by referring to the first storage unit for each of the plurality of groups, and acquires the residue The multiplication value of the value and the significant digit value of each group is calculated, the remainder value corresponding to the multiplication value is obtained by referring to the second storage unit, and the transmission check code is calculated based on the sum of the obtained remainder values. Generation unit to generate and transmission data transmission check A transmitter that transmits the received data, a reception unit that receives the reception check code for the received data, and a value based on the received data is divided into a plurality of groups, and the first storage unit is referenced for each of the plurality of groups. To obtain a remainder value, calculate a multiplication value of the obtained remainder value and the digit value of the significant digit of each group, obtain a remainder value corresponding to the multiplication value with reference to the second storage unit, and obtain the obtained A verification unit that verifies the received data and the reception check code based on the sum of the remainder values, and the second storage unit can simultaneously refer to a plurality of groups from the generation unit and the verification unit.

  A control method according to an aspect of the present invention is a control method for a communication apparatus that includes a storage unit and communicates transmission data and reception data having a predetermined digit, and a part of the predetermined digits is a valid digit. And sets a plurality of groups composed of a plurality of values in which digits other than significant digits are 0, and stores a plurality of remainder values obtained by dividing a plurality of values included in each group by a predetermined value for each group The transmission data is divided into a plurality of groups, a remainder value is obtained by referring to the storage unit for each of the plurality of groups, a transmission check code is generated based on the sum of the obtained remainder values, and the transmission data is The data is transmitted together with the transmission check code, the reception check code for the reception data and the reception data is received, the value based on the reception data is divided into a plurality of groups, and the remainder value is obtained by referring to the storage unit for each of the plurality of groups. And comprises verifying the received data and the reception check code based on the sum of the obtained residue values storage unit can be simultaneously referred to in the generation and verification.

  A control method according to another aspect of the present invention is a control method for a communication apparatus that includes a first storage unit and a second storage unit and communicates transmission data and reception data having a predetermined digit, and includes a predetermined digit. Set multiple groups consisting of multiple values with some of the significant digits and zeros other than valid digits set to 0, and the remainder value obtained by dividing the minimum value in each group by the predetermined value for each group A plurality of remainder values obtained by dividing the plurality of predetermined values by the predetermined values are stored in the second storage unit, the transmission data is divided into a plurality of groups, The remainder value is obtained by referring to the 1 storage section, the multiplication value of the obtained remainder value and the digit value of the significant digit of each group is calculated, and the remainder value corresponding to the multiplication value is obtained by referring to the second storage section. And generate a transmission check code based on the sum of the acquired remainder values. The transmission data is transmitted together with the transmission check code, the reception check code for the reception data and the reception data is received, the value based on the reception data is divided into a plurality of groups, and the first storage unit is referenced for each of the plurality of groups. The remainder value is acquired, the multiplication value of the obtained remainder value and the digit value of the significant digit of each group is calculated, the remainder value corresponding to the multiplication value is obtained by referring to the second storage unit, and the obtained remainder The second storage unit can simultaneously refer to a plurality of groups in generation and verification, including verifying the reception data and the reception check code based on the sum of the values.

  According to the present invention, since the communication device that transmits and verifies the check code can share data for calculating the remainder value at the time of generating and verifying the check code, the storage device can process the check code at high speed. It becomes possible to further reduce the amount of data stored in the.

It is a figure which shows the hardware block diagram of the communication apparatus 100 which concerns on embodiment. It is a schematic diagram for demonstrating a some group. 6 is a flowchart illustrating an example of operation of transmission processing by the communication apparatus 100. 4 is a flowchart illustrating an example of operation of reception processing by the communication apparatus 100. It is a figure which shows the hardware block diagram of the communication apparatus 200 which concerns on other embodiment. It is a figure which shows the hardware block diagram of the communication apparatus 200 which concerns on other embodiment. 5 is a flowchart illustrating an example of an operation of transmission processing by the communication apparatus 200. 6 is a flowchart illustrating an example of operation of reception processing by the communication apparatus 200.

  Hereinafter, a communication device and a control method according to an aspect of the present invention will be described with reference to the drawings. However, it should be noted that the technical scope of the present invention is not limited to these embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 1 is a diagram illustrating a hardware configuration of a communication apparatus according to the embodiment.

  The communication device 100 transmits transmission data to other communication devices together with a transmission check code, and receives reception data from other communication devices together with a reception check code. Hereinafter, CRC will be described as an example of a transmission check code and a reception check code.

  As illustrated in FIG. 1, the communication device 100 includes a storage device 110, a CPU (Central Processing Unit) 120, a generation circuit 130, a transmission circuit 140, a reception circuit 150, and a verification circuit 160. Hereinafter, each part of the communication apparatus 100 will be described in detail.

  The storage device 110 is an example of a storage unit, and includes a memory device such as a ROM (Read Only Memory). The storage device 110 is a multi-port memory, and the storage device 110 stores a first table 111, a second table 112, a third table 113, a fourth table 114, and the like. In the storage device 110, a plurality of groups are set, and the first table 111, the second table 112, the third table 113, and the fourth table 114 hold residue values corresponding to the respective groups.

  FIG. 2 is a schematic diagram for explaining a plurality of groups.

  In the example shown in FIG. 2, the predetermined digits of transmission data and reception data, that is, the number of digits of transmission data and reception data is 32 bits (4 bytes). In this example, the transmission CRC and the reception CRC of 8 bits (1 byte) are calculated by dividing the transmission data and reception data of 32 bits by a divisor value of 9 bits (where the most significant bit is 1). . In communication device 100, the number of digits of transmission data, reception data, divisor value, transmission CRC, and reception CRC is not limited to the above, and may be any number.

  As shown in FIG. 2, a plurality of groups each having a plurality of values in which some of the predetermined digits of transmission data and reception data are effective digits and zeros other than the effective digits are set are set. In the example shown in FIG. 2, the first group having the 0th to 7th bits as significant digits, the second group having the 8th to 15th bits as significant digits, and the 16th to 23rd bits as the significant digits. Four groups are set, the third group and the fourth group having the 24th to 31st bits as significant digits. That is, the first group is composed of 255 values from 00000001 (h) to 000000FF (h). The second group is composed of 255 values from 00000100 (h) to 0000FF00 (h). The third group is composed of 255 values from 00010000 (h) to 00FF0000 (h). The fourth group is composed of 255 values from 01000000 (h) to FF000000 (h). In this way, each group is set so that all of the predetermined digits are valid digits in any group.

  The first table 111 holds a plurality of remainder values obtained by dividing each value included in the first group by a predetermined divisor value, and the digit value of the significant digit corresponding to each value as an index. The digit value means a value when each value is shifted so that the least significant digit in the effective digits becomes the first digit. That is, the digit value is a value in the range of 01 (h) to FF (h). Similarly, the second table 112 holds a plurality of remainder values obtained by dividing each value included in the second group by a predetermined divisor value, and the digit value of the significant digit corresponding to each value as an index. Similarly, the third table 113 holds a plurality of remainder values obtained by dividing each value included in the third group by a predetermined divisor value, and the digit value of the significant digit corresponding to each value as an index. Similarly, the fourth table 114 holds a plurality of remainder values obtained by dividing each value included in the fourth group by a predetermined divisor value, and the digit value of the significant digit corresponding to each value as an index. The predetermined divisor value is different depending on the CRC method. For example, in CRC-8, 9-bit 1D5 (h) is used. Each table further holds a value 0 corresponding to the index 00 (h). That is, each table holds 256 values using 00 (h) to FF (h) as indexes.

  The CPU 120 is connected to the storage device 110, the generation circuit 130, the transmission circuit 140, the reception circuit 150, and the verification circuit 160, and controls each of these units. The CPU 120 controls the operation of the entire communication device 100.

  The CPU 120 outputs transmission data to be transmitted to another communication device to the generation circuit 130 and the transmission circuit 140. In addition, the CPU 120 acquires reception data received from another communication device from the reception circuit 150, and acquires a result of verifying the reception data based on the reception CRC from the verification circuit 160.

  In FIG. 1, the number surrounded by “()” indicates the bit width of the bus indicated by the arrow, and the number surrounded by “[]” indicates the bit number of data transmitted on the bus indicated by the arrow. Show.

  The generation circuit 130 is an example of a generation unit, and includes a division circuit 131 and an addition circuit 132.

  The dividing circuit 131 divides the transmission data output from the CPU 120 into a plurality of groups and outputs the digit values of the significant digits of each group. In the present embodiment, the dividing circuit 131 divides 32-bit transmission data into four groups of the first to fourth groups shown in FIG. The 15th bit digit value, the 16th to 23rd bit digit values, and the 24th to 31st bit digit values are output.

  The generation circuit 130 inputs each digit value of each group output from the division circuit 131 to each table of the storage device 110, and refers to each table of the storage device 110 for each group, and each of the groups included in each group. Gets the remainder value obtained by dividing the value by a predetermined divisor value.

  In the present embodiment, the generation circuit 130 refers to the first table 111, uses the digit values of the 0th to 7th bits as an index, and sets values other than the 0th to 7th bits of transmission data to 0. The remainder value obtained by dividing by the predetermined divisor value is acquired. Similarly, the generation circuit 130 refers to the second table 112 and uses a digit value of the 8th to 15th bits as an index and sets a value in which the bits other than the 8th to 15th bits are set to 0 in the transmission data. Gets the remainder value divided by the divisor value. Similarly, the generation circuit 130 refers to the third table 113 and uses a digit value of the 16th to 23rd bits as an index, and sets a value in which bits other than the 16th to 23rd bits of the transmission data are set to 0. Gets the remainder value divided by the divisor value. Similarly, the generation circuit 130 refers to the fourth table 114 and uses a digit value of the 24th to 31st bits as an index and sets a value in which bits other than the 24th to 31st bits are set to 0 in the transmission data. Gets the remainder value divided by the divisor value.

  The adder circuit 132 modulo-2 adds each residue value acquired with reference to each table, generates the sum of each residue value as a transmission CRC, and outputs the transmission CRC to the transmitter circuit 140. In the present embodiment, the adder circuit 132 generates and outputs an 8-bit transmission check code by modulo-2 addition of each 8-bit residue value.

  The transmission circuit 140 is an example of a transmission unit, and includes a transmission data buffer 141, a transmission CRC buffer 142, and a transmission control circuit 143.

  The transmission data buffer 141 has a memory device such as a RAM (Random Access Memory), and temporarily stores transmission data output from the CPU 120.

  The transmission CRC buffer 142 has a memory device such as a RAM, and temporarily stores the transmission CRC output from the generation circuit 130.

  The transmission control circuit 143 has an interface circuit capable of communicating with other communication devices, and transmits various data and information by being electrically connected to other communication devices or relay devices using cables. The transmission control circuit 143 includes a circuit for performing communication conforming to a standard such as PCI Express. The transmission control circuit 143 may include an interface circuit conforming to a serial bus such as USB (Universal Serial Bus), and may be electrically connected to another communication device using a USB cable. Alternatively, the transmission control circuit 143 may include a circuit conforming to Ethernet (registered trademark) or the like, and may be electrically connected to each communication device using a LAN (Local Area Network) cable.

  The transmission control circuit 143 reads transmission data from the transmission data buffer 141 and reads transmission CRC for the transmission data from the transmission CRC buffer 142. The transmission control circuit 143 arranges the read transmission data and the transmission CRC, performs parallel-serial conversion, and transmits the data to another communication apparatus.

  The reception circuit 150 is an example of a reception unit, and includes a reception control circuit 151, a reception data buffer 152, and a reception CRC buffer 153.

  Similar to the transmission control circuit 143, the reception control circuit 151 has an interface circuit capable of communicating with other communication devices, and is electrically connected to other communication devices or relay devices using cables to transmit various data and Receive information.

  The reception control circuit 151 performs serial-parallel conversion on a signal transmitted from another communication device, and receives reception data and a reception CRC for the reception data. The reception control circuit 151 writes the reception data in the reception data buffer 152 and writes the reception CRC in the reception CRC buffer 153.

  The reception data buffer 152 has a memory device such as a RAM, and temporarily stores the reception data written from the reception control circuit 151.

  The reception CRC buffer 153 has a memory device such as a RAM, and temporarily stores the reception CRC written from the reception control circuit 151.

  The verification circuit 160 is an example of a verification unit, and includes a division circuit 161, an addition circuit 162, and a matching circuit 163.

  The division circuit 161 is a circuit similar to the division circuit 131 of the generation circuit 130, reads the reception data from the reception data buffer 152, divides values based on the reception data into a plurality of groups, and digit values of significant digits of each group Is output. In the present embodiment, the dividing circuit 161 divides the 32-bit received data into four groups of the first to fourth groups shown in FIG. The 15th bit digit value, the 16th to 23rd bit digit values, and the 24th to 31st bit digit values are output.

  The verification circuit 160 inputs each digit value of each group output from the dividing circuit 161 to each table of the storage device 110, and refers to each table of the storage device 110 for each group, and each of the groups included in each group. Gets the remainder value obtained by dividing the value by a predetermined divisor value.

  In the present embodiment, the verification circuit 160 refers to the first table 111, uses the digit values of the 0th to 7th bits as an index, and sets the bits other than the 0th to 7th bits to 0 in the received data. The remainder value obtained by dividing by the predetermined divisor value is acquired. Similarly, the verification circuit 160 refers to the second table 112 and uses a digit value of the 8th to 15th bits as an index and sets a value in which bits other than the 8th to 15th bits of the received data are set to 0. Gets the remainder value divided by the divisor value. Similarly, the verification circuit 160 refers to the third table 113 and uses a digit value of the 16th to 23rd bits as an index, and sets a value in which the bits other than the 16th to 23rd bits of transmission data are set to 0. Gets the remainder value divided by the divisor value. Similarly, the verification circuit 160 refers to the fourth table 114 and uses a digit value of the 24th to 31st bits as an index and sets a value in which the bits other than the 24th to 31st bits are set to 0 in the transmission data. Gets the remainder value divided by the divisor value.

  As described above, the storage device 110 is a multi-port memory, and can be referred to from the generation circuit 130 and the verification circuit 160 at the time of generation of the transmission CRC and verification of the reception CRC. Therefore, since the communication device 100 can share each table when generating and verifying the check code, the size of the table held in the storage device 110 can be reduced.

  The adder circuit 162 is a circuit similar to the adder circuit 132 of the generation circuit 130, modulo 2 addition is performed on each residue value obtained by referring to each table, and the sum of each residue value is calculated and output to the match circuit 163. To do. In the present embodiment, the coincidence circuit 163 calculates and outputs an 8-bit total value by modulo 2 addition of each 8-bit remainder value.

  The matching circuit 163 verifies the received data and the received CRC based on the sum of the remainder values output from the adder circuit 162. The coincidence circuit 163 reads the reception CRC from the reception CRC buffer 153 and compares it with the sum of the remainder values output from the addition circuit 162. The coincidence circuit 163 outputs a value indicating that there is no error in the received data if they match, and a value indicating that there is an error in the received data if they do not match, to the CPU 120 as a verification result.

  The CPU 120 reads the received data from the received data buffer 152 and determines whether or not there is an error in the received data based on the verification result for the received data output from the matching circuit 163.

  In this way, the verification circuit 160 calculates a remainder value from the received data, and verifies the received data and the received CRC depending on whether or not the calculated remainder value matches the received CRC.

  The verification circuit 160 may calculate a remainder value of an addition value obtained by adding the reception CRC to the reception data, and may verify the reception data and the reception CRC depending on whether the calculated remainder value is 0 or not. In that case, the verification circuit 160 further includes an addition circuit that adds the reception data and the reception CRC and outputs the result, and the division circuit 161 divides the addition value of the reception data and the reception CRC into a plurality of groups. The verification circuit 160 refers to each table of the storage device 110 for each group, acquires a remainder value corresponding to each digit value of each group output from the division circuit 161, and the addition circuit 162 Calculate the total value. The coincidence circuit 163 compares the sum of each remainder value with 0, and if it matches, the value indicating that there is no error in the received data, and if not, verifies the value indicating that there is an error in the received data. As a result, it outputs to CPU120. CPU 120 determines whether there is an error in the received data based on the verification result.

  Alternatively, the generation circuit 130 carries the transmission data by the number of CRC digits (8 bits) (that is, shifts left by the number of CRC digits and fills the newly added lower bits with 0), and The transmission CRC may be calculated for the carry data. In that case, the generation circuit 130 divides the carried data into a plurality of groups, acquires a remainder value for each group, and generates a transmission CRC based on the sum of the acquired remainder values. The transmission circuit 140 transmits the data obtained by performing the modulo 2 addition (addition to the lower bit carried by the carry) of the carry data and the transmission CRC to another communication apparatus. On the other hand, the verification circuit 160 of the communication device that has received the data divides the entire received data (that is, the added value of the carry data and the transmission CRC) into a plurality of groups, and acquires a remainder value for each group. Then, the sum of the acquired remainder values is calculated. The coincidence circuit 163 compares the sum of each remainder value with 0, and if it matches, the value indicating that there is no error in the received data, and if not, verifies the value indicating that there is an error in the received data. As a result, it outputs to CPU120. CPU 120 determines whether there is an error in the received data based on the verification result.

  Hereinafter, the reason and the effect that the remainder value of the data can be calculated based on the sum of the remainder values obtained by dividing the data into a plurality of groups and dividing by a divisor value for each of the plurality of groups will be described.

For example, when calculating the 8-bit remainder value obtained by dividing the 32-bit data X = AABBCCDD (h) by the 9-bit divisor n (where the most significant bit is 1), the modulo-two division remainder calculation has a distribution rule. Since this holds, the following equation (1) holds. In equation (1), mod represents an operator for obtaining a remainder by modulo-2 division.
X mod n = AABBCCDD (h) mod n
= (AA000000 (h) + 00BB0000 (h) + 0000CC00 (h) + 000000DD (h)) mod n
= (AA000000 (h) mod n) + (00BB0000 (h) mod n)
+ (0000CC00 (h) mod n) + (000000DD (h) mod n) (1)

  Therefore, the sum of the remainder values obtained by dividing the data into a plurality of groups and dividing the data by the divisor value for each of the plurality of groups is equal to the remainder value obtained by directly dividing the data by the divisor value.

  For example, when an 8-bit remainder value obtained by dividing 32-bit data by a 9-bit divisor is stored in the table in advance, the size of the table is 8 bits × (2 to the power of 32) = about 4 gigabytes. . The communication device that performs CRC generation and verification requires two tables, so the total size of the table is about 8 gigabytes. On the other hand, in the communication apparatus 100 according to the present embodiment, four tables of 8 bits × (2 to the power of 8) = 256 bytes may be stored, so that the total size of the table is 1024 bytes, and the storage of the storage device 110 is performed. The capacity can be greatly reduced.

  When 8-bit data is divided by a 9-bit divisor, the remainder value is the same as the original 8-bit data. Therefore, the remainder value obtained by dividing each value of the first group by the divisor value of 9 bits is the same value as each value of the first group. Therefore, the first table 111 corresponding to the first group may be omitted, and each digit value of the first group output from the dividing circuit 131 or 161 may be directly input to the adding circuit 132 or 162. As a result, the storage capacity of the storage device 110 can be further reduced, and the circuit configuration of the communication device 100 can be simplified.

  Further, the number of transmission ports and reception ports that the communication apparatus 100 has is not limited to one, but may be plural. In that case, the communication apparatus 100 includes the generation circuit 130 and the transmission circuit 140 corresponding to the number of transmission ports, and includes the reception circuit 150 and the verification circuit 160 corresponding to the number of reception ports. On the other hand, the communication device 100 includes only one storage device 110, and the storage device 110 is configured to be accessible simultaneously from all the generation circuits 130 and the verification circuits 160. In that case, each generation circuit 130 and each verification circuit 160 can share each table stored in one storage device 110. Therefore, the communication device 100 can increase the number of transmission ports and reception ports without increasing the size and number of storage devices.

  FIG. 3 is a flowchart illustrating an example of operation of transmission processing by the communication apparatus 100. The operation of the transmission process will be described below with reference to the flowchart shown in FIG. The operation flow described below is mainly executed by the CPU 120 in cooperation with each element of the communication device 100.

  First, the CPU 120 outputs transmission data to the generation circuit 130 and the transmission circuit 140 (step S101). Next, the dividing circuit 131 divides the transmission data into a plurality of groups and outputs the digit values of the significant digits of each group (step S102). Next, the generation circuit 130 inputs each digit value of each group to each table, refers to each table for each group, and calculates a remainder value obtained by dividing each value included in each group by a predetermined divisor value. Obtain (step S103). Next, the adder circuit 132 modulo-2 adds each residue value (step S104), generates the sum of each residue value as a transmission CRC, and outputs it to the transmitter circuit 140 (step S105). Next, the transmission control circuit 143 transmits the transmission data together with the transmission CRC to another communication device (step S106), and ends a series of steps.

  FIG. 4 is a flowchart illustrating an example of operation of reception processing by the communication apparatus 100. The operation of the reception process will be described below with reference to the flowchart shown in FIG. The operation flow described below is mainly executed by the CPU 120 in cooperation with each element of the communication device 100.

  First, the reception control circuit 151 receives received data and a received CRC for the received data from another communication device (step S201). Next, the dividing circuit 161 divides the received data into a plurality of groups, and outputs the digit values of the significant digits of each group (step S202). Next, the verification circuit 160 inputs each digit value of each group to each table, refers to each table for each group, and calculates a remainder value obtained by dividing each value included in each group by a predetermined divisor value. Obtain (step S203). Next, the adder circuit 162 modulo-2 adds each residue value, calculates the sum of each residue value, and outputs it to the match circuit 163 (step S204). Next, the matching circuit 163 verifies the received data and the received CRC by comparing the sum of the remainder values with the received CRC, and outputs the verification result to the CPU 120 (step S205). Next, the CPU 120 reads the received data from the received data buffer 152, determines whether there is an error in the received data based on the verification result (step S206), and ends the series of steps.

  As described above in detail, since the communication device 100 can share data for calculating the remainder value at the time of CRC generation and verification, the amount of data stored in the storage device while processing the CRC at high speed Can be further reduced. As a result, the size and cost of the storage device can be reduced, and the size and cost of the entire communication device can be reduced.

  When a single port memory is used as a storage device, there is only one set of addresses and data that can be accessed at the same time. Therefore, processing delay occurs when CRC generation and verification timing overlap. On the other hand, the communication device 100 can refer to the storage device 110 from different addresses at the same time by using a multi-port memory as the storage device 110. Therefore, the communication apparatus 100 can prevent the processing delay from occurring even when the CRC generation timing and the verification timing overlap.

  5 and 6 are diagrams illustrating a hardware configuration diagram of a communication apparatus according to another embodiment. 5 and 6 show hardware configuration diagrams of the same communication apparatus 200. In FIG. 5, the display of the configuration of the verification circuit 270 is omitted, and in FIG. 6, the display of the configuration of the generation circuit 240 is omitted. ing.

  As shown in FIGS. 5 and 6, the communication device 200 includes a first storage device 210, a second storage device 220, a CPU 230, a generation circuit 240, a transmission circuit 250, a reception circuit 260, and a verification circuit 270. And have. Hereinafter, each part of the communication apparatus 200 will be described in detail. The CPU 230, the generation circuit 240, and the transmission circuit 250 are the same as the CPU 120, the generation circuit 130, and the transmission circuit 140 of the communication apparatus 100 illustrated in FIG.

  The first storage device 210 is an example of a first storage unit, and includes a memory device such as a ROM. The first storage device 210 may be configured by a register. The first storage device 210 is a multiport memory, and holds first data 211, second data 212, third data 213, and fourth data 214. In the first storage device 210, a plurality of groups are set as shown in FIG.

  The first data 211 is a remainder value obtained by dividing the minimum value (00000001 (h)) in the first group by a predetermined divisor value. The second data 212 is a remainder value obtained by dividing the minimum value (00000100 (h)) in the second group by a predetermined divisor value. The third data 213 is a remainder value obtained by dividing the minimum value (00010000 (h)) in the third group by a predetermined divisor value. The fourth data 214 is a remainder value obtained by dividing the minimum value (01000000 (h)) in the fourth group by a predetermined divisor value. As described above, the first storage device 210 holds, for each group, a remainder value obtained by dividing the minimum value in each group by a predetermined value.

  The second storage device 220 is an example of a second storage unit, and includes a memory device such as a ROM. The second storage device 220 is a multi-port memory, and a common table 221 is stored in the second storage device 220.

  The common table 221 holds a plurality of remainder values obtained by dividing a plurality of predetermined values by a predetermined divisor value, and each of the plurality of values is used as an index. The predetermined plural values are values from 0 to the square of the maximum value of the digit value of each group. That is, when 32-bit data is divided into four groups, the predetermined plural values are 65026 values from 0000 (h) to (the square of 00FF (h)).

  The generation circuit 240 is an example of a generation unit, and includes a division circuit 241 and an addition circuit 242. Furthermore, the generation circuit 240 includes a first multiplication circuit 243, a second multiplication circuit 244, a third multiplication circuit 245, and a fourth multiplication circuit 246 for each group.

  The dividing circuit 241 is a circuit similar to the dividing circuit 131 shown in FIG. 1, divides the transmission data output from the CPU 230 into a plurality of groups, and outputs the digit values of significant digits of each group.

  The first to fourth multiplication circuits 243 to 246 refer to the data in the first storage device 210, respectively, and obtain a remainder value obtained by dividing the minimum value in each group by a predetermined divisor value. The first to fourth multiplication circuits 243 to 246 calculate and output a multiplication value by modulo-2 multiplication of the obtained remainder value and each digit value of each group output from the division circuit 241.

  The generation circuit 240 inputs the multiplication values related to each group output from the first to fourth multiplication circuits 243 to 246 to the common table 221 of the second storage device 220, and refers to the common table 221 of the second storage device 220. Then, the remainder value corresponding to each multiplication value is acquired. The generation circuit 240 refers to the common table 221 and obtains a remainder value obtained by dividing each multiplication value by a predetermined divisor value using each multiplication value as an index.

  The adder circuit 242 is a circuit similar to the adder circuit 132 shown in FIG. 1, modulo 2 addition is performed on each residue value obtained with reference to the common table 221, and the sum of each residue value is generated as a transmission CRC. The data is output to the transmission circuit 250.

  The verification circuit 270 is an example of a verification unit, and includes a division circuit 271, an addition circuit 272, and a matching circuit 273. Further, the verification circuit 270 includes a fifth multiplication circuit 274, a sixth multiplication circuit 275, a seventh multiplication circuit 276, and an eighth multiplication circuit 277 for each group.

  The division circuit 271 is a circuit similar to the division circuit 241 of the generation circuit 240, reads the reception data from the reception data buffer 262, divides values based on the reception data into a plurality of groups, and digit values of significant digits of each group Is output.

  The fifth to eighth multiplier circuits 274 to 277 each refer to the data in the first storage device 210 and obtain a remainder value obtained by dividing the minimum value in each group by a predetermined divisor value. The fifth to eighth multiplier circuits 274 to 277 each calculate and output a multiplication value by modulo-2 multiplication of the acquired remainder value and the digit value of each significant digit output from the division circuit 271.

  As described above, the first storage device 210 is a multi-port memory, and can be referred to from the generation circuit 240 and the verification circuit 270 at the time of generation of the transmission CRC and verification of the reception CRC. Therefore, since the communication device 200 can share each data when generating and verifying the check code, it is possible to reduce the size of data stored in the first storage device 210.

  The verification circuit 270 inputs the multiplication values related to the groups output from the fifth to eighth multiplication circuits 274 to 277 to the common table 221 of the second storage device 220, and refers to the common table 221 of the second storage device 220. Then, the remainder value corresponding to each multiplication value is acquired. The verification circuit 270 refers to the common table 221 and obtains a remainder value obtained by dividing each multiplication value by a predetermined divisor value using each multiplication value as an index.

  As described above, the second storage device 220 is a multi-port memory, and can be referred to from the generation circuit 240 and the verification circuit 270 at the time of generation of the transmission CRC and verification of the reception CRC. Further, the second storage device 220 can simultaneously refer to a plurality of groups from the generation circuit 240 and the verification circuit 270. Therefore, since the communication device 200 can share each table when generating and verifying the check code, it is possible to reduce the size of the table held in the second storage device 220.

  The adder circuit 272 is a circuit similar to the adder circuit 242 of the generation circuit 240, and modulo 2 addition is performed on each residue value acquired with reference to the common table 221, and the sum of each residue value is calculated. Output.

  The coincidence circuit 273 is a circuit similar to the coincidence circuit 163 shown in FIG. 1, and verifies the reception data and the reception CRC based on the sum of the remainder values output from the addition circuit 272.

  Hereinafter, the data is divided into a plurality of groups, and the product of the remainder value obtained by dividing the minimum value in each group by the divisor value and the digit value of the significant digit of each group is based on the sum of the remainder values divided by the divisor value. The reason and effect that the remainder value of the data can be calculated will be described.

For example, when calculating the 8-bit remainder value obtained by dividing the 32-bit data X = AABBCCDD (h) by the 9-bit divisor n (where the most significant bit is 1), the modulo-two division remainder calculation has a distribution rule. Since this holds, the following equation (2) holds. In equation (2), mod represents an operator for obtaining a remainder by modulo-2 division.
X mod n = AABBCCDD (h) mod n
= (AA000000 (h) + 00BB0000 (h) + 0000CC00 (h) + 000000DD (h)) mod n
= (AA000000 (h) mod n) + (00BB0000 (h) mod n)
+ (0000CC00 (h) mod n) + (000000DD (h) mod n)
= ((AA (h) * 01000000 (h)) mod n) + ((BB (h) * 00010000 (h)) mod n)
+ ((CC (h) * 00000100 (h)) mod n) + ((DD (h) * 00000001 (h)) mod n) (2)

Here, for data S and T, if the quotient obtained by dividing S and T by the divisor value n is Qs and Qt, and the remainder is Rs and Rt, S = Qs * n + Rs, T = Qt * n + It can be expressed as Qs. The following equation (3) is established for the remainder value obtained by dividing the multiplication value of S and T by the divisor value n. In other words, the remainder value obtained by dividing the multiplication value of S and T by the divisor value n is obtained by dividing the multiplication value of the remainder value obtained by dividing S by the divisor value n and the remainder value obtained by dividing T by the divisor value n by the divisor value n. Is equal to the remainder value.
(S * T) mod n = ((Qs * n + Rs) * (Qt * n + Rt)) mod n
= (((Qs * Qt * n + Qs * Rt + Rs * Qt) * n) + (Rs * Rt)) mod n
= (Rs * Rt) mod n
= ((S mod n) * (T mod n)) mod n (3)

Therefore, equation (2) can be transformed into equation (4) below.
X mod n = (((AA (h) mod n) * (01000000 (h) mod n)) mod n)
+ (((BB (h) mod n) * (00010000 (h) mod n)) mod n)
+ (((CC (h) mod n) * (00000100 (h) mod n)) mod n)
+ (((DD (h) mod n) * (00000001 (h) mod n)) mod n) (4)

Here, since n is a 9-bit divisor value, (AA (h) mod n), ((BB (h) mod n), ((CC (h) mod n), ((DD (h) mod n) is equal to AA (h), BB (h), CC (h), and DD (h), respectively, so equation (4) can be transformed into equation (5) below.
X mod n = ((AA (h) * (01000000 (h) mod n)) mod n)
+ ((BB (h) * (00010000 (h) mod n)) mod n)
+ ((CC (h) * (00000100 (h) mod n)) mod n)
+ ((DD (h) * (00000001 (h) mod n)) mod n) (5)

  Therefore, when the data is divided into multiple groups, the sum of the remainder value obtained by dividing the minimum value in each group by the divisor value and the product of the significant digits of each group divided by the divisor value is the data. Is equal to the remainder obtained by directly dividing by the divisor value.

  As described above, when an 8-bit remainder value obtained by dividing 32-bit data by a 9-bit divisor is stored in the table in advance, the size of the table is 8 bits × (2 to the 32nd power) = about 4 Gigabytes. The communication device that performs CRC generation and verification requires two tables, so the total size of the table is about 8 gigabytes. On the other hand, in the communication device 200 of the present embodiment, the table size is 8 bits × (2 to the 16th power) = about 65 kilobytes, and the storage capacity of the second storage device 220 can be greatly reduced.

  In addition, modulo-2 multiplication is performed by a shift operation and exclusive OR operation and there is no carry, so that the operation result of the upper digit is processed at a higher speed than the modulo-2 division that affects the operation of the lower digit. Therefore, the communication apparatus 200 can generate and verify the CRC at a higher speed than when generating and verifying the CRC by a division operation.

  Note that each modification shown for the communication device 100 can be similarly applied to the communication device 200.

  In particular, in the communication apparatus 200, the first data 211 corresponding to the first group may be omitted, and each digit value of the first group output from the dividing circuit 241 or 271 may be directly used as an index of the common table 221. As a result, the storage capacity of the first storage device 210 can be further reduced, and the circuit configuration of the communication device 200 can be simplified.

  Further, the common table 221 may be divided into a plurality of groups, similarly to the first to fourth tables 111 to 114 of the communication apparatus 100. For example, the common table 221 is divided into a first 'group having the 0th to 7th bits as significant digits and a second' group having the 8th to 15th bits as significant digits.

  In that case, the generation circuit 240 further includes a dividing circuit that divides the multiplication values output from the first to fourth multiplication circuits 243 to 246 into two groups, respectively, and outputs the digit values of the significant digits of each group. The generation circuit 240 inputs each digit value of each group output by each of the division circuits to the first 'group table and the second' group table, and refers to each table for each group. To obtain a remainder value obtained by dividing each value included in the value by a predetermined divisor value. Then, the generation circuit 240 inputs all the acquired remainder values to the addition circuit 242.

  Similarly to the generation circuit 240, the verification circuit 270 divides the multiplication values output from the fifth to eighth multiplication circuits 274 to 277 into two groups, respectively, and outputs a division circuit that outputs the digit value of the significant digit of each group. Also have. The verification circuit 270 inputs each digit value of each group output from each of the division circuits to the table of the first 'group and the table of the second' group, and refers to each table for each group. To obtain a remainder value obtained by dividing each value included in the value by a predetermined divisor value. Then, the verification circuit 270 inputs all the acquired remainder values to the addition circuit 272.

  In this case, since the communication device 200 only needs to store two 256-byte tables, the total size of the tables is 512 bytes, and the storage capacity of the second storage device 220 can be further reduced.

  Further, the table corresponding to the first 'group may be omitted, and each digit value of the first' group output by each newly added division circuit may be directly input to the adding circuit 242 or 272. In this case, the total size of the table is 256 bytes, the storage capacity of the second storage device 220 can be further reduced, and the circuit configuration of the communication device 200 can be simplified.

  FIG. 7 is a flowchart illustrating an example of operation of transmission processing by the communication apparatus 200. The operation of the transmission process will be described below with reference to the flowchart shown in FIG. The operation flow described below is mainly executed by the CPU 230 in cooperation with each element of the communication device 200.

  First, the CPU 230 outputs transmission data to the generation circuit 240 and the transmission circuit 250 (step S301). Next, the dividing circuit 241 divides the transmission data into a plurality of groups, and outputs the digit values of the significant digits of each group (step S302). Next, the first to fourth multiplication circuits 243 to 246 refer to the data in the first storage device 210, respectively, and obtain a remainder value obtained by dividing the minimum value in each group by a predetermined divisor value (step S303). . Next, the first to fourth multiplication circuits 243 to 246 each calculate a multiplication value by modulo-2 multiplication of the obtained remainder value and each digit value of each group output from the division circuit 241 (step S304). ). Next, the generation circuit 240 inputs the multiplication values related to each group to the common table 221, refers to the common table 221, and obtains a remainder value corresponding to each multiplication value (step S 305). Next, the adder circuit 242 adds modulo 2 each residue value (step S306), generates the sum of each residue value as a transmission CRC, and outputs it to the transmitter circuit 250 (step S307). Next, the transmission control circuit 253 transmits the transmission data together with the transmission CRC to another communication device (step S308), and ends a series of steps.

  FIG. 8 is a flowchart illustrating an example of operation of reception processing by the communication apparatus 200. The operation of the reception process will be described below with reference to the flowchart shown in FIG. The operation flow described below is mainly executed by the CPU 230 in cooperation with each element of the communication device 200.

  First, the reception control circuit 261 receives received data and a received CRC for the received data from another communication device (step S401). Next, the dividing circuit 271 divides the received data into a plurality of groups and outputs the digit values of the effective digits of each group (step S402). Next, the fifth to eighth multiplication circuits 274 to 277 refer to the data in the first storage device 210, respectively, and obtain a remainder value obtained by dividing the minimum value in each group by a predetermined divisor value (step S403). . Next, the fifth to eighth multiplication circuits 274 to 277 each calculate a multiplication value by modulo-2 multiplication of the obtained remainder value and the significant digit value of each group (step S404). Next, the verification circuit 270 inputs the multiplication value related to each group to each table, refers to each table for each group, and obtains a remainder value corresponding to each multiplication value (step S405). Next, the adder circuit 272 modulo-2 adds each residue value, calculates the sum of each residue value, and outputs it to the match circuit 273 (step S406). Next, the matching circuit 273 verifies the received data and the received CRC by comparing the sum of the remainder values with the received CRC, and outputs the verification result to the CPU 230 (step S407). Next, the CPU 230 determines whether or not there is an error in the received data based on the verification result (step S408), and ends a series of steps.

  As described above in detail, since the communication device 200 can share data for calculating the remainder value at the time of CRC generation and verification, the amount of data stored in the storage device while processing the CRC at high speed Can be further reduced. As a result, the size and cost of the storage device can be reduced, and the size and cost of the entire communication device can be reduced.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to these embodiments. For example, in the communication device 200, the first storage device 210 is not a multiport memory, and the communication device 200 has a first storage device for the generation circuit 240 and a first storage device for the verification circuit 270 separately. May be.

  An apparatus to which the present invention can be applied is not limited to a communication apparatus, and the present invention can generate a check code such as an information processing apparatus having a hard disk drive or the like and simultaneously writing and reading data. It is also possible to apply to other devices that perform verification at the same time.

100, 200 Communication device 110 Storage device 120, 230 CPU
130, 240 Generation circuit 140, 250 Transmission circuit 150, 260 Reception circuit 160, 270 Verification circuit 210 First storage device 220 Second storage device

Claims (8)

A communication device for communicating transmission data and reception data having a predetermined digit,
A plurality of groups composed of a plurality of values in which a part of the predetermined digits is a valid digit and a digit other than the valid digits is 0 are set, and a plurality of values included in each group are respectively set to a predetermined value. A storage unit for holding a plurality of divided remainder values for each group;
A generation unit that divides transmission data into the plurality of groups, acquires the remainder value with reference to the storage unit for each of the plurality of groups, and generates a transmission check code based on a sum of the obtained remainder values; ,
A transmission unit for transmitting the transmission data together with the transmission check code;
A receiving unit for receiving the received data and a reception check code for the received data;
A value based on the received data is divided into the plurality of groups, the remainder value is obtained for each of the plurality of groups with reference to the storage unit, and the received data and the received data based on a sum of the obtained remainder values A verification unit for verifying the reception check code,
The storage unit can be referred to simultaneously from the generation unit and the verification unit.
A communication device.   The communication device according to claim 1, wherein the storage unit is a multi-port memory. A communication device for communicating transmission data and reception data having a predetermined digit,
A remainder value obtained by setting a plurality of groups composed of a plurality of values in which a part of the predetermined digits is a significant digit and a digit other than the significant digits is 0, and a minimum value in each group is divided by a predetermined value A first storage unit for storing each group,
A second storage unit for holding a plurality of remainder values obtained by dividing a plurality of predetermined values by the predetermined value,
The transmission data is divided into the plurality of groups, the remainder value is obtained for each of the plurality of groups by referring to the first storage unit, and the obtained remainder value is multiplied by the significant digit value of each group. A generation unit that calculates a value, obtains a remainder value corresponding to the multiplication value with reference to the second storage unit, and generates a transmission check code based on a sum of the obtained remainder values;
A transmission unit for transmitting the transmission data together with the transmission check code;
A receiving unit for receiving the received data and a reception check code for the received data;
The value based on the received data is divided into the plurality of groups, and for each of the plurality of groups, the remainder value is obtained by referring to the first storage unit, and the obtained remainder value and the significant digits of each group are obtained. A multiplication value of a digit value is calculated, a remainder value corresponding to the multiplication value is obtained with reference to the second storage unit, and the reception data and the reception check code are verified based on the sum of the obtained remainder values And a verification unit
The second storage unit can simultaneously refer to the plurality of groups from the generation unit and the verification unit.
A communication device.   The communication device according to claim 3, wherein the first storage unit and the second storage unit are multi-port memories.   The communication device according to any one of claims 1 to 4, wherein the group is set such that all of the predetermined digits are valid digits in any group.   The communication device according to any one of claims 1 to 5, wherein the transmission check code and the reception check code are CRCs. A control method of a communication device having a storage unit and communicating transmission data and reception data having a predetermined digit,
A plurality of groups composed of a plurality of values in which a part of the predetermined digits is a valid digit and a digit other than the valid digits is 0 are set, and a plurality of values included in each group are respectively set to a predetermined value. A plurality of divided remainder values are held in the storage unit for each group,
Dividing the transmission data into the plurality of groups, obtaining the remainder value with reference to the storage unit for each of the plurality of groups, generating a transmission check code based on the sum of the obtained remainder values;
Transmitting the transmission data together with the transmission check code;
Receiving the received data and a reception check code for the received data;
A value based on the received data is divided into the plurality of groups, the remainder value is obtained for each of the plurality of groups with reference to the storage unit, and the received data and the received data based on a sum of the obtained remainder values Including verifying the received check code,
The storage unit can be referred to at the same time in the generation and the verification.
A control method characterized by that. A control method for a communication apparatus that includes a first storage unit and a second storage unit and communicates transmission data and reception data having a predetermined digit,
A remainder value obtained by setting a plurality of groups composed of a plurality of values in which a part of the predetermined digits is a significant digit and a digit other than the significant digits is 0, and a minimum value in each group is divided by a predetermined value Is stored in the first storage unit for each group,
Holding a plurality of remainder values obtained by dividing a plurality of predetermined values by the predetermined value in the second storage unit;
The transmission data is divided into the plurality of groups, the remainder value is obtained for each of the plurality of groups by referring to the first storage unit, and the obtained remainder value is multiplied by the significant digit value of each group. Calculating a value, obtaining a remainder value corresponding to the multiplication value with reference to the second storage unit, and generating a transmission check code based on the sum of the obtained remainder values;
Transmitting the transmission data together with the transmission check code;
Receiving the received data and a reception check code for the received data;
The value based on the received data is divided into the plurality of groups, and for each of the plurality of groups, the remainder value is obtained by referring to the first storage unit, and the obtained remainder value and the significant digits of each group are obtained. A multiplication value of a digit value is calculated, a remainder value corresponding to the multiplication value is obtained with reference to the second storage unit, and the reception data and the reception check code are verified based on the sum of the obtained remainder values Including
The second storage unit can simultaneously refer to the plurality of groups in the generation and the verification.
A control method characterized by that.

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