JP2016178425A - Information processing apparatus and delay adjustment method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow for appropriate adjustment of the timing of a clock and data in the data communication, without increasing the design scale.SOLUTION: An information processing apparatus has a PHY section performing the processing of a physical layer in the data communication with an apparatus connected via a network, and a MAC section for transmitting data and clock to the PHY section while delaying the clock with a set delay amount, and performing the processing of a logical layer in the data communication by transmitting and receiving data to and from the PHY section. A CPU makes the MAC section perform transmission of the data and clock by changing the delay amount of the clock, determines whether or not the data communication is performed normally based on the response thereto, and then determines a delay amount which allows for normal data communication from the determination results, and sets the delay amount in the MAC section.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an information processing apparatus and a delay adjustment method.

  An increasing number of information processing apparatuses such as printers, scanners, facsimiles, and multifunction machines have a communication interface such as a LAN (Local Area Network) interface. In addition, as the amount of data handled increases, the maximum communication speed of the communication interface is also required to be increased. In addition, the information processing apparatus is not only required to speed up data communication with other information processing apparatuses, but also needs for downsizing the information processing apparatus itself.

  In order to increase the speed of the communication interface, it is necessary to increase the operating frequency of the devices inside the apparatus. For example, in the interface between the physical layer part (PHY part) of the communication interface and the media access control part (MAC part) which is the upper layer, the LAN speed Gigabit Ethernet (registered trademark) has a clock speed of 125 MHz. Speed up to operating frequency.

  One of the interface standards between the PHY part and the MAC part in Gigabit Ethernet is RGMII (Reduced Gigabit Media Independent Interface). Since RGMII has a smaller number of signal lines between the PHY unit and the MAC unit than GMII (Gigabit Media Independent Interface), it is possible to design a smaller information processing apparatus. However, in RGMII, the time interval for taking in data by a clock is half that of GMII, and it is necessary to adjust the delay of the clock for the data between the PHY part and the MAC part.

  To adjust the clock delay in RGMII, there are known a method of lengthening the physical wiring of the clock and a method of using an internal delay function of the clock built in the device on the receiving side. However, in any of the methods, it is necessary to add a wiring length with a signal wiring called a meander to the physical wiring of the clock and data in designing the board. This hinders downsizing of the information processing apparatus.

  Patent Document 1 below proposes a method of adjusting clock and data timings in a manner that does not require meandering. In this method, data received in the device is temporarily stored in a buffer, the head of data is identified during that time, and a timing adjustment pulse is generated at the timing of the head of the identified data. Further, in the device, a second clock is generated separately from the received first clock, the timing is adjusted between the timing adjustment pulse and the second clock, and the buffered data is transmitted.

International Publication No. 2009/081472

  However, in the technique described in Patent Document 1, it is necessary to newly install a circuit for generating a timing adjustment pulse and a circuit for generating a second clock, which increases the design scale. In addition to the method described above, it is also possible to adjust the clock and data timing by delaying the clock by using a clock delay function built in the device on the transmission side. In this case, it is necessary to consider an actual device variation characteristic with respect to the set delay amount for each device on the transmission side. For example, the actual delay amount may deviate from the delay amount of the clock set in the device on the transmission side by firmware, etc., which may prevent the clock delay amount to be input to the device on the reception side from being satisfied. is there.

  The present invention has been made in view of such circumstances, and an object of the present invention is to enable appropriate adjustment of clock and data timings in data communication without increasing the design scale.

  An information processing apparatus according to the present invention determines the signal level of data received at a received clock, transmits data based on the signal level, and performs physical communication in data communication with a device connected via a network. A physical layer unit that performs layer processing, and delays a clock with respect to an output timing of data by a set delay amount, and transmits the data and the clock to the physical layer unit. A media access control unit that performs transmission and reception and performs logical layer processing in the data communication; and a control unit that controls a delay amount of the clock in the media access control unit, and the control unit includes the delay amount of the clock The data access and the clock are transmitted by the media access control unit by changing the data, and data communication is performed based on a response to the transmission. It determines whether performed normally, and determining the amount of delay that allows the normal data communications from the determination result and sets the media access controller.

  According to the present invention, the delay amount of the clock in the data communication can be appropriately set for each apparatus without using a special circuit, and the timing of the clock and the data in the data communication can be adjusted appropriately without increasing the design scale. It becomes possible.

It is a figure which shows the structural example of the information processing apparatus in embodiment of this invention. It is a figure which shows the example of the connection form of the information processing apparatus in this embodiment. It is a figure which shows the structural example of the MAC part in this embodiment, and a PHY part. It is a figure which shows the example of the process sequence in 1st Embodiment. It is a flowchart which shows the operation example of the information processing apparatus in 1st Embodiment. It is a figure which shows the example of the process sequence in 2nd Embodiment. 10 is a flowchart illustrating an operation example of the information processing apparatus according to the second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
A first embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating a hardware configuration example of an information processing apparatus 100 according to an embodiment of the present invention. The information processing apparatus 100 in this embodiment has a communication interface for performing data communication with other information processing apparatuses and the like. FIG. 1 shows an information processing apparatus 100 having a LAN (Local Area Network) interface as a communication interface as an example.

  The information processing apparatus 100 includes a controller 110, a printer 111, a power supply unit 112, and a panel 114. The controller 110 performs main control of the information processing apparatus 100. The connector 101 is a connector for connecting a modular LAN cable. The transformer 102 is for electrically insulating the information processing apparatus 100 and the network.

  A physical layer unit (PHY unit) 103 performs physical layer processing in data communication. The PHY unit 103 exchanges electrical signals with, for example, a connection destination device to which the information processing apparatus 100 is connected via a LAN interface. The media access control unit (MAC unit) 104 performs logical layer processing in data communication. For example, the MAC unit 104 converts the signal received by the PHY unit 103 into a frame handled by a device in the apparatus. In the present embodiment, the PHY unit and the MAC unit are connected by RGMII (Reduced Gigabit Media Independent Interface), and data is transmitted and received between the PHY unit and the MAC unit.

  TX data TXDT is transmission data transmitted from the MAC unit 104 to the PHY unit 103, and TX clock TXCK is a transmission clock transmitted from the MAC unit 104 to the PHY unit 103. The TX information group TXIF represents a transmission state of transmission data from the MAC unit 104 to the PHY unit 103. The TX information group TXIF can notify the PHY unit 103 of the transmission valid state and transmission error state from the MAC unit 104.

  RX data RXDT is reception data that the MAC unit 104 receives from the PHY unit 103, and RX clock RXCK is a reception clock that the MAC unit 104 receives from the PHY unit 103. RX information group RXIF represents the state of received data that MAC unit 104 receives from PHY unit 103. The RX information group RXIF can notify the MAC unit 104 of the detection state of received data and error information of received data. The management information MNG is used bidirectionally between the PHY unit 103 and the MAC unit 104 to exchange management information.

  When the PHY unit 103 receives the TX clock TXCK, the electrical level of the received TX data TXDT is the timing at which the TX clock TXCK is electrically changed to a high level or a low level. Alternatively, a low level is detected. The signal level (high level or low level) detected here is recognized as data received from the MAC unit 104. However, in the RGMII interface, in order for the PHY unit 103 to normally capture the data transmitted from the MAC unit 104, the TX clock TXCK needs to have a certain amount of delay with respect to the TX data TXDT. If this delay is not the amount of delay in the range determined by the PHY unit 103, the PHY unit 103 cannot detect the electrical high level or low level of the TX data TXDT at the level as transmitted by the MAC unit 104. there is a possibility.

  Further, when the MAC unit 104 receives the RX clock RXCK, the MAC unit 104 sets the electrical high level or low level of the received RX data RXDT at the timing when the RX clock RXCK changes to the electrical high level or low level. Detect. The signal level (high level or low level) detected here is recognized as data received from the PHY unit 103. However, in the RGMII interface, in order for the MAC unit 104 to normally capture the data transmitted by the PHY unit 103, the RX clock RXCK needs to have a certain amount of delay with respect to the RX data RXDT. If this delay is not the amount of delay within the range determined by the MAC unit 104, the MAC unit 104 cannot detect the electrical high level or low level of the RX data RXDT at the level as transmitted by the PHY unit 103. there is a possibility.

  A CPU (Central Processing Unit) 108 executes instructions to devices in the apparatus. A RAM (Random Access Memory) 109 temporarily stores a program executed by the CPU 108. A ROM (Read Only Memory) 116 is a memory that stores setting values and initial data of the information processing apparatus 100. The RTC (Real Time Clock) has a clock function that measures the current time and notifies the CPU 108 of the time as necessary.

  The printer 111 performs printing or image printing in accordance with a command received from the CPU. The panel 114 is for displaying information of the information processing apparatus 100 and inputting a command from the user, and has an LCD (Liquid Crystal Display) 115. The LCD 115 attached to the panel 114 can display commands received by the panel 114 from the CPU 108. The power supply unit 112 supplies power to the inside of the information processing apparatus 100. The power supply unit 112 can be controlled by the CPU 108 and supplies power to the controller 110, the printer 111, the LCD 115, and the like. The power switch 120 is a switch for turning on / off the power supply of the power supply unit 112.

  FIG. 2 is a diagram illustrating an example of a connection form of the information processing apparatus 100 in the present embodiment. Reference numeral 201 denotes a HUB that can be connected to a plurality of LAN lines, and can exchange packets and broadcast packets. The HUB 201 includes a physical layer unit (PHY unit) 204 that is used to connect to other information processing apparatuses and performs physical layer processing in communication, and a media access control unit (MAC unit) 205 that performs logical layer processing in communication. Have multiple sets. The PHY unit 204 and the MAC unit 205 have functions equivalent to the PHY unit 103 and the MAC unit 104, respectively.

  The information processing apparatus 100 is connected to the HUB 201 via a connector 101 via a LAN cable 206 used for communication. Further, a terminal A 202 and a terminal B 203 that perform a print request to the information processing apparatus 100 are connected to a set of the PHY unit 204 and the MAC unit 205 of the HUB 201. Therefore, the information processing apparatus 100 can communicate with the terminal A 202 and the terminal B 203 via the HUB 201. The HUB 201 is connected to a network 211 such as an external Internet.

  The switch LSI 207 has a function of transferring a packet received via the MAC unit 205 in a predetermined direction. The CPU 208 executes instructions to the devices in the HUB 201. The RAM 210 temporarily stores a program executed by the CPU 207. The ROM 209 is a memory that stores setting values and initial data of the HUB 201. The CPU 208 executes commands such as setting changes to the PHY unit 204 and the switch LSI 207.

Next, an operation related to the delay amount setting of the TX clock TXCK of the information processing apparatus 100 in the present embodiment will be described.
FIG. 3 is a diagram illustrating an internal configuration example of the MAC unit 104 and the PHY unit 103 in the present embodiment. The MAC unit 104 includes a TX transmission unit 301 and an RX reception unit 306. The PHY unit 103 includes a TX reception unit 303 and an RX transmission unit 305.

  The TX transmission unit 301 generates a TX clock TXCK and TX data TXDT to be transmitted to the PHY unit 103. The TX delay unit 302 of the TX transmission unit 301 gives an arbitrary delay with respect to the output timing of the TX data TXDT with respect to the TX clock TXCK. The amount of delay that can be set by the TX delay unit 302 can be set by the MAC unit 104 in accordance with an instruction from the CPU 108. The RX receiving unit 306 receives the RX clock RXCK and the RX data RXDT from the PHY unit 103. The RX determination unit 307 included in the RX reception unit 306 determines whether the signal level of the RX data RXDT is high or low based on the RX clock RXCK transmitted by the RX transmission unit 306 of the PHY unit 103. To do.

  The TX reception unit 303 receives the TX clock TXCK and the TX data TXDT from the MAC unit 104. The TX determination unit 304 included in the TX reception unit 303 determines whether the signal level of the TX data TXDT is high or low based on the TX clock TXCK received by the TX reception unit 303. The TX reception unit 303 transmits a signal based on the high level or the low level determined by the TX determination unit 304 to the external interface of the PHY unit 103 as transmission data MDITX. The transmission data MDITX is normally transmitted to an external device via the LAN cable 206 shown in FIG. 2 and is transmitted to the terminal A 202 and the terminal B 203 via the HUB 201. When the HUB 201 is not used, the LAN cable 206 can be directly transmitted to the terminal A 202, the terminal B 203, or the like by directly connecting the LAN cable 206 to the information processing apparatus 100.

  The RX transmission unit 305 transmits the RX clock RXCK and the RX data RXDT to the MAC unit 104. The RX transmission unit 305 receives reception data MDIRX from the external interface of the PHY unit 103. The reception data MDIRX is normally transmitted from an external device such as the terminal A 202 or the terminal B 203 and received via the HUB 201 by the LAN cable 206 shown in FIG. When the HUB 201 is not used, the LAN cable 206 can be directly received from the terminal A 202 or the terminal B 203 by directly connecting the LAN cable 206 to the information processing apparatus 100.

  Further, the PHY unit 103 includes a loop path 308 that can transmit the signal level (high level or low level) of the TX data TXDT determined by the TX determination unit 304 of the TX reception unit 303 to the RX transmission unit 305. That is, the PHY unit 103 has a loopback function, and by using the loop path 308, the TX data TXDT high level or low level received from the TX determination unit 304 can be transmitted as the RX data RXDT. It is. Whether to transmit the high level or low level of the TX data TXDT determined by the TX determination unit 304 using the loop path 308 to the RX transmission unit 305 can be arbitrarily set by the CPU 108. Further, when using the loop path 308, the CPU 108 can transmit arbitrary data as TX data TXDT at an arbitrary timing.

  Further, when the loop path 308 of the PHY unit 103 is used, when the data transmitted as the TX data TXDT is received as the RX data RXDT by the RX receiving unit 306, the high level or the low level determined by the RX determining unit 307 is set. The CPU 108 can confirm. That is, when using the loop path 308, the CPU 108 can confirm whether or not the data transmitted by its own instruction is correctly detected by the TX determination unit 304 based on the received data. Further, the CPU 108 can set an arbitrary delay with respect to the MAC unit 104 by the TX delay unit 302 with its own instruction.

  By using the above functions, the CPU 108 sets an arbitrary delay amount in the TX delay unit 302 in the MAC unit 104, and whether the transmitted data can be normally received by the PHY unit 103 with the delay amount. It is possible to determine whether or not. Therefore, it is possible to obtain the delay of the TX clock TXCK within a range in which the normal communication of the data can be obtained by confirming the normal communication of the data with each delay amount with respect to the various delays set by the CPU 108 in the TX delay unit 302. Thus, an appropriate delay amount can be set. For example, by setting the center value of the range of the delay amount in which the obtained data can be normally communicated to the TX delay unit 302, the delay amount of the TX clock TXCK with respect to the TX data TXDT is the most in the range that the PHY unit 103 can receive It is possible to set an optimum value with a margin.

  FIG. 4 is a diagram illustrating an example of a sequence indicating exchanges between the CPU 108, the MAC unit 104, and the PHY unit 103 in the first embodiment. In step S <b> 401, the CPU 108 instructs the MAC unit 104 to use the loop path 308 in order to set the use of the loop path 308 to the PHY unit 103 via the MAC unit 104. In step S <b> 402, the MAC unit 104 receives a command from the CPU 108 and issues a use instruction for the loop path 308 to the PHY unit 103. When the PHY unit 103 receives a use instruction for the loop path 308, the PHY unit 103 starts using the loop path 308. In step S <b> 403, the CPU 108 sets an arbitrary delay amount for the TX delay unit 302 for the MAC unit 104.

  In step S404, the CPU 108 instructs the MAC unit 104 to transmit data to the network. In step S 405, the MAC unit 104 receives data from the CPU 108 and transmits data to the PHY unit 103. In step S 406, the PHY unit 103 detects the high level or low level of the data received from the MAC unit 104, and then returns the detected high level or low level of the data to the MAC unit 104 via the loop path 308. In step S407, the MAC unit 104 detects the data returned from the PHY unit 103 in step S406, and notifies the CPU 108 of the detection result. The CPU 108 determines whether or not the delay amount set for the TX delay unit 302 in step S403 is acceptable for data communication based on the detection result.

  The CPU 108 can confirm the range of the delay amount of the TX clock TXCK that can communicate data by repeating the above series of processing for the delay amount that can be set for the TX delay unit 302.

  FIG. 5 is a flowchart illustrating an operation example related to the delay amount setting of the TX clock TXCK of the information processing apparatus 100 according to the first embodiment. First, in step S501, the information processing apparatus 100 is turned on (powered on). In step S <b> 502, the PHY unit 103 sets a loopback path for data using the loop path 308 in order to return the data received from the MAC unit 104 to the MAC unit 104.

  In step S503, the MAC unit 104 sets a delay amount of the TX clock TXCK to the TX delay unit 302 in accordance with an instruction from the CPU. In step S <b> 504, the MAC unit 104 transmits arbitrary data to the PHY unit 103 in accordance with a command from the CPU 108. In step S505, the MAC unit 104 receives the data transmitted to the PHY unit 103 in step S504 as the data returned from the PHY unit 103.

  Subsequently, in step S506, the CPU 108 determines whether the data received in step S505 matches the data transmitted to the PHY unit 103 in step S504, that is, whether the data is normally transmitted. . In step S507, the CPU 108 causes the RAM 109 to hold the relationship between the determination result of whether or not the data transmission in step S506 is normal and the delay amount set in the TX delay unit 302 in step S503.

  If there is a delay amount that has not yet been set for the TX delay unit 302 in step S508 (Yes in step S508), the process returns to step S503 to set a delay amount that has not been set. Perform the action. On the other hand, if there is no delay amount that has not been set for the TX delay unit 302 (No in step S508), the process proceeds to step S509.

  In step S509, the CPU 108 calculates an appropriate delay amount from the relationship between the delay amount held in step S507 and whether the data transmission is normal. For example, it is possible to obtain the delay amount with the most margin by calculating the delay amount corresponding to the center from the range of delay amounts in which the data is normally communicated. In step S510, the MAC unit 104 sets the delay amount calculated in step S509 in the TX delay unit 302 in accordance with the instruction from the CPU 108, and ends the operation related to the delay amount setting of the TX clock TXCK.

  In the present embodiment, an example in which only the TX delay unit 302 in the MAC unit 104 performs the delay adjustment has been described. In addition to this, the delay adjustment function of the PHY unit 103 is used, and the delay that can be performed by the PHY unit 103 is set to the TX clock TXCK. May be given.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. In the second embodiment, an appropriate delay amount of the TX clock TXCK is determined without using the loop path 308 in FIG. The configuration of the information processing apparatus 100 in the second embodiment is the same as that of the information processing apparatus 100 in the first embodiment. In the present embodiment, since the loop path 308 is not used, the PHY unit 103 does not need to have the loop path 308.

  In an environment where the information processing apparatus 100 can communicate with an external device using the transmission data MDITX and the reception data MDIRX, the normal communication of data is confirmed by a packet for confirming a response between terminals called Ping for confirming communication. can do. Therefore, the information processing apparatus 100 confirms the Ping response to the terminal A 202 or the terminal B 203 in a state where an arbitrary delay amount of the TX clock TXCK is set for the TX delay unit 302, thereby causing the TX delay unit 302 to You can check whether the set delay amount is appropriate.

  Below, the case where the communication confirmation by Ping between the information processing apparatus 100 and terminal A202 is used is demonstrated to an example. FIG. 6 is a diagram illustrating an example of a sequence indicating exchanges between the CPU 108, the MAC unit 104, the PHY unit 103, and the terminal A 202 in the second embodiment. In step S <b> 601, the CPU 108 sets an arbitrary delay amount for the TX delay unit 302 for the MAC unit 104.

  In step S <b> 602, the CPU 108 issues a Ping transmission command to the MAC unit 104 in order to transmit a Ping packet to the terminal A 202 via the MAC unit 104 and the PHY unit 103. In step S <b> 603, the MAC unit 104 transmits data for sending a Ping to the terminal A 202 to the PHY unit 103 in response to a command from the CPU 108. In step S604, the PHY unit 103 transmits data for sending the Ping received from the MAC unit 104 to the terminal A202.

  In step S605, when the terminal A202 can normally recognize the received Ping, the terminal A202 transmits data of the Ping response to the PHY unit 103 in order to return a response to the CPU. In step S606, the PHY unit 103 transmits the Ping response from the terminal A 202 transmitted in step S605 to the MAC unit 104. In step S607, the MAC unit 104 transmits the Ping response from the PHY unit 103 transmitted in step S606 to the CPU.

  Here, if the delay amount set in the TX delay unit 302 is an amount by which the TX determination unit 304 can correctly detect the signal level (high level or low level), the Ping packet transmitted by the CPU 108 is normally It is transmitted to terminal A202. In that case, the CPU 108 can confirm by receiving a Ping response from the terminal A 202 corresponding to the transmitted Ping packet. On the other hand, if the delay amount set in the TX delay unit 302 is an amount in which the signal level (high level or low level) cannot be correctly detected by the TX determination unit 304, the Ping response corresponding to the transmitted Ping packet is the CPU 108. Not responded to.

  Therefore, by confirming the delay amount of the TX clock TXCK set in the TX delay unit 302 and the reception of the Ping response from the terminal A 202, the CPU 108 has an appropriate delay amount of the TX clock TXCK set in the TX delay unit 302. It is possible to confirm whether or not. An appropriate delay amount can be determined by checking the Ping response corresponding to the transmitted Ping packet as described above while changing the delay amount set in the TX delay unit 302.

  FIG. 7 is a flowchart illustrating an operation example related to the delay amount setting of the TX clock TXCK of the information processing apparatus 100 according to the second embodiment. First, in step S701, the information processing apparatus 100 is turned on (powered on). In step S702, the MAC unit 104 sets a delay amount of the TX clock TXCK to the TX delay unit 302 in accordance with an instruction from the CPU.

  Next, in step S <b> 703, the MAC unit 104 transmits a Ping transmission to the terminal A 202 via the PHY unit 103 in accordance with a command from the CPU 108. In step S704, the CPU 108 determines whether or not a Ping response from the terminal A 202 has been received. In step S705, the CPU 108 stores the relationship between the determination result of whether or not the Ping response is received in step S704 and the delay amount set in the TX delay unit 302 in step S702 in the RAM 109.

  If there is a delay amount that has not yet been set for the TX delay unit 302 in step S706 (Yes in step S706), the process returns to step S702, the delay amount that has not been set is set, and the operations after step S702 are performed. Do. On the other hand, if there is no delay amount that has not yet been set for the TX delay unit 302 (No in step S706), the process proceeds to step S707.

  In step S707, the CPU 108 calculates an appropriate delay amount from the relationship between the delay amount held in step S705 and whether a Ping response has been received. For example, it is possible to obtain the delay amount with the most margin by calculating the delay amount corresponding to the center from the range of the delay amount in which the Ping response has occurred. In step S708, the MAC unit 104 sets the delay amount calculated in step S707 in the TX delay unit 302 in accordance with the instruction from the CPU 108, and ends the operation related to the delay amount setting of the TX clock TXCK.

  As a method for implementing this embodiment, the information processing apparatus 100 may be set to perform a series of flows with a simple operation by providing a maintenance mode such as a service mode. In this embodiment, the delay adjustment is performed only for the TX delay unit 302 in the MAC unit 104. In addition to this, the delay adjustment function of the PHY unit 103 is used, and the delay possible in the PHY unit 103 is set to the TX clock. You may give to TXCK.

(Other embodiments of the present invention)
The present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus read and execute the program This process can be realized. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 100: Information processing apparatus 103: Physical layer part (PHY part) 104: Media access control part (MAC part) 108: CPU 109: RAM 110: Controller 116: ROM 301: TX transmission part 302: TX delay part 303: TX reception Unit 304: TX determination unit 305: RX transmission unit 306: RX processing unit 307: RX determination unit TXDT: TX data TXCK: TX clock RXDT: RX data RXCK: RX clock

Claims (7)

A physical layer unit that determines a signal level of data received by the received clock, transmits data based on the signal level, and performs processing of a physical layer in data communication with a device connected via a network; ,
The clock is delayed with respect to the data output timing by a set delay amount, and the data and the clock are transmitted to the physical layer unit. A media access control unit for performing
A control unit for controlling a delay amount of the clock in the media access control unit,
The control unit causes the media access control unit to transmit the data and the clock by changing the delay amount of the clock, and determines whether data communication has been normally performed based on a response to the transmission. An information processing apparatus characterized by determining the delay amount capable of normal data communication from the determination result and setting the delay amount in the media access control unit.   The information processing apparatus according to claim 1, wherein the control unit sets, in the media access control unit, a center value in a delay amount range in which data communication can be normally performed based on the determination result. The physical layer unit has a loopback function of determining a signal level of data received from the media access control unit and transmitting data based on the signal level to the media access control unit;
The data is transmitted from the media access control unit to the physical layer unit by changing the delay amount of the clock, and the physical layer unit corresponding to the data transmitted to the physical layer unit and the data folded by the loopback function The information processing apparatus according to claim 1, wherein it is determined whether or not data communication is normally performed by determining whether or not the data received from the data matches.   Based on a response corresponding to the communication confirmation data, by changing the delay amount of the clock and transmitting the communication confirmation data from the media access control unit to the device connected via the network. 3. The information processing apparatus according to claim 1, wherein it is determined whether or not data communication has been normally performed.   The information processing apparatus according to claim 1, wherein the physical layer unit and the media access control unit are connected by an RGMII interface. A physical layer unit that determines a signal level of data received by the received clock, transmits data based on the signal level, and performs processing of a physical layer in data communication with a device connected via a network; The data and the clock are transmitted to the physical layer unit by delaying the clock with respect to the data output timing by a set delay amount, and the logical layer in the data communication is transmitted and received with the physical layer unit. A delay adjustment method in an information processing apparatus having a media access control unit that performs processing,
Whether or not the data access and the clock are transmitted by the media access control unit by changing the delay amount of the clock in the media access control unit, and whether or not the data communication is normally performed based on a response to the transmission A determining step;
Determining a delay amount that allows normal data communication from the determination result, and setting the delay amount in the media access control unit. A physical layer unit that determines a signal level of data received by the received clock, transmits data based on the signal level, and performs processing of a physical layer in data communication with a device connected via a network; The data and the clock are transmitted to the physical layer unit by delaying the clock with respect to the data output timing by a set delay amount, and the logical layer in the data communication is transmitted and received with the physical layer unit. A program for causing a computer to execute a delay adjustment method in an information processing apparatus having a media access control unit that performs processing,
Whether or not the data access and the clock are transmitted by the media access control unit by changing the delay amount of the clock in the media access control unit, and whether or not the data communication is normally performed based on a response to the transmission A determining step;
A program for causing a computer to execute the step of determining the delay amount capable of normal data communication from the determination result and setting the delay amount in the media access control unit.

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