JP2016171487A - Drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a drive circuit which can perform pulse drive or on/off drive accurately and stably at a high slew rate, using a simple circuit configuration.SOLUTION: As main components, a drive circuit 10 includes an error amplifier 20, an amplification transistor 22, an output transistor 24, a phase compensation capacitor 26, a first and a second switch 28, 30 and a passive element circuit 32. The error amplifier 20, the amplification transistor 22 and the output transistor 24 constitute a constant current circuit 38 together with a reference voltage source 34 and a monitor resistor 36. The passive element circuit 32 and the second switch 30 are provided to improve a rise-up speed of a drive current DI of the drive circuit 10 or the slew rate, without influencing phase compensation by the phase compensation capacitor 26.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a drive circuit that drives a load in response to a binary signal, and more particularly to a drive circuit having a phase compensation capacitor.

  The drive circuit is an interface circuit that is interposed between a load and a signal generation circuit that generates a signal with a relatively small power, such as a controller, a signal processing circuit, or a logic circuit. To the load. Generally, a driving circuit has one or a plurality of active elements or transistors, and the higher the accuracy, speed, and stability required for driving output, the more transistors are used. .

  Conventionally, operational amplifiers have been used in drive circuits for various purposes. The operational amplifier is internally divided into multiple stages (typically a differential amplification stage, an intermediate amplification stage, and an output stage). Each stage is provided with one or more transistors, and negative feedback is provided for stable operation. Add a loop. The operational amplifier having such a configuration is easy to obtain a large gain and desired input / output characteristics, but easily oscillates undesirably at a high frequency. In order to prevent this oscillation, the gain of negative feedback needs to be 1 or less at a phase delay of 180 °, and as a means for that purpose, a phase compensation capacitor capable of adjusting the phase delay is used. Usually, the built-in phase compensation capacitor is provided by bypassing the intermediate amplification stage.

JP 2000-91857 A JP 2000-349570 A

  For example, driving circuits that handle high-frequency pulses or binary signals, such as PWM (Pulse Width Modulation) driving, have an important factor in the output rising speed, the so-called slew rate, in addition to the operating frequency range (dynamic range). If the rate is not sufficiently high, the response speed of the output pulse to the input pulse is insufficient, and the waveform of the output pulse is distorted. In this regard, in a drive circuit incorporating a capacitor for phase compensation, the slew rate is inversely proportional to the capacitance of the capacitor, and the slew rate increases as the capacitance value decreases, but the effectiveness of phase compensation decreases. Therefore, oscillation and ringing tend to occur, and the slew rate and stability are in a trade-off relationship.

  In the prior art, for example, the drive circuit of Patent Document 1 (FIG. 1) includes current supply means for supplying a current to the phase compensation capacitor when the differential voltage of the differential input exceeds a predetermined threshold. The current supply means includes a switching circuit that is turned on when the differential voltage of the differential input exceeds a threshold value, and a current supply circuit that supplies a current to the phase compensation capacitor when the switching circuit is turned on.

  In addition, the driving circuit of Patent Document 2 (FIG. 4) is connected between an input terminal and an output terminal, and a signal amplifying circuit that can control the driving capability of the current supplied to the load from the outside, and the voltage of the output terminal. A level shift circuit that applies and outputs a predetermined voltage, a potential difference detection circuit that detects a potential difference between the input voltage of the signal amplifier circuit and the output voltage of the level shift circuit, and a rise based on the potential difference detected by the potential difference detection circuit And a control circuit that controls the drive capability of the output stage of the signal amplifier circuit by outputting a control signal that shortens the response time at the time of falling or falling.

  Prior art drive circuits, including the drive circuits of Patent Documents 1 and 2, have a complicated circuit configuration for improving the slew rate, and perform high-speed and fine pulse drive or on / off drive like PWM drive. It is difficult to perform accurately and stably.

  The present invention solves the problems of the prior art, and provides a drive circuit that can perform pulse drive or on / off drive accurately and stably at a high slew rate with a simple circuit configuration.

  The driving circuit according to the first aspect of the present invention inputs a binary signal from the outside, and supplies a predetermined driving voltage or driving current to the load when the logical value of the binary signal is the first logical value. When the logic value of the binary signal is a second logic value, the driving circuit cuts off the supply of the driving voltage or driving current to the load, and has first and second input terminals. And an error amplifier for generating an output voltage corresponding to a difference between the first and second input voltages respectively input to the first and second input terminals, and a first amplifier for amplifying the output voltage of the error amplifier. One transistor, a capacitor connected between a control terminal and an output terminal of the first transistor for phase compensation, and a first node connected to the load via an output circuit or directly , Output terminal of the first transistor A passive element circuit including at least one linear element or nonlinear element connected between the first node and the supply of the output voltage or output current to the first node and the load; It is connected between a reference potential terminal for providing a reference potential, and is turned on when the logical value of the binary signal is the second logical value, and the logical value of the binary signal is the first logical value. A first switch that is turned off when the value is a value, and is connected in parallel with the passive element circuit, and is turned off when the logic value of the binary signal is the second logic value; And a second switch that is turned on when the logic value of the value signal is the first logic value.

  The driving circuit according to the second aspect of the present invention receives an external binary signal, and supplies a constant driving current to a load when the logical value of the binary signal is the first logical value. When the logical value of the binary signal is the second logical value, the driving circuit cuts off the supply of the driving current to the load, and a voltage proportional to the predetermined reference voltage and the current value of the driving current is obtained. And an error amplifier that generates an output voltage corresponding to a difference between the reference voltage and the feedback signal voltage, and a source grounded amplifier circuit, and a control terminal is connected to the output terminal of the error amplifier. A first MOSFET to be connected; a capacitor connected between the control terminal and the output terminal of the first MOSFET for phase compensation; and a second conductivity type second capacitor having an output terminal connected to the load. 2 MOSFETs and A passive element circuit including at least one linear element or non-linear element connected between an output terminal of the first MOSFET and a control terminal of the second MOSFET; a control terminal of the second MOSFET; 2 is connected to a reference potential terminal for providing a predetermined reference potential for turning off the MOSFET, and is turned on when the logical value of the binary signal is the second logical value. A first switch that is turned off when the logic value of the signal is the first logic value and the passive element circuit are connected in parallel, and the logic value of the binary signal is the second logic value. A second switch that is turned off at a certain time and turned on when a logic value of the binary signal is the first logic value.

  In the driving circuit of the present invention, the first transistor for amplification (first MOSFET) and the first switch in the on state are turned on during the period when the logical value of the binary signal is the second logical value. A constant current is passed through the linear element or the non-linear element of the passive element circuit, and the phase compensation capacitor is charged to a sufficiently high voltage by using a voltage drop generated in the passive element circuit. When the logic value of the binary signal changes from the second logic value to the first logic value, the charging voltage of the phase compensation capacitor is changed to the second transistor for output (second transistor) via the second switch in the ON state. The output current or output voltage is raised at high speed.

  In the drive circuit according to the second aspect, the passive element circuit preferably includes a diode-connected second conductivity type fourth MOSFET.

  According to the drive circuit of the present invention, pulse drive or on / off drive can be accurately and stably performed at a high slew rate with a simple circuit configuration by the configuration and operation as described above.

It is a block diagram which shows the typical usage pattern of the drive circuit in this invention. It is a circuit diagram which shows the structure of the drive circuit in one Embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of an error amplifier included in the drive circuit according to the embodiment. It is a wave form diagram which shows the waveform of each part in the drive circuit of embodiment. It is a circuit diagram which shows the structure of the drive circuit of a comparative example. It is a wave form diagram which shows the waveform of each part in the drive circuit of a comparative example. It is a circuit diagram which shows the structure of the drive circuit in one modification. It is a circuit diagram which shows the structure of the drive circuit in another modification.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
[Usage of Drive Circuit in the Present Invention]

  As shown in FIG. 1, the drive circuit 10 in the present invention is typically used by being interposed between a binary signal generation circuit 12 and a load 14. The binary signal generation circuit 12 generates an arbitrary binary signal CS such as a PWM signal, an on / off signal, a digital signal, or the like with a predetermined power (usually relatively small power). The drive circuit 10 receives the binary signal CS from the binary signal generation circuit 12, and supplies a binary level or pulse output corresponding to the binary signal CS to the load 14 with required power.

  Here, there are two types of driving modes for the load 14 of the driving circuit 10, a constant voltage driving type and a constant current driving type. In the case of the constant voltage drive type, the drive voltage DV having a constant voltage level is supplied from the drive circuit 10 to the load 14 during the period in which the binary signal CS is at the H level, and the binary signal CS is set to the L level. During this period, the supply of the driving voltage DV is cut off. In the case of the constant current drive type, the drive current DI having a constant current value is supplied from the drive circuit 10 to the load 14 during the period in which the binary signal CS is at the H level, and the binary signal CS is at the L level. During this period, the supply of the drive current DI is cut off. A relationship (inversion relationship) that reverses the binary logic of the binary signal CS and the binary logic of the drive outputs (DV, DI) is also possible.

  In the constant current drive type, as shown in FIG. 1A, the drive current DI is supplied from the drive circuit 10 to the load 14 (source type), and from the power source through the load 14 as shown in FIG. There is a method (sink type) that draws the drive current DI into the drive circuit 10 side. For example, when an LED (light emitting diode) or a motor is driven by a PWM method, a pull-in (sink) constant current drive type is often used.

The drive circuit 10 in the present invention is preferably constructed as an integrated circuit and may be completely independent of the binary signal generation circuit 12 or may be integrated with the binary signal generation circuit 12 on a common semiconductor chip. May be.

[Configuration of Drive Circuit in Embodiment]

FIG. 2 shows a circuit configuration of the drive circuit 10 according to an embodiment of the present invention. The drive circuit 10 is configured as a CMOS drive circuit used for pull-in (sink type) constant current drive. The drive circuit 10 includes an error amplifier 20, an amplification transistor 22, an output transistor 24, a phase compensation capacitor 26, first and second switches 28 and 30 and a passive element circuit 32 as main components. Yes. The binary signal such as the PWM signal CS is input to the input terminal 10 (IN) of the drive circuit 10 from the binary signal generation circuit 12 (FIG. 1). The output terminal 10 (OUT) of the drive circuit 10 is connected via a load 14 to a power supply terminal that provides a positive drive power supply voltage V _CC .

  The error amplifier 20, the amplification transistor 22 and the output transistor 24 constitute a constant current circuit 38 together with the reference voltage source 34 and the monitor resistor 36.

More specifically, the output transistor 24 is composed of an N-type MOSFET, and its drain terminal (output terminal) is connected to the load 14 via the output terminal 10 (OUT) of the drive circuit 10 and its source terminal is a current. A negative-polarity power supply voltage terminal, that is, a ground potential power supply terminal is connected via a detection monitor resistor 36. Node N _M between the source terminal and the monitor resistor 36 of the output transistor 24 is connected to the positive input terminal of the error amplifier 20 (+).

_Assuming that the resistance value of the monitor resistor 36 is R ₃₆ , when the drive current DI of the current value I _DI flows through the load 14, the monitor voltage V _M represented by V _M = R ₃₆ * I _DI is the node N _M Is obtained. This monitor voltage V _M is input to the positive input terminal (+) of the error amplifier 20. A reference voltage V _S having a predetermined voltage level set in advance from the reference voltage source 34 is input to the negative input terminal (−) of the error amplifier 20.

The error amplifier 20 includes a differential amplifier circuit having a known configuration as shown in FIG. 3, for example. In this differential amplifier circuit, a constant current source 54 is connected in common between the source terminal of each of a pair of N-type MOSFETs 50 and 52 having substantially the same characteristics and the power supply terminal of the ground potential, and the N-type MOSFET 50, A current mirror circuit including a pair of P-type MOSFETs 56 and 58 is connected between each drain terminal 52 and a power supply terminal for applying a positive power supply voltage _Vdd . The gate terminals (control terminals) of the N-type MOSFETs 50 and 52 of the differential pair are connected to the positive input terminal (+) and the negative input terminal (−), respectively. The output terminal 20 (OUT) is connected to a node N _C between the drain terminal of the P-type MOSFET 56 and the drain terminal of the N-type MOSFET 50. With this configuration, an output voltage or an error voltage V _ER corresponding to the difference between both input voltages V _M and V _S (V _M −V _S ) is obtained at the output terminal 20 (OUT) of the error amplifier 20.

In FIG. 2 again, the amplification transistor 22 is composed of a P-type MOSFET, and constitutes a common source amplifier circuit together with the current source 40. More specifically, the gate terminal (control terminal) of the amplifying transistor 22 is connected to the output terminal of the error amplifier 20, the source terminal is connected to the power supply voltage terminal that supplies the positive power supply voltage _Vdd , and the drain terminal (output terminal). ) Is connected to the power supply terminal of the ground potential via the current source 40. Node N _B between the output terminal and the current source 40 of the amplifying transistor 22 is connected to the control terminal of the output transistor 24.

The phase compensation capacitor 26 is connected between the control terminal of the amplification transistor 22 and the output terminal or the node N _A. The capacitance (phase compensation capacitance) C _C of the phase compensation capacitor 26 is set to an optimum value that provides a phase margin that can reliably prevent the occurrence of oscillation or ringing while ensuring the widest possible dynamic range. May be selected.

The first switch 28 is used to intermittently operate the constant current circuit 38 in accordance with the duty ratio of the PWM signal CS. As will be described later, the first switch 28 is turned off when the PWM signal CS is at the H level, switches the constant current circuit 38 to the enable (operation) state, and is turned on when the PWM signal CS is at the L level. Then, the constant current circuit 38 is switched to a disabled (stopped) state. This switch 28 is made of an N-type MOSFET, and its gate terminal (control terminal) is connected to the input terminal 10 (IN) of this drive circuit 10 via an inverter 42, and its source terminal is connected to the power supply terminal of the ground potential. is, the drain terminal is connected to the control terminal of the output transistor 24 through the node N _B.

The passive element circuit 32 and the second switch 30 are provided to improve the rising speed or slew rate of the drive current DI in the drive circuit 10 without affecting the phase compensation by the phase compensation capacitor 26. . As an example of the configuration, the passive element circuit 32 includes one resistor (linear element) 44 connected between the nodes N _A and N _B. The second switch 30 is also connected between the nodes N _A and N _{B in} parallel with the passive element circuit 32. The second switch 30 is an N-type MOSFET, the drain terminal is connected to the node N _A, a source terminal connected to the node N _B, a gate terminal (control terminal) of the input terminal 10 (IN of the driving circuit 10 )It is connected to the. As will be described later, when the PWM signal CS is at the L level, the second switch 30 is turned off so that a current flows through the passive element circuit 32 between the nodes N _A and N _B. When it is at the H level, it is turned on to short-circuit between the nodes N _A and N _B.

[Operation of Drive Circuit in Embodiment]

  Hereinafter, the operation of the drive circuit 10 will be described with reference to FIG. The PWM signal CS applied to the input terminal 10 (IN) from the binary signal generation circuit 12 (FIG. 1) alternately repeats the H level and the L level with a constant frequency and a variable duty ratio.

During the period when the PWM signal CS is at the L level, the first switch (N-type MOSFET) 28 is held in the ON state. First switch 28 that is held in the ON state, falls in the vicinity of potential V _NB ground potential of the node N _B, the output transistor (N-type MOSFET) 24 is turned off. When the output transistor (N-type MOSFET) 24 is off, the drive current DI does not flow through the load 14, and the constant current circuit 38 is stopped. At this time, the potential clogging monitor voltage V _M of the node N _M is equal to ground potential. For this reason, the error voltage _VER obtained at the output terminal of the error amplifier 20 is lowered to the lowest voltage level. Thereby, the amplification transistor (P-type MOSFET) 22 is turned on in the saturation region.

On the other hand, during the period in which the PWM signal CS is at the L level, the second switch (N-type MOSFET) 30 is held in the OFF state. By the second switch 30 is held in the OFF state, the output terminal or node N _A of the amplification transistor (P-type MOSFET) 22 is connected to the node N _B through the resistor 44 of the passive element circuit 32, thus It is connected to the power supply terminal of the ground potential through the first switch 28 in the on state. As a result, the ground potential from the power supply terminal of the power supply voltage _Vdd passes through the amplification transistor (P-type MOSFET) 22 in the on state, the resistor 44 of the passive element circuit 32, and the first switch (N-type MOSFET) 28 in the on state. A constant current flows through the power terminal. Assuming that the current value of this current is I _F and the resistance value of the resistor 44 is R ₄₄ , the voltage drop V _{44 at the} resistor ₄₄ is V ₄₄ = R ₄₄ * I _F. Accordingly, the potential V _NA of the node N _A is higher by V ₄₄ than the potential V _NB (approximately ground potential) of the node N _B.

From another viewpoint, since the amplification transistor (P-type MOSFET) 22 is turned on in the saturation region, the potential V _NA of the node N _A is held at a value close to the power supply voltage V _dd (V _dd −δ).

Thus, during the period in which the PWM signal CS is at the L level, the potential V _NA of the node N _A is held at a value (V _dd −δ) (≈R ₄₄ * I _F ) close to the power supply voltage V _dd. The phase compensation capacitor 26 is charged by the voltage (V _dd −δ) (≈R ₄₄ * I _F ).

When the PWM signal CS changes from the L level to the H level (time points t _a and t _{c in} FIG. 4), the first switch (N-type MOSFET) 28 is switched from the previous on state to the off state, and the second switch The (N-type MOSFET) 30 is switched from the previous off state to the on state.

When the first switch 28 is turned off, the node N _B is electrically disconnected from the power supply terminal of the ground potential. On the other hand, the second switch 30 by being turned on, the node N _B is short-circuited with the node N _A via the second switch 30 is applied to the charging voltage from the phase compensation capacitor 26. Thus, the potential V _NB Node N _B, rises momentarily therefrom to a level near the ground potential. At this time, the discharge current slightly flows from the phase compensation capacitor 26 and the potential V _NA of the node N _A slightly decreases, but still remains at a sufficiently high H level constant value V _H. When the H level voltage V _H is received at the control terminal (gate terminal), the output transistor (N-type MOSFET) 24 is turned on, and the constant current driving operation by the constant current circuit 38 is started (restarted).

In this case, the constant current circuit 38, in response to the rise of the potential V _NB Node N _B, the driving current DI rises quickly rises from the ground potential so far also monitor voltage V _M at high speed. As a result, the output voltage of the error amplifier 20, that is, the error voltage V _ER increases, the output voltage of the amplification transistor (P-type MOSFET) 22, that is, the potentials of the nodes N _A and N _B decreases, and the output transistor (N-type MOSFET) 24 An increase in the drain current, that is, the drive current DI is suppressed. In this way, each part in the constant current circuit 38, particularly the error amplifier 20, in the negative feedback loop, so that both input voltages of the error amplifier 20 are almost equal, that is, the monitor voltage V _M is equal to the reference voltage V _S. Transistor 22 and output transistor 24 operate. The potential V _NA (V _NB ) of the node N _A (N _B ) fluctuates indefinitely under such a constant current driving operation (the dashed lines AL and BL in FIG. 4 indicate this).

Due to the constant current driving operation of the constant current circuit 38, the drive current DI having a constant current value I _S approximated by V _S / R ₃₆ is applied to the load 14 during the period in which the PWM signal CS is at the H level. Supplied.

When the PWM signal CS changes from the H level to the L level again (time points t _b and t _{d in} FIG. 4), the first switch (N-type MOSFET) 28 is switched from the previous off state to the on state, and the second switch The switch (N-type MOSFET) 30 is switched from the previous on state to the off state. As a result, the output transistor (N-type MOSFET) 24 is turned off and the constant current circuit 38 is stopped, while a constant current flows through the resistor 44 of the passive element circuit 32, and the phase compensation capacitor 26 is charged. Is done.

  Thus, the operation and stop of the constant current circuit 38 as described above are alternately repeated in the drive circuit 10 according to the variable duty ratio of the PWM signal CS, and the load 14 corresponds to the variable duty ratio of the PWM signal CS. Drive current DI is supplied.

In the drive circuit 10 of this embodiment, as described above, a constant current is passed through the resistor 44 of the passive element circuit 32 during the period when the constant current circuit 38 is stopped, so that the phase compensation capacitor 26 is sufficiently high. When charging the voltage (H level) and starting the operation of the constant current circuit 38, the charging voltage of the phase compensation capacitor 26 is applied to the control terminal of the output transistor 24, and the output current of the output transistor 24, that is, the drive current DI is increased. I am trying to launch it. Since the passive element circuit 32 is out of the negative feedback loop of the constant current circuit 38 while the constant current circuit 38 is operating, the passive element circuit 32 does not affect the operation (phase compensation) of the phase compensation capacitor 26. Thereby, even if the pulse width of the PWM signal CS is considerably small, the occurrence of oscillation or ringing can be prevented by the action of the phase compensation capacitor 26, so that the dynamic range and the range of the variable duty ratio can be expanded. Further, it is a great advantage that the circuit configuration of the drive circuit 10 is simple.

[Comparative example in the embodiment]

FIG. 5 shows a configuration of a comparative example in this embodiment. This comparative example corresponds to a configuration in which the passive element circuit 32 and the second switch 30 are omitted from the drive circuit 10 in the above embodiment. Therefore, the node N _A and the node N _B is always short-circuited regardless of the logic level of the PWM signal CS.

In this comparative example, during the period in which the PWM signal CS is at the L level, the potential V _NA (V _NB ) of the node N _A (N _B ) is maintained by keeping the first switch 28 in the ON state. Drops to near ground potential. Therefore, the phase compensation capacitor 26 is hardly charged. In this state, when the PWM signal CS changes from the L level to the H level, the node N _A (N _B ) rises from the level near the ground potential to the H level under the output voltage of the amplification transistor 22. At this time, the voltage (charge voltage) higher than the phase compensation capacitor 26 is not supplied to the node N _A (N _B ), and conversely, the rising of the potential V _NA (V _NB ) of the node N _A (N _B ) is phased. It goes around the control terminal (gate terminal) of the amplifying transistor (P-type MOSFET) 22 through the compensation capacitor 26, thereby rising the output voltage of the amplifying transistor (P-type MOSFET) 22, and consequently the potential of the node N _A (N _B ). The rise of V _NA (V _NB ) is delayed. As a result, the rise of the output current of the output transistor 24, that is, the drive current DI is also delayed, and the waveform of the drive current DI is distorted or normal current drive cannot be performed when the PWM duty ratio is small.

In this comparative example, the slew rate can be improved to some extent by reducing the capacity of the phase compensation capacitor 26. However, in this case, the effect of phase compensation is weakened (resulting in sacrificing the effect of phase compensation by the phase compensation capacitor 26), and stable PWM pulse driving cannot be expected.

[Other Embodiments or Modifications]

  The passive element circuit 32 in the embodiment described above is configured to have one resistor (linear element) 44. However, a circuit configuration in which a plurality of resistors are connected in series or in parallel is also possible, and a configuration including a non-linear element such as a diode may be used.

  In particular, when a diode is provided in the passive element circuit 32, as shown in FIG. 7, a diode-connected MOSFET having a threshold voltage that is the same as or close to that of the MOSFET constituting the output transistor 24 (N-type MOSFET in the illustrated example). (N-type MOSFET) 46 can be preferably used. In order to satisfy the requirement of the same or closeness of the threshold voltage, two MOSFET devices cut out from the same semiconductor wafer (more preferably in the vicinity area on the wafer) that have undergone the same semiconductor process are both ( 24, 46).

  In the configuration of FIG. 7, when the threshold voltage of the output transistor (N-type MOSFET) 24 is increased due to variations in the semiconductor process, the threshold voltage of the diode-connected N-type MOSFET 46 in the passive element circuit 32 is also increased. . As a result, the charging voltage of the phase compensation capacitor 26 charged during the period when the constant current circuit 38 is stopped is also increased to that extent. As a result, the increase (variation) in the threshold voltage in the output transistor (N-type MOSFET) 24 can be canceled and the output transistor (N-type MOSFET) 24 can be turned on at high speed, and the drive current DI is increased. Can be kept fast.

Further, the drive circuit 10 in the above embodiment is configured by a CMOS circuit, and in particular, since the output transistor 24 is configured by a MOSFET, the drive current DI flowing through the load 14 flows through the monitor resistor 36 as it is. Therefore, high accuracy of the monitor voltage V _M, there is an advantage that draw constant current drive is highly accurate. However, a part or all of the transistors in the drive circuit 10 can be composed of bipolar transistors. In addition, any one of the first and second switches 28 and 30 (particularly, the second switch 30) can be configured by a transmission gate. A configuration in which the current source 40 is replaced with a resistor is also possible. Further, as an error amplifier 20, the configuration of FIG. 3 is one example, may have any circuit configuration capable of outputting the error voltage V _ER corresponding to the difference between the input voltage V _S, V _M.

  Although the driving circuit 10 in the above embodiment is configured for driving constant current driving, it may be configured for flowing constant current driving. Further, the present invention can be applied to a driving circuit for constant voltage driving, and an example thereof is shown in FIG.

  In the drive circuit of FIG. 8, the error amplifier 20 ′, the amplification transistor 22 ′, the output transistor 24 ′, the phase compensation capacitor 26 ′, the first and second switches 28 ′ and 30 ′, and the passive element circuit 32 ′ are implemented as described above. 2 has the same functions as those of the error amplifier 20, the amplification transistor 22, the output transistor 24, the phase compensation capacitor 26, the first and second switches 28 and 30, and the passive element circuit 32. The input resistor 70 and the feedback resistor 72 define the amplification factor in the non-inverting drive circuit.

  In this drive circuit, when the PWM signal CS is at the H level, the output transistor 24 'is turned on, and the voltage obtained at the output terminal (drain terminal) is applied to the load 14 (FIG. 1) as the drive voltage DV. The When the PWM signal CS is at the L level, the output transistor 24 'is turned off, the voltage of the output terminal (drain terminal) falls to the ground potential, and the supply of the drive voltage DV is cut off.

Further, as a modified example of the driving circuit of the present invention, omitting the output transistor 24, a configuration is possible in the node N _B is connected directly to the load between the amplifying transistor 22 and the current source 40.

DESCRIPTION OF SYMBOLS 10 Drive circuit 12 Binary signal generation circuit 14 Load 20 Error amplifier 22 Amplification transistor 24 Output transistor 26 Phase compensation capacitor 28 First switch 30 Second switch 32 Passive element circuit 34 Reference voltage source 36 Monitor resistance 40 Current source 44 Resistance (Linear element)
46 Diode-connected MOSFET

Claims (8)

When an external binary signal is input and the logical value of the binary signal is the first logical value, a predetermined driving voltage or driving current is supplied to the load, and the logical value of the binary signal is the second logical value. A drive circuit that cuts off the supply of the drive voltage or drive current to the load when the logic value is
An error amplifier having first and second input terminals and generating an output voltage in accordance with a difference between the first and second input voltages respectively input to the first and second input terminals;
A first transistor for amplifying the output voltage of the error amplifier;
A capacitor connected between a control terminal and an output terminal of the first transistor for phase compensation;
A first node connected to the load via an output circuit or directly;
A passive element circuit including at least one linear element or nonlinear element connected between the output terminal of the first transistor and the first node;
The second node is connected between the first node and a reference potential terminal for providing a reference potential for cutting off the supply of the output voltage or output current to the load, and the logical value of the binary signal is the second logic. A first switch that is on when it is a value, and that is off when the logic value of the binary signal is the first logic value;
When connected in parallel with the passive element circuit, when the logical value of the binary signal is the second logical value, it is turned off, and when the logical value of the binary signal is the first logical value And a second switch that is turned on.   2. The error amplifier according to claim 1, wherein the first input voltage is a reference voltage having a constant voltage level, and the second input voltage includes a voltage of a feedback signal corresponding to the driving voltage or driving current. The drive circuit described.   2. The drive circuit according to claim 1, wherein in the error amplifier, the first input voltage is a reference voltage having a preset voltage level, and the second input voltage includes a voltage of the binary signal.   The drive circuit according to claim 1, wherein the output circuit includes a second transistor having a control terminal connected to the first node and an output terminal connected to the load. When a binary signal from the outside is input and the logic value of the binary signal is the first logic value, a constant driving current is supplied to the load, and the logic value of the binary signal is the second logic value. Is a drive circuit that cuts off the supply of the drive current to the load,
An error amplifier that inputs a feedback signal having a predetermined reference voltage and a voltage proportional to the current value of the drive current, and generates an output voltage according to the difference between the reference voltage and the voltage of the feedback signal;
A first MOSFET that constitutes a grounded source amplifier circuit, the control terminal of which is connected to the output terminal of the error amplifier;
A capacitor connected between a control terminal and an output terminal of the first MOSFET for phase compensation;
A second MOSFET of a second conductivity type whose output terminal is connected to the load;
A passive element circuit including at least one linear element or non-linear element connected between the output terminal of the first MOSFET and the control terminal of the second MOSFET;
The second MOSFET is connected between a control terminal of the second MOSFET and a reference potential terminal for providing a predetermined reference potential for turning off the second MOSFET, and the logical value of the binary signal is the second logical value. A first switch that is turned on at one time and turned off when the logic value of the binary signal is the first logic value;
When connected in parallel with the passive element circuit, when the logical value of the binary signal is the second logical value, it is turned off, and when the logical value of the binary signal is the first logical value And a second switch that is turned on.   The drive circuit according to claim 5, further comprising a current source connected in parallel with the first switch.   The drive circuit according to claim 5, wherein the passive element circuit has at least one resistor.   8. The drive circuit according to claim 5, wherein the passive element circuit includes a diode-connected second conductivity type fourth MOSFET. 9.

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