JP6024197B2 - Light emitting element drive circuit - Google Patents

Description

  The present invention relates to a light emitting element driving circuit.

  Patent Document 1 describes a semiconductor laser drive circuit having a shunt drive system. This semiconductor laser driving circuit includes a semiconductor light emitting element, an N-type MOSFET, and an NPN-type bipolar transistor. The anode of the semiconductor light emitting element is connected to a bias current supply terminal. The drain and source of the N-type MOSFET are connected to the anode and the cathode of the semiconductor light emitting device, respectively. The gate of the N-type MOSFET is connected to an input terminal of a modulation signal for modulating the bias current via an NPN bipolar transistor.

JP 2011-023474 A

  FIG. 6 is a circuit diagram showing a configuration of a light emitting element driving circuit according to a conventional shunt driving method. As shown in FIG. 6, the light emitting element driving circuit 100 is a circuit that modulates the bias current Ib supplied from the current source 104 to the light emitting element 102, and includes a transistor 106 and a resistor 108. The transistor 106 is, for example, a MOS type field effect transistor (FET). An input signal Sin is input from the input terminal 122 to the control terminal (gate) of the transistor 106. One current terminal (drain) of the transistor 106 is connected to the anode of the light emitting element 102 via the output terminal 112 and the bonding wire 110. The other current terminal (source) of the transistor 106 is connected to the reference potential line 130.

  In the light emitting element driving circuit 100, when the input signal Sin is in the OFF state, no current flows through the transistor 106. Therefore, most of the bias current Ib output from the current source 104 is supplied to the light emitting element 102. Emits light. Further, since the current flows through the transistor 106 when the input signal Sin is on, the bias current Ib output from the current source 104 flows to the transistor 106, and the amount of current supplied to the light emitting element 102 is reduced. The light emitting element driving circuit 100 can modulate the light emitting element 102 by such an operation.

  However, such a light emitting element driving circuit 100 has the following problems. That is, when the output impedance at the output terminal 112 is high, resonance is caused by the parasitic inductance of the bonding wire 110 and the parasitic capacitance near the output terminal 112, and this resonance affects the current flowing through the light emitting element 102. For example, if the resonance peak and the resonance peak of the optical response in the light emitting element 102 overlap, large peaking occurs in the frequency response of the light output from the light emitting element 102, and it is difficult to obtain an appropriate optical output waveform. Become. Therefore, a conventional shunt drive circuit such as the light emitting element drive circuit 100 has a problem that the modulation speed is limited to a low speed, for example, less than 14 Gbps, in order to suppress such a phenomenon.

  The present invention has been made in view of such problems, and provides a light-emitting element drive circuit that has a shunt drive system and can increase the modulation speed while maintaining a good optical output waveform. Objective.

  In order to solve the above-described problems, a light-emitting element driving circuit according to the present invention is a light-emitting element driving circuit that modulates the magnitude of a current supplied from a bias source to a light-emitting element according to an input signal. An input input terminal, an output terminal connected between the light emitting element and the bias source, a control terminal is connected to the input terminal, one current terminal is connected to the output terminal, and the other current terminal is A first transistor connected to one constant potential line, a first predetermined voltage is applied to the control terminal, and one current terminal is a second constant potential line having a higher potential than the first constant potential line. And a second transistor having the other current terminal connected to the output terminal.

  In this light emitting element driving circuit, since no current flows through the first transistor when the input signal is in an OFF state, most of the current output from the bias source is supplied to the light emitting element, and the light emitting element emits light. In addition, since the current flows through the first transistor when the input signal is in the on state, the current output from the bias source flows to the first transistor, and the amount of current supplied to the light emitting element is reduced. The light emitting element driving circuit can modulate the light emitting element by such an operation (shunt driving).

  The light-emitting element driving circuit includes a second transistor in addition to the first transistor that modulates the current of the light-emitting element by shunt driving. The other current terminal of the second transistor is connected to the output terminal. When the input signal is in the OFF state, the amount of current flowing through the light emitting element is increased, so that the potential of the output terminal is increased and the potential difference between the current terminals of the second transistor is reduced, so that the output impedance at the output terminal is reduced. . Further, when the input signal is in the on state, the amount of current flowing through the light emitting element is reduced, so that the potential of the output terminal is lowered and the potential difference between the current terminals of the second transistor is increased, so that the output impedance at the output terminal is increased. .

That is, since the output impedance of the light emitting element driving circuit dynamically changes with the change of the input signal, the above-described resonance can be suppressed and peaking can be effectively suppressed. Therefore, according to the light emitting element driving circuit, it is possible to increase the modulation speed while maintaining a good light output waveform of the light emitting element.

  Further, when the light emitting element emits light, the output impedance of the light emitting element driving circuit is reduced, so that the rise time of light emission in the light emitting element is increased. On the other hand, when the amount of current flowing through the light emitting element is small (when the light is extinguished), the output impedance of the light emitting element driving circuit is increased and the peaking suppressing action is reduced, so that the fall time of light emission in the light emitting element is shortened. Usually, the light output waveform of a light emitting element such as a semiconductor laser element tends to have a longer fall time than the rise time. According to the light emitting element driving circuit, by increasing the rise time and shortening the fall time in the light output waveform, the asymmetry between the rise time and the fall time of the light output waveform is reduced, and the light output waveform is reduced. The output waveform can be further improved. Therefore, according to the light emitting element driving circuit, a high modulation speed such as 14 Gbps or more can be realized.

  In the light emitting element driving circuit, a second predetermined voltage is applied to the control terminal, one current terminal is connected to the second constant potential line, and the other current terminal is one current terminal of the second transistor. A third transistor connected to may be further provided. Accordingly, the amount of current flowing through the second transistor can be reduced, and the power consumption of the light emitting element driving circuit can be reduced.

  In the light emitting element driving circuit, a third predetermined voltage is applied to the control terminal, one current terminal is connected to the output terminal, and the other current terminal is connected to one current terminal of the first transistor. A fourth transistor may be further provided.

  In the light emitting element driving circuit, the first predetermined voltage input to the control terminal of the second transistor is such that when the first transistor is in the on state, the second transistor operates in the saturation region. It is preferable that the size of the second transistor operate in the triode region when the first transistor is off.

  ADVANTAGE OF THE INVENTION According to this invention, it has a shunt drive system and can provide the light emitting element drive circuit which can make an optical output waveform favorable.

FIG. 1 is a circuit diagram showing a configuration of a light emitting element driving circuit according to the first embodiment of the present invention. FIG. 2 is a graph showing the operating characteristics of the transistor. FIG. 3 is a circuit diagram showing a configuration of a light emitting element driving circuit according to the second embodiment of the present invention. FIG. 4 is a circuit diagram showing a configuration of a light emitting element driving circuit according to the third embodiment of the present invention. FIG. 5 is a circuit diagram showing a configuration of a light emitting element driving circuit according to the fourth embodiment of the present invention. FIG. 6 is a circuit diagram showing a configuration of a light emitting element driving circuit according to a conventional shunt driving method.

  Hereinafter, embodiments of a light emitting element driving circuit according to the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a light emitting element driving circuit 1A according to the first embodiment of the present invention. The light emitting element driving circuit 1A of the present embodiment is a circuit for modulating the magnitude of the current Id supplied from the bias current source 12 to the light emitting element 14 according to the input signal Sin. The light emitting element 14 is a semiconductor light emitting element such as a laser diode or an LED.

  As shown in FIG. 1, the light emitting element driving circuit 1 </ b> A includes an input terminal 22 and an output terminal 24. An input signal Sin is input to the input terminal 22. The input signal Sin is a signal modulated at a high speed, for example, at a speed of 14 Gbps or higher. The output terminal 24 is connected to a node N <b> 1 between the light emitting element 14 and the bias current source 12 through the bonding wire 13. The cathode of the light emitting element 14 is connected to a reference potential line 18 that provides a ground potential. The bias current source 12 is connected between the anode of the light emitting element 14 and the power supply potential line 16 that provides the power supply potential Vcc. In the present embodiment, the reference potential line 18 is a first constant potential line, and the power supply potential line 16 is a second constant potential line having a higher potential than the first constant potential line.

  The light emitting element driving circuit 1A further includes transistors 30 and 40. The transistor 30 is the first transistor in the present embodiment, and is configured by, for example, an NPN bipolar transistor made of a SiGe-based semiconductor or an InP-based semiconductor. The transistor 30 has a base terminal 31 as a control terminal, a collector terminal 32 as one current terminal, and an emitter terminal 33 as the other current terminal. The transistor 30 may be configured by a field effect transistor (for example, an N-channel MOS FET). In this case, the base terminal 31 is a gate terminal, the collector terminal 32 is a drain terminal, and the emitter terminal 33 is a source terminal. Replaced.

  A base terminal 31 of the transistor 30 is connected to the input terminal 22. An input signal Sin is input to the base terminal 31 via the input terminal 22. The collector terminal 32 of the transistor 30 is connected to the output terminal 24 via the node N2. A part Ia of the bias current Ib output from the bias current source 12 is input to the collector terminal 32 via the output terminal 24. The emitter terminal 33 of the transistor 30 is connected to the reference potential line 18 via the terminal 21. As shown in FIG. 1, a resistor 52 may be connected in series with the transistor 30 between the node N <b> 2 and the reference potential line 18. The resistance value of the resistor 52 determines the magnitude of the current Ia. The resistance value of the resistor 52 is, for example, 8 ohms. The resistor 52 is configured by, for example, a resistance element or a transistor different from the transistor 30.

  The transistor 40 is a second transistor in the present embodiment, and is configured by, for example, an FET (P channel MOS type FET in one example). The transistor 40 has a gate terminal 41 as a control terminal, a source terminal 42 as one current terminal, and a drain terminal 43 as the other current terminal. The transistor 40 may be a bipolar transistor, in which case the gate terminal 41 is replaced with a base terminal, the source terminal 42 is replaced with an emitter terminal, and the drain terminal 43 is replaced with a collector terminal. Note that, when the transistor 30 is configured by an NPN bipolar transistor or an N-channel MOS FET as in the present embodiment, the transistor 40 is preferably configured by a PNP bipolar transistor or a P-channel MOS FET.

  The gate terminal 41 of the transistor 40 is connected to the voltage bias circuit 44. A first predetermined voltage Va is applied from the voltage bias circuit 44 to the gate terminal 41. The voltage bias circuit 44 can be connected to a circuit external to the light emitting element driving circuit 1A via the adjustment terminal 28, and increases or decreases the voltage value of the predetermined voltage Va by a signal input via the adjustment terminal 28. Is possible. Therefore, the transistor 40 can operate as a variable resistor whose resistance value can be adjusted by a signal input via the adjustment terminal 28. The source terminal 42 of the transistor 40 is connected to the power supply potential line 16 via the power supply terminal 26. A power supply voltage Vcc is applied to the source terminal 42 from the power supply potential line 16. The drain terminal 43 of the transistor 40 is connected to the output terminal 24 and the collector terminal 32 of the transistor 30 via the node N2.

  The light emitting element driving circuit 1 </ b> A further includes a circuit 53. The circuit 53 is connected between the output terminal 24 and the node N2 and the reference potential line 18. The circuit 53 of this embodiment has a resistor 54 and a capacitor 56. One end of the resistor 54 is connected to the reference potential line 18 via the terminal 21, and the other end is connected to one electrode of the capacitor 56. The other electrode of the capacitor 56 is connected to the output terminal 24 and the node N2. The resistance value of the resistor 54 is, for example, 65 ohms, and the capacitance value of the capacitor 56 is, for example, 1 pF.

  The capacitance 58 shown in FIG. 1 is a parasitic capacitance due to pads and wirings near the output terminal 24. The parasitic capacitance 58 is generated between the wiring near the output terminal 24 and the reference potential line 18.

  In the light emitting element driving circuit 1A, an input signal Sin is input to the input terminal 22 from the outside of the light emitting element driving circuit 1A. When the input signal Sin is off (low level), the transistor 30 is off and no current flows between the collector terminal 32 and the emitter terminal 33. Therefore, most of the bias current Ib output from the bias current source 12 is supplied to the light emitting element 14, and the light emitting element 14 emits light. Further, when the input signal Sin is in an on state (high level), the transistor 30 is in an on state, and a current flows between the collector terminal 32 and the emitter terminal 33. Accordingly, a part Ia of the bias current Ib output from the bias current source 12 flows to the reference potential line 18 through the transistor 30 and the resistor 52, and the current supplied to the light emitting element 14 is reduced. Therefore, the light emitting element 14 emits light. do not do. Note that the magnitude of the current Ia is determined by the resistance value of the resistor 52. In the light emitting element driving circuit 1A of the present embodiment, the light emission of the light emitting element 14 is modulated by repeatedly turning on and off the input signal Sin in such shunt driving.

  Next, the effects obtained by the light emitting element driving circuit 1A of the present embodiment will be described together with the problems of the conventional circuit.

  In the conventional shunt drive type circuit 100 shown in FIG. 6, in order to realize a high-speed operation of, for example, 14 Gbps or more, it is necessary that the transistor 106 connected to the output terminal 112 can operate at high speed. Examples of such a device include an NPN bipolar transistor and an N channel MOS FET. However, when an NPN bipolar transistor is used, the output impedance of the circuit 100 becomes large. Further, by using the N channel MOS type FET, the output impedance can be reduced as compared with the case of using the NPN type bipolar transistor. However, since the transistor 106 is connected in parallel with the light emitting element 102, a voltage drop (for example, 1.1 V to 1.4 V) in the light emitting element 102 is applied between the current terminals of the transistor 106. May be a problem. If two or more N-channel MOS FETs are cascode-connected in order to avoid such a problem, the output impedance also increases.

  When the output impedance of the light emitting element driving circuit is increased, the following problem occurs. In many cases, the light emitting element driving circuit 100 and the light emitting element 102 are connected by a bonding wire 110. In this case, LC resonance occurs due to the inductance of the bonding wire 110 and the parasitic capacitance near the output terminal 112 of the light emitting element driving circuit 100. A typical resonance frequency in this LC resonance is 16.5 GHz to 22.1 GHz. Such a resonance frequency increases or decreases depending on the size of the parasitic component of the light emitting element 102, but when operating at a communication speed of 25.8 Gbps (100 GE), 27.95 Gbps (OTU4), or 28.05 Gbps (32 GFC). This causes ringing in the optical output waveform.

  The light emitting element 102 also has a response characteristic in which the light emission timing is slightly delayed with respect to the input of current, and a resonance phenomenon occurs due to this response characteristic. The resonance frequency in this resonance phenomenon depends on the magnitude of the bias current Ib, but is typically about 15 GHz. Therefore, the resonance frequency in this resonance phenomenon and the above-described LC resonance frequency are close to each other, and large peaking occurs in the optical output waveform. As a result, ringing in the optical output waveform becomes more prominent.

  In order to avoid such a problem, at least one of the frequency of the resonance phenomenon caused by the response characteristic of the light emitting element 102 and the frequency of the LC resonance caused by the inductance of the bonding wire 110 is increased (or decreased). ) However, it is difficult to change the response characteristics of the light-emitting element 102, and changing the inductance of the bonding wire 110 (that is, changing the length of the bonding wire 110) can be performed in various ways in the assembly of the light-emitting element driving circuit. It may be difficult due to restrictions.

  In order to solve the above problems, the light emitting element driving circuit 1A according to the present embodiment includes a transistor 40 in addition to the transistor 30 that modulates the driving current Id to the light emitting element 14 by shunt driving. . The drain terminal 43 of the transistor 40 is connected to the output terminal 24. When the input signal Sin is in the off state, the amount of current Id flowing through the light emitting element 14 is increased, so that the potential of the output terminal 24 is increased. Further, when the input signal Sin is in the on state, the amount of current flowing through the light emitting element 14 is reduced, so that the potential of the output terminal 24 is lowered.

Therefore, when the input signal Sin is in the OFF state, the potential difference between the source terminal 42 and the drain terminal 43 of the transistor 40 is reduced, and the resistance value between the source terminal 42 and the drain terminal 43 is decreased. The output impedance at 24 is reduced. Further, when the input signal Sin is in the on state, the potential difference between the source terminal 42 and drain terminal 43 of the transistor 40 is increased, so want above resistance value between the source terminal 42 and drain terminal 43, The output impedance at the output terminal 24 increases.

That is, since the output impedance of the light emitting element driving circuit 1A dynamically changes with the change of the input signal Sin, LC resonance caused by the parasitic inductance of the bonding wire 13 and the parasitic capacitance 58 near the output terminal 24 can be suppressed. Therefore, peaking of the optical output waveform caused by overlapping of the LC resonance frequency peak and the resonance frequency peak due to the response characteristic of the light emitting element 14 is effectively suppressed. Therefore, according to the light emitting element driving circuit 1A of the present embodiment, the electro-optical response of the light emitting element 14 can be flattened, and the appropriate light output waveform of the light emitting element 14 can be maintained satisfactorily. In addition, this enables the modulation speed of the light emitting element 14 to be higher, for example, 14 Gbps or higher (for example, 25.78 Gbps, 27.95 Gbps, or 28.05 Gbps).

  For example, when the bias current Ib to the light emitting element 14 is 40 mA and the threshold value is 10 mA, the modulation current Id necessary for obtaining the extinction ratio 5 dB of the optical output waveform is about 30 mA. Considering that the differential resistance value of 14 is about 10 ohms, the potential of the output terminal 24 fluctuates by 300 mV at the peak-to-peak value. For example, if the drain-source voltage of the transistor 40 when the input signal Sin is in the on state is 0.2 V, the potential of the output terminal 24 goes up and down by 0.3 V as described above. The drain-source voltage varies in the range of 0.35V. At this time, the output resistance of the drain terminal 43 varies between 150 ohms and 900 ohms. The output impedance of the light emitting element driving circuit 1A dynamically changes with the change of the input signal Sin in the range of about 63 ohms to 73 ohms due to the fluctuation of the output resistance of the drain terminal 43. Thereby, peaking of the optical output waveform is effectively suppressed.

  Further, when the light emitting element 14 emits light, the output impedance of the light emitting element driving circuit 1A becomes small, so that the rise time of light emission in the light emitting element 14 becomes long. On the other hand, when the amount of the current Id flowing through the light emitting element 14 is small (when the light is extinguished), the output impedance of the light emitting element driving circuit 1A is increased and the peaking suppressing action is reduced. Downtime is shortened. Usually, in the light output waveform of the light emitting element 14 such as a semiconductor laser element, the fall time tends to be longer than the rise time. According to the light emitting element driving circuit 1A of the present embodiment, the rise time and the fall time of the light output waveform are reduced by the action of increasing the rise time and shortening the fall time in the light output waveform. The light output waveform can be further improved by relaxing.

  Here, a more preferable embodiment in the present embodiment will be described based on the operating characteristics of the transistor 40. FIG. 2 is a graph showing the operating characteristics of the transistor 40, in which the horizontal axis represents the drain-source voltage, and the vertical axis represents the drain current. As shown in FIG. 2, in the region A1 where the drain-source voltage is relatively small, the slope of the drain current with respect to the increase in drain current is steep, while in the region A2 where the drain-source voltage is relatively large, The slope of the drain current with respect to the increase in the drain current is gentle. The region A1 is called a triode region (unsaturated region), and the region A2 is called a saturated region (active region).

The region A1 is a region where the change in the drain current with respect to the change in the drain-source voltage is large, that is, the resistance value between the drain and the source is small . On the other hand, the region A2 is a region where the change in the drain current with respect to the change in the drain-source voltage is small, that is, the drain-source resistance value is large . Therefore, in this embodiment, the predetermined voltage Va input to the gate terminal 41 of the transistor 40 is such that the transistor 40 operates in the saturation region A2 when the transistor 30 is in the on state, and the transistor 40 when the transistor 30 is in the off state. Is preferably sized to operate in the triode region A1. In order to realize such a predetermined voltage Va, the predetermined voltage Va may be modulated according to the input signal Sin.

  In addition, the light emitting element driving circuit 1 </ b> A according to the present embodiment includes a circuit 53 including a resistor 54 and a capacitor 56. The LC resonance caused by the parasitic inductance of the bonding wire 13 and the parasitic capacitance 58 in the vicinity of the output terminal 24 is subjected to band limitation according to the reciprocal of the impedance of the circuit 53. As a result, the peak of LC resonance can be further suppressed.

(Second Embodiment)
FIG. 3 is a circuit diagram showing a configuration of a light emitting element driving circuit 1B according to the second embodiment of the present invention. The light emitting element driving circuit 1B according to the present embodiment further includes a transistor 60 in addition to the configuration of the light emitting element driving circuit 1A according to the first embodiment. The transistor 60 is the third transistor in the present embodiment.

  The transistor 60 is configured by, for example, an FET (N-channel MOS type FET in one example). The transistor 60 has a gate terminal 61 as a control terminal, a drain terminal 62 as one current terminal, and a source terminal 63 as the other current terminal. The transistor 60 may be a bipolar transistor. In this case, the gate terminal 61 is replaced with a base terminal, the drain terminal 62 is replaced with a collector terminal, and the source terminal 63 is replaced with an emitter terminal.

  The gate terminal 61 of the transistor 60 is connected to the voltage bias circuit 44. A second predetermined voltage Vb different from the first predetermined voltage Va is applied to the gate terminal 61 from the voltage bias circuit 44. Note that the voltage value of the predetermined voltage Vb can also be raised or lowered by a signal input via the adjustment terminal 28. The drain terminal 62 of the transistor 60 is connected to the power supply potential line 16 through the power supply terminal 26. A power supply voltage Vcc is applied from the power supply potential line 16 to the drain terminal 62. The source terminal 63 of the transistor 60 is connected to the source terminal 42 of the transistor 40. In other words, the transistor 60 is connected in series between the transistor 40 and the power supply potential line 16. The transistor 60 has a configuration of, for example, a source follower or a grounded gate circuit, and its source output resistance is low. Therefore, the resistance value of the series circuit of the transistors 40 and 60 is almost determined only by the transistor 40. Further, by providing such a transistor 60, the amount of current flowing through the transistor 40 can be reduced, and the power consumption of the light emitting element driving circuit 1B can be reduced.

  Further, according to the light emitting element driving circuit 1B of the present embodiment, since the configuration of the light emitting element driving circuit 1A of the first embodiment is provided, the electro-optical response of the light emitting element 14 is flattened, and An appropriate optical output waveform can be maintained well. This also makes it possible to make the modulation speed of the light emitting element 14 faster. Further, the asymmetry between the rise and fall of the optical output waveform can be relaxed, and the optical output waveform can be further improved.

(Third embodiment)
FIG. 4 is a circuit diagram showing a configuration of a light emitting element driving circuit 1C according to the third embodiment of the present invention. The light emitting element driving circuit 1C of the present embodiment includes a transistor 70 instead of the resistor 52 of the light emitting element driving circuit 1A of the first embodiment. The transistor 70 is the fourth transistor in this embodiment.

  The transistor 70 is configured by, for example, an FET (N channel MOS type FET in one example). The transistor 70 has a gate terminal 71 as a control terminal, a drain terminal 72 as one current terminal, and a source terminal 73 as the other current terminal. The transistor 70 may be a bipolar transistor. In this case, the gate terminal 71 is replaced with a base terminal, the drain terminal 72 is replaced with a collector terminal, and the source terminal 73 is replaced with an emitter terminal.

  A gate terminal 71 of the transistor 70 is connected to the voltage bias circuit 44. A third predetermined voltage Vc different from the first predetermined voltage Va is applied from the voltage bias circuit 44 to the gate terminal 71. The voltage value of the predetermined voltage Vc can also be raised or lowered by a signal input via the adjustment terminal 28, and the transistor 70 functions as a variable resistor. The drain terminal 72 of the transistor 70 is connected to the output terminal 24 via the node N2. A part Ia of the bias current Ib output from the bias current source 12 is input to the drain terminal 72 via the output terminal 24. The source terminal 73 of the transistor 70 is connected to the drain terminal 32 of the transistor 30. In other words, the transistor 70 is connected in series with the transistor 30 between the node N2 and the reference potential line 18.

  The resistor connected in series with the transistor 30 may be configured by a transistor as in this embodiment. Further, the resistor connected in series with the transistor 30 may be connected between the transistor 30 and the node N2 as in the present embodiment.

  Further, according to the light emitting element driving circuit 1C of the present embodiment, since it has the same configuration as the light emitting element driving circuit 1A of the first embodiment, the electro-optical response of the light emitting element 14 is flattened, and the light emitting element The 14 appropriate optical output waveforms can be maintained well. This also makes it possible to make the modulation speed of the light emitting element 14 faster. Further, the asymmetry between the rise and fall of the optical output waveform can be relaxed, and the optical output waveform can be further improved.

(Fourth embodiment)
FIG. 5 is a circuit diagram showing a configuration of a light emitting element driving circuit 1D according to the fourth embodiment of the present invention. The light emitting element driving circuit 1D of the present embodiment further includes the transistor 60 of the second embodiment in addition to the configuration of the light emitting element driving circuit 1A of the first embodiment. Further, the light emitting element driving circuit 1D of the present embodiment includes the transistor 70 of the third embodiment instead of the resistor 52 of the light emitting element driving circuit 1A of the first embodiment. The configuration and operation of the transistors 60 and 70 are the same as those in the second and third embodiments.

  According to the light emitting element driving circuit 1D of the present embodiment, by providing the transistor 60, the amount of current flowing through the transistor 40 can be reduced, and the power consumption of the light emitting element driving circuit 1D can be reduced. In addition, according to the light emitting element driving circuit 1D of the present embodiment, the light emitting element driving circuit 1A has the same configuration as that of the light emitting element driving circuit 1A of the first embodiment. The 14 appropriate optical output waveforms can be maintained well. This also makes it possible to make the modulation speed of the light emitting element 14 faster. Further, the asymmetry between the rise and fall of the optical output waveform can be relaxed, and the optical output waveform can be further improved.

  The preferred embodiments of the light emitting element driving circuit according to the present invention have been described above. However, the present invention is not necessarily limited to the above embodiments, and various modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1A, 1B, 1C, 1D ... Light emitting element drive circuit, 12 ... Bias current source, 13 ... Bonding wire, 14 ... Light emitting element, 16 ... Power supply potential line, 18 ... Reference potential line, 22 ... Input terminal, 24 ... Output terminal , 26 ... power supply terminal, 28 ... adjustment terminal, 30 ... first transistor, 40 ... second transistor, 44 ... voltage bias circuit, 60 ... third transistor, 70 ... fourth transistor, A1 ... triode region, A2 ... saturation region, N1, N2 ... node, Sin ... input signal, Va, Vb, Vc ... predetermined voltage.

Claims (3)

A light-emitting element driving circuit that modulates the magnitude of a current supplied from a bias source to a light-emitting element according to an input signal;
An input terminal to which the input signal is input;
An output terminal connected between the light emitting element and the bias source;
A first transistor having a control terminal connected to the input terminal, one current terminal connected to the output terminal, and the other current terminal connected to a first constant potential line;
A first predetermined voltage is applied to the control terminal, one current terminal is connected to a second constant potential line having a higher potential than the first constant potential line, and the other current terminal is connected to the output terminal. And a second transistor ,
The first predetermined voltage input to the control terminal of the second transistor is such that when the first transistor is in an on state, the second transistor operates in a saturation region, and the first transistor is off. It said second transistor and said magnitude der Rukoto operating in the triode region in the state, the light emitting element driving circuit.   A second predetermined voltage is applied to the control terminal, one current terminal is connected to the second constant potential line, and the other current terminal is connected to the one current terminal of the second transistor. The light emitting element drive circuit according to claim 1, further comprising 3 transistors.   A fourth transistor in which a third predetermined voltage is applied to the control terminal, one current terminal is connected to the output terminal, and the other current terminal is connected to the one current terminal of the first transistor. The light-emitting element driving circuit according to claim 1, further comprising:

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