JP2016167125A - Data write/read control method to memory device, and memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a risk of erroneous operation by restraining power consumption of a circuit, keeping a consumption current low, and suppressing occurrence of noise when writing and reading to and from a memory device.SOLUTION: A write/read control method to and from a memory device includes a power supply interface part for supplying power to the memory device by changing a direction of current allowed to flow to a terminating resistor according to an output state of the memory device. The method includes a write process for converting a bit train of input data to a bit train including a logic value for reducing a consumption power value and writing the converted bit train in the memory device, and a read process for inversely converting the bit train after conversion written to the memory device to a bit train before writing to read data.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a data write and read control method for a memory device and a memory device, for example, a SSTL (Stub Series Terminated) such as a DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory), a DDR2-SDRAM, or a DDR3-SDRAM. Logic) can be applied to a DDR memory having an interface.

  For example, DDR3-DRAM is currently the mainstream DRAM used as a main storage device for personal computers and servers. As described in Non-Patent Document 1, this DDR3-SDRAM mainly includes signal pins shown below.

  CK, CK #: Clock signal. CK inputs a differential clock for determining timing as an operation reference of the DDR3-SDRAM. All addresses and control input signals are sampled based on the intersection of the rising edge of CK and the falling edge of CK #. CK outputs data.

  CKE: Clock enable signal. CKE determines whether the clock is valid or invalid for the input / output signals of the device. When the CKE input is High, the clock is valid, and when it is Low, the clock is invalid. CKE is set to Low during precharge power down, self refresh, or active power down.

  CS #: Chip select signal. Command input is valid when Low, and all command input is invalid when High. However, the command in operation is continued even if CS # is High.

  RAS #, CAS #, WE #: row address strobe signal (RAS), column address strobe signal, (CAS), write enable signal (WE). RAS #, CAS #, and WE # input a command that determines the operation of the DDR3-SDRAM.

  ODT: On-die termination signal. In the case of High, the built-in termination resistor Rt is effective. ODT is connected only to DQ, DQS, DQS #, DM, and other input pins (CKE, CS #, RAS #, CAS #, WE #, ODT, RESET #, BA0-BA2, A0-Ax (x is a memory) Not connected to))).

  DM (DMU DML): Data mask signal. If High during the write operation, the data input is masked and writing to the device is not performed.

  BA0-BA2: Bank address signals. BA0 to BA2 select a bank to be read / written at the time of an active command. BA0-BA2 are also used to select the type of mode register (MR0 to MR3).

  A0-Ax: Address signal. In A0-Ax, an address for designating a cell position for reading / writing the memory array is input. A0-Ax selects a row address when an active command is input, and a leading column address of a burst operation when a read / write command is input. A0-Ax is also used for mode register setting.

  A10 / AP: Auto precharge signal. A10 is not used for the column address designated at the time of the read / write command. Instead, A10 performs auto precharge (A10 = High) or not (A10) for the bank accessed after read / write. = Low). When a precharge command is input, A10 is used to select a target bank for precharge. When A10 is Low, precharging is performed for only one bank, and when A10 is High, precharging is performed for all banks. The bank to be precharged is selected by bank address.

  A12 / BC #: Burst chop signal. When a read / write command is input, it is selected whether the burst operation is interrupted by four data (A12 = Low) or not (A12 = High).

  RESET #: Reset signal. When Low is input to the reset pin, the device is reset.

  DQ: Data signal. Input and output data.

  DQS DQS #: Data strobe signal. DQS DQS # is a differential strobe signal that specifies data read / write timing.

  The above signal of the DDR memory is connected to a memory controller such as a CPU or FPGA. In order to reduce signal degradation due to noise and reflection caused by the increase in operating frequency, the DDR memory is shown in FIG. A structured SSTL interface is employed.

The SSTL interface has a termination resistor connected to a voltage that is half the power supply voltage of the DDR memory. For example, in the case of a DDR3-SDRAM, since the power supply voltage is 1.5V, 0.75V is connected to the termination resistor. In the DDR3-SDRAM, this termination resistor is built in the DDR memory at the DQ pin, the DQS pin, and the DM pin, and it is recommended that the termination resistor be mounted in the vicinity of the control signal pins such as an address. The direction of the current flowing through the termination resistor _RT varies depending on the output signal level of each terminal of the controller. When the output signal is High, the current is in the source direction, and when the output signal is Low, the current is in the sink direction.

  There are mainly three possible circuit configurations (topologies) using the DDR memory.

  The first is a topology in which a memory controller 51 mounted on a CPU or FPGA and a DDR memory (DDR_a) 52 are connected one-to-one as shown in FIG. 3 as a basic configuration. All control signals such as addresses and data are connected to the memory controller 51 on a one-to-one basis.

  The second is a topology in which one controller 51 is connected to a plurality of (four in FIG. 4) DDR memories (DDR_a to DDR_d) 52-1 to 52-4 in a tree form as shown in FIG. . This topology is adopted in, for example, DDR2-SDRAM and is called a T branch topology. A control signal such as an address is branched from the memory controller 51 and connected to each DDR memory (DDR2-SRAM) 52-1 to 52-4, and data is stored in the memory controller 52 and each DDR memory 52-. It becomes the structure connected by 1 to 1 with 1-52-4.

  Finally, as shown in FIG. 5, the third one is connected in cascade from one memory controller 51 to a plurality (four in FIG. 5) of DDR memories (DDR_a to DDR_d) 52-1 to 52-4. Topology. This topology is adopted from, for example, DDR3-SDRAM and is called a fly-by topology. Address, command, and clock control signals are connected in cascade to all DDR memories (DDR3-SDRAM), and data is input / output in consideration of the difference in signal arrival times to each device. Control is in progress. The data is configured to be connected on a one-to-one basis between the memory controller 51 and each of the DDR memories 52-1 to 52-4.

  For example, there is Patent Document 1 that uses the characteristics of the DDR memory as described above. In the technique described in Patent Document 1, there is data correlation between adjacent pixels of an image. In other words, by using the same data, one of the pixel data is inverted and written to the DDR memory, so that the sink current and the source current of the DQ are offset to suppress current consumption It is.

JP 2007-41668 A

JEDEC JESD79-3F DDR3 SDRAM STANDARD

  However, since the technique described in Patent Document 1 described above requires that the data to be handled is image data, there is a problem that it cannot be used with other data.

  Therefore, it is desired to be easily affected by noise due to high-density mounting on the memory device, and to reduce the power consumption of the device, that is, to reduce the power consumption of the circuit from the viewpoint of eco.

  The sink current and source current of the data bus (DQ) of the DDR memory are canceled out, and only the terminal current of the difference terminal flows to the Vtt power source.

  Therefore, the present invention pays attention to the fact that the termination current does not flow in the Vtt power supply when the number of output signal levels is high and low, and converts the data so that the number of high and low is as equal as possible. An object of the present invention is to provide a memory device writing and reading control method and a memory device that can suppress power consumption of a circuit, suppress current consumption, suppress noise, and reduce a risk of malfunction. Is.

  In order to solve such a problem, the write and read control method for the memory device according to the first aspect of the present invention supplies power to the memory device by changing the direction of the current flowing through the termination resistor according to the output state of the memory device. A method for controlling writing to and reading from a memory device including a power supply interface unit, wherein (1) a bit string of input data is converted into a bit string including a logical value with a low power consumption value, and the converted bit string is converted into a memory device And (2) a read step of reading data by reversely converting the converted bit string written in the memory device into a bit string before writing.

  According to a second aspect of the present invention, there is provided a memory device including: a power supply interface unit that supplies power to the memory device by changing a direction of a current flowing through the termination resistor according to an output state of the memory device; And a writing means for writing the converted bit string into a bit string including a logical value with a low power consumption value, and (2) reverse-converting the converted bit string written in the memory device into the bit string before writing. And reading means for reading data.

  According to the present invention, data is converted so that the number of high and low output signal levels is equal, the power consumption of the circuit is reduced, the current consumption is reduced, the generation of noise is suppressed, and the risk of malfunction is reduced. Can be reduced.

It is a block diagram which shows the structure of the memory controller which concerns on embodiment. It is a circuit diagram which shows the structure of the SSTL interface employ | adopted as a DDR memory. It is a circuit diagram which shows the circuit structure of the conventional DDR memory (the 1). It is a circuit diagram which shows the circuit structure of the conventional DDR memory (the 2). It is a circuit diagram which shows the circuit structure of the conventional DDR memory (the 3). It is a block diagram which shows the structure of the conversion table concerning 5B / 6B code conversion and 3B / 4b code conversion which concerns on embodiment. It is a flowchart which shows operation | movement of the 8B / 10B code conversion process which concerns on embodiment. It is a figure which shows the example allocated to 5 bit group and 3 bit group from LSB of the data before code conversion which concerns on embodiment. It is a figure which shows the example which allocated the data before the encoding conversion which concerns on embodiment at random to 3bit group and 5bit group.

(A) Main Embodiments Hereinafter, embodiments of a data write / read control method and a memory device according to the present invention will be described in detail with reference to the drawings.

(A-1) Configuration of Embodiment FIG. 1 is a configuration diagram illustrating a configuration of a memory controller according to the embodiment. FIG. 1 shows a configuration when the memory controller 1 is connected to a DDR memory unit 2 as a memory device.

  The DDR memory unit 2 includes a plurality of DDR memories, and each DDR memory constituting the DDR memory unit 2 is connected to the memory controller 1. In addition, each DDR memory constituting the DDR memory unit 2 includes an SSTL 21 as a power supply interface in order to reduce signal degradation caused by noise and reflection caused by an increase in operating frequency. For example, DDR-SDRAM, DDR2-SDRAM, DDR3-SDRAM or the like can be applied to each DDR memory constituting the DDR memory unit 2.

  The memory controller 1 performs writing and reading with respect to a plurality of DDR memories constituting the DDR memory unit 2. As shown in FIG. 1, the memory controller 1 includes a memory controller unit 11, a control unit 12, and an 8B / 10B encoder / decoder unit 13.

  For example, a CPU or FPGA can be applied to the control unit 12.

  The memory controller unit 11 is connected to the DDR memory unit 2 via an address / control line 32 and a data bus 32, and receives control signals and data signals such as addresses under the control of the control unit 12. is there. Since the memory controller unit 11 can apply an existing memory controller, a detailed description thereof is omitted here.

  When writing data to the DDR memory unit 2, the 8B / 10B encoder / decoder unit 13 converts data (8-bit data) from the control unit 12 from 8-bit data to 10-bit data, and the converted 10-bit data is stored in the memory. This is given to the controller unit 11. Further, when reading data from the DDR memory unit 2, the 8B / 10B encoder / decoder unit 13 converts the 10-bit data from the memory controller unit 11 into 8-bit data, returns it to the original 8-bit data, and gives it to the CPU 12 .

(A-2) Operation of Embodiment Next, the operation of the write control and read control processing to the memory device 2 in the memory controller 1 according to this embodiment will be described in detail with reference to the drawings.

  The DDR memory unit 2 includes a plurality of DDR memories as described above, and the memory controller 1 performs data writing and data reading with respect to the plurality of DDR memories.

  For example, if the data bus (DQ) is composed of five 16-bit DDR memories, the control unit 12 including the DDR memory unit 2 and the memory controller unit 11 is connected by an 80-bit data bus 32.

  Data to be written to each DDR memory of the DDR memory unit 2 from the control unit 12 such as a CPU is given to the 8B / 10B encoder / decoder unit 13. In the 8B / 10B encoder / decoder unit 13, the 8-bit data from the control unit 12 is converted into 10-bit data, so the data has an overhead of 20%. That is, out of 80 bits, 64 bits are valid data from the control unit 12, and the remaining 16 bits are overhead.

  The 8B / 10B encoder / decoder unit 13 embeds a clock in serial data to transfer the data and the clock with the same signal, and is used for high-speed serial communication. Here, since the data transfer destination regenerates the clock, the system is devised so that there is no bias in the appearance of bit 0 and bit 1.

  For example, this reproduction method divides 8-bit data into 3 bits and 5 bits, performs 3B / 4B code conversion processing that converts 3 bits into 4 bits, and performs 5B / 6B code conversion processing that converts 5 bits into 6 bits, and converts them into 3 bits and 5 bits. 1 bit is added to each divided and converted to 6 bits and 4 bits.

  FIG. 6 is a configuration diagram illustrating a configuration of a conversion table related to 5B / 6B code conversion and 3B / 4B code conversion according to the embodiment. 6A is a 5B / 6B code conversion table, and FIG. 6B is a 3B / 4B code conversion table.

  In FIG. 6A, for 5B / 6B code conversion, the difference between the number of bits 0 and the number of bits 1 (see FIG. 6A) for the bit string after the conversion of the 5 bit data before conversion into 6 bit data. ) Is expressed as “01 difference”) is “+2” (that is, the number of bits 1 is “+2” more than the number of bits 0) or “0” (that is, the difference is “0”). The difference between the number of 32 conversion patterns and the number of bits 0 and 1 is “−2” (bit 1 is “−2”) or “0” (that is, the difference is “0”). There is a conversion pattern.

  Also, in FIG. 6B, similarly for 3B / 4B code conversion, the difference between the number of bits 0 and the number of bits 1 in the converted bit string obtained by converting the 3-bit data before conversion into 4-bit data ( There are 8 conversion patterns with “01 difference”) of “+2” or “0” and 8 conversion patterns with the difference between the number of bits 0 and 1 being “−2” or “0”.

  Thus, the imbalance between the difference between the number of bits 0 and the number of bits 1 is called running disparity and represents whether the bit sequence of the code-converted data is biased to bit 0 or bit 1. ing. When the number of bits 0 is larger than bit 1, it is expressed as “RD−”, and when the number of bits 1 is larger than bit 0, it is expressed as “RD +”. When code conversion is performed in the RD + state, the RD- pattern is selected. On the other hand, in the RD- state, the RD + pattern is selected during code conversion. However, if the number of bits 1 is the same as the number of bits 0, the polarity of RD is continued. By detecting a violation of polarity using this property, it is also possible to detect that an error is included in previous transmission data.

  For example, the 8B / 10B encoder / decoder unit 13 considers valid 64-bit data before code conversion as 64-bit serial data and performs 8B / 10B code conversion processing. It is arbitrary how 64 bits are divided into a 3 bit group and a 5 bit group, but the 3 bit group and the 5 bit group are arranged alternately. Further, whether the initial value of RD is “−” or “+” is arbitrary. However, it is necessary to unify the method of dividing the 3 bit group and the 5 bit group, the arrangement, and the initial value of the RD once determined as the setting.

  FIG. 7 is a flowchart showing an operation of 8B / 10B code conversion processing according to the embodiment.

  FIG. 8 is a diagram illustrating an example in which LSB (least significant bit) of data before code conversion is assigned to a 5-bit group and a 3-bit group. That is, as shown in FIG. 8, 5 bits are assigned to the 5-bit group in order from the LSB, and the next 3 bits are assigned to the 3-bit group.

  FIG. 9 is a diagram illustrating an example in which pre-encoding data is randomly assigned to a 3-bit group and a 5-bit group. In other words, in FIG. 9, the first bit of 8 bits is assigned to the 3-bit group, and the next 7 bits are randomly assigned to the 3-bit group and 5-bit group. However, each bit of the 7-bit sequence excluding the first bit is assigned to the 3-bit group. The regularity distributed to any of the 5-bit groups is made consistent. In FIG. 9, the first bit is distributed to the 3-bit group. However, if regularity can be maintained, the first bit may be distributed to the 5-bit group.

  The 8B / 10B encoder / decoder unit 13 outputs the 80-bit data after code conversion as it is via the memory controller unit 11 from a terminal of a device such as a CPU including the memory controller 1 and writes it to the DDR memory unit 2 Is implemented.

  Here, the operation when the data from the control unit 12 is written in the DDR memory unit 2 will be specifically described. Here, a description will be given using the allocation method illustrated in FIG.

  For example, the case where the write data from the control unit 12 is 64 bits and the write data is “000_00000_000_00000_000_00000_000_00000_000_00000_000_00000_000_00000_000_00000” (all zeros) is exemplified.

  The 8B / 10B encoder / decoder unit 13 assigns all zero-bit 64-bit data to the 5-bit group and 3-bit group in order from the least significant bit, and converts the data into 80-bit data. At this time, when the initial value of the RD is set to “−” for 80-bit data (S101), 5 bits (00000) of the least significant bit to the fifth bit are “RD-” in the 5B / 6B code conversion table. (111001) because it is converted into the pattern (S102).

  Next, the 8B / 10B encoder / decoder unit 13 obtains a cumulative difference between bit 0 and bit 1 of the bit string after the code conversion until immediately before (S103), and the processing is performed when the number of bits 0 <the number of bits 1 The process proceeds to S104. If the number of bits 0 = the number of bits 1, the process proceeds to S105. If the number of bits 0> the number of bits 1, the process proceeds to S106.

  For example, the 8B / 10B encoder / decoder unit 13 performs 3B / 4B code conversion on 3 bits (000) of the 6th to 8th bits, but the bit string (111001) after the code conversion up to immediately before is bit 1 Since “RD +” is more by 2 bits, the process proceeds to S104. Then, the 8B / 10B encoder / decoder unit 13 refers to the 3B / 4B code conversion table and converts the 6th to 8th bits of 3 bits (000) into the pattern “RD +” of the 3B / 4B code conversion table. Convert to (0010). As described above, 1st to 8th bit code conversion can be performed.

  Next, the 8B / 10B encoder / decoder unit 13 similarly performs 5B / 6B code conversion on the 5 bits (00000) of the 9th to 13th bits above it. At this time, since code conversion has not been completed for all bits (S107), the 8B / 10B encoder / decoder unit 13 accumulates the difference between bit 0 and bit 1 of the bit string after code conversion up to immediately before the code converted bit. If the number of bits 0 <the number of bits 1, the process proceeds to S109. If the number of bits 0 = the number of bits 1, the process proceeds to S110, where the number of bits 0> bits. If the number is 1, the process proceeds to S111.

  For example, when code conversion is performed on the 9th to 13th bits of 5 bits (00000), the bit string after the code conversion up to immediately before is (1110010010). At this time, since the number of bits 0 is equal to the number of bits 1 in the bit string after the previous code change (the number of bits 0 and 1 is “5”), RD + is set in the 5B / 6B code conversion. The 5 bits (00000) of the 9th to 13th bits are converted into the RD + pattern (000110) of the 5B / 6 code conversion table.

  When all the 64-bit write data from the control unit 12 is converted in this way, the converted 80-bit data becomes “1101_000110_0010_111100_11101_000110_0010_111110_1110_10001101_0010_1111001_1101_000110_0010_111001”.

  In this 80-bit bit string, the difference between the number of bits 0 and 1 is 0. Of the 80-bit data bus 32 that connects a terminal of a device including the memory controller unit 11 such as a CPU and the DQ terminal of the DDR memory, a sink current flows in the bit 0 bus and a source current flows in the bit 1 bus.

  For example, if the sink / source current is 10 mA, the sink current is 10 mA × 80 bits and the Vtt power supply supplies a current of 800 mA in the configuration without the conventional 8B / 10B encoder / decoder unit 13. On the other hand, according to the memory controller 1 of this embodiment, the sink current is 10 mA × 40 bits, the source current is 10 mA × 40 bits, and the sink current and the source current cancel each other because the directions of the currents are opposite to each other. Thus, the current flowing through the Vtt power supply becomes zero.

  Next, an operation when the control unit 12 reads data from the DDR memory unit 2 will be described.

  When the control unit 12 such as a CPU performs reading from the DDR memory unit 2, the data output from the DDR memory unit 2 is input to the 8B / 10B encoder / decoder unit 13 via the memory controller unit 11. Is done. The 8B / 10B encoder / decoder unit 13 converts the input 80 bits into 64 bits and provides the same to the control unit 2.

  For example, in the above description of the operation of the writing process, a case where data is read from an address written in the DDR memory unit 2 is illustrated. At this time, the 80-bit bit string output from the DDR memory unit 2 becomes “1101_000110_0010_1111001_1101_000110_0010_1111001_1101_000110_0010_1111001_1101_000110_0010_111001” which is the same as that at the time of writing.

  In bit 0, a sink current flows, and in bit 1, a source current flows. Assuming that the sink / source current is 10 mA, the sink current is 10 mA × 40 bits, the source current is 10 mA × 40 bits, and the directions of the currents are opposite to each other. It becomes.

  The 80-bit data input to the 8B / 10B encoder / decoder unit 13 via the memory controller unit 11 starts with “RD− (because the initial RD at the time of writing is −)” in the 5B / 6B code conversion table. The 6-bit (111001) pattern of the 1st to 6th bits of the least significant bit is searched and restored to the corresponding original data (00000).

  Here, the 8B / 10B encoder / decoder unit 13 calculates the cumulative difference between bit 0 and bit 1 of the bit string (6 bits from the first bit to the sixth bit) (111001) after the code conversion until immediately before, as the number of bits 0. <The number of bits 1

  Next, the 8B / 10B encoder / decoder unit 13 searches the 7-bit to 10-bit 4 bits (0010) above it from “RD +” in the 3B / 4B code conversion table, and the 7th to 10th bits. Are restored to the original data (000).

  Thereafter, when the data is restored in the same manner, the 64-bit data becomes “000_00000_000_00000_000_00000_000_00000_000_00000_000_00000_000_00000_000_00000” (all zeros), and can be restored to the original data.

  When restoring to the original data using each code conversion table, if the pattern does not exist in the code conversion table, it is detected that a bit error (error) has occurred during writing or reading. It is possible.

  Up to now, the DDR memory unit 2 has been described as having five individual DDR memory devices. However, for example, writing or reading is performed on a DIMM (Dual Inline Memory Module) configured by a plurality of DDR memories. It is good also as a structure. In general, a DIMM is a data bus of 64 bits or more. Therefore, considering a data bus of 64 bits, data to be written from the control unit 2 such as a CPU to the DDR memory unit 2 is 8B / 10B encoder / decoder unit 8B. The / 10B code conversion has an overhead of 20%. That is, 48 bits out of 64 bits are valid data from the control unit 2, 12 bits are overhead, and the remaining 4 bits are unused.

(A-3) Effect of Embodiment As described above, according to this embodiment, the data bus at the time of data writing to and reading from the DDR memory is obtained by performing 8B / 10B code conversion on the data to be written to the DDR memory. The difference between the number of high level bits and the number of low level bits is ± 2 or 0. The sink current and source current flowing through the termination resistor of the SSTL interface of the data bus are all canceled out when the difference between the number of bits of High and Low is 0, and no current is consumed as the power supply for the termination resistor. . Further, even when the difference between the number of bits of High and Low is ± 2, most of the sink current and source current are canceled out, and an effect that a minimum current consumption is sufficient for the power supply can be obtained. In addition, since the current consumption is kept as low as possible, the current does not change abruptly, that is, the magnetic field or the electric field does not change abruptly, so that the generation of noise can be suppressed and the risk of malfunction can be reduced. .

  Further, according to this embodiment, when restoring to the original data by 8B / 10B code conversion, if the data read from the DDR memory is not in the code conversion table, an error is detected as erroneous data. Is possible.

(B) Other Embodiments In the above-described embodiments, the DDR memory having the SSTL interface has been described. However, the QDR memory having the HSTL interface can be applied because the same termination resistor is used.

  DESCRIPTION OF SYMBOLS 1 ... Memory controller, 11 ... Memory controller part, 12 ... Control part, 13 ... 8B / 10B encoder / decoder part, 2 ... DDR memory part, 21 ... SSTL interface, 31 ... Address / control line, 32 ... Data bus.

Claims (9)

A method of controlling writing and reading to a memory device including a power supply interface unit that supplies power to the memory device by changing a direction of a current flowing through a termination resistor according to an output state of the memory device,
A step of converting the bit string of the input data into a bit string including a logical value with a low power consumption value, and writing the converted bit string into the memory device;
A method for controlling writing to and reading from a memory device, comprising: a step of reversely converting the converted bit string written in the memory device into a bit string before writing and reading the data. The writing step is
The bit string of the input data is converted into the bit string after conversion so that the number of different logical values constituting the bit string after conversion is the same number or an approximate number,
The method for controlling writing and reading in a memory device according to claim 1, wherein an output signal corresponding to the converted bit string is written in the memory device. The writing step is
The input data bit string is converted into the converted bit string so that the source current and the sink current flowing through the termination resistor of the power supply interface unit are offset,
The method for controlling writing and reading in a memory device according to claim 1, wherein an output signal corresponding to the converted bit string is written in the memory device. The writing step converts a bit string of input data into the converted bit string using a predetermined code conversion table,
The method for controlling writing and reading to a memory device according to any one of claims 1 to 3, wherein the reading step reversely converts the converted bit string using the predetermined code conversion table. The writing step converts 8 bits included in the bit string of the input data into 10 bits,
5. The method for controlling writing and reading in a memory device according to claim 1, wherein the reading step converts 10 bits included in a bit string after conversion from the memory device into 8 bits. The writing step is
8 bits extracted from a bit string of input data are assigned to a 3 bit group or a 5 bit group according to a predetermined rule,
Convert 3 bit group to 4 bit group,
6. The method of controlling writing and reading to a memory device according to claim 5, wherein the 5-bit group is converted into a 6-bit group. The writing step is
8 bits extracted from the bit string of the input data are assigned to 5 bit groups or 3 bit groups according to a predetermined rule,
Convert 5 bit group to 6 bit group,
6. The method for controlling writing and reading to a memory device according to claim 5, wherein a 3-bit group is converted into a 4-bit group.   8. The memory device according to claim 1, wherein the reading step confirms whether or not there is an error in writing based on a result of reverse conversion of the bit string after conversion and restoration to data. 9. Write and read control method. In a memory device including a power supply interface unit that supplies power to the memory device by changing the direction of the current flowing through the termination resistor according to the output state of the memory device,
A writing means for converting a bit string of input data into a bit string including a logical value with a low power consumption value and writing the bit string after the conversion;
A memory device comprising: a reading unit that reversely converts the converted bit string written in the memory device into a bit string before writing and reads data.

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