JP2016165056A - Parallel-serial conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parallel-serial conversion circuit capable of ensuring sure bit conversion timing with the suppression of the increase of a consumption current and a circuit area.SOLUTION: The parallel-serial conversion circuit includes: a 4-input 1-output multiplexer 301 which converts 4-bit parallel data into 1-bit serial data; a delay part 200 which adjusts the input timing of the 4-bit data input to the 4-input 1-output multiplexer 301; and a clock generator circuit 401 which generates a clock signal to decide the operation timing of the 4-input 1-output multiplexer 301 and the delay part 200. The 4-input 1-output multiplexer 301 includes: a data input part having 4 sets of differential pairs; a data selection part having 4 sets of switch parts composed of 2-stage cascade connections of switches and respectively corresponding to the 4 sets of differential pairs; and a load resistor part which is a load for the 4 sets of differential pairs.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a parallel-serial conversion circuit of a high-speed serial interface, and more particularly to a parallel-serial conversion circuit that converts a 4-bit parallel signal into a 1-bit serial signal. In particular, it can be applied to a parallel-serial conversion semiconductor integrated circuit (LSI).

  In recent years, in the communication field, transmission data has been increased in speed as the amount of data communication increases. For example, high-speed transmission data is generated from a plurality of low-speed parallel data using a parallel-serial conversion circuit. This type of parallel-serial conversion circuit is configured to adjust the data input timing of a plurality of input data using setup or hold by a plurality of latch circuits or flip-flop circuits driven by a clock signal.

  Multi-bit parallel-serial conversion is generally performed in combination with a parallel-serial conversion circuit that performs conversion from 2 bits to 1 bit (see, for example, Patent Document 1). For example, when 4-bit to 1-bit conversion is performed, three parallel-serial conversion circuits that perform 2-bit to 1-bit conversion are used to perform bit conversion in two stages. Specifically, two parallel-serial conversion circuits are arranged in parallel in the first stage, and their outputs are subjected to 2-bit to 1-bit parallel-serial conversion by the second-stage parallel-serial conversion circuit.

FIG. 1 is a circuit configuration diagram for explaining a conventional parallel-serial conversion circuit that performs conversion from 2 bits to 1 bit.
When performing conventional 2-bit to 1-bit parallel-serial conversion of high-speed data, as shown in FIG. 1, it is used for input data timing adjustment composed of current mode logic (CML; Current Mode Logic) capable of high-speed operation. First to fifth CML LATCH 1 to 5 (latch circuits) 13 to 17, a delay buffer 12 for adjusting an operation clock timing, and a CML multiplexer (CML MUX / hereinafter referred to as a multiplexer) that converts 2-bit data into 1-bit data 18 is used.

  That is, the parallel-serial conversion circuit shown in FIG. 1 has an input terminal 11 that supplies a clock signal CLKP-CLKN, a delay buffer 12 connected to the input terminal 11, and first to third terminals connected to the delay buffer 12. Fifth latch circuits 13 to 17, a multiplexer (selection circuit) 18 connected to the third and fifth latch circuits 15 and 17, and an output terminal 19 connected to the multiplexer 18 are provided. .

The input terminal 11 outputs the input clock signal CLKP-CLKN to the delay buffer 12 and the multiplexer 18. The delay buffer 12 delays the clock signal CLKP-CLKN supplied from the input terminal 11 and outputs the delayed clock signal to the first to fifth latch circuits 13 to 17 as the clock signal CKDATAP-CKDATAN.
The clock signals CKDATAP-CKDATAN output from the delay buffer 12 are inverted and input to the second and fifth latch circuits 14 and 17. The clock signal CKDATAP-CKDATAN output from the delay buffer 12 is input to the first, third, and fourth latch circuits 13, 15, and 16.

  The first input terminal 1 to which the first input data is input outputs the input data D0P-D0N to the fourth latch circuit 16. The first input data D0P-D0N input to the fourth latch circuit 16 is sequentially latched by the fourth and fifth latch circuits 16 and 17 based on the clock signal CKDATAP-CKDATAN. The first input data D0P-D0N sequentially latched by the fourth and fifth latch circuits 16 and 17 are delayed by a half cycle of the clock signal CLKP-CLKN and output to the multiplexer 18 as intermediate data L0P-L0N. The

The second input terminal 2 to which the second input data is input outputs the input data D1P-D1N to the first latch circuit 13. The second input data D1P-D1N input to the first latch circuit 13 is sequentially latched by the first to third latch circuits 13 to 15 based on the clock signal CKDATAP-CKDATAN. The second input data D1P-D1N sequentially latched by the first to third latch circuits 13 to 15 are delayed by one cycle of the clock signal CLKP-CLKN and output to the multiplexer 18 as intermediate data L1P-L1N. The
Accordingly, the intermediate data L0P-L0N and the intermediate data L1P-L1N input to the multiplexer 18 are 180 degrees out of phase with each other.

  The multiplexer 18 receives the clock signal CLKP-CLKN supplied from the input terminal 11. The multiplexer 18 outputs the intermediate data L1P-L1N to the output terminal 19 in synchronization with the falling edge of the clock signal CLKP-CLKN, and outputs the intermediate data L0P-L0N in synchronization with the rising edge of the clock signal CLKP-CLKN. Output to. The output terminal 19 outputs the intermediate data L1P-L1N and the intermediate data L0P-L0N alternately output from the multiplexer 18 as serial data OUTP-OUTN.

FIG. 2 is a circuit configuration diagram for explaining the multiplexer shown in FIG.
As described above, the multiplexer 18 that converts 2-bit data into 1-bit data controls the ON / OFF of the MOS transistor with the high-low of the clock signal CLKP-CLKN and switches the current path as shown in FIG. Which of the inputs to output is selected.

FIGS. 3A to 3G are diagrams showing parallel-serial conversion timings of the parallel-serial conversion circuit that performs the conversion from 2 bits to 1 bit shown in FIG.
The input data D0P-D0N shown in FIG. 3C passes through the fourth and fifth latch circuits 16 and 17, whereas the input data D1P-D1N shown in FIG. As shown in FIGS. 3 (e) and 3 (f), two intermediate data L0P-L0N and L1P-L1N shifted by half a clock cycle are passed through the first to third latch circuits 13 to 15, and are multiplexed. 18 is input.

  As for the data input to the multiplexer 18, intermediate data L0P-L0N is output while the clock signal CLKP is High, and intermediate data L1P-L1N is output while the clock signal CLKN is High. However, if the first and second input data D0P-D0N and D1P-D1N change while the clock signal CLKP-CLKN shown in FIG. 3B is fetched while the clock signal is High, the intermediate data L0P- that is the output thereof changes. Since the length of L0N, L1P-L1N does not become a half cycle of the clock signal CLKP-CLKN, eye pattern deterioration and output error, which are indicators of signal quality, are caused.

  Therefore, when the parallel-serial conversion circuit having this configuration is operated at high speed, the clock signals CKDATA-CKDATAN for the operations of the first to fifth latch circuits 13 to 17 as shown in FIG. It is necessary to adjust the timing by inserting the delay buffer 12 as shown in FIG. 1 between the clock signal CLKP-CLKN for the operation of the multiplexer 18.

U.S. Pat. No. 8,044,833

However, when multi-bit parallel-serial conversion is performed, for example, when converting 4 bits to 1 bit, two sets of parallel-serial conversion circuits that perform conversion from 2 bits to 1 bit are required. Therefore, a latch circuit (CML LATCH) ) Is 15 in total, which increases the power consumption and the circuit scale.
Furthermore, when performing high-frequency operation, there is a problem that a delay buffer is required to perform reliable data selection by shifting the timing of the input data and the input clock of the multiplexer for the purpose of preventing deterioration of the output signal quality.
The present invention has been made in view of such problems, and its purpose is to convert a 4-bit parallel signal into a 1-bit serial signal, and to suppress a consumption current and an increase in circuit area to ensure reliable bit conversion timing. An object of the present invention is to provide a parallel-serial conversion circuit which can be secured.

In the first aspect of the present invention, a 4-input 1-output multiplexer that converts 4-bit parallel data into 1-bit serial data, and a delay unit that adjusts the input timing of the 4-bit data input to the 4-input 1-output multiplexer And a 4-to-1 output multiplexer, and a clock generation circuit for generating a clock signal for determining an operation timing of the delay unit, wherein the 4-input 1-output multiplexer includes four sets A data input unit having four differential pairs, a data selection unit corresponding to each of the four pairs of differential pairs of the data input unit, and four switch units in which switches are cascade-connected in two stages, And a load resistance unit serving as a load of the four differential pairs of the data input unit.
In addition, the aspect mentioned above does not describe all the necessary characteristic configurations of the present invention, and the present invention can be configured by combining other configurations.

According to the present invention, a four-input one-output multiplexer can be realized by using a two-stage switch for switching the current path of the multiplexer. As a result, when performing parallel-serial conversion for converting from 4 bits to 1 bit, the number of multiplexers and the number of latch circuits for data timing adjustment can be reduced, and current consumption and circuit scale can be reduced. .
Also, by adjusting the data input timing to the 4-input 1-output multiplexer, the delay buffer for timing adjustment, which was necessary in the conventional configuration, is no longer necessary. In this respect as well, current consumption and circuit scale can be reduced. It becomes.

It is a circuit block diagram for demonstrating the conventional parallel-serial conversion circuit which performs conversion of 2 bits to 1 bit. It is a circuit block diagram for demonstrating the multiplexer shown in FIG. (A) thru | or (g) is a figure which shows the parallel-serial conversion timing of the parallel-serial conversion circuit which performs the conversion of the conventional 2 bits to 1 bit shown in FIG. It is a block diagram for describing an embodiment of a parallel-serial conversion circuit according to the present invention. FIG. 5 is a circuit configuration diagram for explaining the 4-input 1-output multiplexer shown in FIG. 4. FIG. 5 is a circuit configuration diagram for explaining a clock generation circuit that supplies a clock signal to the 4-input 1-output multiplexer and each latch circuit shown in FIG. 4. (A) thru | or (p) are the figures which show the parallel-serial conversion timing of the parallel-serial conversion circuit which performs conversion of 4 bits to 1 bit shown in FIG.

  In the following detailed description, numerous specific specific configurations are described to provide a thorough understanding of embodiments of the invention. However, it will be apparent that other embodiments may be practiced without limitation to such specific specific configurations. Further, the following embodiments do not limit the invention according to the claims, but include all combinations of characteristic configurations described in the embodiments.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 4 is a block diagram for explaining an embodiment of a parallel-serial conversion circuit according to the present invention. A four-input one-output multiplexer and first to tenth LATCHs (latch circuits) 201 to 201 for data timing adjustment. 2 is a diagram illustrating a parallel-serial conversion circuit that performs conversion from 4 bits to 1 bit using 210. FIG.

The parallel-serial conversion circuit of this embodiment includes a 4-input 1-output multiplexer 301 that converts 4-bit parallel data into 1-bit serial data, and a delay that adjusts the input timing of 4-bit data input to the 4-input 1-output multiplexer 301. Unit 200, a 4-input 1-output multiplexer 301, and a clock generation circuit 401 that generates a clock signal that determines the operation timing of the delay unit 200.
The delay unit 200 includes a plurality of latch circuits 201 to 210 that delay the third bit data and the fourth bit data by a half cycle of the operation clock with respect to the first bit data and the second bit data of the 4 bit data.

  In addition, the parallel-serial conversion circuit of the present embodiment includes first to third input terminals 111, 112, and 113 that supply first to third clock signals and a third input terminal 113 that is connected to the third input terminal 113. First to fourth input data are supplied to the first to tenth latch circuits 201 to 210 and the first, third, fifth, and eighth latch circuits 201, 203, 205, and 208, respectively. Multiplexer 301 connected to first to fourth input terminals 101 to 104 and second, fourth, seventh, and tenth latch circuits 202, 204, 207, and 210, and connected to multiplexer 301 Output terminal 119.

The first input terminal 111 is connected to the multiplexer 301 and supplied with a first clock signal CLKP-CLKN from a clock generation circuit 401 described later. The second input terminal 112 is connected to the multiplexer 301 and supplied with a second clock signal CKDIV_DLYP-CKDIV_DLYN from a clock generation circuit 401 described later. The third input terminal 113 is connected to the multiplexer 301 and the first to tenth latch circuits 201 to 210, and supplied with a third clock signal CDIPIVP-CKDIVN from a clock generation circuit 401 described later. 3 clock signals CKIDIVP-CKDIVN are output to the first to tenth latch circuits 201 to 210.
The third clock signal CDIPIVP-CKDIVN is inverted and input to the second, fourth, sixth, and ninth latch circuits 202, 204, 206, and 209. The first, third, fifth, seventh, eighth, and tenth latch circuits 201, 203, 205, 207, 208, and 210 receive the third clock signal CDIVP-CKDIVN.

  The first input terminal 101 to which the first input data D0P-D0N is supplied is connected to the first latch circuit 201, and outputs the first input data D0P-D0N to the first latch circuit 201. The first input data D0P-D0N input to the first latch circuit 201 is sequentially latched by the first and second latch circuits 201, 202 based on the third clock signal CDIPIVP-CKDIVN. The first input data D0P-D0N sequentially latched by the first and second latch circuits 201, 202 are output to the multiplexer 301 as intermediate data L0P-L0N.

  The second input terminal 102 to which the second input data D1P-D1N is supplied is connected to the third latch circuit 203, and outputs the second input data D1P-D1N to the third latch circuit 203. The second input data D1P-D1N input to the third latch circuit 203 is sequentially latched by the third and fourth latch circuits 203 and 204 based on the third clock signal CDIPIVP-CKDIVN. The second input data D1P-D1N sequentially latched by the third and fourth latch circuits 203, 204 is output to the multiplexer 301 as intermediate data L1P-L1N.

  The third input terminal 103 to which the third input data D2P-D2N is supplied is connected to the fifth latch circuit 205, and outputs the third input data D2P-D2N to the fifth latch circuit 205. . The third input data D2P-D2N input to the fifth latch circuit 205 is sequentially latched by the fifth to seventh latch circuits 205 to 207 based on the third clock signal CDIPIVP-CKDIVN. The third input data D2P-D2N sequentially latched by the fifth to seventh latch circuits 205 to 207 is output to the multiplexer 301 as intermediate data L2P-L2N.

  The fourth input terminal 104 to which the fourth input data D3P-D3N is supplied is connected to the eighth latch circuit 208, and outputs the fourth input data D3P-D3N to the eighth latch circuit 208. The fourth input data D3P-D3N input to the eighth latch circuit 208 is sequentially latched by the eighth to tenth latch circuits 208 to 210 based on the third clock signal CDIVP-CKDIVN. The fourth input data D3P-D3N sequentially latched by the eighth to tenth latch circuits 208 to 210 is output to the multiplexer 301 as intermediate data L3P-L3N.

As described above, the first input data D0P-D0N and the second input data D1P-D1N pass through the first and second latch circuits 201 and 202 and the third and fourth latch circuits 203 and 204, respectively. The intermediate data L0P-L0N and L1P-L1N are input to the 4-input 1-output multiplexer 301.
Further, the third input data D2P-D2N and the fourth input data D3P-D3N pass through the fifth to seventh latch circuits 205 to 207 and the eighth to tenth latch circuits 208 to 210, respectively. The intermediate data L2P-L2N and L3P-L3N are input to the input 1 output multiplexer 301.

Therefore, the third and fourth input data D2P-D2N, D3P-D3N are equal to the first and second input data D0P-D0N, D1P-D1N by a half cycle of the third clock signal CDIVP-CKDIVN. The signal is input to the 4-input 1-output multiplexer 301 with a delay.
The output terminal 119 outputs intermediate data L0P-L0N to intermediate data L3P-L3N alternately output from the multiplexer 301 as serial data OUTP-OUTN.

FIG. 5 is a circuit configuration diagram for explaining the 4-input 1-output multiplexer shown in FIG.
The 4-input 1-output multiplexer 301 corresponds to a data input unit 311 having four differential pairs and four differential pairs of the data input unit 311, and four sets in which switches are cascade-connected in two stages. The data selection unit 312 having the switch unit and the load resistance unit 313 serving as the load of the four differential pairs of the data input unit 311 are provided.

  That is, as shown in FIG. 5, the 4-input 1-output multiplexer 301 can select which of the 4 inputs is output by inserting two current path changeover switches in series. As shown in FIG. 5, the 4-input 1-output multiplexer 301 that converts 4-bit data into 1-bit data controls the on / off of each MOS transistor with High-Low of the clock signals CLKP, CLKN, CKDIVP, CLKDIVN, CKDIV_DLYP, and CKDIV_DLYN. , Which of the four inputs is output is selected by switching the current path.

FIG. 6 is a circuit configuration diagram for explaining a clock generation circuit for supplying a clock signal to the 4-input 1-output multiplexer and the latch circuits shown in FIG.
The clock generation circuit 401 includes a divide-by-2 circuit 410 having two first and second latch circuits 411, 412 that divide the reference clock by two, and a signal obtained by dividing the reference clock by two by the divide-by-2 circuit 410. And a third latch circuit 413 that delays by a half cycle of the reference clock.

That is, the clock generation circuit 401 that supplies a clock signal to the above-described 4-input 1-output multiplexer 301 and the first to tenth latch circuits 201 to 210 has a first latch circuit (CML LATCH_A) as shown in FIG. ) A divide-by-two circuit (DIV2) 410 combining two of the 411 and the second latch circuit (CML LATCH_B) 412 generates a clock signal CKDIVP-CKDIVN divided by two from the reference clock signal CLKP-CLKN. Generate.
In addition, the additionally inserted third latch circuit (CML LATCH_C) 413 generates a clock signal CKDIV_DLYP-CKDIV_DLYN obtained by further delaying the clock signal CKDIVP-CLKDIVN by a half cycle of the clock signal CLKP-CLKN.

FIGS. 7A to 7P are diagrams showing the parallel-serial conversion timing of the parallel-serial conversion circuit that performs the conversion from 4 bits to 1 bit shown in FIG.
The first input data D0P-D0N and the second input data D1P-D1N as shown in FIGS. 7 (h) and (i) are two first and second latch circuits 201 and 202 for data timing adjustment. The intermediate data L0P-L0N and L1P-L1N as shown in FIGS. 7 (l) and 7 (m) are passed through the third and fourth latch circuits 203 and 204 to the 4-input 1-output multiplexer 301, respectively. Whereas the third input data D2P-D2N and the fourth input data D3P-D3N as shown in FIGS. 7J and 7K are input, three fifth to seventh latch circuits 205 are provided. Through 207 and the eighth through tenth latch circuits 208 through 210 to the 4-input 1-output multiplexer 301 to each of the intermediate data L2P-L2N, L3P- as shown in FIGS. L3N is input Therefore, the third and fourth input data D2P-D2N, D3P-D3N are the same as the first and second input data D0P-D0N, D1P-D1N as shown in FIG. It is input to the 4-input 1-output multiplexer 301 with a delay of a half cycle of the clock signal CDIVP-CKDIVN.

  In this way, the current path switching of the 4-input 1-output multiplexer 301 and the internal two-stage switch are the first clock signal CLKP-CLKN serving as a reference and the third clock signal generated by the clock generation circuit 401 described above. Using CKDIVP-CKDIVN and the second clock signal CKDIV_DLYP-CKDIV_DLYN, switching the switch with a combination of two clock signals CLKN and CKDIVN, CLKP and CKDIV_DLYN, CLKN and CKIDIVP, CLKP and CKDIV_DLYP, 1-bit serial data Can be converted to At this time, the total number of latch circuits is ten.

In this way, when performing parallel-serial conversion for converting from 4 bits to 1 bit, the number of multiplexers and the number of latch circuits for data timing adjustment can be reduced, and current consumption and circuit scale can be reduced. is there.
In addition, with respect to the delay of the input data to the 4-input 1-output multiplexer 301 based on the first clock signal CLKP-CLKN, it is theoretically possible to have a margin up to a half cycle of the first clock signal CLKP-CLKN. In addition, since the current path can be switched in a quarter cycle of the input data, a delay buffer for timing adjustment, which has been conventionally required, becomes unnecessary.

  As mentioned above, although embodiment of this invention was described, the technical scope of this invention is not limited to the technical scope as described in embodiment mentioned above. It is possible to add various changes or improvements to the above-described embodiments, and it is possible to add such changes or improvements to the technical scope of the present invention. it is obvious.

  The 4-input 1-output multiplexer of the present invention can realize secure data input / output timing while suppressing increase in current consumption and circuit area, particularly in parallel-serial conversion of high-frequency circuits, and can be used as a high-speed serial interface. Is preferred.

1, 2, 101, 102, 103, 104 Input data input terminals 11, 111, 112, 113 Clock signal input terminals 12 Delay buffers 13 to 17 First to fifth latch circuits 18 CML multiplexer (multiplexer)
19, 119 Output terminal 200 Delay units 201 to 210 First to tenth latch circuits 301 CML multiplexer (multiplexer)
401 clock generation circuit 410 divide-by-2 circuit 411, 412, 413 latch circuit

Claims (5)

A 4-input 1-output multiplexer that converts 4-bit parallel data into 1-bit serial data; a delay unit that adjusts the input timing of the 4-bit data input to the 4-input 1-output multiplexer; the 4-input 1-output multiplexer; A parallel-serial conversion circuit comprising: a clock generation circuit that generates a clock signal that determines an operation timing of the delay unit;
The 4-input 1-output multiplexer is
A data input unit having four differential pairs;
A data selection unit corresponding to each of the four sets of differential pairs of the data input unit and having four sets of switch units in which switches are cascade-connected in two stages;
A load resistance unit serving as a load of the four differential pairs of the data input unit;
A parallel-serial conversion circuit comprising: The clock generation circuit includes:
A divide-by-2 circuit having two first and second latch circuits that divide the reference clock by two;
A third latch circuit that delays a signal obtained by dividing the reference clock by two by the divide-by-2 circuit by a half period of the reference clock;
The parallel-serial conversion circuit according to claim 1, further comprising:   2. The delay unit includes a plurality of latch circuits that delay the third bit data and the fourth bit data by a half cycle of the operation clock with respect to the first bit data and the second bit data of the 4-bit data. Or the parallel-serial conversion circuit of 2. Comprising first to third input terminals to which first to third clock signals from the clock generation circuit are supplied;
4. The device according to claim 1, wherein the first to third input terminals are connected to the four-input one-output multiplexer, and the third input terminal is further connected to the plurality of latch circuits. 2. A parallel-serial conversion circuit according to 1. First to fourth input terminals to which first to fourth input data are supplied;
The first input terminal to which the first input data is supplied is connected to the first latch circuit, and the second input terminal to which the second input data is supplied is the third input terminal. The fourth input terminal connected to the latch circuit and supplied with the third input data is connected to the fifth latch circuit and supplied with the fourth input data. The parallel-serial conversion circuit according to claim 1, wherein the parallel-serial conversion circuit is connected to the eighth latch circuit.

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