JP2016164942A - Manufacturing method of semiconductor device and semiconductor laminate structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress an accumulation of a charge to a semiconductor layer in a wiring forming step using a method with a charge irradiation to the semiconductor layer such as an ionization spatter, without increasing a size of a chip.SOLUTION: A semiconductor substrate including a substrate layer, a first insulation layer provided on the substrate layer, and a semiconductor layer provided on the first insulation layer is prepared. A second insulation layer is formed on a surface of the semiconductor layer. A first contact having a conductivity reaching the semiconductor layer while penetrating the second insulation layer is formed in a device region of the semiconductor substrate defined by a scribe line. A second contact having the conductivity reaching the substrate layer while penetrating the second insulation layer is formed in a region corresponding to the scribe line of the semiconductor substrate. A first wiring electrically connected to the first and second contacts is formed on the surface of the second insulation layer.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor laminated structure.

  An SOI (Silicon On Insulator) substrate has a structure in which a substrate layer and a semiconductor layer formed thereon are insulated and separated by a buried oxide film layer (also referred to as a BOX (Buried Oxide) layer). According to the SOI substrate, it is possible to easily perform insulation isolation between elements formed in the semiconductor layer.

  However, in an SOI device, since the semiconductor layer is insulated and separated from the substrate layer, charges are likely to be accumulated in the semiconductor layer by plasma processing or the like performed in the manufacturing process, and the surface of the semiconductor layer is generated by the electric field generated by this electrification. There is a risk that the gate oxide film formed on the first layer will deteriorate. For example, the following techniques are known as techniques for suppressing charge accumulation in a semiconductor layer of an SOI substrate.

  For example, in Patent Document 1, an insulator layer and a mask layer are formed on a semiconductor layer of an SOI substrate, and a first contact hole and an SOI substrate reaching the substrate layer of the SOI substrate by dry etching through the mask layer. Forming a second contact hole reaching the semiconductor layer and depositing a conductive product produced by dry etching on the inner wall surfaces of the first and second contact holes and the surface of the mask layer. It is described that the layers are electrically connected.

  Further, in Patent Document 2, the surface of the semiconductor substrate under the buried oxide film is exposed by a process using plasma in a scribe line that separates chip regions, thereby releasing charge-up charges generated by the plasma to the semiconductor substrate. It is described.

  In Patent Document 3, a transistor and an element isolation region are formed in a semiconductor layer of an SOI substrate, and these are covered with an insulating film. The SOI film penetrates through the insulating film, the element isolation region, and the buried oxide film layer of the SOI substrate. A first opening that exposes the substrate layer of the substrate is formed, a wiring electrically connected to the transistor, and a wiring connected to the wiring and electrically connected to the substrate layer of the SOI substrate through the first opening. It is described that a dummy wiring is formed on an insulating film. Reference 3 describes that even if charges enter the wiring in the wiring pattern forming step, these charges can be released to the substrate layer of the SOI substrate through the dummy wiring.

JP 2013-191676 A JP-A-9-63994 Japanese Patent Laid-Open No. 2005-5577

  As a method for forming a metal film constituting the wiring of a semiconductor device, an ionized sputtering (IMP) method is known. The ionized sputtering method is a technique in which sputtered particles scattered from a target are ionized and the ionized sputtered particles are drawn perpendicularly to the substrate by applying a bias voltage to the substrate. According to the ionization sputtering method, since the sputtered particles forming the wiring are charged, measures are required to suppress charge accumulation in the semiconductor layer of the SOI substrate.

  The methods described in Patent Documents 1 and 2 described above cannot suppress charge accumulation in the semiconductor layer when forming the wiring. Further, according to the technique described in Patent Document 3, since it is necessary to form a region for releasing electric charges in the semiconductor chip in the substrate layer of the SOI substrate, there is a demerit that the size of the semiconductor chip increases.

  The present invention has been made in view of the above points. In a wiring formation process including a process involving charge irradiation to a semiconductor layer such as ionization sputtering, the charge of the semiconductor layer is not increased without increasing the chip size. It is an object of the present invention to provide a method for manufacturing a semiconductor device and a semiconductor laminated structure capable of suppressing accumulation.

  A semiconductor device manufacturing method according to the present invention includes a substrate layer, a first insulator layer provided on the substrate layer, and a semiconductor layer provided on the first insulator layer. Preparing a second insulator layer on the surface of the semiconductor layer; and in a device region of the semiconductor substrate defined by a scribe line, penetrating through the second insulator layer A step of forming a first contact having conductivity reaching the semiconductor layer, and a conductivity of reaching the substrate layer through the second insulator layer in a region corresponding to the scribe line of the semiconductor substrate. Forming a second contact having, and forming a first wiring electrically connected to the first contact and the second contact on a surface of the second insulator layer. Including .

  A semiconductor multilayer structure according to the present invention includes a substrate layer, a first insulator layer provided on the substrate layer, and a semiconductor layer provided on the first insulator layer, and a scribe line A semiconductor substrate having a device region defined by: a second insulator layer provided on a surface of the semiconductor layer; and passing through the second insulator layer in the device region of the semiconductor substrate, A first contact having conductivity reaching the semiconductor layer and a second contact having conductivity reaching the substrate layer through the second insulator layer in a region corresponding to the scribe line of the semiconductor substrate. A contact and a first wiring provided on a surface of the second insulator layer and electrically connected to the first contact and the second contact.

  According to the method for manufacturing a semiconductor device and the semiconductor multilayer structure according to the present invention, in the wiring formation process using a technique involving charge irradiation to the semiconductor layer such as ionization sputtering, the semiconductor layer can be formed without increasing the chip size. It is possible to suppress the accumulation of electric charges.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. 1 is a plan view of an SOI substrate according to an embodiment of the present invention. It is a top view which shows arrangement | positioning of the contact provided on the scribe line which concerns on embodiment of this invention. It is a top view which shows arrangement | positioning of the contact provided on the scribe line which concerns on embodiment of this invention. It is a top view which shows arrangement | positioning of the contact provided on the scribe line which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding components and parts are denoted by the same reference numerals. 1 to 5 are sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

  First, an SOI substrate 10 configured by laminating a substrate layer 11, a buried oxide film layer (BOX layer) 12, and a semiconductor layer (SOI layer) 13 is prepared (FIG. 1A). The substrate layer 11 can be made of a semiconductor material such as silicon, but is not limited to this, and may be made of a conductor material or the like. The semiconductor layer 13 can be made of a semiconductor material such as silicon, but is not limited to this, and may be made of a semiconductor material other than silicon.

  1 to 5 show a scribe line SL and two device regions D adjacent to each other with the scribe line SL interposed therebetween. FIG. 6 is a plan view of the SOI substrate 10. The scribe line SL is a margin for cutting the SOI substrate 10 by dicing, and extends on the SOI substrate 10 in a lattice shape. The device region D is a rectangular chip region defined by the scribe line SL. That is, in the dicing process, the device region D is cut out as a semiconductor chip by cutting the SOI substrate 10 along the scribe line SL. The SOI substrate 10 is an example of a semiconductor substrate in the present invention. The substrate layer 11 is an example of the substrate layer in the present invention, the buried oxide film layer 12 is an example of the first insulator layer in the present invention, and the semiconductor layer 13 is an example of the semiconductor layer in the present invention.

  Next, the insulating isolation layer 14 that electrically isolates the semiconductor layer 13 into a plurality of regions is formed by a known local oxidation of silicon (LOCOS) method, shallow trench isolation (STI) method, or deep trench isolation (DTI) method. To do. Thereafter, a semiconductor element (not shown) such as a transistor is formed in the semiconductor layer 13 in the device region D of the SOI substrate 10 (FIG. 1B).

  Next, the semiconductor layer 13 and the buried oxide film layer 12 of the SOI substrate 10 are removed in the region corresponding to the scribe line SL by dry etching or wet etching, and the opening 15 is formed. That is, the surface of the substrate layer 11 is exposed in a region corresponding to the scribe line SL (FIG. 1C).

  Next, the alloy layer 16 is formed on the surface of the substrate layer 11 exposed at the bottom surface of the opening 15 (FIG. 2A). The alloy layer 16 plays a role of reducing contact resistance between the substrate layer 11 and a substrate contact 23 described later connected to the substrate layer 11. The alloy layer 16 can be formed, for example, by silicidizing the surface of the substrate layer 11. For example, cobalt is deposited on the exposed portion of the substrate layer 11, and RTA (Rapid Thermal Anneal) treatment is performed. By this heat treatment, cobalt and silicon react to form the alloy layer 16. Thereafter, unreacted cobalt is removed by washing with sulfuric acid / hydrogen peroxide or ammonia. Instead of cobalt, molybdenum, tungsten, titanium, nickel, or the like may be used. The alloy layer 16 may be formed in a salicide process in which an alloy layer is formed in a self-aligned manner on the surfaces of the source, drain, and gate of a transistor (not shown) formed in the device region D. The alloy layer 16 is an example of an alloy layer in the present invention.

Next, the insulator layer 20 is formed so as to cover the entire surface of the semiconductor layer 13 and fill the opening 15 (FIG. 2B). For example, the insulator layer 20 entirely covers the surface of the semiconductor layer 13 with a SiO ₂ film by a CVD (Chemical Vapor Deposition) method using silane (SiH ₄ ) gas and oxygen (O ₂ ) gas as material gases. Is formed. The insulator layer 20 can be made of an insulator other than SiO ₂ . The insulator layer 20 is an example of a second insulator layer in the present invention.

  Next, after a resist (not shown) is formed on the surface of the insulator layer 20 using a known photolithography technique, a contact hole 21 is formed in the insulator layer 20 by etching through the resist. The contact hole 21 is formed at a predetermined position in the device region D and is formed in a region corresponding to the scribe line SL. The contact hole 21 formed at a predetermined position in the device region D reaches the semiconductor layer 13, and the contact hole 21 formed in the region corresponding to the scribe line SL reaches the substrate layer 11. (FIG. 2 (c)).

  Next, a plurality of device contacts 22 and a plurality of substrate contacts 23 having conductivity filling each of the contact holes 21 formed in the insulator layer 20 are formed (FIG. 3A). Each of the device contacts 22 formed in the device region D passes through the insulator layer 20 and reaches the semiconductor layer 13. That is, the device contact 22 is electrically connected to a semiconductor element (not shown) such as a transistor formed in the semiconductor layer 13. On the other hand, each of the substrate contacts 23 formed in the region corresponding to the scribe line SL passes through the insulator layer 20 and reaches the substrate layer 11. That is, each of the substrate contacts 23 is electrically connected to the substrate layer 11 via the alloy layer 16. Since the alloy layer 16 is formed on the surface of the substrate layer 11, the contact resistance between the substrate contact 23 and the substrate layer 11 can be reduced. The upper end surfaces of the device contact 22 and the substrate contact 23 extend substantially in the same plane as the surface of the insulator layer 20. Each of the device contact 22 and the substrate contact 23 is formed by depositing a conductor such as tungsten (W) on the surface of the insulating layer 20 so as to fill each of the contact holes 21 by, for example, a CVD method. It can be formed by removing unnecessary conductors deposited on the surface of the layer 20 by CMP (Chemical Mechanical Polishing) or etch back. The device contact 22 is an example of a first contact in the present invention, and the substrate contact 23 is an example of a second contact in the present invention.

  Next, the wiring 24 constituting the first wiring layer M1 is formed on the surface of the insulator layer 20 by ionization sputtering (FIG. 3B). In this step, a bias voltage is applied to the SOI substrate 10, and ionized metal particles that are the material of the wiring 24 are supplied to the surface of the insulator layer 20. For example, aluminum (Al) can be suitably used as a material constituting the wiring 24, but the material is not limited to this. The wiring 24 is electrically connected to each of the device contacts 22 formed in the device region D, and is connected to each of the substrate contacts 23 formed in a region corresponding to the scribe line SL. That is, the semiconductor layer 13 is electrically connected to the substrate layer 11 via the device contact 22, the wiring 24 and the substrate contact 23. In other words, a conductive path is formed between the semiconductor layer 13 and the substrate layer 11 to electrically connect them. Thereby, the charge injected into the semiconductor layer 13 in this step can move to the substrate layer 11 via the device contact 22, the wiring 24, and the substrate contact 23, and the accumulation of charges in the semiconductor layer 13 is suppressed. . The wiring 24 is an example of a first wiring in the present invention.

  Next, after forming a resist (not shown) on the surface of the wiring 24 using a known photolithography technique, the wiring 24 is patterned by etching through the resist (FIG. 3C). In this step, the wiring portion 24a connected to the device contact 22 of the wiring 24 and the wiring portion 24b connected to the substrate contact 23 of the wiring 24 are separated. That is, the wiring 24 is patterned and the conductive path formed between the semiconductor layer 13 and the substrate layer 11 is separated.

  Next, the insulator layer 30 is formed so as to cover the wiring 24 (wiring portions 24a and 24b) (FIG. 4A). The insulator layer 30 can be formed by a method similar to that of the previously formed insulator layer 20. The insulator layer 30 is an example of a third insulator layer in the present invention.

  Next, after forming a via hole (not shown) in the insulating layer 30 in the region corresponding to the device region D and the scribe line SL, a plurality of conductive vias 32 and 33 filling each of the via holes are formed. (FIG. 4B). Each of the vias 32 formed in the device region D reaches the wiring portion 24 a that penetrates the insulator layer 30 and is connected to the device contact 22 of the wiring 24. That is, the via 32 is electrically connected to the semiconductor layer 13 via the wiring portion 24 a and the device contact 22. On the other hand, each of the vias 33 formed in the region corresponding to the scribe line SL reaches the wiring portion 24 b that penetrates the insulator layer 30 and is connected to the substrate contact 23 of the wiring 24. That is, the via 33 is electrically connected to the substrate layer 11 via the wiring portion 24 b and the substrate contact 23. The vias 32 and 33 can be formed by the same method as the device contact 22 and the substrate contact 23. The via 32 is an example of the first via in the present invention, and the via 33 is an example of the second via in the present invention.

  Next, the wiring 34 which comprises the 2nd wiring layer M2 is formed in the surface of the insulator layer 30 by the ionization sputtering method (FIG.4 (c)). The wiring 34 can be formed by the same method as the wiring 24 in the first wiring layer M1. That is, in this step, a bias voltage is applied to the SOI substrate 10, and ionized metal particles that are the material of the wiring 34 are supplied to the surface of the insulator layer 30. The wiring 34 is electrically connected to each of the vias 32 formed in the device region D, and is connected to each of the vias 33 formed in a region corresponding to the scribe line SL. That is, the semiconductor layer 13 is electrically connected to the substrate layer 11 via the device contact 22, the wiring 24 (wiring portion 24 a), the via 32, the wiring 34, the via 33, the wiring 24 (wiring portion 24 b), and the substrate contact 23. Is done. In other words, a conductive path that electrically connects the semiconductor layer 13 and the substrate layer 11 is formed again. As a result, the charges injected into the semiconductor layer 13 in this step are transmitted through the device contact 22, the wiring 24 (wiring portion 24 a), the via 32, the wiring 34, the via 33, the wiring 24 (wiring portion 24 b), and the substrate contact 23. Therefore, the accumulation of electric charges in the semiconductor layer 13 is suppressed. The wiring 34 is an example of a second wiring in the present invention.

  Next, after a resist (not shown) is formed on the surface of the wiring 34 using a known photolithography technique, the wiring 34 is patterned by etching through the resist (FIG. 5B). In this step, the wiring part 34 a connected to the via 32 of the wiring 34 and the wiring part 34 b connected to the via 33 of the wiring 34 are separated. That is, the wiring 34 is patterned and the conductive path formed between the semiconductor layer 13 and the substrate layer 11 is separated.

  Thereafter, by the same method as described above, formation of an insulator layer, formation of vias, formation of wiring, and patterning of wiring are repeatedly performed to form a plurality of wiring layers (FIG. 5B). FIG. 5B illustrates the configuration of the semiconductor stacked structure 100 having the wiring layers M1 to M5, but the number of wiring layers can be changed as appropriate. Similar to the wirings 24 and 34, the wirings constituting the wiring layers M3 to M5 can be formed by ionization sputtering. Therefore, charges can be injected into the semiconductor layer 13 when forming the wirings constituting the wiring layers M3 to M5. However, the charges injected into the semiconductor layer 13 are provided in regions corresponding to the device region D and the scribe line SL. Since it can move to the substrate layer 11 through the contact and via formed, accumulation of charges in the semiconductor layer 13 is suppressed.

  Next, the SOI substrate 10 is cut along the scribe line SL by the dicing blade 200. Thereby, a plurality of semiconductor chips corresponding to the plurality of device regions D are separated into pieces.

  As described above, according to the manufacturing method of the semiconductor device according to the present embodiment, the semiconductor layer 13 is transferred to the substrate layer 11 via the device contact 22, the wiring and the substrate contact 23 in the wiring forming process using the ionization sputtering method. Electrically connected. As a result, the charge injected into the semiconductor layer 13 in the wiring formation step can be drawn out to the substrate layer 11, and accumulation of charges in the semiconductor layer 13 can be suppressed. Further, since the substrate contact 23 electrically connected to the substrate layer 11 is provided in a region corresponding to the scribe line SL, the area of the semiconductor chip is reduced as compared with the case where the substrate contact 23 is provided in the device region D. It becomes possible to do. That is, according to the manufacturing method of the semiconductor device according to the present embodiment, it is possible to suppress the accumulation of electric charges in the semiconductor layer without increasing the chip size in the wiring forming process using the ionization sputtering method. .

  Further, according to the method of manufacturing a semiconductor device according to the present embodiment, the wiring separation that separates the wiring portion 24 a connected to the device contact 22 of the wiring 24 and the wiring portion 24 b connected to the substrate contact 23 of the wiring 24. Since the process is performed in an etching process for patterning the wiring 24, it is not necessary to add a new process for wiring separation.

  Further, according to the method for manufacturing a semiconductor device according to the present embodiment, the alloy layer 16 is provided on the connection surface of the substrate layer 11 with the substrate contact 23, so that the space between the substrate layer 11 and the substrate contact 23 is provided. The contact resistance can be reduced. As a result, the resistance of the conductive path formed between the semiconductor layer 13 and the substrate layer 11 can be reduced, and the effect of extracting the charge injected into the semiconductor layer 13 to the substrate layer 11 can be promoted. Become.

  FIG. 7 is a plan view showing an example of the arrangement of the substrate contacts 23 connected to the substrate layer 11. As shown in FIG. 7, a contact group 23 </ b> A composed of a plurality of substrate contacts 23 can be arranged on the scribe line SL of the SOI substrate 10.

  FIG. 8 is a plan view showing another example of the arrangement of the substrate contacts 23 connected to the substrate layer 11. The plurality of substrate contacts 23 may be provided at regular intervals along each side of the device region D having a rectangular shape. As a result, it is possible to reduce the deviation of the resistance on the conductive path formed between the semiconductor layer 13 and the substrate layer 11, and to extract the charge injected into the semiconductor layer 13 to the substrate layer 11. Thus, it can be performed substantially uniformly over the entire device region D. The plurality of substrate contacts 23 may be disposed closer to the device region D than the center line C of the scribe line SL in the width direction of the scribe line SL. Thus, by arranging the plurality of substrate contacts 23 close to the device region D, the resistance of the conductive path formed between the semiconductor layer 13 and the substrate layer 11 can be reduced, and the semiconductor layer 13 It is possible to promote the effect of extracting the charges injected into the substrate layer 11.

  FIG. 9 is a plan view showing another example of the arrangement of the substrate contacts 23 connected to the substrate layer 11. The plurality of substrate contacts 23 may be disposed along the scribe line SL, and may be disposed near the center line C in the width direction of the scribe line SL. Thus, by arranging the plurality of substrate contacts 23 in the vicinity of the center line of the scribe line SL, the substrate contacts 23 can be completely removed in the dicing process. Therefore, the conductive path formed between the semiconductor layer 13 and the substrate layer 11 can be cut in the dicing process.

  FIG. 10A and FIG. 10B are cross-sectional views showing a manufacturing method in the case where the conductive path formed between the semiconductor layer 13 and the substrate layer 11 is cut in the dicing step. This corresponds to (b) and FIG.

  As shown in FIG. 10A, the substrate contact 23 and the vias 33, 43, 53, and 63 are provided in a region corresponding to the vicinity of the center of the scribe line SL. Each wiring provided in the wiring layers M <b> 1 to M <b> 5 is electrically connected to the substrate layer 11 and electrically connected to the semiconductor layer 13. That is, in the above embodiment, the conductive path formed between the semiconductor layer 13 and the substrate layer 11 is cut in the etching process when patterning the wiring in each of the wiring layers M1 to M5. In the embodiment, when the wiring patterning in each of the wiring layers M1 to M5 is completed, the conductive path that is formed between the semiconductor layer 13 and the substrate layer 11 and electrically connects them remains. It has become.

  As shown in FIG. 10B, in the dicing process, the SOI substrate along the scribe line SL is removed while removing the substrate contact 23 and the vias 33, 43, 53 and 63 provided in the region corresponding to the scribe line SL. 10 is cut. As a result, the conductive path formed between the semiconductor layer 13 and the substrate layer 11 is cut.

  Note that the cutting of the conductive path formed between the semiconductor layer 13 and the substrate layer 11 may be performed in the dicing process as described above while performing the etching process when patterning each wiring. Thereby, even when the etching process is incomplete and the conductive path formed between the semiconductor layer 13 and the substrate layer 11 is not properly cut, the conductive path is cut in the subsequent dicing process. Can be reliably performed.

  In the above-described embodiment, the case where the alloy layer 16 is formed on the surface of the substrate layer 11 in the region corresponding to the scribe line SL is illustrated, but the alloy layer 16 may be omitted. In this case, it is not necessary to form the opening 15 as shown in FIG. 1C in the region corresponding to the scribe line SL. FIG. 11 is a cross-sectional view showing the structure when the formation of the alloy layer 16 and the opening 15 is omitted, and corresponds to FIG. Also in the configuration shown in FIG. 11, it is possible to obtain the effect of extracting the charge injected into the semiconductor layer 13 into the substrate layer 11.

DESCRIPTION OF SYMBOLS 10 SOI substrate 11 Substrate layer 12 Embedded oxide layer 13 Semiconductor layer 16 Alloy layer 20 Insulator layer 22 Device contact 23 Substrate contact 24 Wiring 100 Semiconductor laminated structure SL Scribe line D Device region M1-M5 Wiring layer

Claims (10)

Preparing a semiconductor substrate including a substrate layer, a first insulator layer provided on the substrate layer, and a semiconductor layer provided on the first insulator layer;
Forming a second insulator layer on the surface of the semiconductor layer;
Forming a first contact having conductivity through the second insulator layer and reaching the semiconductor layer in a device region of the semiconductor substrate defined by a scribe line;
Forming a second contact having conductivity through the second insulator layer and reaching the substrate layer in a region corresponding to the scribe line of the semiconductor substrate;
Forming a first wiring electrically connected to the first contact and the second contact on a surface of the second insulator layer;
A method of manufacturing a semiconductor device including: Further comprising separating the first wiring into a portion connected to the first contact and a portion connected to the second contact.
The manufacturing method according to claim 1. The manufacturing method according to claim 2, wherein separation of the portion connected to the first contact and the portion connected to the second contact of the first wiring is performed together with patterning of the first wiring. . 4. The method according to claim 1, further comprising a step of cutting the semiconductor substrate along the scribe line while removing the second contact after forming the first wiring. 5. Production method. Removing the semiconductor layer and the first insulator layer to expose the substrate layer in a region corresponding to the scribe line of the semiconductor substrate before forming the second insulator layer, and the substrate Further comprising forming an alloy layer on the exposed portion of the layer;
The manufacturing method according to any one of claims 1 to 4, wherein the second contact is connected to the alloy layer. Forming a third insulator layer covering the first wiring;
In the device region of the semiconductor substrate, a first via having conductivity is formed which penetrates the third insulator layer and reaches a portion of the first wiring connected to the first contact. Process,
In the region corresponding to the scribe line of the semiconductor substrate, a second conductive material that penetrates the third insulator layer and reaches a portion of the first wiring connected to the second contact. Forming a via; and
Forming a second wiring electrically connected to the first via and the second via on a surface of the third insulator layer;
The manufacturing method of Claim 2 which further contains these. A semiconductor substrate including a substrate layer, a first insulator layer provided on the substrate layer, and a semiconductor layer provided on the first insulator layer and having a device region defined by a scribe line When,
A second insulator layer provided on the surface of the semiconductor layer;
A first contact having conductivity in the device region of the semiconductor substrate and reaching the semiconductor layer through the second insulator layer;
A second contact having electrical conductivity reaching the substrate layer through the second insulator layer in a region corresponding to the scribe line of the semiconductor substrate;
A first wiring provided on a surface of the second insulator layer and electrically connected to the first contact and the second contact;
A semiconductor laminated structure comprising: In a region corresponding to the scribe line of the semiconductor substrate, further comprising an alloy layer provided on the surface of the substrate layer,
The semiconductor multilayer structure according to claim 7, wherein the second contact is connected to the alloy layer. The first wiring is separated into a portion connected to the first contact and a portion connected to the second contact;
The semiconductor multilayer structure according to claim 7 or 8. A third insulator layer covering the first wiring;
A first via having conductivity in the device region of the semiconductor substrate that reaches the portion of the first wiring connected to the first contact through the third insulator layer;
In the region corresponding to the scribe line of the semiconductor substrate, a second conductive material that penetrates the third insulator layer and reaches a portion of the first wiring connected to the second contact. With vias,
A second wiring provided on a surface of the third insulator layer and electrically connected to the first via and the second via;
The semiconductor multilayer structure according to claim 9, further comprising: