JP2016162992A - Power semiconductor device - Google Patents
Power semiconductor device Download PDFInfo
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- JP2016162992A JP2016162992A JP2015043188A JP2015043188A JP2016162992A JP 2016162992 A JP2016162992 A JP 2016162992A JP 2015043188 A JP2015043188 A JP 2015043188A JP 2015043188 A JP2015043188 A JP 2015043188A JP 2016162992 A JP2016162992 A JP 2016162992A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 242
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 3
- 239000011347 resin Substances 0.000 description 31
- 229920005989 resin Polymers 0.000 description 31
- 230000017525 heat dissipation Effects 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000003825 pressing Methods 0.000 description 5
- 238000001721 transfer moulding Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000004519 grease Substances 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
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- 238000001816 cooling Methods 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000005242 forging Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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Abstract
Description
この発明は、モールド樹脂封止型のパワー半導体モジュールをヒートシンクに搭載したパワー半導体装置に関するものである。 The present invention relates to a power semiconductor device in which a molded resin-sealed power semiconductor module is mounted on a heat sink.
パワーエレクトロニクス装置においては、小型、低コスト、高効率、高性能および高信頼性が望まれている。それに伴って、電力変換用のパワー半導体装置についても小型化、高信頼性が求められている。
パワー半導体装置は、パワー半導体モジュールとヒートシンクとが一体化されたものであって、パワー半導体モジュールは、スイッチング可能なパワー半導体チップと、パワー半導体チップに接続された配線部材とを絶縁樹脂で封止することによって製造されている。
このパワー半導体モジュールの信頼性を確保するために、個々に環境試験および耐久試験など種々の信頼性試験が行われ、試験に合格したパワー半導体モジュールのみがヒートシンクに搭載されている。
パワー半導体モジュールの小型化については、モータージェネレータのような車載用機器などに採用されているモールド封止型のパワー半導体装置では、ヒートシンクがグランド（以下ＧＮＤと表す）電位であるため、パワー半導体モジュールの電極のうち、ＧＮＤ電位となる電極をヒートシンクに電気的に接続し、ＧＮＤ電位以外の電極をヒートシンクから絶縁するために、放熱面に絶縁性部材を配置する必要があり、この絶縁性部材が小型化の弊害となっている。
In power electronics devices, small size, low cost, high efficiency, high performance and high reliability are desired. Accordingly, power semiconductor devices for power conversion are also required to be downsized and highly reliable.
The power semiconductor device is an integrated power semiconductor module and heat sink, and the power semiconductor module encapsulates a switchable power semiconductor chip and a wiring member connected to the power semiconductor chip with an insulating resin. It is manufactured by
In order to ensure the reliability of the power semiconductor module, various reliability tests such as an environmental test and an endurance test are individually performed, and only the power semiconductor module that has passed the test is mounted on the heat sink.
Regarding the miniaturization of the power semiconductor module, in a mold-sealed power semiconductor device employed in a vehicle-mounted device such as a motor generator, the heat sink has a ground (hereinafter referred to as GND) potential. In order to electrically connect the electrode having the GND potential to the heat sink and insulate the electrodes other than the GND potential from the heat sink, it is necessary to dispose an insulating member on the heat dissipation surface. This is a negative effect of miniaturization.
このため、絶縁と放熱の両方の特性を満足させるために様々な検討が行われており、例えば、パワー半導体チップを搭載する金属部材の外側に絶縁層を設け、その絶縁層の熱伝導率を向上させるために、絶縁層として、酸化アルミニウムを溶射し、その後に熱処理を施して熱伝導率を上昇させた絶縁層を用いることによってパワー半導体モジュールの熱抵抗を低減させることが提案されている（特許文献１）。
また、小型化のためには、パワー半導体モジュールの電極の構造を工夫し、パワー半導体チップの上面側の電極に板状の電極を接続して露出させて、パワー半導体モジュールの厚さ方向に電極の取り出しを行うことが提案されている（特許文献２）。
For this reason, various studies have been made to satisfy both insulation and heat dissipation characteristics. For example, an insulating layer is provided outside the metal member on which the power semiconductor chip is mounted, and the thermal conductivity of the insulating layer is increased. In order to improve, it has been proposed to reduce the thermal resistance of the power semiconductor module by using an insulating layer in which aluminum oxide is thermally sprayed and then heat-treated to increase the thermal conductivity as the insulating layer ( Patent Document 1).
In order to reduce the size of the power semiconductor module, the electrode structure of the power semiconductor module is devised, and a plate-like electrode is connected to the electrode on the upper surface side of the power semiconductor chip to expose the electrode in the thickness direction of the power semiconductor module. It has been proposed to take out (Patent Document 2).
特許文献１および特許文献２に示された構成のパワー半導体モジュールでは、パワー半導体モジュールそのものの絶縁と放熱、および省スペース化についての提案が行われている。しかし、パワー半導体モジュールをヒートシンクの上に配置する場合には、何れにしても、パワー半導体モジュールのＧＮＤ電位の電極とＧＮＤ電位以外の電極とを区別して、ヒートシンクと選択的に導通と絶縁を行うことが必要であり、パワー半導体モジュールとヒートシンクとの間に接続部材を設けることになる。このため省スペース化の障害となる。すなわち、パワー半導体装置としては、搭載されるパワー半導体モジュールが個々に信頼性検査を行うことができ、しかも、パワー半導体モジュールをヒートシンクに搭載した構造体として、高性能化、高信頼化および生産性の向上を図ることが課題として残って
いる。
In the power semiconductor modules having the configurations shown in Patent Document 1 and Patent Document 2, proposals have been made for insulation, heat dissipation, and space saving of the power semiconductor module itself. However, when the power semiconductor module is disposed on the heat sink, in any case, the power semiconductor module is selectively conducted and insulated from the heat sink by distinguishing between the GND potential electrode and the non-GND potential electrode. It is necessary to provide a connecting member between the power semiconductor module and the heat sink. For this reason, it becomes an obstacle to space saving. That is, as a power semiconductor device, the mounted power semiconductor module can be individually tested for reliability, and as a structure in which the power semiconductor module is mounted on a heat sink, high performance, high reliability, and productivity are achieved. It is still an issue to improve
この発明は、前述のような従来の課題を解消するためになされたものであり、パワー半導体チップからの放熱性を損なうことなく、パワー半導体モジュールの信頼性検査を単品で実施可能とするととともに、ＧＮＤ接続部品の省略によりパワー半導体装置の省スペース化を可能とするパワー半導体装置を得ることを目的とするものである。 This invention has been made to solve the above-described conventional problems, and without compromising the heat dissipation from the power semiconductor chip, it is possible to perform a reliability test of the power semiconductor module as a single product, An object of the present invention is to obtain a power semiconductor device capable of saving the space of the power semiconductor device by omitting the GND connection parts.
この発明は、第１のパワー半導体チップと、第２のパワー半導体チップと、前記第１のパワー半導体チップの第１の電極に接続されたＰ電極と、前記第２のパワー半導体チップの第１の電極に接続されたＮ電極と、前記第１のパワー半導体チップの第２の電極および前記第２のパワー半導体チップの第２の電極に接続されたＡＣ電極と、前記第１のパワー半導体チップ、前記第２のパワー半導体チップ、前記Ｐ電極、前記Ｎ電極および前記ＡＣ電極を覆う絶縁部材とを備えたパワー半導体モジュール、および前記パワー半導体モジュールと接触して配置され前記パワー半導体モジュールの熱を放熱するヒートシンクを備え、前記Ｎ電極がＧＮＤ電位であって、前記Ｎ電極が前記パワー半導体モジュールから露出して前記ヒートシンクと接触し、前記Ｐ電極および前記ＡＣ電極が前記パワー半導体モジュールの側面から突出するように構成したものである。
また、ヒートシンクとの対向面にＮ電極のみを露出し、ヒートシンクはＧＮＤ電位であり、Ｎ電極とヒートシンクがメタル接触することで電気的に接続する構造とし、Ｎ電極以外の電極は、薄い樹脂層を介してヒートシンクから放熱するように構成したものである。
The present invention provides a first power semiconductor chip, a second power semiconductor chip, a P electrode connected to a first electrode of the first power semiconductor chip, and a first of the second power semiconductor chip. An N electrode connected to the first electrode, an AC electrode connected to the second electrode of the first power semiconductor chip and the second electrode of the second power semiconductor chip, and the first power semiconductor chip A power semiconductor module including an insulating member that covers the second power semiconductor chip, the P electrode, the N electrode, and the AC electrode, and a heat semiconductor module disposed in contact with the power semiconductor module. A heat sink for dissipating heat, wherein the N electrode is at a GND potential, and the N electrode is exposed from the power semiconductor module and contacts the heat sink. The one in which the P electrode and the AC electrode and configured to protrude from a side surface of the power semiconductor module.
Further, only the N electrode is exposed on the surface facing the heat sink, the heat sink is at a GND potential, and the N electrode and the heat sink are electrically connected by metal contact. The electrodes other than the N electrode are thin resin layers. It is configured to dissipate heat from the heat sink via.
この発明によるパワー半導体装置は、前記の構成を採用することによって、パワー半導体チップの電極に接続されたＧＮＤ電位となるＮ電極が、パワー半導体モジュールのヒートシンク対向面側に露出して、ＧＮＤ電位のヒートシンク上に固定されることで電気的に接続されているため、パワー半導体チップ単体で、ＧＮＤ電位のＮ電極とその他の電極の耐圧検査が可能となる。また、ヒートシンクとＮ電極がメタル接触することで電気的に接続されており、改めて、封止樹脂外側にＮ電極の延出部とＧＮＤ接続部品を設ける必要がない。これにより、生産上のロスの増大を防止するとともに、省スペース化が可能となる。また、パワー半導体チップを搭載した電極は、薄い樹脂層を介してヒートシンク接続されており放熱性が損なわれることがない。 In the power semiconductor device according to the present invention, by adopting the above-described configuration, the N electrode having the GND potential connected to the electrode of the power semiconductor chip is exposed to the heat sink facing surface side of the power semiconductor module, and the GND potential is increased. Since it is electrically connected by being fixed on the heat sink, it is possible to inspect the withstand voltage of the N electrode at the GND potential and other electrodes with a single power semiconductor chip. Further, the heat sink and the N electrode are electrically connected by metal contact, and it is not necessary to provide the N electrode extension part and the GND connection part on the outside of the sealing resin again. As a result, an increase in production loss can be prevented and space saving can be achieved. Further, the electrode on which the power semiconductor chip is mounted is connected to the heat sink via a thin resin layer, so that the heat dissipation is not impaired.
実施の形態１
以下、この発明の実施の形態１を図に基づいて説明する。
図１は、実施の形態１に係るパワー半導体装置の構成の一部を模式的に示す斜視図である。また、図２は、図１に示したパワー半導体装置１００のＡ−Ａ線における断面の構成の一部を模式的に示す断面図である。このパワー半導体装置１００は、パワー半導体モジュール１０とヒートシンク２０によって構成されており、パワー半導体モジュール１０は、第１のパワー半導体チップ１と、第２のパワー半導体チップ２と、この第１のパワー半導体チップ１と第２のパワー半導体チップ２に接続されるＰ電極３、Ｎ電極４、ＡＣ電極５とが絶縁部材６（以下モールド樹脂という）によってモールドされたものである。
すなわち、Ｐ電極３の上に第１のパワー半導体チップ１が搭載され、ＡＣ電極５の上に第２のパワー半導体チップ２が搭載され、第１のパワー半導体チップ１の電極はＡＣ電極５に接続され、Ｎ電極４は第２のパワー半導体チップ２に接続されている。言い換えると、第１のパワー半導体チップ１の電極を第１の電極１ａと第２の電極１ｂとすると、Ｐ電極３は、第１のパワー半導体チップ１の第１の電極１ａに接続されており、同様に、第２のパワー半導体チップ２の電極を第１の電極２ａと第２の電極２ｂとすると、Ｎ電極４は、第２のパワー半導体チップ２の第１の電極２ａに接続され、ＡＣ電極５は、第１のパワー半導体チップ１の第２の電極１ｂと第２のパワー半導体チップ２の第２の電極２ｂに接続されているということになる。
Embodiment 1
Embodiment 1 of the present invention will be described below with reference to the drawings.
FIG. 1 is a perspective view schematically showing a part of the configuration of the power semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view schematically showing a part of a cross-sectional configuration taken along line AA of the power semiconductor device 100 shown in FIG. The power semiconductor device 100 includes a power semiconductor module 10 and a heat sink 20. The power semiconductor module 10 includes a first power semiconductor chip 1, a second power semiconductor chip 2, and the first power semiconductor. A P electrode 3, an N electrode 4, and an AC electrode 5 connected to the chip 1 and the second power semiconductor chip 2 are molded by an insulating member 6 (hereinafter referred to as mold resin).
That is, the first power semiconductor chip 1 is mounted on the P electrode 3, the second power semiconductor chip 2 is mounted on the AC electrode 5, and the electrode of the first power semiconductor chip 1 is connected to the AC electrode 5. The N electrode 4 is connected to the second power semiconductor chip 2. In other words, if the electrodes of the first power semiconductor chip 1 are the first electrode 1a and the second electrode 1b, the P electrode 3 is connected to the first electrode 1a of the first power semiconductor chip 1. Similarly, when the electrodes of the second power semiconductor chip 2 are the first electrode 2a and the second electrode 2b, the N electrode 4 is connected to the first electrode 2a of the second power semiconductor chip 2, The AC electrode 5 is connected to the second electrode 1 b of the first power semiconductor chip 1 and the second electrode 2 b of the second power semiconductor chip 2.
また、第１のパワー半導体チップ１には、信号端子１ｃが接続され、第２のパワー半導体チップ２には、信号端子２ｃが接続されている。なお、それぞれの信号端子１ｃ、２ｃは、例えば、ゲート電極、検温ダイオード電極であって、一般的にパワー半導体デバイスにおいて、制御信号用に使用されている電極である。
ここで説明したＰ電極３、Ｎ電極４、ＡＣ電極５は、パワー半導体装置１００のリード端子で、このリード端子は、一般的には、帯状の薄い金属板に所定のパターンで打ち抜かれたリードフレームとして供給され、必要な加工処理後、フレームから切り離されて構成されるものである。
In addition, a signal terminal 1 c is connected to the first power semiconductor chip 1, and a signal terminal 2 c is connected to the second power semiconductor chip 2. Each of the signal terminals 1c and 2c is, for example, a gate electrode and a temperature detection diode electrode, and is an electrode generally used for a control signal in a power semiconductor device.
The P electrode 3, N electrode 4, and AC electrode 5 described here are lead terminals of the power semiconductor device 100, and this lead terminal is generally a lead punched out in a predetermined pattern on a strip-shaped thin metal plate. It is supplied as a frame, and is separated from the frame after necessary processing.
すなわち、リードフレーム（全体を図示していない）は、第１のパワー半導体チップ１の下面の第１の電極１ａに対して導電性部材６を介して接続されるＰ電極３と、第２のパワー半導体チップ２の上面の第１の電極２ａに対して配線部材７を介して接続されるＮ電極４と、第１のパワー半導体チップ１の上面の第２の電極１ｂに対して配線部材７を介して接続されるとともに、第２のパワー半導体チップ２の下面の第２の電極２ｂと導電性部材を介して接続されるＡＣ電極５を備えている。このリードフレームは、金属製であり、たとえば、銅やアルミを基材とした合金を用いる。リードフレームは、板状の材料をエッチング加工や、プレス加工で配線パターン状に成型されており、リードフレーム表面に基材の金属が露出しているものも使用可能であるが、少なくとも一部にめっき処理をされているものも使用可能である。リードフレームは、片側にパワー半導体チップ、導電性部材、配線部材などが搭載され、モールド樹脂６で包み込まれるように封止された後に、電気配線上不要な部分を除去される。これにより、パワー半導体モジュール１０内に回路を構成されている。リードフレームのＮ電極４以外のＰ電極３およびＡＣ電極５は、絶縁部材によるモールド樹脂６の側面から延出し、外部の導線と接続されることで、パワー半導体装置１００の回路を構成している。 That is, the lead frame (not shown in its entirety) includes the P electrode 3 connected to the first electrode 1a on the lower surface of the first power semiconductor chip 1 via the conductive member 6, and the second electrode 1a. The N electrode 4 connected to the first electrode 2a on the upper surface of the power semiconductor chip 2 via the wiring member 7 and the wiring member 7 to the second electrode 1b on the upper surface of the first power semiconductor chip 1 And an AC electrode 5 connected to the second electrode 2b on the lower surface of the second power semiconductor chip 2 via a conductive member. This lead frame is made of metal, and for example, an alloy based on copper or aluminum is used. The lead frame is formed into a wiring pattern by etching or pressing a plate-like material, and it is also possible to use a substrate with the base metal exposed on the lead frame surface. Those that have been plated can also be used. The lead frame is mounted with a power semiconductor chip, a conductive member, a wiring member, etc. on one side and sealed so as to be wrapped with the mold resin 6, and then unnecessary portions on the electrical wiring are removed. As a result, a circuit is configured in the power semiconductor module 10. The P electrode 3 and the AC electrode 5 other than the N electrode 4 of the lead frame extend from the side surface of the mold resin 6 by an insulating member and are connected to an external lead wire, thereby constituting a circuit of the power semiconductor device 100. .
第１のパワー半導体チップ１および第２のパワー半導体チップ２は、チップ上面とチップ裏面に、それぞれ電極１ａ、１ｂ、２ａ、２ｂを備える。それぞれの電極１ａ、１ｂ、２ａ、２ｂは、それぞれ配線部材７と導電性部材８によって、リード端子であるＰ電極３、Ｎ電極４、ＡＣ電極５に機械的、電気的に接続される。通電時の電流は、パワー半導体チップ１、２の厚さ方向に通過する。図１ではパワー半導体チップ１、２は、一例としてＭＯＳＦＥＴを示したが、ＩＧＢＴにも適用可能である。ＭＯＳＦＥＴやＩＧＢＴは、スイッチング可能な素子であり、チップ上面にチップ上面電極とは別の、ゲート部とゲート電極を備える。また、温度を検知する場合には、チップ上面電極およびゲート電極とは別の検温ダイオード部と検温ダイオード電極を設ける。搭載するパワー半導体チップにゲート電極や検温ダイオード電極を搭載するとき、本実施例で示すように、パワー半導体装置は、ゲート電極と電気的に接続するリードフレームの一部で構成されたゲート電極や、検温ダイオード電極に電気的に接続するリードフレームの一部で構成された検温ダイオード電極を搭載する。ゲート電極、検温ダイオード電極は、それぞれリードフレームのゲート電極と検温ダイオード電極などの信号端子１ｃ、２ｃにワイヤーボンドで接続される。パワー半導体チップ１、２の材料としては、Ｓｉのみならず、ＳｉＣ、ＳｉＮ、ＧａＮ、ＧａＡｓなどを用いて作製したものも使用可能である。またパワー半導体チップの上面電極は、Ｎｉめっき層などのはんだ付けできる仕様に備える。 The first power semiconductor chip 1 and the second power semiconductor chip 2 include electrodes 1a, 1b, 2a, and 2b on the chip upper surface and the chip back surface, respectively. The electrodes 1a, 1b, 2a, and 2b are mechanically and electrically connected to the P electrode 3, the N electrode 4, and the AC electrode 5, which are lead terminals, by the wiring member 7 and the conductive member 8, respectively. The current during energization passes in the thickness direction of the power semiconductor chips 1 and 2. In FIG. 1, the power semiconductor chips 1 and 2 are shown as MOSFETs as an example, but can also be applied to an IGBT. A MOSFET or IGBT is a switchable element, and includes a gate portion and a gate electrode, which are different from a chip upper surface electrode, on a chip upper surface. Further, when detecting the temperature, a temperature detecting diode portion and a temperature detecting diode electrode different from the chip upper surface electrode and the gate electrode are provided. When a gate electrode or a temperature detection diode electrode is mounted on a power semiconductor chip to be mounted, as shown in this embodiment, the power semiconductor device includes a gate electrode formed of a part of a lead frame electrically connected to the gate electrode, A temperature detecting diode electrode constituted by a part of a lead frame electrically connected to the temperature detecting diode electrode is mounted. The gate electrode and the temperature detection diode electrode are connected to signal terminals 1c and 2c such as a gate electrode of the lead frame and a temperature detection diode electrode by wire bonds, respectively. As a material of the power semiconductor chips 1 and 2, not only Si but also those manufactured using SiC, SiN, GaN, GaAs, or the like can be used. Moreover, the upper surface electrode of the power semiconductor chip is provided with a specification that can be soldered, such as a Ni plating layer.
配線部材７は、チップ上面電極とリードフレームのＮ電極４もしくはＡＣ電極５を接続する。図１に図示した様に、金属板状の配線部材７を用いる場合は、配線部材７とチップ上面電極１ａの間、配線部材７とＮ電極４もしくはＡＣ電極５の間は、導電性部材８を介して接合される。配線部材７は、モールド樹脂６内部に包括されるように配置されており、製造時に外部から配線部材７を支える部分をもたない。導電性部材８を介して接続される部分同士をつなぐ配線部材７の胴体部は、接続される部分よりもリードフレームから離れる方向に変形している。配線部材７の胴体部の断面積は、通電する電流の量によって決められる。また、実施の形態１では、例として金属板状の配線部材７を示したが、ワイヤーボンドなどの金属線材を用いても良い。 The wiring member 7 connects the chip upper surface electrode and the N electrode 4 or the AC electrode 5 of the lead frame. As shown in FIG. 1, when a metal plate-like wiring member 7 is used, a conductive member 8 is provided between the wiring member 7 and the chip upper surface electrode 1a, and between the wiring member 7 and the N electrode 4 or the AC electrode 5. It is joined via. The wiring member 7 is disposed so as to be included in the mold resin 6 and does not have a portion that supports the wiring member 7 from the outside during manufacture. The body part of the wiring member 7 that connects the parts connected via the conductive member 8 is deformed in a direction away from the lead frame rather than the connected part. The cross-sectional area of the body portion of the wiring member 7 is determined by the amount of current to be applied. Moreover, in Embodiment 1, although the metal plate-shaped wiring member 7 was shown as an example, you may use metal wires, such as a wire bond.
導電性部材８は、チップ上面電極１ａ、２ｂと配線部材７の間、配線部材７とリードフレームのＮ電極４もしくはＡＣ電極５の間、チップ下面電極１ｂ、２ａとＰ電極３もしくはＡＣ電極５の間に配置される。チップ上面電極１ａ、２ｂと配線部材７の間の導電性部材６には、はんだが用いられるが、導電性ペーストなどの微細な金属フィラーと樹脂のコンポジット材を用いても良い。 The conductive member 8 is provided between the chip upper surface electrodes 1a and 2b and the wiring member 7, between the wiring member 7 and the N electrode 4 or AC electrode 5 of the lead frame, and between the chip lower surface electrodes 1b and 2a and the P electrode 3 or AC electrode 5. It is arranged between. Solder is used for the conductive member 6 between the chip upper surface electrodes 1a, 2b and the wiring member 7, but a fine metal filler such as a conductive paste and a resin composite material may be used.
モールド樹脂６は、リードフレームと、パワー半導体チップ１、２と、導電性部材８と、配線部材７を略包み込むように配置されることで実装面を封止する。モールド樹脂６は、リードフレーム上に各種構成部材を実装した後に、トランスファー成形により設置される。モールド樹脂６は、絶縁性のフィラーを含んでおり、パワー半導体チップ１、２で生じた発熱を外部に熱伝導により伝達する。モールド樹脂６は、Ｎ電極４のヒートシンク２０に対向する面が表面に露出するように成形される。封止後に、リードフレームの不要な部分を切り落とし、リードフレームのモールド樹脂６からの延出部を曲げることによってパワー半導体モジュール１０が構成される。また、モールド樹脂６はパワー半導体モジュール１０の厚さ方向の中心線よりもヒートシンク２０側にリードフレームを配置する。これにより、リードフレームはよりヒートシンク２０との距離を小さくすることが可能であり放熱性を向上させることができる。 The mold resin 6 seals the mounting surface by being disposed so as to substantially enclose the lead frame, the power semiconductor chips 1 and 2, the conductive member 8, and the wiring member 7. The mold resin 6 is installed by transfer molding after various components are mounted on the lead frame. The mold resin 6 includes an insulating filler, and transmits heat generated by the power semiconductor chips 1 and 2 to the outside by heat conduction. The mold resin 6 is molded such that the surface of the N electrode 4 facing the heat sink 20 is exposed on the surface. After sealing, the power semiconductor module 10 is configured by cutting off unnecessary portions of the lead frame and bending the lead frame extending from the mold resin 6. The mold resin 6 has a lead frame disposed closer to the heat sink 20 than the center line in the thickness direction of the power semiconductor module 10. As a result, the lead frame can further reduce the distance from the heat sink 20 and improve heat dissipation.
絶縁性部材９は、少なくともパワー半導体チップ１、２を搭載するＰ電極３やＡＣ電極５のヒートシンク２０側を覆うように配置されている。このとき、絶縁性部材９はＮ電極４が露出している面以外のヒートシンク側２０を覆っていても良い。また、絶縁性部材９は、パワー半導体装置１００をヒートシンク２０に搭載した際に、ヒートシンク２０の対向面とヒートシンク２０が接するように構成されている。これにより、パワー半導体モジュールで生じた発熱を薄い絶縁性部材９を介してヒートシンク２０へ伝達し、ヒートシンク２０から外部へ排出される。絶縁性部材９とヒートシンク２０の間には、接触部の熱抵抗を減少させる放熱グリース９１を用いるのが良い。放熱グリース９１を使用すると、パワー半導体モジュール１０をヒートシンク２０に固着する際の隙間の調整として役立ち、密着性がよくなる。絶縁性部材９は、樹脂に絶縁性のフィラーを混合した絶縁性樹脂を用いる。絶縁性部材９は、トランスファー成形により形成され、必要とされる放熱性により部材の熱伝導率を変化させればよく、放熱性を満たせばモールド樹脂６と同じ材料で構成してもよい。モールド樹脂６で構成する場合には、トランスファー成形時に一括に絶縁性部材９を構成することができ生産性をよくできる。また、絶縁性部材９の厚さを薄くすることで、ヒートシンク２０とＰ電極３やＡＣ電極５とヒートシンク２０との距離を短くし、熱抵抗を小さくすることで放熱性を向上できる。また、絶縁性部材とモールド樹脂６で、Ｎ電極４とＰ電極３とＡＣ電極５もしくは信号端子１ｃ、２ｃはそれぞれ絶縁されおり、パワー半導体モジュール１０単品で耐圧検査が可能となる。 The insulating member 9 is disposed so as to cover at least the P electrode 3 on which the power semiconductor chips 1 and 2 are mounted and the AC electrode 5 on the heat sink 20 side. At this time, the insulating member 9 may cover the heat sink side 20 other than the surface where the N electrode 4 is exposed. The insulating member 9 is configured such that when the power semiconductor device 100 is mounted on the heat sink 20, the opposing surface of the heat sink 20 and the heat sink 20 are in contact with each other. Thereby, the heat generated in the power semiconductor module is transmitted to the heat sink 20 through the thin insulating member 9 and is discharged from the heat sink 20 to the outside. Between the insulating member 9 and the heat sink 20, it is preferable to use a heat radiation grease 91 that reduces the thermal resistance of the contact portion. When the heat dissipating grease 91 is used, it serves as adjustment of a gap when the power semiconductor module 10 is fixed to the heat sink 20, and adhesion is improved. The insulating member 9 uses an insulating resin in which an insulating filler is mixed with a resin. The insulating member 9 may be formed by transfer molding, and the thermal conductivity of the member may be changed depending on the required heat dissipation. The insulating member 9 may be made of the same material as the mold resin 6 as long as the heat dissipation is satisfied. In the case of using the mold resin 6, the insulating member 9 can be formed collectively at the time of transfer molding, and the productivity can be improved. Further, by reducing the thickness of the insulating member 9, the distance between the heat sink 20 and the P electrode 3 or the AC electrode 5 and the heat sink 20 can be shortened, and the heat dissipation can be improved by reducing the thermal resistance. Further, the N electrode 4, the P electrode 3, and the AC electrode 5 or the signal terminals 1c and 2c are insulated from each other by the insulating member and the mold resin 6, so that the power semiconductor module 10 can be individually tested for withstand voltage.
ヒートシンク２０は、アルミニウムもしくは銅などの金属を基材にした合金を、鋳造、鍛造、板金加工、切削加工などで加工して構成される。ヒートシンク２０は、強制空冷用であり、パワー半導体モジュール１０の搭載面の反対側には図示しない放熱フィンなどの面積拡大機構を備える。パワー半導体モジュール１０の搭載部は、Ｎ電極４と接触するようにパワー回路用モジュールの放熱面に合せた形状を備える。パワー半導体モジュール１０のＮ電極４とヒートシンク２０の搭載面が押し付けられることで電気的に接続される。また、Ｎ電極４の露出部のモールド樹脂６の凹みとヒートシンク２０の凸部が嵌ることでパワー半導体モジュールの位置決め効果も得られる。 The heat sink 20 is configured by processing an alloy based on a metal such as aluminum or copper by casting, forging, sheet metal processing, cutting, or the like. The heat sink 20 is for forced air cooling, and includes an area expansion mechanism such as a radiation fin (not shown) on the opposite side of the mounting surface of the power semiconductor module 10. The mounting portion of the power semiconductor module 10 has a shape matching the heat radiation surface of the power circuit module so as to be in contact with the N electrode 4. The power semiconductor module 10 is electrically connected by pressing the mounting surface of the N electrode 4 and the heat sink 20. Further, the positioning effect of the power semiconductor module can be obtained by fitting the concave portion of the mold resin 6 in the exposed portion of the N electrode 4 and the convex portion of the heat sink 20.
パワー半導体モジュール１０は、ヒートシンク２０のパワー半導体モジュール１０搭載面に対して垂直な方向に貫通穴３０を備える。また、ヒートシンク２０は、パワー半導体モジュール１０の貫通穴３０と適合する位置にねじ穴３１を備え、図２に示すように、パワー半導体モジュール１０のヒートシンク２０に対して反対側からねじ３２によってねじ留めして固定される。このとき、Ｎ電極４とヒートシンク２０が押し付けられて接触し、電気的に接続する。これにより、パワー半導体モジュール１０にＮ電極４の延出部と、Ｎ電極４とヒートシンク２０のＧＮＤ接続部材を省略でき、パワー半導体装置１００の小型化が可能となる。また、組み立て工程を簡略化するとともに、分解も可能となる。 The power semiconductor module 10 includes a through hole 30 in a direction perpendicular to the power semiconductor module 10 mounting surface of the heat sink 20. Further, the heat sink 20 is provided with a screw hole 31 at a position matching with the through hole 30 of the power semiconductor module 10, and is screwed with a screw 32 from the opposite side to the heat sink 20 of the power semiconductor module 10 as shown in FIG. 2. Fixed. At this time, the N electrode 4 and the heat sink 20 are pressed against each other and are electrically connected. Thereby, the extension part of the N electrode 4 and the GND connection member of the N electrode 4 and the heat sink 20 can be omitted from the power semiconductor module 10, and the power semiconductor device 100 can be downsized. In addition, the assembly process can be simplified and disassembled.
前述のように構成されることで、パワー半導体装置１００は、パワー半導体チップ１、２からの放熱性を損なうことなく、パワー半導体モジュール１０の耐圧検査を単品で実施可能とするととともに、ＧＮＤ接続部品の省略によりパワー半導体モジュール１０の省スペース化が可能となる。
実施の形態２
By being configured as described above, the power semiconductor device 100 can perform the breakdown voltage test of the power semiconductor module 10 as a single product without impairing the heat dissipation from the power semiconductor chips 1 and 2, and the GND connection component. Omission of the power semiconductor module 10 can save space.
Embodiment 2
つぎに、実施の形態２を図に基づいて説明する。
図３は、実施の形態２に係るパワー半導体装置１００の構成の一部を模式的に示す断面図である。実施の形態２によるパワー半導体装置１００は、パワー半導体モジュール１０の貫通穴３０を通してヒートシンク２０にねじ留めするときに、ねじ３２の座面とパワー半導体装置１００の間に皿ばね３３を備える。ねじ３２を締めたときに、皿ばね３３がねじ３２の座面で押されパワー半導体モジュール１０がヒートシンク２０に押し付けられることで、Ｎ電極４とヒートシンク２０が電気的に接続される。
Next, Embodiment 2 will be described with reference to the drawings.
FIG. 3 is a cross-sectional view schematically showing a part of the configuration of the power semiconductor device 100 according to the second embodiment. The power semiconductor device 100 according to the second embodiment includes a disc spring 33 between the seating surface of the screw 32 and the power semiconductor device 100 when screwed to the heat sink 20 through the through hole 30 of the power semiconductor module 10. When the screw 32 is tightened, the disc spring 33 is pushed by the seating surface of the screw 32 and the power semiconductor module 10 is pushed against the heat sink 20, whereby the N electrode 4 and the heat sink 20 are electrically connected.
皿ばね３３を介して加圧する場合は、ねじ３２の座面でパワー半導体モジュール１０がヒートシンク２０に直接加圧される場合と比較して、パワー半導体モジュール１０の上の被加圧面積を大きくすることができ、ねじ３２の締め付けによるモールド樹脂６の割れ耐性を向上できる。また、パワー半導体モジュール１０は、通電時の自己発熱や、外部からの受熱により、温度が変化した時に線膨張係数に基づいた膨張をするが、皿ばね３３が変形することで吸収し、接触部の応力が高まりモールド樹脂６が割れたり、内部のパワー半導体チップ１、２が損傷したりすることを防止する。逆に、設置された雰囲気温度が低下した場合など、パワー半導体装置１００の温度が低下した場合でも、パワー半導体モジュール１０は収縮するが、これに関しても皿ばね３３が変形することによって締め付け力の低下を防止し、ねじ３２の締め付け保持寿命を向上させるとともに、パワー半導体モジュール１０とヒートシンク２０との接触面の圧力の低下を防止し、放熱性を確保することが可能となる。
実施の形態３
When the pressure is applied via the disc spring 33, the area to be pressed on the power semiconductor module 10 is increased as compared with the case where the power semiconductor module 10 is directly pressed against the heat sink 20 by the seating surface of the screw 32. The crack resistance of the mold resin 6 by tightening the screws 32 can be improved. In addition, the power semiconductor module 10 expands based on the linear expansion coefficient when the temperature changes due to self-heating when energized or received heat from the outside, but absorbs the deformation of the disc spring 33, and the contact portion To prevent the mold resin 6 from being cracked and the internal power semiconductor chips 1 and 2 from being damaged. Conversely, even when the temperature of the power semiconductor device 100 decreases, such as when the installed ambient temperature decreases, the power semiconductor module 10 contracts, but also in this regard, the disc spring 33 is deformed to reduce the tightening force. It is possible to prevent the decrease in pressure on the contact surface between the power semiconductor module 10 and the heat sink 20 and to ensure heat dissipation.
Embodiment 3
次に、実施の形態３を図に基づいて説明する。
図４は、実施の形態３に係るパワー半導体装置１００の構成を模式的に示す断面図である。実施の形態３によるパワー半導体装置１００においては、貫通穴３０をＮ電極４の平面内を通るように設け、Ｎ電極４の上面と下面の両面をモールド樹脂６から露出するように構成している。この構成においてねじ３２を締め付けると、ねじ３２の座面によってＮ電極４の露出面が加圧され、Ｎ電極４がヒートシンクに押し付けられることで電気的に接続される。
Next, Embodiment 3 will be described with reference to the drawings.
FIG. 4 is a cross-sectional view schematically showing the configuration of the power semiconductor device 100 according to the third embodiment. In power semiconductor device 100 according to the third embodiment, through hole 30 is provided so as to pass through the plane of N electrode 4, and both the upper and lower surfaces of N electrode 4 are exposed from mold resin 6. . When the screw 32 is tightened in this configuration, the exposed surface of the N electrode 4 is pressed by the seating surface of the screw 32, and the N electrode 4 is pressed against the heat sink to be electrically connected.
この構造を備えることで、ねじ締めによりパワー半導体モジュール１０をヒートシンク２０に固定するときに、モールド樹脂６を介さないでねじ締めすることが可能となり、モールド樹脂６の割れを防止するために制約されるねじ３２の締め付けトルクを大きくできる。これにより、パワー半導体モジュール１０とヒートシンク２０を強固に固定できる。また、Ｎ電極の露出部分のみを加圧する構造となるため、モールド樹脂６の内部に封止された各種部品に応力が生じるのを回避できる。また、締め付けトルクを大きくしたことで、Ｎ電極４とヒートシンク２０が強力に押し付けられ、接触面の電気抵抗をより小さくすることができる。 With this structure, when the power semiconductor module 10 is fixed to the heat sink 20 by screw tightening, it is possible to tighten the screw without using the mold resin 6, and it is restricted to prevent cracking of the mold resin 6. The tightening torque of the screw 32 can be increased. Thereby, the power semiconductor module 10 and the heat sink 20 can be firmly fixed. In addition, since only the exposed portion of the N electrode is pressurized, it is possible to avoid stress from being generated in various parts sealed inside the mold resin 6. Further, by increasing the tightening torque, the N electrode 4 and the heat sink 20 are strongly pressed, and the electrical resistance of the contact surface can be further reduced.
また、Ｎ電極４の露出部を、変形しやすい可撓性の構造体とすることによってさらに効果的な締め付けを行うことができる。たとえば、図５に示すような可撓性構造部３４とすることで、ねじ締め付け時にねじ３２の座面でＮ電極４の可撓性構造部３４が押されることで、ねじ締め方向に変形する。Ｎ電極４の露出部が変形することで、モールド樹脂６とリード端子（Ｐ電極、ＡＣ電極）との間に生じる応力を低減し、界面が剥がれるのを防止できることになる。また、本発明では、ねじ３２でパワー半導体モジュール１０をヒートシンク２０に固定した時に、Ｎ電極４とヒートシンク２０が電気的に接続されるとともに、絶縁性部材９がヒートシンク２０に押し付けられることで良好な放熱経路を形成する構造である。このとき、Ｎ電極４のヒートシンク２０への対向面と絶縁性部材９の段差寸法は、本構造を実現できる高い精度が必要となる。Ｎ電極４の露出部が可撓性構造部３４を備えることで、締め付け時に変形によって例え段差が存在していても、可撓性構造部３４の僅かな変形によってより調整されるため、段差の寸法許容値を大きく設定することが可能となり、生産性が向上し、コストを低減できる。 Further, by making the exposed portion of the N electrode 4 a flexible structure that can be easily deformed, more effective tightening can be performed. For example, when the flexible structure portion 34 as shown in FIG. 5 is used, the flexible structure portion 34 of the N electrode 4 is pushed by the seating surface of the screw 32 at the time of screw tightening, so that it deforms in the screw tightening direction. . By deforming the exposed portion of the N electrode 4, the stress generated between the mold resin 6 and the lead terminal (P electrode, AC electrode) can be reduced and the interface can be prevented from peeling off. In the present invention, when the power semiconductor module 10 is fixed to the heat sink 20 with the screw 32, the N electrode 4 and the heat sink 20 are electrically connected, and the insulating member 9 is pressed against the heat sink 20, which is favorable. It is a structure that forms a heat dissipation path. At this time, the step size of the surface of the N electrode 4 facing the heat sink 20 and the insulating member 9 needs to be highly accurate to realize this structure. Since the exposed portion of the N electrode 4 includes the flexible structure portion 34, even if a step is present due to deformation at the time of tightening, it is further adjusted by slight deformation of the flexible structure portion 34. It becomes possible to set a large dimensional tolerance, which improves productivity and reduces costs.
また、図６に示すような金属板３５をパワー半導体モジュール１０の表面の貫通穴３０の出口に備えても良い。この場合も、ねじ締めされたときに、モールド樹脂６は接触面積がねじ３２の座面よりも大きい金属板３５を介して加圧されるので、モールド樹脂６の割れを防ぐことができる。金属板３５は、トランスファー成形時に一体成型しても良いし、トランスファー成形時に金属板３５を配置する窪みを形成し、ヒートシンク２０にパワー半導体モジュール１０を取り付けるときに配置しても良い。あとから金属板３５を配置する場合は、金属製の座金、ばね座金などを使用するとねじ緩みの耐性を向上する効果がある。
実施の形態４
A metal plate 35 as shown in FIG. 6 may be provided at the outlet of the through hole 30 on the surface of the power semiconductor module 10. Also in this case, since the mold resin 6 is pressurized through the metal plate 35 having a contact area larger than the seating surface of the screw 32 when screwed, the mold resin 6 can be prevented from cracking. The metal plate 35 may be integrally formed at the time of transfer molding, or may be disposed at the time of attaching the power semiconductor module 10 to the heat sink 20 by forming a recess in which the metal plate 35 is disposed at the time of transfer molding. When the metal plate 35 is disposed later, the use of a metal washer, a spring washer or the like has an effect of improving the resistance to screw loosening.
Embodiment 4
つぎに、実施の形態４を図に基づいて説明する。
図７は、実施の形態４に係るパワー半導体装置１００の構成を模式的に示す断面図である。パワー半導体装置１００は、パワー半導体モジュール１０を固定するばね４０を備え、パワー半導体モジュール１０は、ヒートシンク２０にばね４０で加圧されることでヒートシンク２０上に固定される。この場合は、パワー半導体モジュール１０に貫通穴３０は設けない。ばね４０の固定部は、パワー半導体装置１００のヒートシンク２０上に設置されても良いし、パワー半導体装置１００を組み込む製品の筐体に設置されていても良い。
Next, a fourth embodiment will be described with reference to the drawings.
FIG. 7 is a cross-sectional view schematically showing the configuration of the power semiconductor device 100 according to the fourth embodiment. The power semiconductor device 100 includes a spring 40 that fixes the power semiconductor module 10. The power semiconductor module 10 is fixed onto the heat sink 20 by being pressed against the heat sink 20 by the spring 40. In this case, the through hole 30 is not provided in the power semiconductor module 10. The fixing portion of the spring 40 may be installed on the heat sink 20 of the power semiconductor device 100 or may be installed in a housing of a product in which the power semiconductor device 100 is incorporated.
前述の構成を備えることで、組み立て時にパワー半導体モジュール１０はヒートシンク２０に搭載し、ばね４０で加圧することで固定できるため、組み立てが容易になる。また、パワー半導体モジュール１０は、ねじ３２で固定する場合のような貫通穴３０を備える必要がなく、さらなる小型化が可能となる。この加圧方法では、パワー半導体モジュール１０の表面の任意の箇所を複数点加圧することができるため、Ｎ電極４とヒートシンク２０の接触面や、絶縁性部材９とヒートシンク２０の接触面を均等に加圧することでできる。この時、ばね４０は、パワー半導体モジュール１０のヒートシンク２０の反対側の面内で、パワー半導体チップ１、２の搭載部の投影面上に重ならない面を加圧するようにすることで、パワー半導体チップ１、２とその近傍にある部材に生じる応力を低減でき、加圧力の許容範囲を広げ、導電性部材８の寿命を長くできる効果がある。
実施の形態５
With the above-described configuration, the power semiconductor module 10 can be mounted on the heat sink 20 during assembly, and can be fixed by applying pressure with the spring 40, so that assembly is facilitated. Further, the power semiconductor module 10 does not need to include the through hole 30 as in the case of being fixed with the screw 32, and can be further downsized. In this pressurizing method, a plurality of points on the surface of the power semiconductor module 10 can be pressed, so that the contact surface between the N electrode 4 and the heat sink 20 and the contact surface between the insulating member 9 and the heat sink 20 are evenly distributed. It can be done by applying pressure. At this time, the spring 40 pressurizes a surface that does not overlap the projection surface of the mounting portion of the power semiconductor chips 1 and 2 within the surface of the power semiconductor module 10 on the side opposite to the heat sink 20. The stress generated in the chips 1 and 2 and the members in the vicinity thereof can be reduced, the allowable range of the applied pressure can be expanded, and the life of the conductive member 8 can be extended.
Embodiment 5
つぎに、実施の形態５を図に基づいて説明する。
図８は、実施の形態５に係るパワー半導体モジュール１０の構成を模式的に示す断面図である。パワー半導体モジュール１０のＮ電極４の露出面と絶縁性部材９のヒートシンク対向面は、略同一平面に配置させている。本構造は、Ｎ電極４がパワー半導体モジュール１０を成形後に絶縁性部材と同一平面になるように、リードフレームのＮ電極をあらかじめ折り曲げたり、プレス加工により半せん断状態にすることで段差を設けたりして構成できる（図８（Ａ））。また、少なくともリードフレームのＮ電極４の一部を、Ｐ電極３およびＡＣ電極５に比べて厚さを増大させることで構成することも可能である（図８（Ｂ））。もしくは、Ｎ電極４に電気的に接続され、絶縁性部材９の厚さと略同じ厚さを持つ配線部材５０を配置することで構成することも可能である（図８（Ｃ））。
Next, a fifth embodiment will be described with reference to the drawings.
FIG. 8 is a cross-sectional view schematically showing the configuration of the power semiconductor module 10 according to the fifth embodiment. The exposed surface of the N electrode 4 of the power semiconductor module 10 and the heat sink facing surface of the insulating member 9 are arranged on substantially the same plane. In this structure, the N electrode 4 of the lead frame is bent in advance so that the N electrode 4 becomes flush with the insulating member after the power semiconductor module 10 is molded, or a step is provided by making it into a semi-shear state by pressing. (FIG. 8A). It is also possible to configure at least a part of the N electrode 4 of the lead frame by increasing the thickness as compared with the P electrode 3 and the AC electrode 5 (FIG. 8B). Alternatively, it may be configured by arranging a wiring member 50 that is electrically connected to the N electrode 4 and has substantially the same thickness as the insulating member 9 (FIG. 8C).
この構成とすることで、パワー半導体モジュール１０がヒートシンク２０に押し付けられた時に絶縁性部材９とＮ電極４の露出面が均等に加圧され、良好なコンタクトと接触部の小さい熱抵抗を容易に実現できる。また、パワー半導体モジュール１０をトランスファー成型する際に、金型の構造を簡略化しやすく金型費を低減できる。ヒートシンク２０は、パワー半導体モジュール１０の搭載面を平面とすればよく、ヒートシンクの成形が容易となる。さらに、ヒートシンク２０とパワー半導体モジュール１０の放熱面および固定面となる面積が増加するため、放熱性と耐振性が向上する。
実施の形態６
With this configuration, when the power semiconductor module 10 is pressed against the heat sink 20, the exposed surfaces of the insulating member 9 and the N electrode 4 are evenly pressurized, and a good contact and a small thermal resistance of the contact portion can be easily achieved. realizable. Further, when the power semiconductor module 10 is transfer-molded, the mold structure can be easily simplified and the mold cost can be reduced. The heat sink 20 only needs to have a flat mounting surface for the power semiconductor module 10, and the heat sink can be easily formed. Further, since the areas of the heat sink 20 and the power semiconductor module 10 serving as the heat radiating surface and the fixing surface are increased, the heat radiating property and the vibration resistance are improved.
Embodiment 6
つぎに、実施の形態６を図に基づいて説明する。
図９は、実施の形態６に係るパワー半導体装置１００の構成を模式的に示す平面図である。また図１０は、実施の形態６に係るパワー半導体装置１００の構成を模式的に示す回路図である。パワー半導体モジュール１０は、三相交流回路の少なくとも1つの相を構成し、上アームのパワー半導体チップを搭載するＰ電極３と、下アームのパワー半導体チップを搭載するＡＣ電極５はそれぞれ、パワー半導体モジュール１０の略反対側の側面から延出している。また、Ｐ電極３の延出部をヒートシンクの平面上の中心方向に配置し、ＡＣ電極５の延出部がヒートシンク２０の外周部に配置するように、１つのヒートシンク上に複数個搭載し、それぞれＰ電極用バスバー９１およびＡＣ電極用バスバー９２で接続することで、三相交流回路を構成している。
Next, a sixth embodiment will be described with reference to the drawings.
FIG. 9 is a plan view schematically showing the configuration of the power semiconductor device 100 according to the sixth embodiment. FIG. 10 is a circuit diagram schematically showing the configuration of the power semiconductor device 100 according to the sixth embodiment. The power semiconductor module 10 constitutes at least one phase of a three-phase AC circuit, and the P electrode 3 on which the upper arm power semiconductor chip is mounted and the AC electrode 5 on which the lower arm power semiconductor chip is mounted are respectively power semiconductors. It extends from the substantially opposite side surface of the module 10. Further, a plurality of extending portions of the P electrode 3 are arranged in the center direction on the plane of the heat sink, and a plurality of the extending portions of the AC electrode 5 are mounted on one heat sink so that they are arranged on the outer peripheral portion of the heat sink 20, A three-phase AC circuit is configured by connecting the P electrode bus bar 91 and the AC electrode bus bar 92 respectively.
パワー半導体モジュール１０は、Ｐ電極３とＡＣ電極５をそれぞれ反対側の側面から延出させる構造により、電流の経路を直線状にすることで低インダクタンス化できる。また、１相分をパワー半導体モジュール１０の内部に備えることで、同じパワー半導体モジュール１０を複数個組み合わせることで三相交流回路を容易に構成できるとともに、製造面でも同じパワー半導体モジュール１０を複数個製造すればよく、製造コストが低減できる。また、三相交流回路を複数回路並列接続する回路を構成する場合、２相分もしくは３相分をパワー半導体モジュール内部に設けることで、同じモジュールを複数個組み合わせることで、容易に回路を構成できるとともに、製造コストを低減できる。 The power semiconductor module 10 has a structure in which the P electrode 3 and the AC electrode 5 are extended from the opposite side surfaces, respectively, and can reduce the inductance by making the current path straight. In addition, by providing one phase portion inside the power semiconductor module 10, a three-phase AC circuit can be easily configured by combining a plurality of the same power semiconductor modules 10, and a plurality of the same power semiconductor modules 10 are also manufactured in terms of manufacturing. What is necessary is just to manufacture, and manufacturing cost can be reduced. In addition, when configuring a circuit in which a plurality of three-phase AC circuits are connected in parallel, by providing two or three phases inside the power semiconductor module, the circuit can be easily configured by combining a plurality of the same modules. At the same time, the manufacturing cost can be reduced.
パワー半導体モジュール１０を、Ｐ電極３の延出部をヒートシンク２０の内側に配置してＰ電極用バスバー９１で接続し、ＡＣ電極５の延出部をヒートシンク２０の外周部に配置してＡＣ電極用バスバー９２で接続して複数個組み合わせ、三相交流回路もしくは三相交流回路を複数回路並列接続する回路を構成することで、モータージェネレータ用の電力変換装置となる。Ｐ電極３はバスバーなどの配線部材を介してバッテリーなどの電源に接続される。また、ＡＣ電極５はモールド樹脂からの延出部、もしくは延出部と接続された配線部材とモーター用のコイル口出し線と接続される。Ｎ電極と接続したＧＮＤ電位のヒートシンクは、同じくＧＮＤ電位のモーターハウジングと接続される。このように、モーター部と接続されることでモータージェネレータ用の電力変換装置となる。 In the power semiconductor module 10, the extension part of the P electrode 3 is arranged inside the heat sink 20 and connected by the P electrode bus bar 91, and the extension part of the AC electrode 5 is arranged on the outer peripheral part of the heat sink 20. A power converter for a motor generator is formed by connecting a plurality of three-phase AC circuits or a plurality of three-phase AC circuits in parallel by connecting a plurality of bus bars 92. The P electrode 3 is connected to a power source such as a battery via a wiring member such as a bus bar. Further, the AC electrode 5 is connected to an extension portion from the mold resin, or a wiring member connected to the extension portion and a coil lead wire for the motor. The GND potential heat sink connected to the N electrode is also connected to the GND potential motor housing. Thus, it becomes a power converter device for motor generators by being connected with a motor part.
なお、本発明は、その発明の範囲内において、各実施の形態を適宜、変形、省略することが可能である。 In the present invention, each embodiment can be appropriately modified or omitted within the scope of the invention.
１ 第１のパワー半導体チップ、２ 第２のパワー半導体チップ、３ Ｐ電極、
４ Ｎ電極、５ ＡＣ電極、６ モールド樹脂、７ 配線部材、８ 導電性部材、
９ 絶縁性部材、１０ パワー半導体モジュール、２０ ヒートシンク
３０ 貫通穴、３１ ねじ穴、３２ ねじ、３３ 皿ばね、３４ 可撓性構造部、
３５ 金属板、４０ ばね、５０ 配線部材、９１ Ｐ電極用バスバー、
９２ ＡＣ電極用バスバー、１００ パワー半導体装置
1 first power semiconductor chip, 2 second power semiconductor chip, 3 P electrode,
4 N electrode, 5 AC electrode, 6 Mold resin, 7 Wiring member, 8 Conductive member,
9 Insulating member, 10 Power semiconductor module, 20 Heat sink 30 Through hole, 31 Screw hole, 32 Screw, 33 Belleville spring, 34 Flexible structure,
35 metal plate, 40 spring, 50 wiring member, 91 P electrode bus bar,
92 AC electrode bus bar, 100 power semiconductor device
この発明は、一方の面に第１の電極を有し、他方の面に第２の電極を有する第１のパワー半導体チップ、一方の面に第１の電極を有し、他方の面に第２の電極を有する第２のパワー半導体チップ、前記第１のパワー半導体チップの前記第１の電極に接続されるＰ電極と、前記第２のパワー半導体チップの前記第１の電極に接続されるＮ電極と、前記第１のパワー半導体チップの前記第２の電極と前記第２のパワー半導体チップの前記第２の電極に接続されるＡＣ電極の配線パターン状に成型されたリードフレーム、および前記リードフレームの前記Ｐ電極の上に前記第１のパワー半導体チップが搭載され、前記ＡＣ電極５の上に前記第２のパワー半導体チップが搭載され、前記第１のパワー半導体チップの電極が前記ＡＣ電極に接続され、前記Ｎ電極が前記第２のパワー半導体チップ２に接続され、モールドするモールド部材を備えたパワー半導体モジュールと、前記パワー半導体モジュールに接触して配置され前記パワー半導体モジュールの熱を放熱するヒートシンクを備え、前記Ｎ電極をＧＮＤ電位として、前記Ｎ電極が前記パワー半導体モジュールから露出して前記ヒートシンクと接触し、前記Ｐ電極および前記ＡＣ電極が前記パワー半導体モジュールの側面から突出するように構成したものである。
The present invention includes a first power semiconductor chip having a first electrode on one surface and a second electrode on the other surface, a first electrode on one surface, and a first power semiconductor chip on the other surface. second power semiconductor chip having second electrodes, said first power semiconductor chips P electrode to which the Ru is connected to the first electrode of Ru is connected to the first electrode of the second power semiconductor chip and N electrodes, said first power semiconductor chip and the second electrode and the second power semiconductor chip the lead frame molded to the wiring pattern of the second electrode connected to Ru AC electrodes, and the The first power semiconductor chip is mounted on the P electrode of the lead frame, the second power semiconductor chip is mounted on the AC electrode 5, and the electrode of the first power semiconductor chip is the AC power. Connected to the electrode, front N electrode connected to the power semiconductor chip 2 of the second, and the power semiconductor module having a mold member for molding, is disposed in contact with the power semiconductor module comprising a heat sink for radiating heat of the power semiconductor module, The N electrode is set to a GND potential , the N electrode is exposed from the power semiconductor module and is in contact with the heat sink, and the P electrode and the AC electrode protrude from the side surface of the power semiconductor module. .
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