JP2016162871A - Semiconductor light-emitting element and lighting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element and a lighting device having a higher efficiency and a larger optical output.SOLUTION: A semiconductor light-emitting element 100 has such a structure that at least a first semiconductor layer 30, a light-emitting semiconductor layer 40 and a second semiconductor layer 50 are laminated on an optical base material 10 where a fine uneven structure 20 is formed on one principal surface partially or entirely, and a reflective layer 90 is provided on the other principal surface on the opposite side of one principal surface. Average pitch of the fine uneven structure 20 is 200-1500 nm, a ratio M=W1×W2/(2T(W1+W2)) determined by the width W1 in the longitudinal direction and the width W2 in the traverse direction and the depth T of the optical base material 10 is 1 or more, and the reflectance of the reflective layer 90 is 80% or more.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor light emitting element and a lighting device.

  Semiconductor light emitting elements, such as light emitting diodes (LEDs), have many advantages over conventional light emitting devices such as conventional fluorescent lamps and incandescent bulbs. For example, the small size, high power efficiency, fast on-off response, resistance to vibration, and long device life can be mentioned as advantages.

  Taking advantage of such advantages, lighting using LEDs has begun to spread. However, to replace conventional fluorescent lamps, it is necessary to further increase the efficiency, output, and cost of LEDs. It is known that the efficiency can be further improved by providing a concavo-convex structure on the LED semiconductor layer interface, the light exit surface, and the like. For example, in Patent Document 1, light extraction efficiency is improved by providing irregularities on the surface of a semiconductor layer to change the traveling direction of light. Patent Document 2 proposes a technique in which a concavo-convex structure is provided on a substrate and the light guiding direction in the semiconductor crystal layer is changed to increase the light extraction efficiency LEE. Patent Document 3 proposes a technique in which the size of the concavo-convex structure provided on the single crystal substrate is nano-sized. It has been reported that this technique improves internal quantum efficiency. Patent Document 4 proposes a technique for improving electron injection efficiency by providing a concavo-convex structure on the upper surface of a p-type semiconductor layer and reducing contact resistance with a transparent conductive film.

  The efficiency of an LED is determined by the product of three efficiencies: internal quantum efficiency, light extraction efficiency, and electron injection efficiency. And as described in the cited patent document, it has been shown that these efficiencies can be improved by providing a micro-order to nano-order uneven structure.

Japanese Patent No. 4874155 JP 2003-318441 A JP 2007-294972 A JP 2005-259970 A Japanese Patent No. 5126800

Appl. Phys. Lett. 91. 183507 (2007)

  When an LED is used for illumination, it is important to increase the output of the LED. The lighting device has a light output or a light flux required depending on its use, and usually a desired light output is output using a plurality of LEDs. Therefore, when the light output of the LED is improved, the number of LEDs required for the device can be reduced. This leads to a reduction in cost due to a decrease in the number of mounted components, and further spread of LED lighting.

  In order to increase the light output per LED, simply increase the injection current density. However, the relationship between the injection current density and the light output is not linear, and it is known that a decrease in internal quantum efficiency called “drop” occurs as the injection current increases (see, for example, Non-Patent Document 1). The drop in efficiency due to droop means that the ratio of heat input to the LED is converted to heat, and the lighting device design complicates the heat dissipation part, hindering cost reduction and reducing the size of the device. Make it difficult.

  On the other hand, in order to increase the light output per LED, it is conceivable to increase the size of the LED while maintaining the injection current density. However, in the conventional micro-sized pattern, the light extraction efficiency is not sufficiently improved under the condition that the chip size is large. Conventionally used micro-sized patterns increase the light extraction efficiency by scattering. However, particularly in a semiconductor light emitting device having an optical substrate, when the size is increased, the return light from the optical substrate side to the semiconductor layer increases. Also at this time, the components that are scattered and contribute to the extraction decrease. Therefore, in the conventional concavo-convex structure, the light extraction efficiency has not been maximized especially under the condition that the chip size is large.

  Further, Patent Document 5 discloses a semiconductor light emitting device in which nano-order irregularities are provided on an optical substrate and a reflective layer having a high reflectance is provided. However, although the light emission output ratio in flip-chip mounting is described, the behavior in face-up mounting was not clear. In general, flip-chip mounting has the disadvantages of higher cost and lower yield than face-up mounting. Therefore, for further widespread use of LED lighting, further improvement in efficiency in face-up mounting at low cost and high light output under the condition of a large chip size have been desired.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor light-emitting element and a lighting device that are more efficient and have a large light output.

  The semiconductor light-emitting device of the present invention includes at least a first semiconductor layer, a light-emitting semiconductor layer, and a second semiconductor layer laminated on an optical base material having a fine concavo-convex structure formed on a part or the whole of one main surface, and A semiconductor light emitting device having a structure in which a reflective layer is provided on the other main surface opposite to the one main surface, wherein an average pitch Pav of the fine concavo-convex structure is 200 nm or more and 1500 nm or less, and The ratio M shown in the following formula (1) determined from the width W1 in the longitudinal direction and the width W2 in the lateral direction and the thickness T of the optical substrate is 1 or more, and the reflectance of the reflective layer is 80% or more. Features.

  With this configuration, since the internal quantum efficiency IQE is improved and the high light extraction efficiency LEE is maintained even in a large area, the semiconductor light emitting device is more efficient and has a large light output.

  The illumination device of the present invention is characterized by mounting the above-described semiconductor light emitting element.

  According to the present invention, it is possible to provide a semiconductor light emitting device with higher efficiency and a higher light output, and an illumination device using the same.

1 is a schematic cross-sectional view showing a semiconductor light emitting element according to an embodiment. It is explanatory drawing which shows ratio W1 / T of the width | variety W1 and thickness T of the optical base material in the semiconductor light-emitting device concerning this Embodiment, and the behavior of light. It is explanatory drawing which shows the widths W1 and W2 in the semiconductor light-emitting device in this Embodiment. It is the top view which looked at the 1st semiconductor layer of the semiconductor light-emitting device concerning this Embodiment from the surface side in which the fine concavo-convex structure was formed. It is the top view which looked at the 1st semiconductor layer of the semiconductor light-emitting device concerning this Embodiment from the surface side in which the fine concavo-convex structure was formed. It is a top view which shows the case where the fine grooving | roughness structure of the semiconductor light-emitting device concerning this Embodiment is a dot structure. It is a cross-sectional schematic diagram which shows the fine concavo-convex structure in the line segment position corresponded to the pitch P shown in FIG. It is a top view which shows the case where the fine concavo-convex structure of the semiconductor light emitting element concerning this Embodiment is a hole structure. It is a cross-sectional schematic diagram which shows the fine concavo-convex structure in the line segment position corresponded to the pitch P shown in FIG.

  Hereinafter, an embodiment of the present invention (hereinafter abbreviated as “embodiment”) will be described in detail. In addition, this invention is not limited to the following embodiment, It can implement by changing variously within the range of the summary.

  As a result of intensive research to solve the above problems, the present inventor has found that when the nano-pattern fine uneven structure provided on the optical substrate and the dimensional ratio of the optical substrate satisfy a specific condition, the internal quantum efficiency It has been found that a semiconductor light emitting device with higher efficiency and a higher light output can be obtained by improving the IQE and maintaining the light extraction efficiency LEE even with a large area device.

(Semiconductor light emitting device)
First, the structure of the semiconductor light emitting device according to the present embodiment will be described with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing a semiconductor light emitting device according to the present embodiment. As shown in FIG. 1, in the semiconductor light emitting device 100, the optical substrate 10 has a fine concavo-convex structure 20 formed on one main surface thereof. The first semiconductor layer 30, the light emitting semiconductor layer 40, and the second semiconductor layer 50 are sequentially stacked from the bottom on one main surface including the fine concavo-convex structure 20 of the optical substrate 10. In FIG. 1, the fine concavo-convex structure 20 can also be provided on a part of the main surface of the optical substrate 10.

  Further, as shown in FIG. 1, a reflective layer 90 is provided on the other main surface of the optical substrate 10 opposite to the one main surface including the fine concavo-convex structure 20.

  Here, the emitted light generated in the light emitting semiconductor layer 40 is extracted from the upper second semiconductor layer 50 side or the lower optical substrate 10. Further, the first semiconductor layer 30 and the second semiconductor layer 50 are different semiconductor layers. Here, it is preferable that the first semiconductor layer 30 planarizes the fine concavo-convex structure 20. By providing the first semiconductor layer 30 so as to planarize the fine concavo-convex structure 20, the performance of the first semiconductor layer 30 as a semiconductor can be reflected in the light emitting semiconductor layer 40 and the second semiconductor layer 50. Therefore, the internal quantum efficiency IQE is improved.

  The first semiconductor layer 30 may be composed of an undoped first semiconductor layer 31 and a doped first semiconductor layer 32, as shown in FIG. Here, the undoped first semiconductor layer 31 is provided so as to planarize the fine concavo-convex structure 20, so that the performance of the undoped first semiconductor layer 31 as a semiconductor is the same as that of the doped first semiconductor layer 32 and the light emitting semiconductor layer. 40 and the second semiconductor layer 50 can be reflected, so that the internal quantum efficiency IQE is improved.

  Furthermore, the undoped first semiconductor layer 31 preferably includes a buffer layer 33 as shown in FIG. In the semiconductor light emitting device 100, the buffer layer 33 is provided on the fine concavo-convex structure 20, and then the undoped first semiconductor layer 31 and the doped first semiconductor layer 32 are sequentially stacked, thereby crystallizing the first semiconductor layer 30. Nucleation and nucleus growth, which are initial conditions for growth, are improved, and the performance of the first semiconductor layer 30 as a semiconductor is improved, so that the degree of improvement in internal quantum efficiency IQE is improved. Here, the buffer layer 33 may be arranged so as to planarize the fine concavo-convex structure 20, but since the growth rate of the buffer layer 33 is slow, from the viewpoint of shortening the manufacturing time of the semiconductor light emitting device 100, the buffer layer 33. It is preferable to planarize the fine concavo-convex structure 20 with the undoped first semiconductor layer 31 provided thereon. By providing the undoped first semiconductor layer 31 so as to planarize the fine concavo-convex structure 20, the performance of the undoped first semiconductor layer 31 as a semiconductor is improved by the doped first semiconductor layer 32, the light emitting semiconductor layer 40, and the first semiconductor layer 31. 2 can be reflected in the semiconductor layer 50, so that the internal quantum efficiency IQE is improved. In FIG. 1, the buffer layer 33 is disposed so as to cover the surface of the fine concavo-convex structure 20, but may be partially provided on the surface of the fine concavo-convex structure 20. In particular, the buffer layer 33 can be preferentially provided at the bottom of the concave portion of the fine concavo-convex structure 20.

  Furthermore, the transparent conductive film 60 can be provided on the second semiconductor layer 50, the anode electrode 70 can be provided on the transparent conductive film 60, and the cathode electrode 80 can be provided on the first semiconductor layer 30. The arrangement of the transparent conductive film 60, the anode electrode 70, and the cathode electrode 80 is not limited because it can be appropriately optimized by the semiconductor light emitting device, but is generally provided as illustrated in FIG. 1. In FIG. 1, the transparent conductive film 60 covers the entire second semiconductor layer 50, but may be provided so that a part of the second semiconductor layer 50 is not covered.

  The semiconductor light emitting device 100 shown in FIGS. 1 and 2 is an example applied to a semiconductor light emitting device having a double hetero structure, but the stacked structure of the first semiconductor layer 30, the light emitting semiconductor layer 40, and the second semiconductor layer 50 is the same. It is not limited to.

  In the semiconductor light emitting device 100 according to the present embodiment, the average pitch Pav of the fine concavo-convex structure 20 formed on the entire or part of one main surface of the optical substrate 10 is 200 nm or more and 1500 nm or less (hereinafter, a predetermined range). And the ratio M between the width W1 and the thickness T of the optical substrate 10 is 1 or more.

  Hereinafter, the principle that the semiconductor light emitting device 100 according to the present embodiment exerts an effect will be described.

  In general, the light emission efficiency of a semiconductor light emitting device is determined by the internal quantum efficiency IQE and the light extraction efficiency LEE. In order to improve IQE, it is necessary to achieve both reduction of crystal defects and drop due to a nano-order concavo-convex structure, and destruction of the waveguide mode and effective extraction outside the chip in order to improve LEE. Become.

  In particular, in order to break the waveguide mode, conventionally, a micro-order concavo-convex structure is provided on the growth substrate to scatter light and improve the light extraction efficiency LEE.

  However, the inventor can emphasize the wave nature of light by setting the fine concavo-convex structure to the nano-order, and pays attention to the resulting light diffraction, particularly the number of diffraction modes and the diffraction angle. It has been found that by controlling this mode according to the parameters of the fine concavo-convex structure, the light inside the semiconductor light emitting device can be effectively taken out of the chip, and the light extraction efficiency can be maintained high even in a large area. As a result, the waveguide mode is effectively destroyed by the reduction of crystal defects when the semiconductor layer is formed by the fine concavo-convex structure provided on the optical base material, and the diffraction by the fine concavo-convex structure. The action of effectively taking out can be obtained.

  Furthermore, the light output of 1 LED can be improved by setting it as a larger area. Therefore, from the relationship of the parameters that characterize the optical substrate 10, it is possible to create an LED with a large light output by increasing the area of the element in addition to improving the internal quantum efficiency IQE and the light extraction efficiency LEE. It became.

(Average pitch Pav)
First, the reason why the average pitch Pav of the fine uneven structure 20 is preferable in the predetermined range will be described.

  In general, the interaction between the emitted light generated in the light emitting layer of the semiconductor light emitting element and the uneven structure is determined by the relationship between the optical wavelength λ of the emitted light in the semiconductor light emitting element and the size of the fine uneven structure.

  The micro-order concavo-convex structure conventionally used is about 10 times as large as the optical wavelength λ of the emitted light in the semiconductor light emitting device, and the interaction between the light and the concavo-convex structure is scattering. However, when the size of the concavo-convex structure is nano-ordered to improve the internal quantum efficiency IQE, the optical wavelength λ of the emitted light in the semiconductor light emitting device is about the same as the optical wavelength λ, and is about several times larger. It is emphasized that light diffraction occurs as an interaction.

  Factors that characterize light diffraction are the mode, which is the number of intensifying directions after diffraction, the light output angle of each mode, and the intensity of each mode. In light diffraction, due to its wave nature, a plurality of intensifying directions are generated by reflection and transmission at the concavo-convex structure.

  The number of modes of light diffraction is small when the ratio between the average pitch Pav and the optical wavelength is small, and increases as the ratio between the average pitch Pav and the optical wavelength is large. That is, the number of modes is limited under the condition that the ratio between the average pitch Pav and the optical wavelength is small. This is observed when the diffracted light has directivity.

  On the other hand, the number of modes of light diffraction increases as the ratio between the average pitch Pav and the optical wavelength increases. At this time, the strength of each mode decreases as the number of modes increases. In addition, the distribution of the light emission angle gradually becomes wider. Its behavior is observed as scattered.

  By having the average pitch Pav of the fine concavo-convex structure 20 within the predetermined range, the wave nature of light incident on the fine concavo-convex structure 20 becomes remarkable. Since it has directivity, it is easier to control the behavior of light in the semiconductor light emitting device 100 by changing the parameters constituting the fine concavo-convex structure 20 compared to the conventional micro-order concavo-convex structure. There is.

(Optical substrate)
Next, the optical substrate will be described.
FIG. 2 is an explanatory diagram showing the behavior of light and the ratio W1 / T between the width W1 and the thickness T of the optical substrate in the semiconductor light emitting device according to the present embodiment. In FIG. 2, it is shown in one dimension for convenience. As shown in FIG. 2, as the ratio W1 / T between the width W1 and the thickness T of the optical base material 10 increases, the light generated inside the semiconductor light emitting element is less likely to escape from the side surface of the optical base material 10, and the fine uneven structure 20 easily enters from the optical substrate 10 side.

  FIG. 2A shows the case of W1 / T = 3, and FIG. 2B shows the case of W1 / T = 5.

  For example, when the optical substrate 10 is a sapphire substrate, the thickness T of the optical substrate 10 is generally set to about 100 μm to 200 μm from the viewpoint of the dicing process and the subsequent handling, and the laminated semiconductor layer is several μm. In comparison, it is about 10 to 20 times thicker. For this reason, light extraction from the side surface of the optical substrate 10 cannot be ignored.

  As shown in FIG. 2A, when W1 / T is small, the light incident on the optical base material 10 from the laminated semiconductor layer is applied to the side surface of the optical base material 10 before entering the fine concavo-convex structure 20 again from the optical base material 10 side. And reaches the outside of the semiconductor light emitting device.

  On the other hand, as W1 / T increases as shown in FIG. 2B, the light incident on the optical base material 10 from the laminated semiconductor layer becomes difficult to reach the side surface of the optical base material 10, and the fine concavo-convex structure again from the optical base material 10 side. The rate of incidence on 20 increases.

  At this time, in the conventional micro-order pattern, it is scattered even when incident from the optical substrate 10 side, and a new waveguide mode is generated. In this path, it is necessary to change the angle so that it is totally reflected within the laminated semiconductor layer at least once and is incident on the fine concavo-convex structure 20 again to extract the traveling direction of light. It is known that there is absorption in the laminated semiconductor layer and the transparent conductive film 60, and a loss occurs, and as a result, improvement in LEE due to the fine concavo-convex structure 20 is reduced.

  In order to create a high-efficiency LED with high light output, in order to suppress the decrease in internal quantum efficiency due to droop, while ensuring a light-emitting area that becomes an appropriate current density region, the light extraction efficiency can be improved even under a large area condition. It is necessary to keep improving. However, it is not optimal because it has a scattering property in the micro order as described above, and it is made possible by controlling the behavior by the wave nature of light generated by making it in the nano order.

  Although shown in FIG. 2 as one-dimensional for convenience, an actual chip has a depth. Therefore, the ratio M is described as in equation (1). In Formula (1), W1 represents the width in the longitudinal direction of the optical substrate 10, W2 represents the width in the short direction of the optical substrate 10, and T represents the thickness of the optical substrate 10. Since the incidence frequency from the optical base material 10 to the semiconductor layer increases as the ratio M increases, the effect of forming the fine concavo-convex structure 20 becomes remarkable. When the fine concavo-convex structure 20 is provided, M is preferably 1 or more, more preferably 1.1 or more, and still more preferably 1.2 or more.

  In FIG. 2, the dimensions of the fine concavo-convex structure 20 are exaggerated and do not represent the dimensional ratio between the fine concavo-convex structure 20 and the actual optical substrate 10.

  The reflection layer 90 has a reflectance of 80% or more at the wavelength of light generated inside the element.

  This is because, as shown in FIG. 2, particularly in face-up mounting, the light is incident on the fine concavo-convex structure 20 from the optical substrate 10 side due to reflection on the other main surface of the optical substrate 10. Therefore, in order to reduce the attenuation of this component, it is preferable that the reflective layer 90 is provided and the reflectance of the reflective layer 90 is high. Specifically, it is preferably 80% or more, more preferably 85% or more, and most preferably 90% or more. As the reflective layer 90, for example, a single layer film or a multilayer film of a metal such as Ag or Al or an alloy thereof, or a dielectric multilayer film can be provided. The film formation method is not particularly limited, and for example, a known method such as a vacuum evaporation method or sputtering can be used.

  The contribution of this path increases as the ratio M between the cross-sectional area and the side area of the optical substrate 10 increases. Therefore, the effect of increasing the reflectance is greater as M is larger. M is preferably 1 or more, more preferably 1.1 or more, and still more preferably 1.2 or more.

  The emission wavelength of the element can be determined by, for example, a wavelength meter or a spectral radiance meter. The reflectance can be measured by preparing a substrate on which only the reflective layer 90 is formed and, for example, using a spectral reflectance measuring device.

  FIG. 3 is an explanatory diagram showing the widths W1 and W2 in the semiconductor light emitting device in the present embodiment. As shown in FIG. 3A, when the cross section of the semiconductor light emitting device 100 is substantially square, W1 and W2 are substantially equal. As shown in FIG. 3B, in the case of a rectangle, the longitudinal direction and the lateral direction are W1 and W2, respectively. That is, W1 and W2 are different.

  The widths W1 and W2 of the optical substrate 10 can be measured by, for example, an optical microscope. The thickness T of the optical substrate 10 can be measured by, for example, STEM (scanning transmission electron microscope). The boundary with the stacked semiconductor layer of about several μm can be clarified from the contrast of the image, which is preferable.

  The lighting device according to the present embodiment is characterized in that a semiconductor light emitting element 100 is mounted. By using the semiconductor light emitting element 100 for a lighting device, a lighting device with lower cost and longer life can be obtained. In the lighting application, the light output or light flux required by the application and place used is determined, and in order to achieve this standard, a plurality of LEDs are usually mounted on the lighting device. Therefore, if the light output per LED is improved, the number of LEDs used in the lighting device can be reduced. This also leads to a reduction in the number of parts required for mounting. An increase in the number of mounted LEDs leads to an increase in failure rate such as electrode peeling, contact failure, and drive circuit failure. This is a situation in which it is difficult to say that the LED has a long life characteristic as a lighting device. The reduction in the failure rate due to the decrease in the number of mounting points and the reduction in cost contribute to the further spread of the LED as a lighting device. Is.

  Hereinafter, parameters of the fine uneven structure 20 will be described. The fine concavo-convex structure 20 includes a plurality of convex portions or concave portions. If the fine concavo-convex structure 20 has a convex part or a concave part, the shape and arrangement thereof are not limited, and the internal quantum efficiency IQE and the light extraction efficiency LEE can be increased. For this reason, for example, a line-and-space structure in which a plurality of fence-like bodies are arranged, a dot structure in which a plurality of dot (convex portions, protrusions) -like structures are arranged, a hole structure in which a plurality of hole (concave) -like structures are arranged, etc. Can be adopted. Examples of the dot structure and the hole structure include a cone, a cylinder, a quadrangular pyramid, a quadrangular prism, a hexagonal pyramid, a hexagonal pyramid, a polygonal pyramid, a double ring shape, and a multiple ring shape. These shapes include a shape in which the outer diameter of the bottom surface is distorted and a shape in which the side surface is curved. The dot structure is a structure in which a plurality of convex portions are arranged independently of each other. That is, each convex part is separated by a continuous concave part. In addition, each convex part may be smoothly connected by the continuous recessed part. On the other hand, the hole structure is a structure in which a plurality of recesses are arranged independently of each other. That is, each recessed part is separated by the continuous convex part. In addition, each recessed part may be smoothly connected by the continuous convex part.

  As the arrangement of the fine concavo-convex structure 20, a regular hexagonal arrangement, a regular tetragonal arrangement, a quasi-hexagonal arrangement, a quasi-tetragonal arrangement, or the like can be adopted. Furthermore, a combination of these sequences can also be employed. For example, an array in which a regular hexagonal array and a regular tetragonal array are alternately arranged, an array that gradually changes from a regular hexagonal array to a regular tetragonal array, and gradually returns from the regular tetragonal array to the regular hexagonal array, and the like. Here, the quasi-hexagonal array is defined as an array in which the distance (pitch) between adjacent convex portions of the regular hexagonal array has a deviation of ± 15% or less. This deviation amount may be a uniform deviation amount in the array, or a distribution may be provided for the deviation amount. Moreover, the arrangement of the fine concavo-convex structure 20 may be different.

  Next, parameters used in the fine concavo-convex structure 20 are defined. The parameter measurement method will be described after the description of the parameters. Further, in the following description, the case where the fine concavo-convex structure 20 has a dot structure will be described. However, in the description of the case of a hole structure, the following terms may be used in the same manner, except for a specific distinction. it can.

<Pitch P and average pitch Pav>
FIG. 4 is a top view of the first semiconductor layer of the semiconductor light emitting device according to the present embodiment as viewed from the surface side where the fine concavo-convex structure is formed. When the fine concavo-convex structure 20 is a dot structure in which a plurality of convex portions 20a are arranged in the concave portions 20b, the center of a certain convex portion A1 and the convex portions B1-1 to B1- adjacent to the convex portion A1. the distance _{P A1B1-1} ~ distance _{P A1B1-6} between the center of 6, is defined as a pitch P. However, as shown in FIG. 4, when the pitch P differs depending on the adjacent convex portions, the average pitch Pav is determined according to the following procedure. (1) A plurality of arbitrary convex portions A1, A2,... AN are selected. (2) The pitches P _{AMBM-1 to} P _AMBM-k between the convex portions AM (1 ≦ M ≦ N) and the convex portions (BM-1 to BM-k) adjacent to the convex portion AM are measured. (3) For the convex portions A1 to AN, the pitch P is measured as in (2). (4) An arithmetic average value of the pitches P _{A1B1-1 to} P _ANBN-k is defined as an average pitch Pav. However, N is 5 or more and 10 or less, and k is 4 or more and 6 or less. In the case of the hole structure, the average pitch Pav can be defined by replacing the convex portion 20a described in the dot structure with a concave opening.

FIG. 5 is a top view of the first semiconductor layer of the semiconductor light emitting device according to the present embodiment as viewed from the surface side on which the fine concavo-convex structure is formed. As shown in FIG. 5, when the fine concavo-convex structure 20 is a line-and-space structure, the center line of a certain convex line A1, and the center lines of the convex line B1-1 and the convex line B1-2 adjacent to the convex line A1 The arithmetic mean of the shortest distance P _A1B1-1 and the shortest distance P _A1B1-2 is defined as the pitch P. However, as shown in FIG. 5, when the pitch P differs depending on the selected convex line, the average pitch Pav is determined according to the following procedure. (1) An arbitrary plurality of convex lines A1, A2,... AN are selected. (2) The pitches P _AMBM-1 and P _AMBM-2 between the convex lines AM (1 ≦ M ≦ N) and the convex lines (BM-1, BM-2) adjacent to the convex line AM are measured. (3) For the convex lines A1 to AN, the pitch P is measured as in (2). (4) An arithmetic average value of the pitches P _{A1B1-1 to} P _ANBN-2 is defined as an average pitch Pav. However, N is 5 or more and 10 or less.

<Convex top width lcvt, concave opening width lcct, convex bottom width lcvb, concave bottom width lccb>
FIG. 6 is a top view showing a case where the fine uneven structure of the semiconductor light emitting device according to the present embodiment has a dot structure. A line segment indicated by a broken line in FIG. 6 is a distance between the center of a certain convex portion 20a and the center of the convex portion 20a closest to the convex portion 20a, and means the pitch P described above. FIGS. 7A and 7B show schematic cross-sectional views of the fine concavo-convex structure 20 at the line segment position corresponding to the pitch P shown in FIG. FIG. 7 is a schematic cross-sectional view showing a fine concavo-convex structure at a line segment position corresponding to the pitch P shown in FIG.

  As shown in FIG. 7A, the convex portion top width lcvt is defined as the width of the top surface of the convex portion 20a, and the concave portion opening width lcct is a difference value (P−lcvt) between the pitch P and the convex portion top width lcvt. Defined.

  As shown in FIG. 7B, the convex bottom width lcvb is defined as the bottom width of the convex portion 20a, and the concave bottom width lccb is defined as a difference value (P−lcvb) between the pitch P and the convex bottom width lcvb. Is done.

  FIG. 8 is a top view showing a case where the fine uneven structure of the semiconductor light emitting device according to the present embodiment has a hole structure. FIG. 8 shows a top view when the fine relief structure 20 has a hole structure. A line segment indicated by a broken line in FIG. 8 is the distance between the center of a certain recess 20b and the center of the recess 20b closest to the recess 20b, and means the pitch P described above. FIGS. 9A and 9B show schematic cross-sectional views of the fine concavo-convex structure 20 at the line segment position corresponding to the pitch P shown in FIG. FIG. 9 is a schematic cross-sectional view showing a fine concavo-convex structure at a line segment position corresponding to the pitch P shown in FIG.

  As shown in FIG. 9A, the recess opening width lcct is defined as the opening width of the recess 20b, and the protrusion top width lcvt is defined as a difference value (P−lcct) between the pitch P and the recess opening width lcct.

  As shown in FIG. 9B, the convex bottom width lcvb is defined as the width of the convex portion 20a, and the concave bottom width lccb is defined as a difference value (P-lcvb) between the pitch P and the convex bottom width lcvb. Is done.

<Duty>
In the case of the dot structure, the duty is defined by a ratio (lcvb / P) between the convex bottom width lcvb and the pitch P. On the other hand, in the case of the hole structure, it is defined by the ratio of the recess bottom width lccb to the pitch P (lccb / P).

  First, the influence of the duty on the fine concavo-convex structure 20 will be described. From the above definition, a small duty indicates that there are many flat surfaces at the bottom of the recesses in the case of a flat part of the concavo-convex structure, that is, an arrangement of dot structures. This is advantageous in terms of crystal growth because nucleation is likely to occur, but it is preferable that the number of flat portions that do not contribute to diffraction is small in terms of light extraction.

  On the other hand, the upper limit of the duty is determined from the crystal growth of the semiconductor layer. If the area of the flat portion of the optical substrate is too small, nucleation during crystal growth is hindered, resulting in a decrease in crystal quality.

  Further, the diffraction is characterized by the volume of the convex portion 20a. In a dot structure or a hole structure, which is an array of independent protrusions 20a or recesses 20b, the duty is square with respect to the volume of the protrusions 20a. Considering the above, in the fine concavo-convex structure 20, the duty is preferably 0.3 or more, and more preferably 0.5 or more, with respect to the arrangement of the convex portions 20a of the dot structure. The upper limit is preferably 0.91 or less, and more preferably 0.86 or less.

  Furthermore, in the fine concavo-convex structure 20 having continuous convex portions such as a line and space structure, the volume of the convex portions is linear with respect to the duty. Therefore, the duty is more preferably 0.3 or more, and most preferably 0.5 or more. The upper limit is preferably 0.83 or less, and more preferably 0.74 or less.

<Height H>
The height H of the fine concavo-convex structure 20 is defined as the shortest distance between the average position of the bottom of the concave portion 20b of the fine concavo-convex structure 20 and the average position of the top of the convex portion 20a of the concavo-convex structure. The number of sample points for calculating the average position is preferably 10 or more.

  The larger the height H, the more modes interact with the incident light from the group of diffraction modes determined by the average pitch Pav. That is, when the height H is small, incident light acts through only the diffracted light of a limited mode from the group of diffraction modes determined by the average pitch Pav through the fine concavo-convex structure 20, but the height H is When it is larger, more diffraction modes in the group of diffraction modes determined by the average pitch Pav interact with the incident light. That is, as the height H is larger, the interaction between the incident light and the fine concavo-convex structure 20 becomes more scattering in behavior. The larger the height H, the more the modes interact, but this includes modes that do not contribute to light extraction. Therefore, if it is scattering, a loss occurs. Therefore, the fine concavo-convex structure 20 does not need to have an excessively high shape.

  In particular, in the case where the average pitch Pav of the fine concavo-convex structure 20 is in the predetermined range, the thickness of the first semiconductor layer 30 required for planarization can be reduced because the protrusions 20a are in the nanometer order. Therefore, warpage and cracks in the semiconductor light emitting device 100 derived from the difference in the lattice constant between the optical substrate 10 and the semiconductor layer or the difference in the thermal expansion coefficient can be suppressed. From the above viewpoint, the height H of the fine concavo-convex structure 20 is preferably not more than 1 time and more preferably not more than 0.7 times the average pitch Pav.

  Next, a method for measuring the parameters will be described. The parameters such as the duty, the side inclination angle Θ, and the height H can be obtained for each concavo-convex structure from the above definition by observing a fine concavo-convex structure, for example, by imaging with a scanning electron microscope (SEM). it can. In this specification, an arithmetic average is taken in the local range described below, and the obtained value is set as a parameter value of the fine concavo-convex structure.

(Arithmetic mean)
When N measured values of a distribution of a certain element (variable) are x1, x2,..., Xn, the arithmetic mean value is defined by the following equation (2).

  The number N of sample points when calculating the arithmetic mean is defined as 20. The reason is set to 20 in order to obtain a sufficient statistical average when individual concavo-convex structures are arbitrarily selected within the following local range.

  Here, the local range used for observation is defined as a range of about 5 to 50 times the average pitch Pav of the fine concavo-convex structure. For example, if the average pitch Pav is 700 nm, the observation is performed within the observation range of 3500 nm to 35000 nm. For this reason, for example, a field image of 7500 nm is captured at, for example, the center position in a region having a fine concavo-convex structure, and an arithmetic average is obtained using the imaging. For example, a scanning electron microscope (SEM) can be used to capture the field image.

  Next, materials and the like of each layer constituting the semiconductor light emitting element 100 will be described. In the semiconductor light emitting device 100 according to the present embodiment, the fine concavo-convex structure 20 provided on the upper surface of the optical substrate 10 satisfies the predetermined range, and the dimensional ratio M of the optical substrate 10 is expressed by the above formula (1). By satisfying the above, it becomes the semiconductor light emitting device 100 in which both the internal quantum efficiency IQE and the light extraction efficiency LEE are improved. As long as this effect is exhibited, the material, state, number of layers or thickness of each semiconductor layer, The material, the number of layers, the arrangement or thickness, the material of the light emitting semiconductor layer, the number of layers or thickness, the material of the growth substrate, the plane orientation, the thickness, and the like can be appropriately selected and are not particularly limited.

  A first light emitting semiconductor layer 30, a light emitting semiconductor layer 40, and a second semiconductor layer 50 are sequentially stacked from the bottom of the optical base material 10 having the fine concavo-convex structure 20 formed on the upper surface. To do. Here, the semiconductor light emitting device 100 according to the present embodiment is characterized in that the emitted light generated in the light emitting semiconductor layer 40 is extracted from the optical substrate 10. Further, the first semiconductor layer 30 and the second semiconductor layer 50 are different semiconductor layers. Here, it is preferable that the first semiconductor layer 30 planarizes the fine concavo-convex structure 20. By providing the first semiconductor layer 30 so as to planarize the fine concavo-convex structure 20, the performance of the first semiconductor layer 30 as a semiconductor can be reflected in the light emitting semiconductor layer 40 and the second semiconductor layer 50. Therefore, the internal quantum efficiency IQE is improved. The first semiconductor layer 30 may be composed of an undoped first semiconductor layer 31 and a doped first semiconductor layer 32.

  Further, the light emitting semiconductor layer 40 and the second semiconductor layer 50 are stacked following the first semiconductor layer 30. Thereafter, the transparent conductive film 60 is formed on the second semiconductor layer 50 of the semiconductor light emitting device 100, the anode electrode 70 is formed on the upper surface of the transparent conductive film 60, the cathode electrode 80 is formed on the upper surface of the first semiconductor layer 30, and the optical substrate 10. The reflective layer 90 can be provided on the back surface of each. The arrangement of the transparent conductive film 60, the anode electrode 70, and the cathode electrode 80 is not limited because it can be appropriately optimized by the semiconductor light emitting element, but is generally provided as illustrated in FIG.

First semiconductor layer 30
The first semiconductor layer 30 is not particularly limited as long as it can be used as an n-type semiconductor layer suitable for a semiconductor light emitting device (LED). For example, elemental semiconductors such as silicon and germanium, and compound semiconductors such as III-V, II-VI, and VI-VI can be appropriately doped with various elements.

  The first semiconductor layer 30 and the optical base material 10 on which the fine concavo-convex structure 20 described later can be combined as appropriate from the viewpoint of reducing dislocations inside the first semiconductor layer 30. When the flat surface of the bottom of the concave portion 20b of the fine concavo-convex structure 20 and the surface substantially parallel to the stable growth surface of the first semiconductor layer 30 are parallel to each other, in the vicinity of the concave portion 20b of the fine concavo-convex structure 20 Since the disorder of the growth mode of the first semiconductor layer 30 is increased and the dislocations in the first semiconductor layer 30 can be effectively dispersed according to the fine concavo-convex structure 20, the internal quantum efficiency IQE is improved. The stable growth surface is the surface with the slowest growth rate in the material to be grown.

  Further, since the fine concavo-convex structure 20 is nano-order, the thickness necessary for planarizing the fine concavo-convex structure 20 in the first semiconductor layer 30 is reduced. For this reason, since the semiconductor layer that absorbs light from the light emitting semiconductor layer 40 is thinned, the light extraction efficiency LEE is expected to be further improved, and the first semiconductor layer 30 and the light emitting semiconductor layer 40 sequentially stacked thereon are also provided. And it becomes possible to suppress the curvature of the 2nd semiconductor layer 50, and it can be set as the semiconductor light emitting element 100 of a larger area than before. For this reason, the thickness of the first semiconductor layer 30 is preferably 5 μm or less, more preferably 4 μm or less, further preferably 3.5 μm or less, still more preferably 2.5 μm or less, and most preferably 1.5 μm or less.

-Light emitting semiconductor layer 40
The light emitting semiconductor layer 40 is not particularly limited as long as it has a light emitting characteristic as a semiconductor light emitting element (for example, LED). For example, as the light emitting semiconductor layer 40, a semiconductor layer such as AsP, GaP, AlGaAs, InGaN, GaN, AlGaN, ZnSe, AlHaInP, or ZnO can be applied. Further, the light emitting semiconductor layer 40 may be appropriately doped with various elements according to characteristics.

Second semiconductor layer 50
The second semiconductor layer 50 is not particularly limited as long as it can be used as a p-type semiconductor layer suitable for a semiconductor light emitting element (for example, LED). For example, elemental semiconductors such as silicon and germanium, and compound semiconductors such as III-V, II-VI, and VI-VI can be appropriately doped with various elements.

Optical substrate 10
The material of the optical substrate 10 is not particularly limited as long as it can be used as a substrate for a semiconductor light emitting device. Sapphire, SiC, SiN, GaN, W-Cu, silicon, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron oxide, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, oxidation Substrates such as lithium aluminum, neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium, tungsten, molybdenum, GaP, and GaAs can be used. Of these, sapphire, GaN, GaP, GaAs, SiC substrate, Si substrate, spinel substrate and the like are preferably used from the viewpoint of lattice matching with the semiconductor layer. Furthermore, it may be used alone, or may be a heterostructure substrate in which another substrate is provided on the substrate body using these. Particularly in face-up mounting, it is preferable that the optical substrate 10 has a small absorption with respect to the emission wavelength. For example, a sapphire substrate having a C plane (0001) as the main surface can be used as the optical base material 10.

・ Transparent conductive film 60
In the semiconductor light emitting device 100 according to the present embodiment, the material of the transparent conductive film 60 is not particularly limited as long as it can be used as the transparent conductive film 60 suitable for LEDs, for example. For example, a metal thin film such as a Ni / Au electrode or a conductive oxide film such as ITO, ZnO, In ₂ O ₃ , SnO ₂ , IZO, or IGZO can be applied. In particular, ITO is preferable from the viewpoints of transparency and conductivity.

Reflective layer 90
The material of the reflective layer 90 is not particularly limited as long as the reflectance at the emission wavelength is high. For example, for metal, Ag, Al, or an alloy thereof is selected, for example, from reflectivity and adhesion to the optical substrate 10. Alternatively, a dielectric multilayer film may be formed in order to obtain a higher reflectance. The film thickness and the number of layers are not particularly limited as long as the reflectance is in a desired range. For example, titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, aluminum nitride, low refractive index as a high refractive index layer Silicon oxide can be used as the layer. Further, after forming the dielectric multilayer film, a metal film may be formed.

  In order to improve the adhesion with the optical substrate 10, an adhesion layer may be provided between the optical substrate 10 and the reflective layer 90. For example, silicon oxide can be used for the adhesion layer.

  Next, each process of the manufacturing method of the semiconductor light emitting device 100 according to the present embodiment will be described.

-Fine concavo-convex structure preparation process If the above-described fine concavo-convex structure 20 can be formed, the production method is not limited, and a transfer method, a photolithography method, a thermal lithography method, an electron beam drawing method, an interference exposure method, and nanoparticles It can be manufactured by a lithography method using a mask as a mask, a lithography method using a self-organized structure as a mask, or the like. In particular, it is preferable to employ a transfer method from the viewpoint of processing accuracy and processing speed of the fine relief structure 20.

  The transfer method in this specification is defined as a method including a step of transferring a texture of a mold having a texture on the surface to an object to be processed (the optical substrate 10 before producing the fine concavo-convex structure 20). That is, it is a method including at least a step of bonding a texture of a mold and an object to be processed through a transfer material and a step of peeling the mold. More specifically, the transfer method can be classified into two.

  First, the transfer material transferred to the object to be processed is used as a permanent agent. In this case, particularly in the fine concavo-convex structure 20, the materials constituting the optical substrate 10 main body and the fine concavo-convex structure 20 are different. Further, the fine uneven structure 20 remains as a permanent agent and is used as the semiconductor light emitting device 100. Since the semiconductor light emitting device 100 is used for a long period of tens of thousands of hours, when the transfer material is used as a permanent agent, the material constituting the transfer material preferably contains a metal element. In particular, it is preferable to include a metal alkoxide that generates a hydrolysis / polycondensation reaction or a metal alkoxide condensate as a raw material because the performance as a permanent agent is improved.

  Secondly, there is a nanoimprint lithography method. The nanoimprint lithography method includes a step of transferring a texture of a mold onto a target object, a step of providing a mask for processing the target object by etching, and a step of etching the target object. For example, when one type of transfer material is used, first, the object to be processed and the mold are bonded via the transfer material. Subsequently, the transfer material is cured by heat or light (UV), and the mold is peeled off. Etching typified by oxygen ashing is performed on the concavo-convex structure made of a transfer material to partially expose the object to be processed. Thereafter, the object to be processed is processed by etching using the transfer material as a mask. As a processing method at this time, dry etching and wet etching can be employed. Dry etching is useful for increasing the height of the concavo-convex structure. For example, when two types of transfer materials are used, a first transfer material layer is first formed on the object to be processed using the first transfer material. Subsequently, the first transfer material layer and the mold are bonded via the second transfer material. Thereafter, the transfer material is cured by heat or light (UV), and the mold is peeled off. Etching typified by oxygen ashing is performed on the concavo-convex structure composed of the second transfer material layer to partially expose the first transfer material layer. Subsequently, the first transfer material layer is etched by dry etching using the second transfer material layer as a mask. Thereafter, after the etching, the object to be processed is processed by etching using the remaining first transfer material layer and second transfer material layer as a mask. As a processing method at this time, dry etching and wet etching can be employed. Dry etching is useful for increasing the height of the fine relief structure.

  As described above, by adopting the transfer method, the texture of the mold can be reflected on the object to be processed, so that the optical substrate 10 or the fine concavo-convex structure 20 having the fine concavo-convex structure 20 is provided. The semiconductor light emitting device 100 can be obtained.

  The material of the nanoimprint mold is not particularly limited, and non-flexible glass, quartz, sapphire, nickel, or flexible resin can be used. Among them, it is preferable to use a flexible mold because the transfer accuracy of the texture of the mold is improved and the accuracy of the fine uneven structure 20 to be formed is improved.

-Semiconductor layer and transparent conductive film lamination process On the fine uneven structure 20 of the optical base material 10, the 1st semiconductor layer 30, the light emitting semiconductor layer 40, the 2nd semiconductor layer 50, and the transparent conductive film 60 are formed into a film in order. The method for forming each semiconductor layer is not particularly limited, but the well-known metal organic chemical vapor deposition method (MOCVD method), molecular beam crystal growth method (MBE method), halide vapor phase epitaxy method (HVPE method), sputtering method, It can be formed by an ion plating method, an electron shower method, or the like.

  Since the fine concavo-convex structure 20 has a nano-order structure, the thickness of the first semiconductor layer 30 for planarization can be reduced. This means that the manufacturing time and cost are reduced as compared with the conventional method. In LED manufacturing, the (MO) CVD process, which is a semiconductor crystal layer deposition process, is rate-limiting, lowering throughput and raising material costs. The ability to reduce the amount of semiconductor crystals means an improvement in throughput of the (MO) CVD process and a reduction in materials used, which is an important requirement for manufacturing.

-Electrode formation process The anode electrode 70 and the cathode electrode 80 are formed with respect to the wafer formed into a film as mentioned above. These electrodes are formed by a known method. For example, a photoresist is formed, and photolithography is performed to pattern the semiconductor light emitting device 100. The portion not covered with the resist is etched down to the first semiconductor layer 30 by chlorine-based dry etching, and then the resist is removed. A photoresist is formed again, and photolithography is performed to pattern the electrode pad formation site. Next, a metal (Cr, Ti, Au, etc.) as an electrode pad material is formed on the entire surface by a known method such as vacuum deposition or sputtering. Thereafter, the resist and the electrode pad material formed on the resist are removed by a lift-off method, and the anode electrode 70 and the cathode electrode 80 are formed.

  The material of the anode electrode 70 and the cathode electrode 80 may be any material that can contact the semiconductor layer to which the electrodes are bonded with low resistance. The anode electrode 70 and the cathode electrode 80 may have a structure including only a pad portion. However, a wiring electrode having a grid pattern or a radial pattern continuous to the pad portion is provided to improve current diffusion in the element surface direction. You may make it make it.

-Reflective layer formation process The reflective layer 90 is formed in the other surface opposite to one main surface which has the fine concavo-convex structure 20 of the optical base material 10. FIG. The material of the reflective layer 90 is, for example, Al, Ag, or an alloy thereof. In order to obtain a higher reflectance, a dielectric multilayer film may be formed as the reflective layer 90. For example, titanium oxide, zirconium oxide, niobium oxide, tantalum oxide, aluminum nitride can be used as the high refractive index layer, and silicon oxide can be used as the low refractive index layer. Further, after forming the dielectric multilayer film, a metal film may be formed.

  In order to improve the adhesion with the optical substrate 10, an adhesion layer may be provided between the optical substrate 10 and the reflective layer 90. For example, silicon oxide can be used for the adhesion layer.

  The reflective layer 90 can be formed by a known method such as vacuum vapor deposition or sputtering.

  Further, before the reflective layer 90 is formed, for example, the optical substrate 10 may be polished to reduce the thickness.

・ Cutting process Using a laser scrip or a laser dicer, etc., a singulation process is performed to divide into light emitting elements.

First, an LED substrate was prepared. The pattern of the board | substrate for LED was created using the nano process sheet | seat. The nano-processed sheet will be described later. A 2-inch single-sided mirror c-plane sapphire was prepared and washed. Subsequently, sapphire was placed on a 120 ° C. hot plate. Next, the nano-processed sheet was bonded to sapphire using a laminate roll heated to 120 ° C. The bonding was performed at a pressure of 0.5 MPa and a linear speed of 50 mm / second. The sapphire bonded with the nano-processed sheet was irradiated with ultraviolet rays through the sapphire. The ultraviolet rays were irradiated from a UV-LED light source having a wavelength of 365 nm, and the integrated light amount was set to 1500 mJ / cm ² . Next, the nano-processed sheet and sapphire were sandwiched between two parallel flat plates heated to 120 ° C. The sandwiching pressure was 0.3 MPa and the time was 10 seconds. Subsequently, it was cooled to room temperature by air cooling, and the nano-processed sheet was peeled from sapphire at a speed of 50 mm / second. With the above operation, a two-layer resist layer was transferred onto the main surface of sapphire. An uneven structure is provided on the surface of the resist layer. The pattern of the LED substrate was controlled by the shape and arrangement of the concavo-convex structure, the layer structure of the two-layer resist, and the dry etching conditions described below.

  The nano-processed sheet is a molded body that can transfer and apply a processing mask onto the object to be processed by a bonding operation and a peeling operation. The configuration includes a resin mold, a first resist layer, and a second resist layer. The resin mold has a concavo-convex structure on the surface, and the first resist layer is filled inside the concave portion of the concavo-convex structure. Then, the second resist layer is disposed so as to flatten the uneven structure of the resin mold and the first resist layer.

  First, a resin mold was manufactured using a roll-to-roll optical nanoimprint method. The width is 500 mm and the length is 180 m. As a layer structure, there is a structure in which a transfer layer having a thickness of 1.5 μm is provided on an easily adhesive surface of a PET film having a thickness of 50 μm, and there is a concavo-convex structure transferred onto the surface of the transfer layer by an optical nanoimprint method. Moreover, the contact angle of the water droplet with respect to the concavo-convex structure surface of the resin mold was between 140 ° and 153 °.

  Next, the 1st resist layer was formed into a film with the die-coating method with respect to the uneven structure of a resin mold. The first resist layer is a titanium-containing organic-inorganic composite resist. The titanium-containing organic-inorganic composite resist was diluted with a mixed solvent in which a solvent A having a surface tension of 24.0 mN / m or less and a solvent B having a surface tension of 27.0 or more were mixed to prepare a coating solution. When coating by the die coating method, the upstream side of the die lip was decompressed. The filling speed of the first resist layer was controlled by controlling the discharge rate at a coating speed of 10 m / min. After coating, air at 120 ° C. was blown and dried, and then wound up and collected. Here, the resin mold on which the first resist layer was formed was analyzed to grasp the state of the first resist layer. For the analysis, a scanning electron microscope, a transmission electron microscope, and energy dispersive X-ray spectroscopy were used in combination. The first resist layer was filled in the concave portion of the concave-convex structure of the resin mold. On the other hand, a residue (aggregate) of the first resist layer on the order of several nanometers was sometimes observed on the upper surface of the convex portion of the concavo-convex structure of the resin mold, but the first resist layer was observed on the upper surface. A thick film was not formed. Further, regarding die coating, it was confirmed that the filling amount of the first resist layer was changed by changing the discharge amount of the coating liquid, and the filling diameter of the first resist layer was changed accordingly.

  Next, a second resist layer was formed on the resin mold filled with the first resist layer. The film forming method was the same as that for the first resist layer. The second resist layer is a novolac resin having an acryloyl group in the side chain, and diluted with a solvent having a surface tension of 25.0 mN / m or less to obtain a coating solution. Drying was performed at 105 ° C. After drying, a PE / EVA protective film having a haze (turbidity) of 10% or less was bonded, wound and collected. Here, the manufactured nano-processed sheet was analyzed, and the states of the first resist layer and the second resist layer were grasped. For the analysis, a scanning electron microscope, a transmission electron microscope, and energy dispersive X-ray spectroscopy were used in combination. The first resist layer did not change before and after the second resist layer was formed. The second resist layer could be formed so as to flatten the uneven structure of the resin mold and the first resist layer. In addition, it was confirmed that the film thickness can be controlled by changing the discharge amount of the die coat film formation. That is, the discharge amount of the die coat film formation was controlled to change the filling diameter of the first resist layer and the film thickness of the second resist layer.

Using the manufactured nano-processed sheet, as already described, a two-layer resist layer composed of a first resist layer and a second resist layer was transferred onto the main surface of sapphire. Next, etching for processing the resist layer and etching for processing sapphire were continuously performed in the same chamber. Oxygen gas was used for etching the resist layer. Here, the first resist layer functions as an etching mask for the second resist layer, and the second resist layer is etched until the main surface of sapphire is partially exposed. The etching conditions were a processing gas pressure of 1 Pa and a processing power of 300 W. Subsequently, reactive ion etching using a mixed gas of BCl ₃ gas and Cl ₂ gas was performed to etch sapphire. Here, sapphire was etched using the second resist layer as an etching mask. The processing conditions were ICP: 150 W, BIAS: 50 W, and pressure 0.2 Pa.

  The etched sapphire was taken out and washed with a solution in which sulfuric acid and hydrogen peroxide were mixed at a weight ratio of 2: 1. At this time, the temperature of the treatment liquid was controlled to 100 ° C. or higher.

  A pattern was formed on the main surface of the manufactured sapphire. The shape of the pattern (diameter φ, height H of the convex bottom) can be arbitrarily adjusted depending on the filling diameter of the first resist layer and the thickness of the second resist layer of the nano-processed sheet, and the dry etching processing conditions. It was.

  On the obtained sapphire base material, a low-temperature growth buffer layer of AlxGa1-xN (0 ≦ x ≦ 1) was formed as a buffer layer in a thickness of 100 mm. Next, undoped GaN was formed as an undoped first semiconductor layer, and Si-doped GaN was formed as a doped first semiconductor layer. Subsequently, a strain absorption layer is provided, and then, as a light emitting semiconductor layer, a multi-quantum well active layer (well layer, barrier layer = undoped InGaN, Si-doped GaN) is formed as a well layer with a thickness of (60 mm, 250 mm). Were alternately stacked so that there were 6 layers and 7 barrier layers. On the light emitting semiconductor layer, Mg-doped AlGaN, undoped GaN, and Mg-doped GaN were laminated as a second semiconductor layer so as to include an electroblocking layer, to obtain a laminated semiconductor layer.

  Thereafter, ITO was formed as a transparent conductive film, and after the electrode forming step, the sapphire substrate was polished from 120 μm to 150 μm in thickness to provide a reflective layer on the back surface. The reflective layer was formed of a dielectric multilayer film made of an Ag—Pd—Cu alloy or titanium oxide / silicon oxide. Thereafter, the semiconductor light-emitting element obtained through the cutting process was mounted face up. A gold-plated TO can was joined with an Ag paste, and wire bonding was performed to pass a current between the p electrode pad and the n electrode pad, and the light emission output was measured. At this time, as shown in Table 1, the chip dimensions are 120 μm * 360 μm square (Comparative Example 1), 120 μm * 500 μm square (Example 1), 135 μm * 600 μm square (Example 2), and 150 μm * thick. Four types of 550 μm × 1100 μm (Example 3) were prepared. The current was 20 mA for a 360 μm square chip, and for other size chips, the conditions were such that the current density was equivalent when converted to the area where ITO was deposited. The light emission output ratio is a semiconductor light emitting device produced from a base material having a commercially available micro-size pattern as a concave-convex structure, specifically, a base material having a conical concave-convex structure with a period of 3000 nm, a height of 1500 nm, and a bottom diameter of 2500 nm. The light emission output was set to 1 for each chip size. The emission wavelength was 450 nm.

  The internal quantum efficiency IQE was determined from the PL intensity. The internal quantum efficiency IQE is defined by (number of photons emitted from the light emitting semiconductor layer per unit time / number of electrons injected into the semiconductor light emitting element per unit time). In this example, (PL intensity measured at 300K / 10 PL intensity measured at 10K) was adopted as an index for evaluating the internal quantum efficiency IQE. From Tables 2 to 4, it is understood that IQE is higher than that of commercially available PSS, that is, the crystallinity is improved by using a nano-order fine uneven structure.

  Table 2 shows the case where an alloy material of Ag—Pd—Cu is used as the reflective layer. The reflectance at the emission wavelength was 89%.

  It can be seen that when M is greater than 1, the light emission output ratio is improved over PSS. When the light emission output ratio exceeds 1, it is a more efficient LED, and there are further effects such as simplification of the device heat radiation part by reducing heat generation over the light emission output ratio of the chip, which is industrially useful. Although it is obvious that even if the light emission output ratio is 1, the height of the convex portion is smaller than the PSS of the comparative example in the substrate used in the example, so that the productivity of the substrate by shortening the etching time when processing the substrate In addition, the GaN layer required for film formation of the semiconductor layer can be made thinner, which contributes to improvement of LED productivity and cost reduction.

  Table 3 shows the case where a multilayer film made of titanium oxide and silicon oxide is used as the reflective layer. As the adhesion layer, a multi-layer film was used in which a silicon oxide film having a thickness of 500 nm was formed, and then a titanium oxide film having a thickness of 55 nm and a silicon oxide film having a thickness of 75 nm. The reflectance at the emission wavelength was 99%. Since the dielectric multilayer film has a higher reflectance than the alloy material of Table 1, it can be seen that the degree of improvement is greater than the results of Table 1.

  Table 4 shows a case where no reflective layer is provided, and the Ag paste used for bonding becomes a substantial reflective layer. The reflectance was 70%. At this time, it can be seen that the improvement in light extraction efficiency due to the fine concavo-convex structure is not effectively exhibited regardless of the size of the chip.

  In addition, this invention is not limited to the said embodiment, It can change and implement variously. In the above-described embodiment, the size, shape, and the like illustrated in the drawings are not limited to this, and can be appropriately changed within a range in which the effects of the present invention are exhibited.

  The present invention can be suitably applied to a semiconductor light emitting element such as a light emitting diode (LED).

DESCRIPTION OF SYMBOLS 10 Optical base material 20 Fine uneven structure 30 1st semiconductor layer 40 Light emitting semiconductor layer 50 2nd semiconductor layer 60 Transparent conductive film 70 Anode electrode 80 Cathode electrode 90 Reflective layer 100 Semiconductor light emitting element

Claims (2)

At least a first semiconductor layer, a light emitting semiconductor layer, and a second semiconductor layer are stacked on an optical base material having a fine concavo-convex structure formed on a part or the whole of one main surface, and the one main surface is A semiconductor light emitting device having a structure in which a reflective layer is provided on the other main surface on the opposite side,
The average pitch Pav of the fine concavo-convex structure is 200 nm or more and 1500 nm or less, and
The ratio M shown in the following formula (1) determined from the width W1 in the longitudinal direction and the width W2 in the lateral direction and the thickness T of the optical substrate is 1 or more,
A semiconductor light emitting device, wherein the reflective layer has a reflectance of 80% or more.

An illumination device comprising the semiconductor light emitting element according to claim 1.

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