JP2016139714A - Semiconductor module and method for designing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the length of a surface layer wiring.SOLUTION: A semiconductor module comprises: a semiconductor chip D1F mounted on a first surface layer 20F of a module substrate 20 and including a signal input terminal 31; a semiconductor chip D1B mounted on a second surface layer 20B of the module substrate 20 and including a signal input terminal 32; a stub TL2_1 which is provided in the first surface layer 20F and whose one end is connected to the signal input terminal 31; a stub TL2_2 which is provided in the second surface layer 20B and whose one end is connected to the input signal terminal 32; at least one stub TL1_2 provided in an inner layer of the module substrate 20; a through hole conductor TH1 for connecting the stub TL1_2 and the other end of the stub TL2_1; and a through hole conductor TH2 for connecting the stub TL1_2 and other end of the stub TL2_2. According to the present invention, the length of the surface layer wiring can be shortened even when the semiconductor module is used as a first rank product.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a semiconductor module and a design method thereof, and more particularly to a semiconductor module in which a plurality of semiconductor chips are mounted on a module substrate and a design method thereof.

  A semiconductor module such as a memory module has a configuration in which a plurality of semiconductor chips are mounted on a module substrate. For example, the semiconductor module described in Patent Document 1 includes a module substrate having a multilayer wiring structure and a plurality of semiconductor chips mounted on the front and back of the module substrate. A plurality of inner layer wirings are provided on the inner layer of the module substrate. Each inner layer wiring is connected to one end of a surface layer wiring provided on the surface layer of the module substrate via a through-hole conductor provided through the module substrate. The other end of the surface layer wiring is connected to the terminal electrode of the semiconductor chip.

JP 2008-135597 A

  Here, since the plurality of semiconductor chips mounted on the module substrate are chips having the same configuration, the terminal layout of the semiconductor chip mounted on one surface layer (front surface) of the module substrate and the other of the module substrate The terminal layouts of the semiconductor chips mounted on the surface layer (back surface) of the semiconductor substrate are mirror images of each other when viewed in plan, for example, when viewed from one surface layer of the module substrate. For this reason, in so-called two-rank products, signal mirroring processing is performed when accessing a semiconductor chip mounted on the front surface of the module substrate and when accessing a semiconductor chip mounted on the back surface of the module substrate. By doing so, it becomes possible to shorten the length of the surface layer wiring.

  However, in the case of a so-called 1-rank product, since the semiconductor chip mounted on the front surface of the module substrate and the semiconductor chip mounted on the back surface are accessed simultaneously, the signal mirroring process cannot be performed. For this reason, depending on the position of the through-hole conductor, the length of the surface layer wiring becomes long, and there is a problem that the signal quality deteriorates. Moreover, unless the through-hole conductors are arranged at the center between the corresponding terminals, the length of the surface wiring formed on one surface layer (front surface) of the module substrate and the other surface layer (back surface) of the module substrate are formed. There is also a problem that a large difference occurs in the length of the surface layer wiring.

  A semiconductor module according to the present invention includes a module substrate having a first surface layer, a second surface layer located opposite to the first surface layer, and an inner layer located between the first and second surface layers, A first semiconductor chip mounted on the first surface layer of the module substrate and having a first signal input terminal, and a first semiconductor chip mounted on the second surface layer of the module substrate and having a second signal input terminal. Two semiconductor chips, a first surface layer wiring provided on the first surface layer of the module substrate, one end of which is connected to the first signal input terminal of the first semiconductor chip, and the module substrate A second surface layer wiring provided on the second surface layer, one end of which is connected to the second signal input terminal of the second semiconductor chip; and at least one inner layer provided on the inner layer of the module substrate. wiring A first through-hole conductor connecting the other end of the inner layer wiring and the first surface layer wiring, and a second through-hole conductor connecting the inner layer wiring and the other end of the second surface layer wiring. It is characterized by providing.

  In the present invention, the at least one inner layer wiring includes a first inner layer wiring that supplies the command address signal to the first through-hole conductor, the first through-hole conductor, and the second through-hole conductor. It is preferable to include a second inner layer wiring to be connected.

  The semiconductor module design method according to the present invention includes a first compensation length from the first inner layer wiring to the first signal input terminal of the first semiconductor chip, and a second compensation from the first inner layer wiring to the second inner layer wiring. And calculating a second compensation length to the second signal input terminal of the semiconductor chip, and based on the first and second compensation lengths, the first inner layer wiring of the first semiconductor chip is calculated. The third compensation length and the fourth compensation length of the first inner layer wiring with respect to the second semiconductor chip are corrected, and the first inner layer wiring is corrected based on the third and fourth compensation lengths. It is characterized by determining the length.

  According to the semiconductor module of the present invention, the length of the surface wiring can be shortened even when used as a one-rank product. Further, according to the semiconductor module design method of the present invention, the difference between the signal characteristics of the semiconductor chip mounted on the front surface of the module substrate and the signal characteristics of the semiconductor chip mounted on the back surface of the module substrate is reduced. The

1 is a development view of a semiconductor module 10 according to an embodiment of the present invention, in which an upper diagram is a front side and a lower diagram is a back side. 2 is a side view of the semiconductor module 10. FIG. It is a figure for demonstrating the propagation path | route of the command address signal CA. FIG. 4 is a cross-sectional view for explaining an internal structure of the module substrate 20. 4 is a schematic diagram for explaining an example of a connection relationship between each semiconductor chip 30 and a command address wiring. FIG. It is typical sectional drawing for demonstrating an example of the connection relation of semiconductor chip D1F and D1B and through-hole conductors TH1 and TH2. It is sectional drawing by the 1st reference example, and shows the case where it is a 2 rank product. FIG. 8 is a schematic plan view for explaining the positional relationship between through-hole conductors and terminals in the two-rank product shown in FIG. 7 and shows a configuration seen transparently from the semiconductor chip D1F side. It is a typical top view for demonstrating the positional relationship of the through-hole conductor and terminal in the 1 rank product which is a 2nd reference example, and has shown the structure seen transparently from the semiconductor chip D1F side. FIG. 4 is a schematic plan view for explaining the positional relationship between through-hole conductors and terminals in an embodiment of the present invention, and shows a configuration seen transparently from the semiconductor chip D1F side. It is typical sectional drawing for demonstrating the other example of the connection relation of semiconductor chip D1F and D1B and through-hole conductors TH1 and TH2. It is a schematic diagram for demonstrating the other example of the connection relation of each semiconductor chip 30 and command address wiring. It is a figure which shows the eye pattern of the command address signal CA at the time of designing on the basis of the compensation length CLF. It is a figure which shows the eye pattern of the command address signal CA at the time of designing in consideration of the value of the correction value α.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a development view of a semiconductor module 10 according to an embodiment of the present invention, in which an upper diagram is a front side and a lower diagram is a back side.

  As shown in FIG. 1, the semiconductor module 10 according to the present embodiment includes a module substrate 20 and a plurality of semiconductor chips 30 mounted on the module substrate 20. Although not particularly limited, the semiconductor chip 30 is a dynamic random access memory (DRAM). The module substrate 20 is a rectangular substrate whose longitudinal direction is the X direction, and four semiconductor chips 30 are mounted on the front and back sides thereof.

  In FIG. 1, four semiconductor chips 30 mounted on the first surface layer 20 </ b> F side of the module substrate 20 are denoted by reference signs D <b> 1 </ b> F to D <b> 4 </ b> F, and 4 mounted on the second surface layer 20 </ b> B side of the module substrate 20. Reference numerals D1B to D4B are attached to the two semiconductor chips 30. These semiconductor chips 30 are all arranged in the X direction. A plurality of external terminals 21 are arranged in the X direction on the long side of the module substrate 20.

  As shown in FIG. 2, the semiconductor chips D1F and D1B are mounted at positions that overlap in a plan view. Similarly, the semiconductor chips D2F and D2B are mounted at positions overlapping in plan view, the semiconductor chips D3F and D3B are mounted at positions overlapping in plan view, and the semiconductor chips D4F and D4B are mounted at positions overlapping in plan view. Since these semiconductor chips are DRAMs having the same configuration, the terminal arrays of two semiconductor chips (for example, D1F and D1B) located on the front and back are mirror images of each other. When the semiconductor chip 30 is a DRAM, the types of terminals include a data input / output terminal for inputting / outputting data, a signal input terminal for inputting a command address signal, a power supply terminal for supplying power, and the like. .

  The plurality of external terminals 21 include a command address terminal 21CA to which a command address signal CA is input and a data terminal 21DQ for inputting / outputting data DQ. As shown in FIG. 3, the command address signal CA input via the command address terminal 21CA is commonly input to the plurality of semiconductor chips 30 in a fly-by format. Although not particularly limited, in this embodiment, a register buffer or the like is not provided between the semiconductor chip 30 and the command address terminal 21CA.

  On the other hand, part or all of the data DQ output from the plurality of semiconductor chips 30 is output to the outside via different data terminals 21DQ. Similarly, part or all of the data DQ input from the outside is supplied to the plurality of semiconductor chips 30 via different data terminals 21DQ. Although not particularly limited, in the present embodiment, a register buffer or the like is not provided between the semiconductor chip 30 and the data terminal 21DQ.

  FIG. 4 is a cross-sectional view for explaining the internal structure of the module substrate 20.

  As shown in FIG. 4, the module substrate 20 according to this example has a multilayer wiring structure having ten wiring layers. Among these, the wiring layer L1 is a wiring layer on which the surface layer wiring S1 located on the front surface (first surface layer 20F) side of the module substrate 20 is formed, and the wiring layer L10 is the back surface of the module substrate 20 (second surface layer 20B). This is a wiring layer in which the surface layer wiring S10 located on the () side is formed. On the other hand, the wiring layers L2 to L9 are wiring layers in which inner layer wirings S2 to S9 provided in the inner layer of the module substrate 20 are respectively formed. The wiring layers L1 to L10 are insulated and separated from each other by a dielectric 23 made of resin or the like.

  Although not particularly limited, the wiring layer L2 is a wiring layer in which ground wiring is mainly formed, and the wiring layers L3 and L8 are wiring layers in which command address wiring is mainly formed. L7 is a wiring layer in which power supply wiring is mainly formed, wiring layers L5 and L6 are wiring layers in which data wiring is mainly formed, and wiring layer L9 is mainly formed by mixing ground wiring and power supply wiring. Wiring layer.

  Further, the module substrate 20 is provided with a plurality of through holes penetrating the module substrate 20, and these through holes are filled with a through hole conductor TH. Each through-hole conductor TH is connected to one of the inner layer wirings S2 to S9 formed in the wiring layers L2 to L9, one end of which is connected to or released from the surface layer wiring S1 formed in the wiring layer L1, The other end is connected to or released from the surface layer wiring S10 formed in the wiring layer L10. In the example shown in FIG. 4, the left through-hole conductor TH is connected to the inner layer wiring S3 formed in the wiring layer L3, and the right through-hole conductor TH is connected to the inner layer wiring S8 formed in the wiring layer L8. Yes.

  FIG. 5 is a schematic diagram for explaining the connection relationship between each semiconductor chip 30 and the command address wiring.

  As shown in FIG. 5, the command address signal CA input via the command address terminal 21CA is input in common to the eight semiconductor chips D1F to D4F and D1B to D4B via a plurality of stubs.

  In FIG. 5, the stub to which reference sign TL0 is attached is constituted by the surface layer wiring S1 or S10, and its impedance is designed to be 40Ω, for example. The stub labeled TL1_1 is constituted by the inner layer wirings S2 to S9, and the impedance is designed to be 40Ω, for example. Furthermore, stubs to which reference signs TL1_2, TL3_1, TL3_2, TL3_3, and TL4 are provided are configured by inner layer wirings S2 to S9, and the impedance is designed to be 55Ω, for example. The stub labeled TL2_1 is constituted by the surface layer wiring S1, and its impedance is designed to be 55Ω, for example. The stub labeled TL2_2 is constituted by the surface layer wiring S10, and its impedance is designed to be 55Ω, for example.

  One end of the stub TL4 is connected to the termination resistor RT through the through-hole conductor TH and the stub TL5. The stub TL5 is configured by the surface layer wiring S1 or S10, and its impedance is designed to be 55Ω, for example.

  As shown in FIG. 5, the same command address signal CA input to two semiconductor chips (for example, D1F and D1B) positioned on the front and back in plan view is transmitted through different through-hole conductors TH. For example, the command address signal CA that has passed through the stub TL1_2 is supplied to the stub TL2_1 including the surface layer wiring S1 through the through-hole conductor TH1, and is input to the semiconductor chip D1F. On the other hand, the command address signal CA input to the semiconductor chip D1B located on the back surface of the semiconductor chip D1F is supplied via another through-hole conductor TH2 different from the through-hole conductor TH1. Specifically, the command address signal CA that has passed through the stub TL3_1 is supplied to the stub TL2_2 including the surface layer wiring S10 via the through-hole conductor TH2, and is input to the semiconductor chip D1B.

  The same applies to the other pair of semiconductor chips positioned on the front and back in plan view, and the same command address signal CA is input through different through-hole conductors TH.

  FIG. 6 is a schematic cross-sectional view for explaining the connection relationship between the semiconductor chips D1F and D1B and the through-hole conductors TH1 and TH2.

  In the example shown in FIG. 6, the stub TL1_2 constituted by the inner layer wiring is connected to the through-hole conductor TH1, and one end of the through-hole conductor TH1 is connected to the stub TL2_1. The other end of the through-hole conductor TH1 (the end on the second surface layer 20B side) is open. The stub TL2_1 is configured by a surface layer wiring S1 provided in the first surface layer 20F, and is connected to a signal input terminal 31 provided in the semiconductor chip D1F. Accordingly, the command address signal CA supplied via the stub TL1_2 is input to the signal input terminal 31 via the through-hole conductor TH1 and the stub TL2_1.

  Furthermore, the through-hole conductor TH1 is connected to another through-hole conductor TH2 via the stub TL3_1. In the example shown in FIG. 6, the stub TL1_2 and the stub TL3_1 are located in the same wiring layer, but the present invention is not limited to this, and as shown in FIG. 11 described later, the stub TL1_2 and the stub TL3_1 They may be located in different wiring layers.

  One end of the through-hole conductor TH2 is connected to the stub TL2_2. The other end of the through-hole conductor TH2 (the end on the first surface layer 20F side) is open. The stub TL2_2 is configured by a surface layer wiring S10 provided in the second surface layer 20B, and is connected to a signal input terminal 32 provided in the semiconductor chip D1B. Thereby, the command address signal CA supplied via the stub TL1_2 is input to the signal input terminal 32 via the through-hole conductor TH1, the stub TL3_1, the through-hole conductor TH2, and the stub TL2_2.

  As described above, in the present embodiment, the same command address signal CA to be input to the two semiconductor chips D1F and D1B located on the front and back sides is input via the different through-hole conductors TH1 and TH2. As a result, even when two semiconductor chips located on the front and back sides are selected at the same time as in a one-rank product, the length of the surface wiring can be shortened. In addition, the difference between the length of the surface wiring formed on one surface layer 20F of the module substrate 20 and the length of the surface wiring formed on the other surface layer 20B of the module substrate 20 can be reduced.

  FIG. 7 is a cross-sectional view according to the first reference example, and shows a case of a two-rank product.

  In the example shown in FIG. 7, the stub TL1_2 is connected to the through-hole conductor TH1, and the stub TL1_3 is connected to the through-hole conductor TH2. The stub TL1_2 is an inner layer wiring that transmits the command address signal CA1, and the stub TL1_3 is an inner layer wiring that transmits the command address signal CA2.

  Of the end portions of the through-hole conductor TH1, the end portion on the first surface layer 20F side is connected to the stub TL2_1 composed of the surface layer wiring S1, and the end portion on the second surface layer 20B side is connected to the stub TL2_4 composed of the surface layer wiring S10. Is done. The stub TL2_1 is connected to the signal input terminal 31 of the semiconductor chip D1F, and the stub TL2_4 is connected to the signal input terminal 34 of the semiconductor chip D1B. As a result, the command address signal CA1 is input in common to the signal input terminal 31 of the semiconductor chip D1F and the signal input terminal 34 of the semiconductor chip D1B.

  Of the end portions of the through-hole conductor TH2, the end portion on the first surface layer 20F side is connected to the stub TL2_3 including the surface layer wiring S1, and the end portion on the second surface layer 20B side is connected to the stub TL2_2 including the surface layer wiring S10. Is done. The stub TL2_3 is connected to the signal input terminal 33 of the semiconductor chip D1F, and the stub TL2_2 is connected to the signal input terminal 32 of the semiconductor chip D1B. As a result, the command address signal CA2 is commonly input to the signal input terminal 33 of the semiconductor chip D1F and the signal input terminal 32 of the semiconductor chip D1B.

  Here, since the semiconductor chip D1F and the semiconductor chip D1B are semiconductor chips having the same configuration, the terminal layouts are mirror images of each other. Specifically, the signal input terminal 31 and the signal input terminal 32 are terminals having the same function, and the signal input terminal 33 and the signal input terminal 34 are terminals having the same function. Therefore, if the command address signals CA1 and CA2 are mirrored in the case of selecting the semiconductor chip D1F and the case of selecting the semiconductor chip D1B, the same signal can be input to the signal input terminals 31 and 32. The same signal can be input to the input terminals 33 and 34.

  FIG. 8 is a schematic plan view for explaining the positional relationship between the through-hole conductor and the terminal in the two-rank product shown in FIG. 7, and shows a configuration seen transparently from the semiconductor chip D1F side.

  In the example shown in FIG. 8, the signal input terminals 31 and 34 are present at the same position in plan view, and the signal input terminals 33 and 32 are present at the same position in plan view. In this case, the wiring length of the stubs TL2_1 to TL2_4 can be shortened by forming the through-hole conductor TH1 in the vicinity of the signal input terminals 31 and 34 and forming the through-hole conductor TH2 in the vicinity of the signal input terminals 33 and 32. I understand. The reason why such a configuration can be adopted is that, as described above, in the 2-rank product, the signal mirroring process is possible.

  However, in the case of a one-rank product that cannot perform signal mirroring, if one through-hole conductor TH is assigned to one signal to be input to the two semiconductor chips D1F and D1B located on the front and back sides, the surface wiring becomes long. At the same time, the difference in wiring length increases.

  FIG. 9 is a schematic plan view for explaining the positional relationship between the through-hole conductor and the terminal in the first rank product as the second reference example, and shows a configuration seen transparently from the semiconductor chip D1F side. Yes.

  As shown in FIG. 9, when the same through-hole conductor TH is assigned to the same signal to be input to the two semiconductor chips D1F and D1B in the one-rank product, it is difficult to reduce the length of the surface wiring. For example, when the through-hole conductor TH is formed in the vicinity of the signal input terminal 31 as in the example shown in FIG. 9, although the wiring length of the stub TL2_1 can be reduced, the wiring length of the stub TL2_2 is very long. turn into. Further, the wiring length difference between the stub TL2_1 and the stub TL2_2 is also increased.

  On the other hand, in the present embodiment, since different through-hole conductors TH1 and TH2 are assigned to the same signal to be input to the two semiconductor chips D1F and D1B, the above-described problem in the one-rank product is solved. Is possible.

  FIG. 10 is a schematic plan view for explaining the positional relationship between the through-hole conductor and the terminal in the present embodiment, and shows a configuration transparently viewed from the semiconductor chip D1F side.

  As shown in FIG. 10, in the present embodiment, the through-hole conductor TH <b> 1 is formed in the vicinity of the signal input terminal 31, and the through-hole conductor TH <b> 2 is formed in the vicinity of the signal input terminal 32. For this reason, it is possible to reduce the lengths of the stub TL2_1 and the stub TL2_2 and to reduce the wiring length difference between them. Thereby, it becomes possible to solve the above-mentioned problem in the one-rank product.

  However, in this embodiment, since the same command address signal CA is input to the two semiconductor chips located on the front and back sides through different through-hole conductors TH, there is a slight difference in signal transmission conditions. Sometimes.

Specifically, in the configuration shown in FIG. 11, the command address signal CA supplied from the stub TL1_2 is branched into two and input to the semiconductor chips D1F and D1B. Here, when attention is paid to the compensated length of the transmission path of the command address signal CA input to the semiconductor chip D1F, the first component CL1 (wiring layer immediately before the stub TL3_1 (FIG. 3) passing through the through-hole conductor TH1). 11 shows that the compensation length from the stub TL1_2) to the stub TL2_1) and the second component CL2 passing through the stub TL2_1 which is the surface layer wiring are included. In other words, if the compensation length of the transmission path from the branch point to the semiconductor chip D1F is CLF,
CLF = CL1 + CL2
Can be expressed as

On the other hand, paying attention to the compensation length of the transmission path of the command address signal CA input to the semiconductor chip D1B, the third component CL3 (wiring layer immediately before the stub TL3_1 (example of FIG. 11) passing through the through-hole conductor TH1. Then, the compensation length from the stub TL1_2) to the stub TL3_1), the fourth component CL4 passing through the inner layer wiring stub TL3_1, and the fifth component CL5 passing through the through-hole conductor TH2 (wiring layer immediately before the stub TL3_1) (Compensation length from the stub TL1_2 in the example of FIG. 11) to the stub TL2_2) and the sixth component CL6 passing through the stub TL2_2 that is the surface layer wiring are included. That is, assuming that the compensation length of the transmission path from the branch point to the semiconductor chip D1B is CLB,
CLB = CL3 + CL4 + CL5 + CL6
Can be expressed as

And since the difference between CLF and CLB is the difference between the transmission conditions of both, if this difference is 2α,
2α = CLB-CLF
It becomes. For this reason, when a semiconductor module is designed based on the compensation length CLF, a delay corresponding to 2α occurs in the command address signal CA input to the semiconductor chip D1B mounted on the second surface layer 20B. On the other hand, when the compensation length CLB is used as a reference, the command address signal CA input to the semiconductor chip D1F mounted on the first surface layer 20F has a progress corresponding to 2α.

Considering this point, in the present embodiment, for the semiconductor chip D1F mounted on the first surface layer 20F, when the compensation length of the command address wiring is CLD1F, this compensation length is CLD1F-α.
For the semiconductor chip D1B mounted on the second surface layer 20B, if the compensation length of the command address wiring is CLD1B, this compensation length is CLD1B + α
Design as.

In the above example, the semiconductor chip D1F mounted on the first surface layer 20F uses the front through-hole conductor TH1, and the semiconductor chip D1B mounted on the second surface layer 20B uses the rear through-hole conductor TH2. However, depending on the command address signal CA, the through-hole conductor TH used is reversed as shown in FIG. In this case, for the semiconductor chip D1F mounted on the first surface layer 20F, the compensation length is CLD1F + α
For the semiconductor chip D1B mounted on the second surface layer 20B, the compensation length is CLD1B-α
Design as

  In the actual design, the overall compensation length of the command address wiring can be optimized by adjusting the length of the stub TL1_2.

  FIG. 13 is a diagram showing an eye pattern of the command address signal CA when designed based on the compensation length CLF.

  As shown in FIG. 13, when designed based on the compensation length CLF, good signal quality is obtained for the command address signal CA input to the semiconductor chips D1F to D4F mounted on the first surface layer 20F. On the other hand, the command address signal CA input to the semiconductor chips D1B to D4B mounted on the second surface layer 20B has a large eye pattern and is separated into two.

  The eye pattern is largely separated into two because the input timing to the semiconductor chips D1B to D4B is delayed with respect to the command address signal CA input to the semiconductor chips D1F to D4F first, but later the semiconductor chips D1F to D4F. This is because the input timing to the semiconductor chips D1B to D4B is advanced with respect to the command address signal CA input to.

  FIG. 14 is a diagram showing an eye pattern of the command address signal CA when designed in consideration of the correction value α.

  As shown in FIG. 14, when designed in consideration of the value of α, the command address signal CA input to the semiconductor chips D1F to D4F mounted on the first surface layer 20F and the surface mounted on the second surface layer 20B. For any of the command address signals CA input to the semiconductor chips D1B to D4B, the eye pattern is separated into two.

  This is because the input timing of the command address signal CA input to the semiconductor chips D1F to D4F or D1B to D4B first is advanced by α, and the command address input to the semiconductor chips D1F to D4F or D1B to D4B later. This is because the input timing of the signal CA is delayed by α. Therefore, since the command address signal CA input to any semiconductor chip has an error of α, the eye pattern is separated into two. However, the separation width is half that of the case shown in FIG. 13 and the separation width is uniform for all the semiconductor chips 30, so that it is possible to ensure high signal quality as a whole.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

10 Semiconductor Module 20 Module Substrate 20B First Surface Layer (Front Side)
20F 2nd surface layer (back surface)
21 External terminal 21CA Command address terminal 21DQ Data terminal 23 Dielectric 30 Semiconductor chip 31-34 Signal input terminal CA Command address signal CL1 1st component CL2 2nd component CL3 3rd component CL4 4th component CL5 5th Component CL6 Sixth component D1F to D4F, D1B to D4B Semiconductor chips L1 to L10 Each wiring layer RT Termination resistor S1, S10 Surface layer wiring S2 to S9 Inner layer wiring TH, TH1, TH2 Through-hole conductor TL Stub

Claims (9)

A module substrate having a first surface layer, a second surface layer located on the opposite side of the first surface layer, and an inner layer located between the first and second surface layers;
A first semiconductor chip mounted on the first surface layer of the module substrate and having a first signal input terminal;
A second semiconductor chip mounted on the second surface layer of the module substrate and having a second signal input terminal;
A first surface layer wiring provided on the first surface layer of the module substrate and having one end connected to the first signal input terminal of the first semiconductor chip;
A second surface layer wiring provided on the second surface layer of the module substrate and having one end connected to the second signal input terminal of the second semiconductor chip;
At least one inner layer wiring provided in the inner layer of the module substrate;
A first through-hole conductor connecting the inner layer wiring and the other end of the first surface layer wiring;
A semiconductor module comprising: the inner layer wiring; and a second through-hole conductor connecting the other end of the second surface layer wiring.   The semiconductor module according to claim 1, wherein the first and second semiconductor chips are memory devices activated simultaneously.   3. The same command address signal is input to the first signal input terminal of the first semiconductor chip and the second signal input terminal of the second semiconductor chip, respectively. The semiconductor module as described.   The at least one inner layer wiring includes a first inner layer wiring that supplies the command address signal to the first through-hole conductor, and a second connection that connects the first through-hole conductor and the second through-hole conductor. The semiconductor module according to claim 3, further comprising: an inner layer wiring.   The semiconductor module according to claim 4, wherein the first inner layer wiring and the second inner layer wiring are located in different wiring layers. A method for designing a semiconductor module according to claim 4 or 5,
A first compensation length from the first inner layer wiring to the first signal input terminal of the first semiconductor chip, and the second signal input of the second semiconductor chip from the first inner layer wiring. Calculate the second compensation length to the terminal,
Based on the first and second compensation lengths, a third compensation length of the first inner layer wiring for the first semiconductor chip and a fourth compensation length of the first inner layer wiring for the second semiconductor chip. Correct the compensation length of
A method for designing a semiconductor module, wherein a length of the first inner layer wiring is determined based on the third and fourth compensation lengths.   The method of designing a semiconductor module according to claim 6, wherein the correction is performed based on a difference between the first compensation length and the second compensation length. The first compensation length includes a first component that is a compensation length from the first inner layer wiring to the first surface layer wiring, and a second component that is a compensation length of the first surface layer wiring. ,
The second compensation length is a third component that is a compensation length from the first inner layer wiring to the second inner layer wiring, and a fourth component that is a compensation length of the second inner layer wiring. 7. A fifth component that is a compensation length from the second inner layer wiring to the second surface layer wiring and a sixth component that is a compensation length of the second surface layer wiring are included. Or a method for designing a semiconductor module according to 7; Calculating a correction value that is half the value obtained by subtracting the sum of the first and second components from the sum of the third, fourth, fifth and sixth components;
9. The method of designing a semiconductor module according to claim 8, wherein the correction is performed by adding the correction value to the third compensation length and subtracting the correction value from the fourth compensation length. .

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