JP2016128758A - Circuit design device, circuit design method, program, and circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit design device, circuit design method, program, and circuit device.SOLUTION: A circuit design device 110 includes: reading means 112 that reads design data 102 on circuits including a scan chain; division means 120 that divides the scan chain into a plurality of sets on the design data, and inserts a set selection circuit of selecting whether a test is implemented via a part chain of the set or avoidance thereof to each of the plurality of sets; element selection circuit insertion means 124 that inserts an element selection circuit of selecting whether the test is implemented via elements consisting of the part chain of each of the plurality of sets or avoidance thereof to each of the plurality of elements on the design data; and writing means 128 that writes out the design data processed by the set selection circuit insertion means 120 and the element selection circuit insertion means 124.SELECTED DRAWING: Figure 2

Description

  The present invention relates to circuit test technology, and more particularly to a circuit design device, a circuit design method, a program, and a circuit device.

  2. Description of the Related Art Conventionally, a scan test using a scan circuit is known as a technique for testing a failure after manufacturing a semiconductor integrated circuit chip and selecting a good product and a defective product. In this scan test, the scan flip-flop is replaced with a scan flip-flop to form a scan chain, and a test pattern automatically generated by an ATPG (Automatic Test Pattern Generator) is used to pass or Judge failure.

  In the scan test, if the failure occurs due to timing failure on the scan chain or a physical failure, it can be determined that the chip is defective. However, in the prior art, it has not been possible to specify at which part of the chip the failure has occurred.

  If the failure is infrequent, it is sufficient if the pass or fail can be determined for each chip, so that defective products can be excluded. However, if the failure occurs universally, the failure layout is specified and the chip layout is revised. It is desirable. In such cases, use failure analysis techniques such as STA (Static Timing Analysis) to identify faulty parts, correct the parts by FIB (Focused Ion Beam) processing or layout revision, and operate normally. You can check whether or not. However, this method is not sufficient in terms of time and cost, because it must be a trial and error if it is out of register.

  Japanese Unexamined Patent Publication No. 2006-90837 (Patent Document 1) is known in relation to a failure on a scan chain. Patent Document 1 discloses a configuration in which flip-flops in a chip are grouped into a predetermined number, and a scan test is performed while a plurality of groups are variably connected.

  However, since the failure location cannot be specified in units of flip-flops, it has been inevitably corrected by trial and error, which is not sufficient in terms of increasing time and cost.

  The present invention has been made in view of the insufficiency in the above-described prior art, and the present invention is a circuit that can design a circuit that can bypass and test a specific element on a scan chain. An object is to provide a design device.

  In order to solve the above problems, the present invention provides a circuit design apparatus having the following characteristics. The circuit design device reads the design data of the circuit including the scan chain, and divides the scan chain into a plurality of groups on the design data, and each of the plurality of groups passes through the partial chain of the group. Dividing means for inserting a set selection circuit for selecting whether to bypass or bypass, and whether to pass through or bypass each of a plurality of elements constituting a partial chain of each of the plurality of sets on the design data Element selection circuit insertion means for inserting an element selection circuit for selecting the above, and a set selection circuit insertion means and a writing means for writing design data processed by the element selection circuit insertion means described above.

  With the above configuration, it is possible to design a circuit that can be tested by bypassing a specific element on the scan chain.

FIG. 6 is a diagram illustrating a conventional scan circuit. The functional block diagram of the integrated circuit design apparatus by this embodiment. The figure which illustrates the data structure of (A) in-group FF number designation | designated information, (B) decoder circuit input signal information, and (C) selector circuit input signal information. 5 is a flowchart showing an integrated circuit design method executed by the integrated circuit design apparatus according to the present embodiment. FIG. 3 is a schematic diagram illustrating a circuit configuration including a scan chain dividing unit and a decoder circuit inserting unit according to the present embodiment. FIG. 3 is a diagram for explaining the outline of a decoder circuit inserted by a decoder circuit insertion unit according to the present embodiment. FIG. 6 is a diagram for explaining a test target switching operation in a circuit configuration including a scan chain division unit and a decoder circuit insertion unit according to the present embodiment. Schematic which shows the circuit structure comprised by the FF detour circuit insertion part by this embodiment, and a selector circuit insertion part. The figure explaining the switching operation | movement of FF element of a test object in the circuit structure comprised by the FF detour circuit insertion part by this embodiment, and a selector circuit insertion part. The figure which shows the output side connection structure of the selector circuit in the circuit structure comprised by the FF detour circuit insertion part by this embodiment, and a selector circuit insertion part. The figure explaining operation | movement in the case of respond | corresponding at the time of the multiple location failure on a scan chain in the circuit structure comprised by the integrated circuit design apparatus by this embodiment. 1 is a schematic diagram for explaining a semiconductor test environment and a semiconductor test method for a semiconductor integrated circuit based on a netlist designed by an integrated circuit design apparatus according to an embodiment; 6 is a timing chart for explaining an operation during a test in the semiconductor integrated circuit based on circuit design data generated by the circuit design apparatus according to the present embodiment. 6 is a timing chart for explaining the details of the operation at the time of testing each group in the semiconductor integrated circuit based on the circuit design data generated by the circuit design apparatus according to the present embodiment. The hardware block diagram of the integrated circuit design apparatus by this embodiment.

  Hereinafter, although this embodiment is described, the embodiment is not limited to the embodiment described below. In the embodiment to be described, an integrated circuit design apparatus for designing a testable semiconductor integrated circuit will be described as an example of the circuit design apparatus.

  First, before describing the integrated circuit design apparatus according to the present embodiment, a scan test using a conventional scan circuit will be described. FIG. 1 is a diagram for explaining a conventional scan circuit.

  As shown in FIG. 1, the conventional scan circuit has a scan input terminal SIN and a scan output terminal SOUT as an input terminal and an output terminal of the circuit chip. The scan input terminal SIN is connected to an input pin SI of a first flip-flop (hereinafter sometimes referred to as FF for short) element 502-1 constituting the scan chain. The output pin Q of the first FF element 502-1 is connected to the input pin SI of the second FF element 502-2, and all the FF elements 502 in the chip are similarly connected. The output pin Q of the last FF element 502-m is connected to the scan output terminal SOUT. A circuit 500 in which the plurality of FF elements 502 are connected in a daisy chain is referred to as a scan chain.

  By using this scan chain, the following two things are possible. First, arbitrary values can be set for all the FF elements 502 constituting the scan chain in the chip by sequentially inputting arbitrary signals from the scan input terminal SIN and shifting them. . Second, by shifting the values of all the FF elements in the chip, the values of all the FF elements 502 constituting the scan chain in the chip can be confirmed at the scan output terminal SOUT. By using the above-described characteristics, it is possible to detect a failure using a scan chain.

  However, if a failure occurs in a certain FF element (502-n in FIG. 1) constituting the scan chain, the following problems occur. That is, the signal from the scan input terminal SIN is cut off at the failure location, and an arbitrary value cannot be set for the FF elements (502- (n + 1) to 502-m in FIG. 1) after that. At the same time, the values of the FF elements (502-1 to 502- (n-1) in FIG. 1) before the failure location are cut off at the failure location and cannot be observed at the scan output terminal SOUT. For this reason, the conventional scan circuit cannot determine the actual number of FF elements that have failed.

  As described above, a failure with a low frequency is sufficient because defective products can be excluded. However, if a failure occurs universally, it is desirable to specify the failure location and revise the chip layout. However, in the conventional scan circuit as shown in FIG. 1, the failure location cannot be specified in units of FF elements, so the revision work must be trial and error, and the time and cost increase.

  Therefore, the integrated circuit design apparatus according to the present embodiment divides the scan chain into a plurality of groups on the design data of the circuit including the scan chain, and each of the plurality of groups passes through the partial chain of the group or bypasses it. A set selection circuit for selecting whether to do is inserted. The integrated circuit design apparatus further inserts, on the design data, an element selection circuit for selecting whether to go through or bypass the element for each of the plurality of elements constituting the partial chain of each of the plurality of sets. As a result, it is possible to efficiently design a circuit that can bypass a specified element on the scan chain and perform a test, thereby reducing the time required for correction and reducing the cost.

  Hereinafter, the integrated circuit design apparatus according to the present embodiment and the integrated circuit design method executed by the integrated circuit design apparatus will be described in more detail with reference to FIGS.

  FIG. 2 is a diagram showing a functional block 100 of the integrated circuit design apparatus 110 according to the present embodiment. As shown in FIG. 2, the integrated circuit design device 110 includes a net list reading unit 112, an in-group FF number designation information reading unit 114, a decoder circuit input signal information reading unit 116, and a selector circuit input signal information reading unit 118. And comprising. In the integrated circuit design device 110 according to the present embodiment, the input net list 102, the in-group FF number designation information 104, the decoder circuit input signal information 106, and the selector circuit input signal information 108 are prepared as the input information. Input to the integrated circuit design apparatus 110. The reading units 112 to 118 read these pieces of information, respectively. 3A to 3C illustrate data structures of the in-group FF number designation information 104, the decoder circuit input signal information 106, and the selector circuit input signal information 108. FIG.

  The input netlist 102 read by the netlist reading unit 112 is design data including connection information between cells and macrocells in the semiconductor integrated circuit. In the embodiment to be described, the input netlist 102 is a netlist after a process for inserting a scan chain by a conventional technique is performed on the netlist of the original circuit in advance. However, the present invention is not limited to this. In other embodiments, the net list reading unit 112 may read the net list of the original circuit. In this case, the integrated circuit design apparatus 110 performs a process of inserting a scan chain on the read net list of the original circuit, and prepares a net list to be used in the subsequent processes.

  The in-group FF number designation information reading unit 114 read by the in-group FF number designation information reading unit 114 is information for designating how many groups each FF element constituting the scan chain is divided into. The format of the in-group FF number designation information 104 is exemplified in FIG. In the example shown in FIG. 3A, it is specified that the scan chain is divided into groups of 10 FF elements.

  The decoder circuit input signal information 106 read by the decoder circuit input signal information reading unit 116 is information for designating the name of an input terminal of a circuit chip to which an input signal to a decoder circuit described later is assigned. The format of the decoder circuit input signal information 106 is exemplified in FIG. In the example shown in FIG. 3B, it is specified that the input terminals of the circuit chips named DECIN1, DECIN2, and DECIN3 are assigned to the decoder circuit inputs for use.

  The selector circuit input signal information 108 read by the selector circuit input signal information reading unit 118 is information for designating the name of an input terminal of a circuit chip to which an input signal to a selector circuit described later is assigned. The format of the selector circuit input signal information 108 is exemplified in FIG. In the example shown in FIG. 3C, it is specified that the input terminals of the circuit chips named SELIN1 to SELIN10 are assigned to the selector circuit for use.

  The integrated circuit design apparatus 110 according to the present embodiment further performs processing on the net list read by the net list reading unit 112 based on the information read by the reading units 114 to 118, respectively. 128. More specifically, the integrated circuit design device 110 includes a scan chain dividing unit 120, a decoder circuit inserting unit 122, an FF bypass circuit inserting unit 124, a selector circuit inserting unit 126, and a net list writing unit 128. Consists of.

  The scan chain dividing unit 120 divides the scan chain into a plurality of sets for each number of FF elements designated by the in-group FF number designation information reading unit 114 on the net list read by the net list reading unit 112. The scan chain dividing unit 120 inserts a set selection circuit for selecting whether to pass through a partial chain of the set or to bypass each set of divided sets on the net list. The scan chain dividing unit 120 constitutes a dividing unit in the present embodiment.

  The decoder circuit insertion unit 122 inserts a decoder circuit to which the input terminal designated by the decoder circuit input signal information reading unit 116 is allocated on the net list processed by the scan chain dividing unit 120. The decoder circuit insertion unit 122 constitutes a set selection control circuit insertion unit in the present embodiment. The inserted decoder circuit controls the group selection circuit of each of the plurality of groups so that a specified partial chain of the plurality of divided groups is connected to the scan input terminal SIN and the scan output terminal SOUT. It is a set selection control circuit in this embodiment.

  Details of the scan chain dividing unit 120 and the decoder circuit inserting unit 122 will be described later with reference to FIGS.

  Whether the FF bypass circuit insertion unit 124 passes through or bypasses each of the plurality of FF elements constituting the partial chain of each of the plurality of sets on the net list processed by the decoder circuit insertion unit 122 An element selection circuit for selecting is inserted. The FF bypass circuit insertion unit 124 constitutes an element selection circuit insertion unit in the present embodiment.

  The selector circuit insertion unit 126 inserts a selector circuit to which the input terminal designated by the selector circuit input signal information reading unit 118 is allocated on the net list processed by the FF bypass circuit insertion unit 124. The selector circuit insertion unit 126 constitutes an element selection control circuit insertion unit in the present embodiment. The inserted selector circuit controls the element selection circuit of each of the plurality of FF elements so that at least one specified FF element of the plurality of FF elements is bypassed. Configure. The selector circuit is shared among the plurality of sets described above in the preferred embodiment.

  Details of the FF bypass circuit insertion unit 124 and the selector circuit insertion unit 126 will be described later with reference to FIGS. 4 and 8 to 11.

  The net list writing unit 128 is a writing unit that writes the net list processed by the processing units 120 to 126 as the output net list 130. Thereafter, a semiconductor integrated circuit is manufactured based on the output net list 130.

  Hereinafter, the operation of the integrated circuit design apparatus 110 and the designed circuit configuration will be described in more detail with reference to FIGS. FIG. 4 is a flowchart showing the integrated circuit design method executed by the integrated circuit design apparatus 110 according to the present embodiment. The process shown in FIG. 4 is started from step S100 in response to input information such as the input netlist 102 being prepared and instructed by the user to start a circuit design process specifying the input information.

  In step S101, the integrated circuit design device 110 has inserted the scan chain by the net list reading unit 112, the in-group FF number designation information reading unit 114, the decoder circuit input signal information reading unit 116, and the selector circuit input signal information reading unit 118. Input net list 102, in-group FF number designation information 104, decoder circuit input signal information 106 and selector circuit input signal information 108 are read.

  In step S <b> 102, the integrated circuit design device 110 divides the scan chain for each number of FF elements as designated by the in-group FF number designation information 104 for the read input netlist 102 by the scan chain divider 120. The process is performed. Further, the scan chain dividing unit 120 inserts a multiplexer as a set selection circuit after the last FF element in the set, and inputs a path that passes through a partial chain of each set and a bypass path to the multiplexer. Apply.

  FIG. 5 is a schematic diagram illustrating a circuit configuration including the scan chain dividing unit 120 and the decoder circuit inserting unit 122 according to the present embodiment. As shown in FIG. 5, the scan chain includes, for example, a first set including FF elements 210 to 219, a second set including FF elements 220 to 229, for each number specified by the in-group FF number specifying information 104. ... divided into groups such as the m-th group including the FF elements 230 to 239. Multiplexers 241 to 249 are inserted after the last FF elements 219, 229,..., 239 of each group, and a path that passes through a partial chain constituting each group and a path that bypasses this partial chain. Either of the circuit configurations can be selected.

  Referring to FIG. 4 again, in step S103, the integrated circuit design device 110 uses the decoder circuit insertion unit 122 to perform processing to insert a decoder circuit into the processed netlist. The decoder circuit insertion unit 122 further performs processing to connect the output signal of the decoder circuit to the selection control of each set of multiplexers and to connect the input of the decoder circuit to the input terminal specified by the decoder circuit input signal information.

  Referring to FIG. 5 again, a decoder circuit 250 is added to the circuit configuration, and selection control signals of a total of m sets of multiplexers 241 to 249 and output signals decout1 to decoutm of the decoder circuit 250 are respectively connected. . The input signal of the decoder circuit 250 is connected to the input terminals DECIN1 to DECINn of the circuit chip specified by the decoder circuit input signal information 106.

  In the circuit configuration as shown in FIG. 5, the value of the selection control signal of an arbitrary multiplexer can be set to 1 by controlling the input signal to the decoder circuit 250. Then, a state in which only the partial chain of the preceding set of multiplexers is connected to the scan chain from the scan input terminal SIN to the scan output terminal SOUT is realized.

  Since the decoder circuit 250 is a general circuit, a detailed description thereof will be omitted, but the outline will be described with reference to FIG. In the example shown in FIG. 6, the value of any one of the eight output signals decout1 to decout8 is 1 and the values of the other output signals are 0 depending on the states of the three input terminals DECIN1 to DECIN3. Yes. By controlling the input signal to the input terminals DECIN1 to DECIN3 of the circuit chip using the characteristics of the decoder circuit, the control signal for selecting only one of the eight sets of multiplexers is set to 1. A circuit can be realized.

  The configuration of the decoder circuit is uniquely determined based on input information. The number of output signals is required by the number of inserted multiplexers, that is, the number of divided sets. For this reason, the number of output signals is determined by the number of FFs constituting the scan chain in the input netlist 102 and the number of FFs in the group designated by the in-group FF number designation information 104.

  The number of input signals is determined based on the number of output signals. For example, when the scan chain is divided into eight sets, the number of digits that can realize eight or more values in binary number, that is, three input signals. The decoder circuit itself is determined by the decoder circuit input signal information 106 described above and the number of input signals and output signals described above.

  FIG. 7 is a diagram for explaining a test target switching operation in the circuit configuration constituted by the scan chain dividing unit 120 and the decoder circuit inserting unit 122 according to the present embodiment.

  Referring to FIG. 7, in FIG. 7A, only the selection control signal of the multiplexer in the subsequent stage of the first set is 1. A scan chain that bypasses the partial chain from the second set to the final set through the first set of partial chains from the scan input terminal SIN to the scan output terminal SOUT is established. On the other hand, in FIG. 7B, only the selection control signal of the second set of multiplexers in the second stage is 1, and only the second set of partial chains are connected to the scan input terminal SIN and the scan output terminal SOUT. It has become a state. Similarly, in FIG. 7C, only the final m-th set of partial chains are connected to the scan input terminal SIN and the scan output terminal SOUT.

  As described above, the circuit designed by the integrated circuit design apparatus 110 according to the present embodiment has a mechanism that allows only a specified group of partial chains on the scan chain to be connected to the scan terminals SIN and SOUT. It is characterized by having.

  Here, FIG. 4 will be referred to again. In step S104, the integrated circuit design device 110 performs processing for replacing the macro cell of each FF element with a macro cell having a multiplexer as an element selection circuit in the subsequent stage, with respect to the processed netlist, by the FF bypass circuit insertion unit 124. . The FF detour circuit insertion unit 124 further performs processing so as to input a path passing through each FF element and a detour path to a subsequent multiplexer.

  FIG. 8 is a schematic diagram illustrating a circuit configuration including the FF bypass circuit insertion unit 124 and the selector circuit insertion unit 126 according to the present embodiment. Note that the circuit configuration shown in FIG. 8 corresponds to an enlarged version of one set in the circuit configuration shown in FIG.

  As shown in FIG. 8, in the replaced macro cells 310 to 319, multiplexers 330 to 339 are provided at the subsequent stage of the FF elements 320 to 329. By adding a multiplexer to the subsequent stage of each FF element, it is possible to select either a path passing through each FF element or a path bypassing each FF element. In FIG. 8, the multiplexer (for example, 330) is described as being combined with the preceding FF element (for example, 320) to constitute one scan circuit macro cell 310, but it is not necessarily required to be combined. Does not prevent it from being configured as a separate cell.

  Referring to FIG. 4 again, in step S105, the integrated circuit design device 110 uses the selector circuit insertion unit 126 to perform processing for inserting a selector circuit into the processed netlist. The selector circuit insertion unit 126 further connects the output signal of the inserted selector circuit to the selection control signal of each of the multiplexers 330 to 339, and connects the input signal to the input terminal of the circuit chip specified by the selector circuit input signal information. The process is performed.

  Referring to FIG. 8 again, a selector circuit 350 is added to the circuit configuration, and the selection control signals of the multiplexers 330 to 339 of the total p macro cells 310 to 319 and the output signals selout1 to seloutp of the selector circuit 350 are obtained. It is connected. An input signal to the selector circuit 350 is connected to input terminals SELIN1 to SELINp of the circuit chip set by the selector circuit input signal information 108.

  By mounting a circuit as shown in FIG. 8, the input signal to the selector circuit 350 is controlled, and the value of the selection control signal of the multiplexer of any macro cell out of the total p is set to 1. As a result, only the macro cell corresponding to the multiplexer can be excluded from the scan chain in units of one FF element.

  FIG. 9 is a diagram illustrating the switching operation of the FF element to be tested in the circuit configuration configured by the FF bypass circuit insertion unit 124 and the selector circuit insertion unit 126 according to the present embodiment.

  Referring to FIG. 9, in FIG. 9A, the selection control signal of the multiplexer subsequent to the first FF element is 1, and the first FF element is bypassed from the input to this set. As a result, a scan chain is established that passes through the second through the final ones to the output of this group. On the other hand, in FIG. 9B, the selection control signal of the second multiplexer is 1, and the second one is bypassed via the first FF element from the input to this set. As a result, a scan chain that passes through the third to final FF elements to the output of this group is established. Similarly in FIG. 9C, a scan chain in which the last FF element is excluded is established.

  As described above, the circuit designed by the integrated circuit design apparatus 110 according to the present embodiment has a mechanism capable of selecting whether the FF elements constituting each set are to be routed or bypassed in units of one. It is said.

  In the above description, the FF elements are excluded in units of one unit. However, it is also possible to exclude a plurality of FF elements from the scan chain at the same time by controlling the input signal to the selector circuit. Is possible. That is, it is possible to deal with a case where a plurality of points are broken on the scan chain. As the simplest configuration of the selector circuit, external inputs prepared for the number of multiplexers inserted in each set and directly connected from the external input to the output of the selector circuit can be used.

  FIG. 10 is a diagram showing an output side connection configuration of the selector circuit 350 in the circuit configuration configured by the FF bypass circuit insertion unit 124 and the selector circuit insertion unit 126 according to the present embodiment. Connections in one set have been described with reference to FIG. On the other hand, as described above, the scan chain can be composed of a number of sets. In a specific embodiment, the above-described selector circuit may be provided for each existing set. However, in the preferred embodiment, as shown in FIG. 10, the output signal of the selector circuit can be similarly connected to other groups, and the selector circuit can be shared among a plurality of groups. For example, the output signal selout1 can be connected to the selection control signal of the multiplexer of the first FF macrocell in all sets. In this preferred embodiment, only one selector circuit is required, and the number of control signals to the selector circuit can be minimized.

  FIG. 11 is a diagram for explaining an operation in a case where a plurality of failures on the scan chain are dealt with in the circuit configuration constituted by the integrated circuit design apparatus 110 according to the present embodiment. FIG. 11 shows a first set and a second set of partial chains divided by 10 sets of FF elements.

  As shown in FIG. 11, a case is considered in which the second FF element from the front of the first set and the third FF element from the front of the second set are out of order. Since the second and third FF elements from the front are out of order, the second and third output signals (indicated by dotted lines) of the selector circuit 350 are normally set to 1, and these FF elements are scan-chained. Can be excluded from

  However, in this state, the third FF element from the front of the first set and the second FF element from the front of the second set are excluded from the scan chain even though they do not fail. Therefore, even if the test is performed in this state, the presence or absence of the failure of the third FF element from the front of the first set and the second FF element from the front of the second set remains unclear.

  On the other hand, the circuit configuration configured by the integrated circuit design apparatus 110 according to the present embodiment is configured so that each group can be tested in order as described with reference to FIG. For this reason, even when the selector circuit 350 is shared, it is possible to exclude only an arbitrary FF element from the test target by changing the input signal to the selector circuit 350 for each test period.

  In the example shown in FIG. 11, the input signal can be set so that only the second output signal selout2 of the selector circuit 350 is set to 1 during the test period for the first set. In the test period for the second set, the input signal can be set so that only the third output signal selout3 of the selector circuit 350 is set to 1. As a result, it is possible to test by excluding only the FF elements that are really faulty from the scan chain.

  Referring to FIG. 4 again, in step S106, the integrated circuit design device 110 outputs the netlist subjected to the above processing as an output netlist 130 by the netlist writing unit 128, and ends this processing in step S107. To do.

  Hereinafter, a semiconductor test method for a semiconductor integrated circuit designed by the integrated circuit design apparatus 110 will be described with reference to FIGS. FIG. 12 is a diagram for explaining the outline of the semiconductor test environment 400 and the semiconductor test method for the semiconductor integrated circuit based on the netlist designed by the integrated circuit design apparatus 110 according to the present embodiment.

  A circuit design device 410 illustrated in FIG. 12 generates circuit design data 412. The integrated circuit design device 110 according to the present embodiment described with reference to FIGS. 2 to 11 may be included in the circuit design device 410. The circuit design device 410 scans all or part of the FF elements in the circuit with respect to the original netlist designed manually or the original netlist automatically generated from the data described in the hardware description language by the logic synthesis tool. By replacing the FF element, a net list with the scan chain inserted is generated. Using this net list as the input net list 102, the circuit design device 410 generates the output net list 130 by performing the above-described processing. The circuit design device 410 further inputs the output netlist 130 to the automatic layout design tool, and outputs the mask layout pattern of the circuit chip as circuit design data 412 through the floor planning, placement, clock distribution circuit, and wiring. . Then, a photomask is created from the obtained circuit design data 412 and the semiconductor integrated circuit 430 is manufactured by a wafer process.

  Further, the test pattern generation apparatus 420 can automatically generate a test pattern 422 by ATPG based on the output netlist 130. The semiconductor tester 440 tests the manufactured semiconductor integrated circuit 430 as a DUT (Device Under Test) based on the test pattern 422, and determines pass and fail.

  As described above, the semiconductor integrated circuit 430 includes a plurality of groups for selecting whether the scan chain divided into a plurality of groups and a partial chain of each of the plurality of groups divided from the scan chain are routed or bypassed. Each multiplexer is included. The semiconductor integrated circuit 430 also includes a multiplexer for each of the plurality of elements for selecting whether to pass through or bypass each of the plurality of elements constituting the partial chain of each of the plurality of sets. The semiconductor integrated circuit 430 further includes a scan input terminal SIN, a scan output terminal SOUT, and a group selection input terminal DECIN * (* represents an arbitrary number in a necessary range) for controlling the multiplexers of each of the plurality of groups. And an element selection input terminal SELIN * (* represents an arbitrary number in a necessary range) for controlling the multiplexer of each of the plurality of elements. The semiconductor integrated circuit 430 includes a decoder circuit connected to the set selection input terminal DECIN * and each of the plurality of sets of multiplexers, and a selector connected to the element selection input terminal SELIN * and the subsequent stage multiplexers of each of the plurality of FF elements. A circuit.

  At the time of testing, the semiconductor tester 440 uses a multiplexer provided for each partial chain of a plurality of groups constituting a scan chain incorporated in the semiconductor integrated circuit based on the test pattern 422 as a specified group of the plurality of groups. Are controlled so that the partial chain is connected to the scan input terminal and the scan output terminal. The semiconductor tester 440 also includes, based on the test pattern 422, a multiplexer provided for each of the plurality of FF elements constituting each partial chain of each of the plurality of sets, at least one FF specified among the plurality of FF elements. Control is performed so that the element is bypassed.

  The semiconductor tester 440 configures a specified set of partial chains from the scan input terminal SIN based on the test pattern 422, and sets a value for each FF element to be tested excluding at least one specified element, The value of each test target element is observed from the scan output terminal SOUT.

  FIG. 13 is a timing chart for explaining the operation at the time of the test in the semiconductor integrated circuit based on the circuit design data generated by the circuit design device 410 according to the present embodiment. For convenience of explanation, it is assumed that there are eight FF elements corresponding to the decoder circuit shown in FIG. In the example of FIG. 6, the test pattern generation device 420 generates a test pattern that applies a signal having a waveform as shown in FIG. 13 to the input terminals DECIN1, DECIN2, and DECIN3 to the decoder circuit during the test. The signals from the output 1 to the output 8 become 1 in order, and a test pattern can be obtained in which the first to eighth sets are tested in order.

  FIG. 14 is a timing chart for explaining the details of the operation at the time of testing each set in the semiconductor integrated circuit based on the circuit design data generated by the circuit design device 410 according to the present embodiment. In the example shown in FIG. 13, each set includes 10 FF elements. Here, it is assumed that the second FF element from the front of the first set is out of order, and this FF element. Shall be tested without

  In the example of FIG. 14, the test pattern generation device 420 creates a test pattern that applies a signal having a waveform as shown in FIG. 14 to the input terminals SELIN1 to SELIN10 of the selector circuit. Thus, a test pattern for performing a test in a state where the second FF from the front of the first set is excluded from the scan chain can be obtained.

  Since the signal waveform applied from the scan input terminal SIN needs to test both 0 stuck-at fault and 1 stuck-at fault, first, the value 0 is set to all 9 FF elements except for the excluded 1 FF element. Next, a test pattern in which a signal waveform for setting a value of 1 is applied to all nine FF elements is used. Further, in the case of FIG. 14, the expected value to be set to the scan output terminal SOUT is indefinite until the ninth cycle in which values are set from all the FF elements from the scan input terminal SIN, and the value 0 can be observed. A value of 0 is set from the 10th cycle to the 19th cycle, and a value of 1 is set from the 20th cycle to the 28th cycle where the value 1 can be observed.

  By creating a test pattern under such conditions, the test pattern generation device 420 can obtain a test pattern that can perform a scan chain test excluding only the FF elements that are found to be faulty.

  Therefore, there is no need to register the failure location, correct the location by FIB processing or layout revision, and check whether the operation is normal. This is because, before the layout revision, a failure location on the scan chain can be identified and it can be confirmed by a semiconductor tester that there is no mistake at the failure location. This eliminates the need for trial and error for FIB processing and layout revision, and as a result, the layout correction work period can be shortened and the cost can be reduced.

  Hereinafter, the hardware configuration of the integrated circuit design apparatus 110 according to the present embodiment will be described with reference to FIG. FIG. 15 is a diagram illustrating a hardware configuration of the integrated circuit design apparatus 110 according to the present embodiment. The integrated circuit design apparatus 110 according to the present embodiment is configured as a general-purpose computer such as a desktop personal computer or a workstation. An integrated circuit design apparatus 110 shown in FIG. 15 includes a single-core or multi-core CPU (Central Processing Unit) 12, a north bridge 14 that connects the CPU 12 and a memory, and the north bridge 14 via a dedicated bus or a PCI bus. And a south bridge 16 that is connected to an I / O such as a PCI bus or USB.

  Connected to the north bridge 14 are a RAM (Random Access Memory) 18 that provides a work area for the CPU 12 and a graphic board 20 that outputs a video signal. The graphic board 20 is connected to the display 50 via a video output interface.

  The south bridge 16 includes a peripheral component interconnect (PCI) 22, a LAN port 24, an IEEE (The Institute of Electrical and Electronics Engineers, Inc.) 1394 port 26, a universal serial bus (USB) port 28, and a hard disk drive (HDD). And an auxiliary storage device 30 such as an SSD (Solid State Drive), an audio input / output 32, and a serial port 34 are connected. The auxiliary storage device 30 stores an OS for controlling the computer device, a control program for realizing the above-described functional units, various system information, and various setting information. The LAN port 24 is an interface device that connects the integrated circuit design apparatus 110 to the LAN.

  Input devices such as a keyboard 52 and a mouse 54 may be connected to the USB port 28, and a user interface for receiving input of various instructions from an operator of the integrated circuit design device 110 can be provided. . The integrated circuit design device 110 according to the present embodiment reads the control program from the auxiliary storage device 30 and develops it in the work space provided by the RAM 18 to realize the above-described functional units and processes under the control of the CPU 12. . The test pattern generation apparatus 420 can be configured in the same manner as the hardware shown in FIG.

  As described above, according to the present embodiment, a circuit design device, a circuit design method, a program, and a circuit device that can design a circuit that can be tested by bypassing a specific element on a scan chain. Can be provided.

  The functional unit can be realized by a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark), an object-oriented programming language, or the like. ROM, EEPROM, EPROM , Stored in a device-readable recording medium such as a flash memory, a flexible disk, a CD-ROM, a CD-RW, a DVD-ROM, a DVD-RAM, a DVD-RW, a Blu-ray disc, an SD card, an MO, or through an electric communication line Can be distributed.

  Although the embodiments of the present invention have been described so far, the embodiments of the present invention are not limited to the above-described embodiments, and those skilled in the art may conceive other embodiments, additions, modifications, deletions, and the like. It can be changed within the range that can be done, and any embodiment is included in the scope of the present invention as long as the effects of the present invention are exhibited.

DESCRIPTION OF SYMBOLS 100 ... Functional block, 102 ... Input net list, 104 ... FF number designation information in group, 106 ... Decoder circuit input signal information, 108 ... Selector circuit input signal information, 110 ... Integrated circuit design device, 112 ... Net list reading part, 114: In-group FF number designation information reading unit, 116: Decoder circuit input signal information reading unit, 118 ... Selector circuit input signal information reading unit, 120 ... Scan chain dividing unit, 122 ... Decoder circuit inserting unit, 124 ... FF bypass circuit Insertion unit 126 ... Selector circuit insertion unit 128 ... Netlist writing unit 130 130 Output netlist 210 ... FF element 220 ... FF element 230 ... FF element 241 Multiplexer 250 250 Decoder circuit 310 Macro cell 320 ... FF element 330 ... Multiplexer 350 ... Selector times , 400 ... Semiconductor test environment, 410 ... Circuit design device, 412 ... Circuit design data, 420 ... Test pattern generation device, 422 ... Test pattern, 430 ... Semiconductor integrated circuit, 440 ... Semiconductor tester, 500 ... Circuit, 502 ... FF element , 12 ... CPU, 14 ... North Bridge, 16 ... South Bridge, 18 ... RAM, 20 ... Graphic Board, 22 ... PCI, 24 ... LAN Port, 26 ... IEEE 1394 Port, 28 ... USB Port, 30 ... Auxiliary Storage Device, 32 ... Audio input / output, 34 ... Serial port, 50 ... Display, 52 ... Keyboard, 54 ... Mouse

JP 2006-90837 A

Claims (10)

A circuit design device for designing a circuit,
Reading means for reading design data of the circuit including the scan chain,
Dividing means for dividing the scan chain into a plurality of sets on the design data and inserting a set selection circuit for selecting whether to pass or bypass the partial chains of the set for each of the plurality of sets;
On the design data, an element selection circuit insertion means for inserting an element selection circuit for selecting whether to pass or bypass the element for each of the plurality of elements constituting the partial chain of each of the plurality of sets;
A circuit design apparatus including: a set selection circuit insertion unit; and a writing unit for writing design data processed by the element selection circuit insertion unit.   A set selection for controlling the set selection circuit of each of the plurality of sets so that a specified partial chain of the plurality of sets is connected to a scan input terminal and a scan output terminal on the design data The circuit design device according to claim 1, further comprising set selection control circuit insertion means for inserting a control circuit.   Inserting an element selection control circuit for controlling the element selection circuit of each of the plurality of elements so that at least one specified element of the plurality of elements is bypassed on the design data. The circuit design device according to claim 1, further comprising control circuit insertion means.   The circuit design apparatus according to claim 3, wherein the element selection control circuit is shared among the plurality of sets. The scan chain includes a plurality of flip-flop elements,
The set selection circuit is a multiplexer connected to a subsequent stage of the last flip-flop element in each of the plurality of sets,
The element selection circuit is a multiplexer connected to a subsequent stage of each of the plurality of flip-flop elements constituting the scan chain.
The circuit design apparatus of any one of Claims 1-4. A circuit design method for designing a circuit, comprising:
Reading the design data of the circuit including the scan chain;
A step of dividing the scan chain into a plurality of sets for the design data, and inserting a set selection circuit for selecting whether to pass or bypass the partial chains of the sets in each of the plurality of sets. When,
A process of inserting an element selection circuit for selecting whether to pass through or bypass each of the plurality of elements constituting the partial chain of each of the plurality of sets with respect to the design data;
A circuit design method comprising: a step of performing processing to insert the set selection circuit; and a step of writing design data processed in the step of processing to insert the element selection circuit. A set selection for controlling the set selection circuit of each of the plurality of sets so that a specified partial chain of the plurality of sets is connected to a scan input terminal and a scan output terminal with respect to the design data Processing to insert a control circuit;
Processing to insert an element selection control circuit for controlling the element selection circuit of each of the plurality of elements so that at least one specified element of the plurality of elements is bypassed with respect to the design data; The circuit design method according to claim 6, further comprising: applying.   A program for realizing a circuit design device for designing a circuit, the program causing a computer to function as each means according to any one of claims 1 to 5. A scan chain divided into multiple sets;
A set selection circuit for each of the plurality of sets for selecting whether to pass through or bypass a partial chain of each of the plurality of sets divided from the scan chain;
An element selection circuit for each of the plurality of elements for selecting whether to bypass or bypass each of the plurality of elements constituting the partial chain of each of the plurality of sets;
A scan input terminal of the scan chain;
A scan output terminal of the scan chain;
A set selection input terminal for controlling the set selection circuit of each of the plurality of sets;
And a device selection input terminal for controlling the device selection circuit of each of the plurality of devices. A set selection control circuit connected to the set selection input terminal and the set selection circuit of each of the plurality of sets, wherein a specified partial chain of the plurality of sets includes the scan input terminal and the scan A set selection control circuit for controlling the set selection circuit of each of the plurality of sets to be connected to an output terminal;
An element selection control circuit connected to the element selection input terminal and the element selection circuit of each of the plurality of elements, wherein at least one specified element of the plurality of elements is in a detoured state. The circuit device according to claim 9, further comprising: an element selection control circuit that controls the element selection circuit of the plurality of elements.