JP2016115818A - Plasma processing apparatus - Google Patents
Plasma processing apparatus Download PDFInfo
- Publication number
- JP2016115818A JP2016115818A JP2014253582A JP2014253582A JP2016115818A JP 2016115818 A JP2016115818 A JP 2016115818A JP 2014253582 A JP2014253582 A JP 2014253582A JP 2014253582 A JP2014253582 A JP 2014253582A JP 2016115818 A JP2016115818 A JP 2016115818A
- Authority
- JP
- Japan
- Prior art keywords
- sample
- voltage
- electrode
- frequency
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Plasma Technology (AREA)
- Drying Of Semiconductors (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
本発明は、半導体デバイスを製造する半導体製造装置に関するものであり、特にプラズマを用いて、レジスト材料等で形成されたマスクパタン形状どおりにシリコンやシリコン酸化膜等の半導体材料をエッチングするドライエッチング技術に関する。
The present invention relates to a semiconductor manufacturing apparatus for manufacturing a semiconductor device, and in particular, a dry etching technique for etching a semiconductor material such as silicon or a silicon oxide film according to a mask pattern shape formed of a resist material using plasma. About.
ドライエッチングに代表されるプラズマ処理は、真空排気手段を有する真空容器内に原料ガスを導入し、該原料ガスを電磁波によりプラズマ化して被加工試料にさらすことで被加工試料表面のマスク部以外をエッチングすることで所望の形状を得る半導体微細加工方法である。プラズマ生成には、誘導結合方式、電子サイクロトロン共鳴方式および平行平板方式(マグネトロン方式含む)が主に用いられている。
In plasma processing represented by dry etching, a raw material gas is introduced into a vacuum vessel having a vacuum exhaust means, and the raw material gas is converted into plasma by electromagnetic waves and exposed to the sample to be processed, except for the mask portion on the surface of the sample to be processed. This is a semiconductor micromachining method for obtaining a desired shape by etching. For the plasma generation, an inductive coupling method, an electron cyclotron resonance method, and a parallel plate method (including a magnetron method) are mainly used.
誘導結合方式のプラズマ生成には主に13.56MHzが用いられ、電子サイクロトロン共鳴方式には2.45GHzの電磁波が主に用いられる。これら誘導結合方式および電子サイクロトロン共鳴方式では、プラズマ生成とは別に被加工試料表面への入射イオンのエネルギーを制御する目的でRF帯の電磁波が被加工試料に印加される構造となっている。
13.56 MHz is mainly used for inductively coupled plasma generation, and 2.45 GHz electromagnetic waves are mainly used for electron cyclotron resonance. These inductive coupling method and electron cyclotron resonance method have a structure in which an electromagnetic wave in the RF band is applied to the sample to be processed for the purpose of controlling the energy of incident ions on the surface of the sample to be processed separately from plasma generation.
一方、平行平板方式では、従来プラズマ生成には13.56MHzの電磁波が広く用いられてきたが、近年VHF帯(30MHz〜300MHz)の電磁波が用いられるようになり、また先の誘導結合方式や電子サイクロトロン共鳴方式と同様に被加工試料表面への入射イオンのエネルギーを独立に制御するRF帯の電磁波もプラズマ生成とは別に用いられるようになってきた。
On the other hand, in the parallel plate method, electromagnetic waves of 13.56 MHz have been widely used for plasma generation in the past, but in recent years, electromagnetic waves in the VHF band (30 MHz to 300 MHz) have been used. Similar to the cyclotron resonance method, RF band electromagnetic waves that independently control the energy of incident ions on the surface of the workpiece are also used separately from plasma generation.
これらプラズマ処理装置では、被加工試料の温度を精度良く保つため被加工試料設置手段に被加工試料を静電吸着させ、被加工試料と被加工試料設置手段間にヘリウムガスを流す構造が一般的に用いられている。静電吸着方式には、単極と両極の2方式が主に用いられる。
These plasma processing apparatuses generally have a structure in which a workpiece sample is electrostatically adsorbed on a workpiece sample placement means and helium gas is allowed to flow between the workpiece sample and the workpiece sample placement means in order to keep the temperature of the workpiece sample with high accuracy. It is used for. As the electrostatic adsorption method, two methods of a single electrode and a bipolar electrode are mainly used.
静電吸着はセラミック等で形成された薄い絶縁膜を介して、金属電極と被加工試料間に直流電圧を与えることで実施される。また被加工試料には、プラズマからのイオンを加速して入射されるため高周波電圧が印加されている。従って、静電吸着力を支配する金属電極と被加工試料間の電位差は、金属電極に印加する直流電圧と高周波印加により被加工試料とプラズマ間に生成されるセルフバイアス電圧との電圧差となる。
The electrostatic adsorption is performed by applying a DC voltage between the metal electrode and the sample to be processed through a thin insulating film made of ceramic or the like. In addition, a high frequency voltage is applied to the sample to be processed because ions from plasma are accelerated and incident. Therefore, the potential difference between the metal electrode that controls the electrostatic attraction force and the sample to be processed is a voltage difference between a DC voltage applied to the metal electrode and a self-bias voltage generated between the sample to be processed and the plasma by applying a high frequency. .
セルフバイアス電圧が金属電極に印加する直流電圧に比べて十分小さい場合は、ほぼ吸着力は直流電源電圧できまるが、被加工試料に印加する高周波バイアス電圧が大きくセルフバイアス電圧が直流電圧に比べて無視できない大きさとなる場合、印加する高周波電圧により吸着力が変化し安定しない。また高周波バイアス電圧が非常に高い場合には、金属電極と被加工試料間に配置される薄い絶縁膜の耐電圧を超える場合、静電吸着部を破壊してしまう可能性が生じる。
If the self-bias voltage is sufficiently small compared to the DC voltage applied to the metal electrode, the adsorption power can be almost equal to the DC power supply voltage, but the high-frequency bias voltage applied to the workpiece is large and the self-bias voltage is less than the DC voltage. When the size is not negligible, the attractive force changes due to the applied high-frequency voltage and is not stable. In addition, when the high frequency bias voltage is very high, there is a possibility that the electrostatic chucking portion is destroyed when the withstand voltage of the thin insulating film disposed between the metal electrode and the sample to be processed is exceeded.
上記する高周波電圧によって発生するセルフバイアス電圧が直流電源電圧に比べて影響が大きい場合の対処方法として、特開2006−210726号公報(特許文献1)に記載する技術が開示されている。この従来技術は、前記高周波電圧に対応して発生するセルフバイアス電圧の静電吸着電圧への影響を回避するため、高周波バイアス電圧をモニタし、その高周波電圧に対応して直流電源電圧を制御することを開示している。
Japanese Patent Application Laid-Open No. 2006-210726 (Patent Document 1) discloses a technique for coping with the case where the self-bias voltage generated by the high-frequency voltage has a greater influence than the DC power supply voltage. In this prior art, in order to avoid the influence of the self-bias voltage generated in response to the high-frequency voltage on the electrostatic adsorption voltage, the high-frequency bias voltage is monitored and the DC power supply voltage is controlled in accordance with the high-frequency voltage. It is disclosed.
上記従来の技術では、次の点について考慮が不十分であったため問題が生じていた。
The above-described conventional technique has a problem because the following points are insufficiently considered.
すなわち、従来の技術は、静電吸着用直流電圧電源の出力値を被加工試料に印加する高周波バイアス電圧のモニタ値を参照して制御するものが開示されている。この技術では、直流電源電圧の制御速度は比較的遅い(例えば0.1秒以上)場合にしか対応できない。
That is, the prior art discloses a technique for controlling the output value of a DC voltage power supply for electrostatic attraction with reference to a monitor value of a high frequency bias voltage applied to a workpiece. This technique can only cope with a case where the control speed of the DC power supply voltage is relatively slow (for example, 0.1 seconds or more).
しかし、半導体ウエハ等の基板状の被加工試料へ高周波バイアス電力を印加するもののなかには、数十ミリ秒乃至1ミリ秒以下の時間の間隔(数十Hz〜数kHzの周波数)でON/OFFまたは高い振幅及び低い振幅を繰り返して所定の周波数の高周波(Radio Frequency:RF)電力を印加する(以下、TM:Time Modulationまたは時間変調と呼ぶ)場合がある。従来の技術により直流電源の電圧を制御するものでは、このような高い周波数で繰り返されるTMの動作に対応して値を増減することは困難であった。
However, among those that apply high-frequency bias power to a substrate-like workpiece such as a semiconductor wafer, ON / OFF at intervals of several tens of milliseconds to 1 millisecond (frequency of several tens of Hz to several kHz) There is a case where high frequency (Radio Frequency: RF) power of a predetermined frequency is applied by repeating high amplitude and low amplitude (hereinafter referred to as TM: Time Modulation or time modulation). In the case of controlling the voltage of the DC power supply by the conventional technique, it is difficult to increase or decrease the value corresponding to the TM operation repeated at such a high frequency.
このため、従来の技術では、TM動作の場合に静電吸着力の安定性と静電吸着用絶縁材料への過剰な電圧印加を防止することができないという問題が有った。そして、このために試料の処理の結果が所期の許容される範囲のものから外れてしまい、処理の歩留まりが損なわれてしまうという問題が生じていた点について、従来の技術では考慮されていなかった。
For this reason, in the conventional technique, there is a problem that in the case of TM operation, the stability of the electrostatic adsorption force and the application of excessive voltage to the insulating material for electrostatic adsorption cannot be prevented. For this reason, the conventional technique has not taken into consideration that the result of the processing of the sample deviates from the expected allowable range and the processing yield is impaired. It was.
本発明の目的は、試料に印加するバイアス形成用の高周波の電圧が静電吸着に用いられる直流電源電圧に対して無視できない程度以上の値である場合であって、高周波電力の電圧を数十Hz〜数kHzの周波数でON/OFFする変調動作する場合であっても、試料の吸着の状態をより安定させて処理の歩留まりを向上させたプラズマ処理装置を提供することにある。また、静電吸着用絶縁材料への過剰な電圧印加を防止することのできるプラズマ処理装置を提供することにある。
An object of the present invention is a case where the high-frequency voltage for bias formation applied to the sample is a value that is not negligible with respect to the DC power supply voltage used for electrostatic adsorption, and the voltage of the high-frequency power is reduced to several tens. An object of the present invention is to provide a plasma processing apparatus that can stabilize the state of sample adsorption and improve the processing yield even when performing a modulation operation that is turned ON / OFF at a frequency of Hz to several kHz. It is another object of the present invention to provide a plasma processing apparatus capable of preventing an excessive voltage application to the electrostatic adsorption insulating material.
上記目的は、真空容器内部の処理室内に配置されその上面に処理対象の試料が載せられる試料台と、この試料台の前記試料が載せられる面を構成し内部に当該試料を吸着して保持する静電気力を発生するための膜状の吸着用電極を備えた誘電体製の膜と、前記試料台内部に配置され所定の周波数で高い出力と低い出力とが繰り返される高周波電力が供給される試料台内電極とを備え、 前記誘電体膜上に前記試料が保持された状態で前記試料台内電極に供給される前記高周波電力の前記出力の高低の繰り返しに合わせて、前記吸着用電極に供給される直流電源からの電力を各々で容量の異なる複数の給電経路の間で切り替える制御部とを備えたプラズマ処理装置により達成される。
The purpose is to arrange a sample stage on the upper surface of the vacuum chamber, on which a sample to be processed is placed, and a surface on which the sample is placed, and to adsorb and hold the sample inside. A dielectric film provided with a film-like adsorption electrode for generating electrostatic force, and a sample which is arranged inside the sample table and which is supplied with high frequency power that repeats high and low output at a predetermined frequency And supply to the adsorption electrode according to the repetition of the output of the high-frequency power supplied to the sample stage electrode in a state where the sample is held on the dielectric film. This is achieved by a plasma processing apparatus including a control unit that switches electric power from a direct current power source between a plurality of power supply paths each having a different capacity.
本発明により、高周波バイアス電圧の値(高周波バイアスON時)に対応した静電吸着用直流電圧の制御に加えて、高速にコンデンサを経由する経路での直流電圧印加回路と切り替えることでON/OFFの大きな高周波バイアス電圧印加の変化に対応した静電吸着電圧の制御が可能となる。結果、高周波バイアス電圧をTM動作させる場合においても安定した吸着力の確保と、静電吸着用絶縁材料への過剰電圧印加を防止できる。
According to the present invention, in addition to the control of the DC voltage for electrostatic attraction corresponding to the value of the high frequency bias voltage (when the high frequency bias is ON), it is switched ON / OFF by switching to the DC voltage application circuit in the path through the capacitor at high speed. It is possible to control the electrostatic chucking voltage corresponding to a large change in application of a high-frequency bias voltage. As a result, even when the high frequency bias voltage is TM-operated, it is possible to secure a stable attracting force and prevent application of excessive voltage to the electrostatic attracting insulating material.
本発明の実施の形態を以下、図面を用いて説明する。
Embodiments of the present invention will be described below with reference to the drawings.
本発明の実施例1を図1乃至7を用いて説明する。図1は、本発明の実施例に係るプラズマ処理装置の試料台の構成の概略を模式的に示す縦断面図である。本図では、プラズマ処理装置を構成する真空容器の内部に配置される試料台とこれに電気的または物理的に接続される複数の回路を模式的に示している。
A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a longitudinal sectional view schematically showing an outline of a configuration of a sample stage of a plasma processing apparatus according to an embodiment of the present invention. In this figure, a sample stage disposed inside a vacuum vessel constituting the plasma processing apparatus and a plurality of circuits electrically or physically connected to the sample stage are schematically shown.
本図において、本発明に係る試料台100は、図示しない真空容器内部に配置された処理室内に配置されるものであり、その上面に加工対象である試料が載置される載置面を備えている。真空容器内部の密封された処理室は、真空容器下方に配置された図示しないターボ分子ポンプ等の真空ポンプと連結され、処理室内の空間のガスは当該真空ポンプの動作により排気され処理室内が所定の真空度まで減圧される構成となっている。試料台100は、処理室内部の空間の下方に配置され、上方の空間には試料4を処理するために減圧された状態で供給される処理用ガスが供給されるとともに、真空容器外部から供給された電界または磁界の作用により処理用ガスの原子または分子が励起されてプラズマ16が形成される空間である。
In this figure, a sample stage 100 according to the present invention is disposed in a processing chamber disposed inside a vacuum vessel (not shown), and has a mounting surface on which a sample to be processed is mounted. ing. The sealed processing chamber inside the vacuum vessel is connected to a vacuum pump such as a turbo molecular pump (not shown) disposed below the vacuum vessel, and the gas in the space in the processing chamber is exhausted by the operation of the vacuum pump, and the processing chamber is predetermined. The pressure is reduced to a degree of vacuum. The sample stage 100 is disposed below the space inside the processing chamber, and the upper space is supplied with processing gas supplied in a decompressed state for processing the sample 4 and supplied from outside the vacuum vessel. This is a space in which plasma 16 is formed by exciting atoms or molecules of the processing gas by the action of the applied electric field or magnetic field.
本実施例の試料台100は、上面が半導体ウエハ等の基板状の試料4を載せて保持する円形またはこれと見做せる程度に近似した形状を有し、上下方向の中心軸に対称な円板または円筒或いはこれらと見做せる程度に近似した形状を備えている。主な構成部材は、金属等の熱伝導、導電性を有した円筒またはこれに近似した形状を備えた基材部1と、その上面上方を被って酸化アルミニウムや酸化イットリウム等のセラミックを含んで構成された誘電体製の膜を備えている。
The sample stage 100 of the present embodiment has a circular shape in which the upper surface is placed and held on a substrate-like sample 4 such as a semiconductor wafer, or a shape approximated to the extent that it can be regarded as this, and a circle that is symmetric with respect to the central axis in the vertical direction. It has a shape that approximates to a level that can be regarded as a plate or a cylinder or these. The main constituent members include a base material portion 1 having a shape similar to a cylinder having heat conduction or conductivity such as metal or the like, and a ceramic such as aluminum oxide or yttrium oxide covering the upper surface thereof. A dielectric film is formed.
当該膜の上面が試料4の載置面を構成し、その内部には直流電力が供給されて誘電体材料の表面と試料4裏面とに形成された電荷同士の間の静電気力により試料4を膜上面に吸着する膜状のESC電極3が配置されている。つまり、誘電体製の膜はESC膜2を構成し、内部のESC電極3は別々の極性が付与される複数の膜を備えて両極式の静電吸着電極を構成しており、本実施例では、特にESC電極3が偶数枚の膜から構成され、各々の極性が付与される膜の面積の合計が等しくなるようにESC膜内に配置されている。
The upper surface of the film constitutes the mounting surface of the sample 4, and DC power is supplied to the inside of the film to cause the sample 4 to be electrostatically generated between the charges formed on the surface of the dielectric material and the back surface of the sample 4. A film-like ESC electrode 3 adsorbed on the upper surface of the film is disposed. That is, the dielectric film constitutes the ESC film 2, and the internal ESC electrode 3 comprises a plurality of films provided with different polarities to constitute a bipolar electrostatic adsorption electrode. In particular, the ESC electrode 3 is composed of an even number of films, and is arranged in the ESC film so that the total areas of the films to which the respective polarities are imparted are equal.
本実施例では、図上2個が示されたESC電極3は各々が別々の直流電源5に電気的に接続されて直流電力が供給されて所期の極性が付与される。また、それぞれの直流電源5の一方の端部は接地されたアースと接続され他方の端部は低域通過フィルタ(LPF)6及び半導体スイッチ部7を介してESC電極3と接続されている。図示されるように、2枚あるESC電極3各々には、極性の異なる直流電圧が供給されプラズマ16が無い状態ではそれぞれに印加した直流電圧の電位差により試料4がESC膜2に静電吸着される。
In the present embodiment, two ESC electrodes 3 shown in the drawing are electrically connected to separate DC power sources 5 and supplied with DC power to be given the desired polarity. One end of each DC power source 5 is connected to a grounded earth, and the other end is connected to the ESC electrode 3 via a low-pass filter (LPF) 6 and a semiconductor switch unit 7. As shown in the figure, each of the two ESC electrodes 3 is supplied with a DC voltage of different polarity and in the absence of the plasma 16, the sample 4 is electrostatically adsorbed to the ESC film 2 by the potential difference of the DC voltage applied to each of them. The
半導体スイッチ部7は、各々のESC電極3と低域通過フィルタ6との間の電気的な接続を、コンデンサ8を介したものの介さないものとに切り替えるスイッチの機能を備えている。この切り替えの動作の時刻や各々の接続の間隔は、直流電源5および半導体スイッチ7と信号を通信可能に構成された制御部9からの信号により調節される。
The semiconductor switch unit 7 has a function of a switch for switching the electrical connection between each ESC electrode 3 and the low-pass filter 6 to one that does not pass through the capacitor 8. The time of the switching operation and the interval between the connections are adjusted by a signal from the control unit 9 configured to communicate signals with the DC power supply 5 and the semiconductor switch 7.
本実施例において、コンデンサ8は各ESC電極3と試料4と間の静電容量と同程度の静電容量を有する。また、本実施例は、その一方の端部側が接地されるかアース電位にされた箇所と電気的に接続され、他方側の端部が高周波電圧検知部10、高周波整合器11を介してTiあるいはこれを成分として含む金属製の基材部1と電気的に接続された高周波電源12を備えている。試料4が試料台100上部のESC膜2上で載せられて吸着され保持された状態で高周波電源12からの高周波電力が基材部1に印加され、ESC膜2及び試料4の上面上方にバイアス電位が形成される。
In this embodiment, the capacitor 8 has a capacitance comparable to the capacitance between each ESC electrode 3 and the sample 4. Further, in this embodiment, one end side is electrically connected to a place grounded or grounded, and the other end is connected to Ti via a high-frequency voltage detector 10 and a high-frequency matching unit 11. Or the high frequency power supply 12 electrically connected with the metal base part 1 which contains this as a component is provided. In a state where the sample 4 is placed on the ESC film 2 above the sample stage 100 and is adsorbed and held, the high frequency power from the high frequency power source 12 is applied to the base portion 1, and a bias is applied above the upper surfaces of the ESC film 2 and the sample 4. A potential is formed.
基材部1の内部には冷媒流路13が配置され図示しないチラーユニット等の温度調節器と管路を介して接続され、温度調節器から流出した冷媒が冷媒流路13を通って戻る循環路が構成されている。所定の温度にされた冷媒が冷媒流路13内を流れつつこれを構成する基材部1の部材との間で熱交換することで基材部1の温度が処理や装置の運転に適した温度の範囲内の所望の値に調節される。さらに、円筒形状を有した試料台100の中心軸またはその近傍には、基材部100及びESC膜2を貫通して図示しないガス源である貯留部と連結されたガス供給路14が配置されている。
A refrigerant flow path 13 is disposed inside the base member 1 and is connected to a temperature controller such as a chiller unit (not shown) via a conduit, and the refrigerant flowing out of the temperature controller returns through the refrigerant flow path 13. A road is constructed. The temperature of the base material part 1 is suitable for processing and operation of the apparatus by exchanging heat with the member of the base material part 1 constituting the refrigerant at a predetermined temperature while flowing in the refrigerant flow path 13. It is adjusted to the desired value within the temperature range. Furthermore, a gas supply path 14 that penetrates the base material 100 and the ESC film 2 and is connected to a storage unit that is a gas source (not shown) is disposed at or near the central axis of the sample stage 100 having a cylindrical shape. ing.
ガス供給路14の上端であるESC膜2中央部の開口は試料4がESC膜2上に載せられた状態で、試料4裏面とESC膜2上面との間のすき間に面している。この開口を通りガス源からガス供給路14を通り流れてきたヘリウムガスが当該すき間に導入され、所定の範囲の値の圧力となるように調節されたこのヘリウムガスによって試料4とESC膜2との間の熱伝導が高くされている。
The opening at the center of the ESC film 2, which is the upper end of the gas supply path 14, faces the gap between the back surface of the sample 4 and the upper surface of the ESC film 2 with the sample 4 placed on the ESC film 2. The helium gas that has flowed from the gas source through the gas supply path 14 through this opening is introduced into the gap, and the helium gas adjusted to have a pressure within a predetermined range is used for the sample 4 and the ESC film 2. The heat conduction between is high.
また、本実施例の高周波電源12および制御部9は、制御部15と通信可能に接続され、これらの動作を調節するための制御部15からの指令信号に基づいて動作する。以下に説明する制御部9,15は、内部に半導体製のマイクロプロセッサ等の演算器と記載されたアルゴリズムに沿ってこの演算器が動作するソフトウエアやデータが記録され格納される記憶装置と外部との間の通信を繋ぐインターフェースとこれら演算器、記憶装置、インターフェース同士を通信可能に接続する通信経路とを備え、インターフェースは高周波電源12等の制御対称と無線あるいは有線で通信可能に接続されこれらの間で信号を授受可能に構成されている。
The high-frequency power source 12 and the control unit 9 of the present embodiment are communicably connected to the control unit 15 and operate based on a command signal from the control unit 15 for adjusting these operations. The control units 9 and 15 described below include a storage device in which software and data for operating the arithmetic unit are recorded and stored in accordance with an algorithm described as an arithmetic unit such as a semiconductor microprocessor. And an interface for connecting the communication between these and the arithmetic unit, the storage device, and a communication path for connecting the interfaces so that they can communicate with each other. It is comprised so that a signal can be exchanged between.
本実施例に係るプラズマ処理装置の従来の技術について、図2乃至5を用いて説明する。図2は、従来の技術に係るプラズマ処理装置が備える高周波電源12から時間的に連続した高周波の電圧が試料台またはその基材部に供給された場合の当該試料台上部に配置された両極式静電吸着用の電極の動作を表すタイミングチャートである。
A conventional technique of the plasma processing apparatus according to the present embodiment will be described with reference to FIGS. FIG. 2 shows a bipolar system arranged on the upper part of the sample stage when a time-continuous high-frequency voltage is supplied from the high-frequency power source 12 included in the plasma processing apparatus according to the prior art to the sample stage or its base part. It is a timing chart showing operation | movement of the electrode for electrostatic attraction.
このような両極式の静電吸着の従来技術では、試料台の上面である載置面を構成する誘電体製の膜内に配置された静電吸着用の複数の金属製の膜であって各々の面積が1:1かこれと見做せる程度に近似した値となる複数の電極に極性の異なる直流電圧が直流電源から印加される。図2では、図1の実施例のESC電極3に相当する静電吸着電極を構成する電極Cに+2000V、同じく電極Dに−2000Vが印加された場合の例が示されている。
In the prior art of such bipolar electrostatic adsorption, a plurality of metal films for electrostatic adsorption arranged in a dielectric film constituting the mounting surface which is the upper surface of the sample stage, A DC voltage having a different polarity is applied from a DC power source to a plurality of electrodes each having an area close to 1: 1 or a value approximated to such an extent. FIG. 2 shows an example in which +2000 V is applied to the electrode C constituting the electrostatic chucking electrode corresponding to the ESC electrode 3 of the embodiment of FIG. 1 and −2000 V is applied to the electrode D.
この状態において、さらに処理室内の試料台の上方においてプラズマ16が着火されておらず且つ高周波電源から高周波電力が基材部に供給されていない条件の下では、試料上に形成される電位はそれぞれに印加された極性が逆である直流電力の電圧の中間の電位(図2の例では0Vまたはこれに近似した値)となり、試料と静電吸着電極C,Dと間の電位差はそれぞれ印加した直流電圧の和と同じかこれに近似した値になる。この状態でプラズマ16が着火しても高周波電圧が印加されない状態では、電極C−D間の電位差はプラズマ16形成前のものと同等に保たれる。
In this state, under the condition that the plasma 16 is not ignited above the sample stage in the processing chamber and the high-frequency power is not supplied from the high-frequency power source to the base material part, the potentials formed on the sample are respectively The potential applied is an intermediate potential of the voltage of the DC power having the opposite polarity (0 V in the example of FIG. 2 or a value close thereto), and the potential difference between the sample and the electrostatic adsorption electrodes C and D was applied respectively. The value is the same as or close to the sum of the DC voltages. In this state, even if the plasma 16 is ignited, the potential difference between the electrodes CD is kept equal to that before the plasma 16 is formed in a state where a high frequency voltage is not applied.
しかし、高周波電力の電圧が印加されると試料には、高周波電圧の振幅に対応したセルフバイアス電圧(Vdc)が発生する。Vdcは負の電位であり、被加工試料の電位はこのVdcの値となる。
However, when a high-frequency power voltage is applied, a self-bias voltage (Vdc) corresponding to the amplitude of the high-frequency voltage is generated in the sample. Vdc is a negative potential, and the potential of the sample to be processed is the value of Vdc.
このVdcが各ESC電極C,Dに印加した直流電圧に比べて無視できない程度に有意な差異を生じる電圧が発生すると、図2に示すように、直流電源により正の直流電圧を印加したESC電極Cと被加工試料間の電位差は直流電源により印加した直流電圧に|Vdc|を加えた値となる。一方、直流電源より負の電位を印加したESC電極Dと被加工試料間の電位差は直流電源により印加した電圧から|Vdc|を差し引いた値となる。
When a voltage that causes a significant difference between Vdc and the DC voltage applied to each ESC electrode C and D is generated, an ESC electrode to which a positive DC voltage is applied by a DC power source as shown in FIG. The potential difference between C and the sample to be processed is a value obtained by adding | Vdc | to a DC voltage applied by a DC power source. On the other hand, the potential difference between the ESC electrode D to which a negative potential is applied from the DC power source and the sample to be processed is a value obtained by subtracting | Vdc | from the voltage applied by the DC power source.
静電吸着力は、各ESC電極C,Dと誘電体膜上に載せられた試料間の電位差により支配的に依存するため、図2に示す高周波の電圧が印加された状態となると、ESC電極Cと試料との間は吸着力が増加する一方でESC電極Dと試料との間は吸着力が低下する。よって、静電吸着力を発生する面積の1/2を占めるESC電極Dの吸着力が低下することで、全体として被加工試料の吸着力が低下してしまう。また、ESC電極Cとの間に印加した直流電圧より高い電位差が生じるため、Vdcの値によってはこれらESC膜C,Dの耐電圧を超えてしまう場合が生じてしまう虞が有る。
The electrostatic attraction force depends predominantly on the potential difference between the ESC electrodes C and D and the sample placed on the dielectric film. Therefore, when the high frequency voltage shown in FIG. 2 is applied, the ESC electrode While the adsorption force increases between C and the sample, the adsorption force decreases between the ESC electrode D and the sample. Therefore, the adsorption force of the ESC electrode D occupying 1/2 of the area where the electrostatic adsorption force is generated is reduced, so that the adsorption force of the sample to be processed is reduced as a whole. In addition, since a potential difference higher than the DC voltage applied to the ESC electrode C is generated, the withstand voltage of the ESC films C and D may be exceeded depending on the value of Vdc.
そこで、図3に示すように、従来の技術では試料に印加される高周波電力の電圧を検知し、その検知した値の大小に応じて各ESC電極C,Dに印加する直流電力の電圧を調節している。例えば、図3に示す例では、プラズマ16の着火が無く(プラズマ16が形成されておらず)高周波電圧が印加されていない状態では、ESC電極C,Dにそれぞれ+2000V、−2000Vが印加される。プラズマ16が着火されて形成され、試料台の基材部等の内部の金属製の電極に高周波電圧が印加されると高周波電圧の振幅Vppに一定の定数(従来は0.3〜0.5程度)を乗じた値の直流電圧をそれぞれのESC電極に印加する電圧に加減する。
Therefore, as shown in FIG. 3, in the conventional technique, the voltage of the high frequency power applied to the sample is detected, and the voltage of the DC power applied to each ESC electrode C, D is adjusted according to the detected value. doing. For example, in the example shown in FIG. 3, +2000 V and −2000 V are applied to the ESC electrodes C and D, respectively, in a state where the plasma 16 is not ignited (the plasma 16 is not formed) and no high frequency voltage is applied. . When the plasma 16 is ignited and a high frequency voltage is applied to an internal metal electrode such as the base portion of the sample stage, a constant constant (conventionally 0.3 to 0.5) is applied to the amplitude Vpp of the high frequency voltage. The direct current voltage multiplied by the degree is adjusted to the voltage applied to each ESC electrode.
具体的には正の直流電圧を印加しているESC電極Cの電圧(+2000V)は減少させ、負の直流電圧(−2000V)を印加しているESC電極Dの電圧は増加させるよう調節される。例えば、高周波電圧振幅Vppが5000V、Vdcを推定するための定数を0.4とした場合、プラズマ16着火前に+2000Vを印加していたESC電極Cの印加電圧は0Vとし、同様にプラズマ16着火前に−2000Vを印加していたESC電極Dの印加電圧を−4000Vとする。このようにすることで、高周波電圧が印加された後も各ESC電極C,Dと試料間の電位差の変動が抑制され、吸着力の安定化とESC膜同士の間に過剰な電位差が形成されることが抑制される。
Specifically, the voltage (+2000 V) of the ESC electrode C to which a positive DC voltage is applied is decreased, and the voltage of the ESC electrode D to which a negative DC voltage (−2000 V) is applied is adjusted to increase. . For example, when the high-frequency voltage amplitude Vpp is 5000 V and the constant for estimating Vdc is 0.4, the applied voltage of the ESC electrode C to which +2000 V was applied before the plasma 16 ignition is 0 V, and similarly the plasma 16 ignition is performed. The applied voltage of the ESC electrode D to which −2000V was previously applied is −4000V. By doing this, even after a high frequency voltage is applied, fluctuations in the potential difference between the ESC electrodes C and D and the sample are suppressed, and an excessive potential difference is formed between the adsorption force stabilization and the ESC films. Is suppressed.
近年の半導体デバイスの製造のための半導体ウエハ等試料の工程においては、図1乃至3の例のように高周波電圧が時間的に連続して印加される場合のみでなく、図4,5に示すように、高周波電圧が時間の経過に伴なってON/OFFまたは高出力及び低出力を特定の間隔或いは周波数で繰り返す場合が有る。本実施例では、このようなバイアス電位の形成のための高周波電力の供給を変調バイアス印加方式、特に時間変調(Time Modulation方式:TM方式)と以下に呼称する。
In the process of a sample such as a semiconductor wafer for manufacturing a semiconductor device in recent years, not only a case where a high-frequency voltage is continuously applied as in the example of FIGS. As described above, the high-frequency voltage may repeat ON / OFF or high output and low output at a specific interval or frequency as time elapses. In this embodiment, the supply of high-frequency power for forming such a bias potential is hereinafter referred to as a modulation bias application method, particularly time modulation (Time Modulation method: TM method).
なお、図4,5に示す例では、試料台内の電極への高周波電力の供給は時間の経過に伴ってOn/Offされる一方で、処理室内の試料台上方の空間でのプラズマ16の生成は連続して行なわれている。
In the example shown in FIGS. 4 and 5, the supply of high-frequency power to the electrodes in the sample table is turned on / off as time passes, while the plasma 16 in the space above the sample table in the processing chamber is supplied. Generation is performed continuously.
TM方式の場合において、図1と同様に一定のESC用の直流電圧を各ESC電極C,Dに印加した場合では、図4に示すように、高周波電圧がOnの期間でESC電極Cと試料との間の電位差は直流電圧より高い電位差となり、ESC電極Dと試料との間の電位差は高周波電圧Onの期間で直流電圧より低い値となる。このため、図4の例でも図1と同様に高周波電圧がOnの期間でESC電極Dの吸着力の不足と、ESC電極Cに過剰な電圧の印加が生じる虞が生じる。
In the case of the TM method, when a constant ESC DC voltage is applied to each of the ESC electrodes C and D as in FIG. 1, as shown in FIG. Is a potential difference higher than the DC voltage, and the potential difference between the ESC electrode D and the sample is a value lower than the DC voltage during the period of the high-frequency voltage On. For this reason, in the example of FIG. 4 as well, in the period when the high-frequency voltage is On, there is a possibility that the adsorption force of the ESC electrode D is insufficient and an excessive voltage is applied to the ESC electrode C.
図5は、図2に示す例と同様に、高周波電圧Vppの値に応じてESC電極C,Dに供給される直流電圧の値を調節してする場合を示している。本図の例も、図2と同様の吸着力の安定化とESC膜同士の間の過剰な電位差の生起の抑制とを図るものである。しかし、一般に直流電圧の値を高周波のON/OFFに対応させて所定の値に増減することは技術的に困難である。何故なら、試料の静電吸着に必要なだけの直流の高い電圧をTMの周期、周波数に合わせて加減すると、無効電流分に対応した電源容量が必要となり電源の大型化や印加回路の複雑化を招いてしまう。
FIG. 5 shows a case where the value of the DC voltage supplied to the ESC electrodes C and D is adjusted according to the value of the high-frequency voltage Vpp, as in the example shown in FIG. The example in this figure also aims to stabilize the adsorption force similar to that in FIG. 2 and suppress the occurrence of an excessive potential difference between the ESC films. However, in general, it is technically difficult to increase or decrease the value of the DC voltage to a predetermined value corresponding to ON / OFF of the high frequency. This is because if a high direct current voltage necessary for electrostatic attraction of the sample is adjusted according to the TM cycle and frequency, a power capacity corresponding to the reactive current is required, resulting in a larger power supply and a complicated application circuit. Will be invited.
また、本例における試料台上のESC電極C,Dに電力を供給する直流電源には、試料台内の電極に印加される高周波電力の一部が漏洩して流れる可能性が有り、このような電力に対しても直流電源を保護するため、直流電源とESC電極との間には低域通過フィルタが配置されているものが一般的である。このような低域通過フィルタは、TM方式の変調による電圧変動も考慮した帯域を備えているため、例え直流電源がバイアス形成用の高周波電力の高速な変調(値の時間的な増減)に対応して増減できたとしても低域通過フィルタによりこれが阻止されてしまう。
Further, in the DC power supply for supplying power to the ESC electrodes C and D on the sample stage in this example, there is a possibility that a part of the high frequency power applied to the electrodes in the sample stage leaks and flows. In order to protect the direct current power supply against a large amount of power, a low pass filter is generally disposed between the direct current power supply and the ESC electrode. Since such a low-pass filter has a band that also takes into account voltage fluctuations due to TM modulation, the DC power supply supports high-speed modulation of the high-frequency power for bias formation (time increase / decrease in value). Even if it can be increased or decreased, this is prevented by the low-pass filter.
このような理由から、図5に示すように、高周波電圧ON時の高周波電圧振幅Vppに対応した値で制御しようとすると、高周波電圧がOffの期間にESC電極Cと試料との間の電位差は低くなり、ESC電極Dと試料との間の電位差は過剰となる。図4,5に示すように、従来の技術ではTM方式に対応して直流電源からの出力を制御して増減することは困難であり、安定した静電吸着力確保とESC膜に加わる過剰電位差を抑止することが困難であった。
For this reason, as shown in FIG. 5, when the control is performed with a value corresponding to the high-frequency voltage amplitude Vpp when the high-frequency voltage is ON, the potential difference between the ESC electrode C and the sample during the high-frequency voltage off period is The potential difference between the ESC electrode D and the sample becomes excessive. As shown in FIGS. 4 and 5, it is difficult to control the output from the DC power supply in accordance with the TM method, and it is difficult to increase / decrease with the conventional technique, ensuring a stable electrostatic attracting force and excess potential difference applied to the ESC film. It was difficult to deter.
次に、図1及び6を用いて本実施例1の動作を説明する。図6は、図1に示す実施例に係るプラズマ処理装置の高周波電源12から高周波の電圧が試料台100またはその基材部1に供給された場合の当該試料台100上部に配置された両極式静電吸着用のESC電極3の動作を表すタイミングチャートである。
Next, the operation of the first embodiment will be described with reference to FIGS. FIG. 6 shows a bipolar type disposed on the sample stage 100 when a high frequency voltage is supplied from the high frequency power supply 12 of the plasma processing apparatus according to the embodiment shown in FIG. 6 is a timing chart showing the operation of the ESC electrode 3 for electrostatic adsorption.
図6の例では、プラズマ16が着火前でかつ高周波(RF)の電圧が印加される以前は、図2乃至5に示した従来の技術と同様に、ESC電極Cに+2000V、ESC電極Dに−2000Vの直流電圧が直流電源5から供給され、ESC膜2と試料4との間に形成された静電気力により試料4がESC膜2上に吸着されて保持される。この際、試料4と各ESC電極C及びDと間の電位差は各々2000Vまたはこれと見做せる程度に近似した値となる。
In the example of FIG. 6, before the plasma 16 is ignited and before the radio frequency (RF) voltage is applied, the ESC electrode C is + 2000V and the ESC electrode D is applied to the ESC electrode D, as in the conventional technique shown in FIGS. A DC voltage of −2000 V is supplied from the DC power source 5, and the sample 4 is adsorbed and held on the ESC film 2 by the electrostatic force formed between the ESC film 2 and the sample 4. At this time, the potential difference between the sample 4 and each of the ESC electrodes C and D is 2000 V or a value approximated to the extent that it can be regarded as this.
次に、プラズマ16が着火されて処理室内にプラズマ16が形成され、高周波電源12からの高周波(RF)電力が試料台100の基材部1に供給され試料4表面上方にバイアス電位が形成される。上記の通り、本例では高周波の電力は時間変調(TM)されて所定の周波数(間隔)でOn/Offされて高周波電源12から基材部1に供給される。この際、本例のプラズマ16は時間的に連続して形成され(非断続的に形成され)ており、両者のうち基材部1を介して試料4に印加されるバイアス形成用の高周波電力のみその電圧がTM方式で動作する。
Next, the plasma 16 is ignited to form the plasma 16 in the processing chamber, and high frequency (RF) power from the high frequency power source 12 is supplied to the base portion 1 of the sample stage 100 to form a bias potential above the surface of the sample 4. The As described above, in this example, high-frequency power is time-modulated (TM), turned on / off at a predetermined frequency (interval), and supplied from the high-frequency power source 12 to the base member 1. At this time, the plasma 16 of this example is continuously formed (discontinuously formed) in time, and among them, a high-frequency power for forming a bias applied to the sample 4 via the base member 1. Only that voltage operates in TM mode.
本例では、高周波電圧の印加と同時に、図示しない電圧センサにより高周波電圧がOnにされる時点での電圧を検知し、この検知結果に応じて負の電圧が印加されるESC電極Dの直流電圧を変化させる。具体的には、直流電源5からESC電極Dに印加される直流電圧は、図3、図4で示した従来技術と同様に検出した高周波電圧振幅(Vpp)に任意に定められる係数(本例では0.3〜0.5)を乗じた分だけ増加される。
In this example, simultaneously with the application of the high-frequency voltage, the voltage at the time when the high-frequency voltage is turned on is detected by a voltage sensor (not shown), and the DC voltage of the ESC electrode D to which a negative voltage is applied according to the detection result. To change. Specifically, the DC voltage applied from the DC power source 5 to the ESC electrode D is a coefficient (this example) arbitrarily determined by the high-frequency voltage amplitude (Vpp) detected in the same manner as the prior art shown in FIGS. In this case, the value is increased by a factor of 0.3 to 0.5).
例えば、Vppが5000V、係数を0.4とした場合、負の電圧が印加されるESC電極Dの電圧は−2000Vから−4000Vに低下する。この際、各々の制御部9からの指令信号に応じて、正の電圧が印加されているESC電極Cと接続された半導体スイッチ部7は高周波の電圧がOnの期間において図1中に示すA接点側に接続するようにされ、コンデンサ8を介さずに直流電源5の電圧がESC電極Cに印加される構成となっている。一方、負の電圧が印加されているESC電極Dと接続された半導体スイッチ部7はB接点側にされ、コンデンサ8を介して直流電源5の電圧をESC電極Dに印加されている。このB接点側に切り替えられて接続された直流電源5からESC電極Dへの給電経路は半導体スイッチ部7がA接点側に切り替えられた場合の給電経路よりコンデンサ8の静電容量の分だけインピーダンスまたは静電容量が大きくされている。
For example, when Vpp is 5000V and the coefficient is 0.4, the voltage of the ESC electrode D to which a negative voltage is applied decreases from −2000V to −4000V. At this time, the semiconductor switch unit 7 connected to the ESC electrode C to which a positive voltage is applied corresponds to the command signal from each control unit 9 and the A switch shown in FIG. The connection is made on the contact side, and the voltage of the DC power supply 5 is applied to the ESC electrode C without passing through the capacitor 8. On the other hand, the semiconductor switch unit 7 connected to the ESC electrode D to which a negative voltage is applied is on the B contact side, and the voltage of the DC power supply 5 is applied to the ESC electrode D via the capacitor 8. The power supply path from the DC power supply 5 switched to the B contact side and connected to the ESC electrode D has an impedance corresponding to the capacitance of the capacitor 8 from the power supply path when the semiconductor switch unit 7 is switched to the A contact side. Or the capacitance is increased.
一方、高周波電圧がOFFの際は、ONの期間とは逆に、正の電圧が印加されているESC電極Cと接続される半導体スイッチ部7では、B接点側(コンデンサ8を介して直流電源5の電圧をESC電極Cに印加される構成)とし、負の電圧が印加されているESC電極Dと接続される半導体スイッチ部7ではA接点側(直に直流電源5の電圧をESC電極Dに印加される構成)にされる。このような動作により、従来技術で課題となる高周波電圧ON/OFFに伴う吸着電圧の低下や過剰電圧の印加が回避される。
On the other hand, when the high-frequency voltage is OFF, contrary to the ON period, the semiconductor switch unit 7 connected to the ESC electrode C to which a positive voltage is applied has a B contact side (DC power supply via the capacitor 8). 5 is applied to the ESC electrode C), and the semiconductor switch unit 7 connected to the ESC electrode D to which a negative voltage is applied has a contact A side (the voltage of the DC power supply 5 is directly applied to the ESC electrode D). To be applied). By such an operation, it is possible to avoid a decrease in adsorption voltage and application of excessive voltage, which are problems in the prior art, due to the high-frequency voltage ON / OFF.
上記動作における高周波電圧ON時の状態を説明する。プラズマ16が着火して形成され、高周波電圧が基材部1に印加されると、試料4上面の電位はセルフバイアスの電位となる。この電位は負の値であって、通常高周波電圧の振幅Vppの0.3〜0.5倍程度となる。
The state when the high-frequency voltage is ON in the above operation will be described. When the plasma 16 is ignited and a high frequency voltage is applied to the base member 1, the potential on the upper surface of the sample 4 becomes a self-bias potential. This potential is a negative value and is usually about 0.3 to 0.5 times the amplitude Vpp of the high-frequency voltage.
よって、半導体スイッチ部7等によって直流電源5の出力の値を変化させない場合での高周波電圧ONの期間では正の電圧が印加されるESC電極Cと試料4間の電位差はセルフバイアス電圧分大きくなることになる。このため、その分だけ大きな電位差が2つのESC膜2の間に形成され、負の電圧が印加されるESC電極Dと試料4と間では、これらの電位差がセルフバイアス電圧分小さくなり吸着力が低下する。
Therefore, the potential difference between the ESC electrode C to which the positive voltage is applied and the sample 4 is increased by the self-bias voltage during the high-frequency voltage ON period when the output value of the DC power supply 5 is not changed by the semiconductor switch unit 7 or the like. It will be. For this reason, a large potential difference is formed between the two ESC films 2, and the potential difference between the ESC electrode D and the sample 4 to which a negative voltage is applied is reduced by the self-bias voltage and the adsorption force is reduced. descend.
そこで、本実施例では、高周波電圧ONの期間で半導体スイッチ部7をA接点側に切り替えることでコンデンサ8の静電容量分の容量またはインピーダンスが相対的に小さくされた給電経路を通して直流電源5から電力を負の値にされたESC電極Dに供給することにより、Vppの値に応じたセルフバイアス電位に相当する電圧の分だけ直流電源5からESC電極Dに供給される電圧を、図6に示すように、低減するように変化させる。このような構成により負の電圧が印加されているESC電極Dと試料4との間の電位差の変化が抑制され吸着力の変化が低減する。
Therefore, in this embodiment, the semiconductor switch unit 7 is switched to the A contact side during the high-frequency voltage ON period, so that the capacitance or impedance corresponding to the capacitance of the capacitor 8 is reduced from the DC power source 5 through the power supply path. By supplying electric power to the ESC electrode D having a negative value, the voltage supplied from the DC power source 5 to the ESC electrode D by the amount corresponding to the self-bias potential corresponding to the value of Vpp is shown in FIG. As shown, change to reduce. With such a configuration, a change in potential difference between the ESC electrode D to which a negative voltage is applied and the sample 4 is suppressed, and a change in adsorption force is reduced.
一方、正の電圧を印加しているESC電極Cには過剰な電位差が発生しないように、半導体スイッチ部7を動作させ直流電源5からESC電極Cへの電力の供給の経路をコンデンサ8の静電容量分の容量またはインピーダンスが相対的に大きくされたB側のものに切り替える(固体スイッチC)。この例において、半導体スイッチ部7のコンデンサ8はESC電極Dと試料4との間の静電容量と同程度な値(例えば9000pF程度)に構成される。このことにより、ESC電極Cに印加される電圧は静電容量比により分圧され、ESC電極Cと試料4との間の電位差はコンデンサを介さない場合に対して半分程度となり、結果としてESC電極Cと試料4と間の電位差の増大を抑制し安定化させることができる。
On the other hand, the semiconductor switch unit 7 is operated so that an excessive potential difference does not occur in the ESC electrode C to which a positive voltage is applied, so that the power supply path from the DC power supply 5 to the ESC electrode C is statically connected to the capacitor 8. Switch to the one on the B side where the capacity or impedance of the electric capacity is relatively increased (solid switch C). In this example, the capacitor 8 of the semiconductor switch unit 7 is configured to have a value similar to the capacitance between the ESC electrode D and the sample 4 (for example, about 9000 pF). As a result, the voltage applied to the ESC electrode C is divided by the capacitance ratio, and the potential difference between the ESC electrode C and the sample 4 is about half that when no capacitor is interposed. As a result, the ESC electrode An increase in potential difference between C and sample 4 can be suppressed and stabilized.
次に、高周波電圧OFF時の動作を説明する。プラズマ16が形成された状態で、高周波電圧がOFFになると試料4の電位はプラズマ16のフローティングポテンシャルで決まる電位となり、十数〜数十V程度とほぼ0V近辺となる。よって、図6に示す高周波電圧ON状態における直流電源5からの電力の供給の条件のままではESC電極Dと試料4との間に過剰な電位差で電圧が印加されることになる。
Next, the operation when the high frequency voltage is OFF will be described. When the high frequency voltage is turned off in the state where the plasma 16 is formed, the potential of the sample 4 becomes a potential determined by the floating potential of the plasma 16, which is about 10 to several tens V, which is around 0V. Therefore, the voltage is applied with an excessive potential difference between the ESC electrode D and the sample 4 under the condition of supplying power from the DC power source 5 in the high-frequency voltage ON state shown in FIG.
しかし、従来の技術では、直流電源5の電圧の値は高周波電源12からの電力の電圧の周期的なON/OFFに追従してこれを変化させることが困難であるため、高周波電圧がONである期間の値を参照し決定される構成にされることが一般的であった。図6に示す実施例では、高周波電圧がOFFとなる期間では、半導体スイッチ部7においてB接点側に切り替えて直流電源5からESC電極Dへの電力の供給をコンデンサ8を介した経路に切り替える。
However, in the conventional technique, it is difficult to change the voltage value of the DC power supply 5 following the periodic ON / OFF of the voltage of the power from the high-frequency power supply 12, so that the high-frequency voltage is ON. In general, a configuration is determined by referring to a value of a certain period. In the embodiment shown in FIG. 6, during the period when the high-frequency voltage is OFF, the semiconductor switch unit 7 switches to the B contact side and switches the power supply from the DC power supply 5 to the ESC electrode D to the path via the capacitor 8.
さらに、直流電源5からESC電極Cへ直流電力を供給する経路を半導体スイッチ部7においてA接点側に切り替えて、直流電源5からESC電極Cへの電力の供給をコンデンサ8を介さない経路に切り替える。このような構成により、先に説明した高周波電圧ONの状態でのESC電極Cと同様に、ESC電極Dに印加される直流電圧はESC膜とコンデンサ8に分圧され、結果としてESC電極Dと試料4との間の電位差を安定化させることができる。
Further, the path for supplying DC power from the DC power supply 5 to the ESC electrode C is switched to the A contact side in the semiconductor switch unit 7, and the power supply from the DC power supply 5 to the ESC electrode C is switched to a path not via the capacitor 8. . With this configuration, the DC voltage applied to the ESC electrode D is divided into the ESC film and the capacitor 8 in the same manner as the ESC electrode C in the state of the high-frequency voltage ON described above. The potential difference with the sample 4 can be stabilized.
本実施例では、試料4の上面に予め配置された膜層のうち処理対象の膜を処理する工程が開始されて終了するまでの期間で、上記の半導体スイッチ部7の切り替えの動作を高周波電力の電圧が周期的にON/OFFされる当該周期に追従あるいは同期させて実施する。このことにより、試料4の処理中において、TM方式により変化する高周波の電圧に対応してESC電極C,Dに供給される直流電力の電圧値を変化させこれらの電極と試料4との間の電位差の変動を抑制でき、これにより静電吸着力を安定化し過剰電圧印加に伴う絶縁破壊を抑制できる。
In the present embodiment, the switching operation of the semiconductor switch unit 7 is performed during the period from the start to the end of the process of processing the film to be processed among the film layers previously disposed on the upper surface of the sample 4. This is carried out following or synchronizing with the period in which the voltage is periodically turned ON / OFF. As a result, during the processing of the sample 4, the voltage value of the DC power supplied to the ESC electrodes C and D is changed corresponding to the high-frequency voltage changed by the TM method, so that the voltage between these electrodes and the sample 4 is changed. The fluctuation of the potential difference can be suppressed, whereby the electrostatic attraction force can be stabilized and the dielectric breakdown accompanying excessive voltage application can be suppressed.
図1に示した実施例では、コンデンサ8の容量値が、直流電源5に接続されるESC電極3と試料4との間のESC膜2を挟んだ静電容量と同程度のものにされているが、ESC電極3と試料4間の静電容量の1/4〜4倍の範囲のコンデンサを配置することでも同様な結果を得ることができる。一般に、ESC電極3と試料4との間の電位差VESCはESC電極3と試料4との間の静電容量(C1)とコンデンサ8の静電容量(C2)で以下の式(1)により決定できる。
In the embodiment shown in FIG. 1, the capacitance value of the capacitor 8 is set to be approximately the same as the capacitance sandwiching the ESC film 2 between the ESC electrode 3 connected to the DC power source 5 and the sample 4. However, a similar result can be obtained by arranging a capacitor in a range of 1/4 to 4 times the capacitance between the ESC electrode 3 and the sample 4. In general, the potential difference VESC between the ESC electrode 3 and the sample 4 is determined by the following equation (1) based on the capacitance (C1) between the ESC electrode 3 and the sample 4 and the capacitance (C2) of the capacitor 8. it can.
VESC=C2×VG/(C1+C2) (1)
この式に従えば、コンデンサ8の容量値(C2)をESC電極3と試料4との間の静電容量(C1)に対して1/4〜4倍の範囲に設定すると、ESC電極3と試料4との間の電位差を直流電源5の出力値(VG)の0.2〜0.8の範囲で調節できることが判る。
VESC = C2 × VG / (C1 + C2) (1)
According to this equation, when the capacitance value (C2) of the capacitor 8 is set to a range of 1/4 to 4 times the capacitance (C1) between the ESC electrode 3 and the sample 4, the ESC electrode 3 It can be seen that the potential difference with the sample 4 can be adjusted within the range of 0.2 to 0.8 of the output value (VG) of the DC power supply 5.
図1の実施例では、コンデンサ8は1種類であり、使用条件に対して最も変動抑制が可能な分圧条件でコンデンサ8を選択する必要がある。一連の処理で幅広い高周波電圧に対応するためには、後述する変形例の構成を用いることでより吸着電圧の安定化をはかることができ、吸着力の安定性および過剰電圧印加の抑制精度を高めることができる。
In the embodiment of FIG. 1, there is one type of capacitor 8, and it is necessary to select the capacitor 8 under a voltage dividing condition that can most suppress fluctuations with respect to the use conditions. In order to deal with a wide range of high-frequency voltages in a series of processing, it is possible to further stabilize the adsorption voltage by using the configuration of the modified example described later, and improve the stability of the adsorption force and the suppression accuracy of excessive voltage application. be able to.
図7を用いて、図1の実施例とは別のESC電極3の動作について説明する。図7は、図1の実施例に係るプラズマ16処理装置の高周波電源12から高周波の電圧が試料台100またはその基材部1に供給された場合の当該試料台100上部に配置された両極式静電吸着用の電極の動作の別の例を表すタイミングチャートである。
The operation of the ESC electrode 3 different from the embodiment of FIG. 1 will be described with reference to FIG. 7 shows a bipolar type disposed on the sample stage 100 when a high frequency voltage is supplied from the high frequency power supply 12 of the plasma 16 processing apparatus according to the embodiment of FIG. It is a timing chart showing another example of operation of the electrode for electrostatic attraction.
本例では、プラズマ16の着火が無く、高周波電圧のESC電極3への印加も無い条件においては、図6と同様にESC電極C,Dにそれぞれ+2000V,−2000Vの直流電圧が直流電源5から供給されて試料4をESC膜上に静電吸着させている。次に、プラズマ16が着火されプラズマ16が形成され高周波(RF)電力が印加されると、これに合わせてESC電極Dに供給される電圧を負の値である−2000Vから正の値である+2000Vに変化させる。
In this example, under the condition that the plasma 16 is not ignited and the high frequency voltage is not applied to the ESC electrode 3, DC voltages of +2000 V and −2000 V are respectively applied to the ESC electrodes C and D from the DC power source 5 as in FIG. 6. The sample 4 is supplied and electrostatically adsorbed on the ESC film. Next, when the plasma 16 is ignited, the plasma 16 is formed, and radio frequency (RF) power is applied, the voltage supplied to the ESC electrode D in accordance with this is changed from a negative value of −2000 V to a positive value. Change to + 2000V.
この状態で電極C,Dには共に直流電力の+2000Vが印加され、実質的に単極方式によって試料4が吸着されている。この状態を基本とし、高周波の電圧がONにされている期間では直流電源5と電極C,Dの各々との間の電力の給電経路は、電極C,Dに各々接続される半導体スイッチ部7においてコンデンサ8を介して相対的に容量またはインピーダンスが大きいB接点側の経路に切り替え、高周波電圧がOFFの期間では当該コンデンサ8を介さず直流電圧を印加するA接点側の経路に切り替える。
In this state, +2000 V of DC power is applied to both the electrodes C and D, and the sample 4 is substantially adsorbed by the monopolar method. Based on this state, the power supply path between the DC power source 5 and each of the electrodes C and D is a semiconductor switch unit 7 connected to the electrodes C and D during the period when the high-frequency voltage is ON. In FIG. 2, the path is switched to the B contact side having a relatively large capacity or impedance via the capacitor 8 and switched to the A contact side path to which a DC voltage is applied without passing through the capacitor 8 during a period when the high frequency voltage is OFF.
この半導体スイッチ部7の切り替えの動作は、高周波電力の電圧の周期的なON/OFF或いは高出力と低出力との繰り返しに追従または同期して実施され繰り返される。この動作により、図7の例においてもESC電極と試料4との間の電位差の変動を抑制でき、静電吸着力の安定化とESC膜への過剰な電圧印加が抑制することができる。なお、本図の例においても、コンデンサ8の静電容量は図1,6の例と同様に、直流電源5に接続されるESC電極3と試料4との間のESC膜2を挟んだ静電容量と同程度のものを含み、ESC電極3と試料4間の静電容量の1/4〜4倍の範囲の値にされている。
The switching operation of the semiconductor switch section 7 is performed and repeated in accordance with periodic ON / OFF of high-frequency power voltage or repetition of high output and low output. With this operation, also in the example of FIG. 7, fluctuations in the potential difference between the ESC electrode and the sample 4 can be suppressed, and electrostatic attraction force can be stabilized and excessive voltage application to the ESC film can be suppressed. Also in the example of this figure, the electrostatic capacity of the capacitor 8 is the same as in the examples of FIGS. 1 and 6, and the static electricity sandwiching the ESC film 2 between the ESC electrode 3 connected to the DC power source 5 and the sample 4. The value is in the range of 1/4 to 4 times the capacitance between the ESC electrode 3 and the sample 4, including the same level as the capacitance.
以下に、図1に示した実施例の変形例を図8,9を用いて説明する。図8は、図1に示す実施例の変形例に係るプラズマ処理装置の試料台の構成の概略を模式的に示す縦断面図である。図9は、図8に示す変形例に係るプラズマ処理装置の高周波電源12から高周波の電圧が試料台800またはその基材部1に供給された場合の当該試料台800上部に配置された単極式のESC電極3の動作を表すタイミングチャートである。
A modification of the embodiment shown in FIG. 1 will be described below with reference to FIGS. FIG. 8 is a longitudinal sectional view schematically showing the outline of the configuration of the sample stage of the plasma processing apparatus according to the modification of the embodiment shown in FIG. FIG. 9 shows a single electrode disposed on the sample stage 800 when a high frequency voltage is supplied from the high frequency power source 12 of the plasma processing apparatus according to the modification shown in FIG. 4 is a timing chart showing the operation of the ESC electrode 3 of the equation.
図1、図6、図7で説明した実施例は、試料台100上面を構成する誘電体膜内に両極式のESC電極3を備えたものである。図8,9に示す例は、試料台100上面を構成する誘電体膜内に単極式のESC電極3を備えたものである。すなわち、図8の変形例ではESC電極3は試料4に対して単一の極性が付与されるものであり、これに直流電力を供給する直流電源5及びこの直流電源5とESC膜3との間を電気的に接続する給電経路並びにこの上に配置された低域通過フィルタ6及び半導体スイッチ部7或いはコンデンサ8は1つまたは複数の集合であって協働して当該同一の極性を与えるための動作をするものとなる。
The embodiment described with reference to FIGS. 1, 6, and 7 includes a bipolar ESC electrode 3 in a dielectric film constituting the upper surface of the sample stage 100. The examples shown in FIGS. 8 and 9 are provided with a monopolar ESC electrode 3 in a dielectric film constituting the upper surface of the sample stage 100. That is, in the modification of FIG. 8, the ESC electrode 3 has a single polarity with respect to the sample 4, and the DC power source 5 that supplies DC power to the sample 4 and the DC power source 5 and the ESC film 3 In order to provide the same polarity, the power supply path that electrically connects them, and the low-pass filter 6 and the semiconductor switch unit 7 or the capacitor 8 disposed on the power supply path cooperate with each other as one or a plurality of sets. It becomes the operation of.
本変形例に係る試料台800のこの他の構成は、図1に示した実施例と同等であって、高周波電源12から金属製の基材部1に供給される高周波電力の電圧も、所定の周波数の電圧が時間の経過に伴って周期的にON/OFFまたは振幅が大きな高出力と小さな低出力とを繰り返す時間変調(TM)をされる点も同様である。
The other configuration of the sample stage 800 according to this modification is the same as that of the embodiment shown in FIG. 1, and the voltage of the high-frequency power supplied from the high-frequency power source 12 to the metal substrate 1 is also predetermined. The same is true in that the voltage of the frequency is periodically ON / OFF with time, or time-modulated (TM) in which high output with a large amplitude and low output with a small amplitude are repeated.
図9に、図8に示す変形例に係る試料台800のESC膜3の動作の具体的な例を示す。本例においても、実施例と同様に、高周波電源12からの高周波電力の電圧がONとなる期間で高周波電圧検知部10の検知結果を用いてVppを検出し、この結果に基づいて直流電源5からESC膜3に供給される直流電力は高周波電力により試料4に生じるセルフバイアス電圧分だけ加または減じた値の直流電圧が供給される。
FIG. 9 shows a specific example of the operation of the ESC film 3 of the sample stage 800 according to the modification shown in FIG. Also in this example, Vpp is detected using the detection result of the high-frequency voltage detector 10 during the period when the voltage of the high-frequency power from the high-frequency power source 12 is ON, and the DC power source 5 is based on this result. The DC power supplied to the ESC film 3 is supplied with a DC voltage having a value that is increased or decreased by a self-bias voltage generated in the sample 4 by the high-frequency power.
より、具体的には、Vppが5000V、推定されるセルフバイアス電圧の定数が0.4の場合、高周波(RF)電力の電圧が供給される際に、直流電源5からESC電極3に供給する電圧を2000V負側に減じる(初期吸着電圧が−2000Vである場合には−4000Vにする)。この際、直流電力の給電経路の半導体スイッチ部7ではコンデンサ8を介さない給電経路であるA側に接続されている。
More specifically, when Vpp is 5000 V and the estimated self-bias voltage constant is 0.4, the DC power supply 5 supplies the ESC electrode 3 when a high frequency (RF) power voltage is supplied. The voltage is reduced to the negative side of 2000V (when the initial adsorption voltage is -2000V, it is set to -4000V). At this time, the semiconductor switch unit 7 in the DC power supply path is connected to the A side, which is a power supply path not passing through the capacitor 8.
次に、高周波電圧OFFの際には、半導体スイッチ部7は、ESC電極3と試料4との間の静電容量の1/4〜4倍の範囲にその静電容量が設定されたコンデンサ8を介し供給する経路となるB側に切り替える。このように、本変形例においても、セルフバイアス電圧の大きさに応じて直流電力の電圧値を加減するとともにTMによる高周波電力の周期的なON/OFFに同期または追従して給電経路を切り換える動作を繰り返すことで、単極方式においてもESC電極3と試料4間の電位差の変動が抑制され静電吸着力の安定化とESC膜2へ過剰な電圧が印加されることが抑制される。
Next, when the high-frequency voltage is OFF, the semiconductor switch unit 7 has the capacitor 8 whose capacitance is set in a range of 1/4 to 4 times the capacitance between the ESC electrode 3 and the sample 4. Switch to the B side, which is the route to supply via As described above, also in the present modification, the voltage value of the DC power is adjusted according to the magnitude of the self-bias voltage, and the power supply path is switched in synchronization with or following the periodic ON / OFF of the high-frequency power by the TM. By repeating the above, even in the unipolar method, the fluctuation of the potential difference between the ESC electrode 3 and the sample 4 is suppressed, the electrostatic attraction force is stabilized, and the excessive voltage is applied to the ESC film 2.
図10を用いて、図1に示した実施例の別の変形例を説明する。図10は、図1に示す実施例の別の変形例に係るプラズマ処理装置の試料台1000の構成の概略を模式的に示す縦断面図である。図11は、図10に示す変形例に係るプラズマ処理装置の高周波電源12から高周波の電圧が試料台1000またはその基材部1に供給された場合の当該試料台1000上部に配置された単極式のESC電極3の動作を表すタイミングチャートである。
Another modification of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 10 is a longitudinal sectional view schematically showing an outline of the configuration of the sample stage 1000 of the plasma processing apparatus according to another modification of the embodiment shown in FIG. 11 shows a single electrode disposed on the sample stage 1000 when a high-frequency voltage is supplied from the high-frequency power source 12 of the plasma processing apparatus according to the modification shown in FIG. 4 is a timing chart showing the operation of the ESC electrode 3 of the equation.
図1,6,7に示した実施例、及び図8,9に示した変形例では、半導体スイッチ部7においてESC電極3と試料4との間の電位差を制御するコンデンサ8は単一の静電容量を備えたものである。このため、半導体スイッチ部7においてB側に切り替えて直流電源5からの給電経路をコンデンサ8を介する経路にした場合での高周波電圧の変動を抑制することのできる高周波の周波数の範囲が相対的に小さいという課題が有った。
In the embodiment shown in FIGS. 1, 6, and 7 and the modification shown in FIGS. 8 and 9, the capacitor 8 that controls the potential difference between the ESC electrode 3 and the sample 4 in the semiconductor switch unit 7 is a single static. It has electric capacity. For this reason, the frequency range of the high frequency which can suppress the fluctuation | variation of the high frequency voltage in the case where it switches to the B side in the semiconductor switch part 7 and makes the electric power feeding path from the direct-current power supply 5 the path | route via the capacitor | condenser 8 is relatively. There was a problem of being small.
そこで、本例では半導体スイッチ部7に容量の異なる複数のコンデンサを並列に配置したコンデンサアレー17を具備し、高周波電圧検知部10の検知した結果を用いて検出した高周波電力のVppの値に応じて半導体スイッチによりコンデンサアレー17のうちの1つコンデンサを選択してこれを介した給電経路に切り替える構成を備えた。この構成により、TMにより周期的にON/OFFまたは高出力と低出力とが繰り返される高周波(RF)電力の供給に対応してこれに同期あるいは追従してESC膜3への直流電力の供給を増減して調節し吸着力安定化とESC膜3へ過剰な電圧が印加されることを抑制できる高周波電圧の適用範囲を拡大することが可能となる。
Therefore, in this example, the semiconductor switch unit 7 is provided with a capacitor array 17 in which a plurality of capacitors having different capacities are arranged in parallel, and according to the value of Vpp of the high-frequency power detected using the detection result of the high-frequency voltage detection unit 10. Thus, a configuration is provided in which one of the capacitors array 17 is selected by a semiconductor switch and switched to a power feeding path through the capacitor. With this configuration, the DC power is supplied to the ESC film 3 in synchronization with or following the supply of the high frequency (RF) power that is periodically turned ON / OFF by the TM or the high output and the low output. It is possible to expand the application range of the high-frequency voltage that can be adjusted by increasing / decreasing to stabilize the adsorption force and suppress the application of excessive voltage to the ESC film 3.
本例での図10のコンデンサアレー17の各コンデンサの値は、実施例1で説明したESC電極3と試料4との間のESC膜2を挟んだ静電容量の1/4〜4倍の範囲にされている。
In this example, the value of each capacitor of the capacitor array 17 of FIG. 10 is 1/4 to 4 times the electrostatic capacity sandwiching the ESC film 2 between the ESC electrode 3 and the sample 4 described in the first embodiment. Has been in range.
図11は、図10の変形例を単極式のESC電極を備えた試料台に適用したものの構成を示している。本例おける単極式のESC電極3においても、高周波電源12からの高周波電力のVppを高周波電圧検知部10の検知した結果を用いて検出し、この値に応じてコンデンサアレー17の適切なコンデンサを選択することで、時間変調された高周波電力が基材部1に供給される場合でも吸着力を安定化しESC膜3へ過剰な電圧が印加されることを抑制できる高周波電圧の適用範囲を拡大することができる。図10と同様に、コンデンサアレー8の各コンデンサの値は、実施例1で説明したESC電極3と試料4間の静電容量の1/4〜4倍の範囲とする。
FIG. 11 shows a configuration of the modification of FIG. 10 applied to a sample stage equipped with a monopolar ESC electrode. Also in the unipolar ESC electrode 3 in this example, the Vpp of the high frequency power from the high frequency power supply 12 is detected using the result detected by the high frequency voltage detection unit 10, and an appropriate capacitor of the capacitor array 17 is determined according to this value. By expanding the range of application of the high-frequency voltage that can stabilize the adsorption force and suppress the application of excessive voltage to the ESC film 3 even when time-modulated high-frequency power is supplied to the substrate 1. can do. Similarly to FIG. 10, the value of each capacitor of the capacitor array 8 is set to a range of ¼ to 4 times the capacitance between the ESC electrode 3 and the sample 4 described in the first embodiment.
本発明は、半導体装置の製造装置、特にリソグラフィー技術によって描かれたパタンをマスクに半導体材料のエッチング処理を行うプラズマエッチング装置に関する。通常プラズマエッチング装置は、被加工試料を被加工試料設置手段に静電吸着させることで、高精度な温度制御を行うことで加工精度を維持している。本発明は、この静電吸着に関する発明であり、被加工試料に印加する高周波電圧振幅が数kVと高く、かつその電圧印加を数十〜数kHzの周期でON/OFFするTM動作の場合に課題となる被加工試料の静電吸着力安定化と静電吸着膜への過剰電圧印加抑制を実現する。
The present invention relates to a semiconductor device manufacturing apparatus, and more particularly to a plasma etching apparatus that performs an etching process of a semiconductor material using a pattern drawn by a lithography technique as a mask. Usually, the plasma etching apparatus maintains the processing accuracy by performing high-accuracy temperature control by electrostatically adsorbing the processing sample to the processing sample setting means. The present invention relates to this electrostatic adsorption, and the high frequency voltage amplitude applied to the sample to be processed is as high as several kV, and in the TM operation in which the voltage application is turned ON / OFF at a period of several tens to several kHz. It is possible to stabilize the electrostatic attraction force of the workpiece to be processed and to suppress the application of excessive voltage to the electrostatic adsorption film.
1…基材部、2…ESC膜、3…ESC電極、4…試料、5…直流電源、6…低域通過フィルタ、7…半導体スイッチ部、8…コンデンサ、9…制御部、10…高周波電圧検知部、11…高周波整合器、12…高周波電源、13…冷媒流路、14…ガス供給路、15…制御部、16…プラズマ、17…コンデンサアレー。 DESCRIPTION OF SYMBOLS 1 ... Base material part, 2 ... ESC film | membrane, 3 ... ESC electrode, 4 ... Sample, 5 ... DC power supply, 6 ... Low-pass filter, 7 ... Semiconductor switch part, 8 ... Capacitor, 9 ... Control part, 10 ... High frequency Voltage detector, 11... High-frequency matching unit, 12... High-frequency power source, 13... Refrigerant path, 14.
Claims (6)
前記誘電体膜上に前記試料が保持された状態で前記試料台内電極に供給される前記高周波電力の前記出力の高低の繰り返しに合わせて、前記吸着用電極に供給される直流電源からの電力を各々で容量の異なる複数の給電経路の間で切り替える制御部とを備えたプラズマ処理装置。
A processing chamber that is disposed inside the vacuum vessel and in which plasma is formed inside, a sample table that is disposed in the processing chamber and on which a sample to be processed using the plasma is placed, and the sample on the sample table includes A dielectric film having a film-like adsorption electrode for generating an electrostatic force that constitutes a surface to be placed and adsorbs and holds the sample inside, and is disposed inside the sample stage and is in the process A sample stage electrode that is supplied with high-frequency power in which a high output and a low output are repeated at a predetermined frequency;
Power from a DC power source that is supplied to the adsorption electrode in accordance with repetition of the output of the high-frequency power that is supplied to the sample stage electrode while the sample is held on the dielectric film And a controller that switches between a plurality of power supply paths each having a different capacity.
前記吸着用電極は、複数の膜状の電極を備えて各々に異なる極性が付与されて前記試料を吸着する双極型の吸着用電極を構成し、
前記誘電体膜上に前記試料が保持された状態で前記試料台内電極に供給される前記高周波電力の前記出力の高低の繰り返しに合わせて、異なる極性が付与される前記双極型の吸着用電極の各々に供給される直流電源からの電力を前記複数の給電経路のうち容量が大きい給電経路と容量が小さい給電経路との間で各々逆に切り替える制御部とを備えたプラズマ処理装置。
The plasma processing apparatus according to claim 1,
The adsorption electrode comprises a plurality of film-like electrodes, each having a different polarity and constituting a bipolar adsorption electrode that adsorbs the sample,
The bipolar type adsorption electrode to which different polarities are given according to repetition of the output of the high-frequency power supplied to the electrode in the sample stage in a state where the sample is held on the dielectric film. And a control unit that reversely switches power from a DC power source supplied to each of the power supply paths having a large capacity and a power supply path having a small capacity among the plurality of power supply paths.
前記制御部は、前記高周波電力が高出力である期間においては、正の極性が付与された前記吸着用電極へ前記容量の小さい給電経路を通し、負の極性が付与された前記吸着用電極へ前記容量の大きい給電経路を通して前記電力を供給し、前記高周波電力が低出力である期間においては、正の極性が付与された前記吸着用電極へ前記容量の大きい給電経路を通し、負の極性が付与された前記吸着用電極へ前記容量の小さい給電経路を通して前記電力を供給するように前記給電経路を切り換えるプラズマ処理装置。
The plasma processing apparatus according to claim 2,
In the period when the high-frequency power is high output, the control unit passes the power feeding path with a small capacity to the adsorption electrode to which a positive polarity is given, and then supplies the adsorption electrode to which a negative polarity is given. The electric power is supplied through the large-capacity power supply path, and during the period when the high-frequency power is low output, the negative electrode has a negative polarity passing through the large-capacity power supply path to the adsorption electrode provided with a positive polarity. The plasma processing apparatus which switches the said electric power feeding path so that the said electric power may be supplied to the provided said electrode for adsorption | suction through the said electric power feeding path with a small capacity | capacitance.
前記給電経路を切り換えるスイッチ部が、各々異なる静電容量を備えたコンデンサが配置された複数の給電経路を前記高周波電力の電圧値に応じて選択して切り替えるプラズマ処理装置。
A plasma processing apparatus according to any one of claims 1 to 3,
The plasma processing apparatus, wherein the switch unit that switches the power supply path selects and switches a plurality of power supply paths in which capacitors each having a different capacitance are arranged according to the voltage value of the high-frequency power.
前記スイッチ部の前記複数のコンデンサの静電容量は前記誘電体膜を挟んだ前記吸着用電極と前記試料との間の静電容量の1/4乃至4倍の範囲にされたプラズマ処理装置。
The plasma processing apparatus according to any one of claims 1 to 4,
The plasma processing apparatus in which the capacitance of the plurality of capacitors in the switch unit is in a range of ¼ to four times the capacitance between the adsorption electrode and the sample with the dielectric film interposed therebetween.
前記高周波電力の電圧の最大値に応じて前記給電経路を選択するプラズマ処理装置。 The plasma processing apparatus according to claim 4 or 5, wherein
The plasma processing apparatus which selects the said electric power feeding path according to the maximum value of the voltage of the said high frequency electric power.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014253582A JP2016115818A (en) | 2014-12-16 | 2014-12-16 | Plasma processing apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014253582A JP2016115818A (en) | 2014-12-16 | 2014-12-16 | Plasma processing apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2016115818A true JP2016115818A (en) | 2016-06-23 |
Family
ID=56142243
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014253582A Pending JP2016115818A (en) | 2014-12-16 | 2014-12-16 | Plasma processing apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2016115818A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190112634A (en) * | 2018-03-26 | 2019-10-07 | 가부시키가이샤 히다치 하이테크놀로지즈 | Plasma processing apparatus |
CN110416116A (en) * | 2018-04-27 | 2019-11-05 | 东京毅力科创株式会社 | Etaching device and engraving method |
-
2014
- 2014-12-16 JP JP2014253582A patent/JP2016115818A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20190112634A (en) * | 2018-03-26 | 2019-10-07 | 가부시키가이샤 히다치 하이테크놀로지즈 | Plasma processing apparatus |
KR102150929B1 (en) * | 2018-03-26 | 2020-09-02 | 주식회사 히타치하이테크 | Plasma processing apparatus |
TWI709158B (en) * | 2018-03-26 | 2020-11-01 | 日商日立全球先端科技股份有限公司 | Plasma processing device |
CN110416116A (en) * | 2018-04-27 | 2019-11-05 | 东京毅力科创株式会社 | Etaching device and engraving method |
CN110416116B (en) * | 2018-04-27 | 2024-03-29 | 东京毅力科创株式会社 | Etching apparatus and etching method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR102545994B1 (en) | Control method and plasma treatment device | |
JP7455174B2 (en) | RF generator and method | |
TWI726258B (en) | Method and system for plasma processing and relevant non-transitory computer-readable medium | |
US9055661B2 (en) | Plasma processing apparatus | |
US9053908B2 (en) | Method and apparatus for controlling substrate DC-bias and ion energy and angular distribution during substrate etching | |
US10410902B2 (en) | Plasma processing apparatus | |
JP2020095793A (en) | Substrate processing apparatus and substrate processing method | |
US7153387B1 (en) | Plasma processing apparatus and method of plasma processing | |
KR20160102892A (en) | Plasma processing method and plasma processing apparatus | |
US20060037704A1 (en) | Plasma Processing apparatus and method | |
KR980012066A (en) | Plasma processing equipment | |
KR20140105467A (en) | Plasma-treatment apparatus | |
JP7000521B2 (en) | Plasma processing equipment and control method | |
KR102189323B1 (en) | Apparatus for treating substrate and method for treating apparatus | |
KR102191228B1 (en) | Plasma processing apparatus and plasma processing method | |
KR20240017919A (en) | Plasma uniformity control in pulsed DC plasma chambers | |
TWI815975B (en) | Apparatus and method to electrostatically remove foreign matter from substrate surfaces | |
JP2016115818A (en) | Plasma processing apparatus | |
CN105719930A (en) | Plasma etching method | |
JP2006100485A (en) | Branch switch for high frequency power and etching apparatus | |
JP2006339391A (en) | Dry-etching apparatus | |
KR20140112710A (en) | Inductively coupled plasma processing apparatus and plasma processing method using the same | |
JP2016096342A (en) | Plasma processing device | |
KR102724209B1 (en) | Plasma process system with synchronized signal modulation | |
JPS61166028A (en) | Dry etching equipment |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20170117 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20170124 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20170803 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20170804 |