JP2016114490A - Data collection device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a measurement wait time during a data transfer after the termination of integration while suppressing an increase in cost and improve the throughput of analysis.SOLUTION: Each time data is obtained by one session of measurement, a thirty-two times integration unit 10 adds this new data and data under integration that is read out from an internal RAM 121 and stores the sum in the same area of the RAM 121. This is repeated, and the data integrated thirty-two times is written into an inexpensive external memory DDR3-SDRAM 2. A parallel integration unit 13 reads out and adds two latest integration data stored in the external memory along with integration by the 32 times integration unit 10, and writes the sum into the memory. As integration data for 32×2=64 sessions of measurement is thereby stored in the external memory, the integration data is read out in a period when integration using the memory is not preformed and transfers the read data to a readout data processing unit. Thus, it is possible to perform data integration and integrated data transfer at the same time while suppressing a storage capacity of the expensive internal SRAM 121.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a data collection device that collects digital data obtained by an analysis device or the like and uses it for data processing. More specifically, the present invention relates to data collection for collecting and collecting data obtained in each of a plurality of repeated measurements. Relates to the device.

  In an analyzer such as a mass spectrometer, an analog detection signal obtained by a detector is sampled at a predetermined sampling time interval, and the sample value is converted into digital data in an analog / digital converter (hereinafter referred to as “ADC”). It is converted and input to the data processor. In recent analyzers, in many cases, the function of the data processing unit is achieved by executing dedicated data processing software (program) on a general-purpose personal computer.

  For example, a time-of-flight mass spectrometer (hereinafter referred to as “TOFMS”) usually has a low analysis sensitivity because the amount of ions analyzed by one ion flight operation is small. For this reason, the S / N ratio is improved by repeatedly measuring the same sample a plurality of times and integrating the time-of-flight spectrum data indicating the relationship between the time of flight and the ion intensity (signal intensity) obtained in each measurement. I am doing so. By converting the time of flight in the time-of-flight spectrum thus obtained into a mass-to-charge ratio, a mass spectrum indicating the relationship between the mass-to-charge ratio and the signal intensity can be obtained. For example, in the TOFMS described in Patent Document 1, the time-of-flight spectrum data obtained in each of a plurality of repeated measurements is integrated and supplied to a data processing unit and written into a memory.

A data acquisition circuit that integrates the time-of-flight spectrum data after being converted into a digital value by the ADC and transfers the data to the data processing unit generally performs a memory that temporarily stores the data being integrated and an addition process of the data And an adder. Since high-speed processing is required for the addition processing, the adder is configured by a hardware circuit such as an FPGA (Field Programmable Gate Array) and the memory is a general-purpose QDR (Quad Data Rate) SRAM or DDR (Double Data Rate) SDRAM is often used.
FIGS. 5A to 5C are diagrams showing a schematic configuration of a data acquisition circuit that performs integration processing, which is generally used in the past.

  FIG. 5A is a schematic configuration diagram of a data acquisition circuit using a QDR SRAM as a memory. The analog detection signal obtained by the TOFMS detector 41 is amplified by the amplifier 42, then sampled by the ADC 43, and converted into digital data for each sample. The FPGA 50 includes an ADC value fetching unit 51 and an adding unit 52, and a QDR SRAM 60 is connected to the FPGA 50. The ADC value fetching unit 51 reads the data output from the ADC 43 and sends it to the adding unit 52. The adder 52 receives the data from the ADC value take-in unit 51 and reads the accumulated data (data being accumulated) immediately before that stored in the QDR SRAM 60, adds both, and the QDR SRAM 60 is adding the data. Overwrite the data with the new data. By repeating such an addition operation a predetermined number of times, if integrated data obtained by adding a predetermined number of data is obtained, the data is transferred to a data processing unit (not shown).

  In the QDR SRAM, since the data read port and the write port are provided independently, the data read operation and the write operation can be executed in parallel. Therefore, there are few restrictions on control. Further, the idle time between the addition processes is not substantially required, and high-speed processing is possible, which is advantageous in increasing the measurement repetition rate. On the other hand, when the storage capacity is the same, the QDR SRAM is tens of times the price of the DDR SDRAM, which is a disadvantage in terms of cost.

FIG. 5B is a schematic configuration diagram of a data collection circuit using a DDR SDRAM as a memory. The same components as those in FIG. 5A are denoted by the same reference numerals.
Since the DDR SDRAM needs to be controlled by a command, the DDR controller 53 is built in the FPGA 50, and data is read from and written to the DDR SDRAM 61 via the DDR controller 53. Since the DDR SDRAM is much cheaper than the QDR SRAM, the advantage of the configuration shown in FIG. 5B is an overwhelmingly low cost. On the other hand, since the read operation and the write operation cannot be executed in parallel in the DDR SDRAM, the addition process and the data take-in cannot be performed by the pipeline process. Further, since the access is also slow, an idle time is required between the addition process and the next addition process, which makes it difficult to increase the measurement repetition rate.

  FIG. 5C is a schematic configuration diagram of a data collection circuit using an internal SRAM 54 built in the FPGA 50 without using a general-purpose memory. In this configuration, access to the memory via the external wiring is unnecessary, and control is easy. However, since the internal SRAM is built in the FPGA, the FPGA becomes large and the cost is the highest.

  In any of the above configurations, it is necessary to read out the data stored in the memory after completion of the predetermined number of integration processes and transfer it to the data processing unit or the like. Since a new integration process using can not be performed, a measurement waiting time occurs. Therefore, there is a common problem that the measurement takes extra time for the waiting time and the analysis throughput is reduced.

JP 2008-70122 A (paragraph [0035] etc.) JP 2010-19655 A

  The present invention has been made to solve the above-mentioned problems, and its main object is to reduce the cost as much as possible and to solve the problem common to the conventional configuration in which a waiting time for measurement occurs at the time of data transfer after the integration is completed. It is an object of the present invention to provide a data collection device that can solve the problem and improve the throughput of analysis.

In order to solve the above problems, the present invention collects measurement data by repeatedly performing an operation of accumulating data respectively obtained by a predetermined number of repeated measurements to obtain one measurement data. In the data collection device,
a) a first memory for temporarily storing data during integration;
b) Reading data in the middle of accumulation stored in the first memory, adding the data and newly obtained data for one measurement, and obtaining the obtained data as the first data A first addition unit that acquires data accumulated N times (N is an integer of 2 or more) by repeating the operation of writing to the memory of
c) a second memory for storing data after being multiplied N times by the first memory and the first adder;
d) The data stored in the second memory that has been integrated N times and the data that has been stored N times or the data that has been integrated N times immediately before are stored M−1 times (M is 2). By repeating the operation of reading out the integrated data) and adding the data together and writing the added data in the second memory M times (M is an integer of 2 or more), N A second adder for acquiring data accumulated × M times;
e) a data transfer unit that reads the data accumulated in N × M times stored in the second memory and transfers the data to the outside;
DDR SDRAM is used as the second memory, and the first memory, the first adder, the second adder, and the data transfer unit are included in a one-chip integrated circuit. It is characterized by that.

  As a typical aspect of the data collection device according to the present invention, the one-chip integrated circuit may be a field programmable gate array (FPGA). Further, an SRAM included in the FPGA may be used as the first memory.

  In the data collection device according to the present invention, for example, an analog obtained every moment by a detector such as a liquid chromatograph-ion trap time-of-flight mass spectrometer (LC-IT-TOFMS) disclosed in Patent Document 2 or the like. Digital data obtained by converting the detection signal by an analog / digital converter is input. In TOFMS, spectrum data (time-of-flight spectrum data) over a predetermined time-of-flight range corresponding to a predetermined mass-to-charge ratio range is obtained by one measurement, and this data is integrated. That is, the ion intensity is integrated for each flight time on the flight time spectrum.

  The integration of N times for the data input from the analog / digital converter is performed by the first adder and the first memory. That is, when data for one measurement is newly input, the first addition unit reads out the data in the middle of accumulation stored in the first memory, adds the new data to the data, The added data is written in the same storage area as the data being accumulated on the first memory. In other words, the data is overwritten. By repeating this N times, data accumulation for N times is performed. In the initial state of N integrations, the value of data stored in the first memory during integration may be reset to zero.

  Each time data is accumulated N times by the first adder and the first memory, the accumulated data is written to the second memory. Each time the N data integration is performed, the second adder performs integration of the data accumulated N times stored in the second memory, and obtains the obtained integrated value as a second value. Write to memory. In the case where M = 3 or more accumulations are executed by the second adder and the second memory, one data added in the second adder is already accumulated M−1 times in the adder. Data. As a result, the integrated value of the data for N × M times is stored in the second memory. Then, after performing M times of integration in the second addition unit, the data transfer unit reads the data accumulated N × M times stored in the second memory as measurement data, for example, to the data processing unit And forward. The integration by the second addition unit and the second memory is performed in parallel with the N integrations by the first addition unit and the first memory.

  Since both the first memory and the first adder are included in a one-chip integrated circuit, the integration by the first adder and the first memory performs access to the second memory at all. It is carried out without. On the other hand, since the second memory is a DDR SDRAM different from the integrated circuit, it takes more time than the integration using the first memory, but the time required for accessing the second memory for that is the first. This is a part of a period in which N times of accumulation by one adder and the first memory are executed. Therefore, in a part of the period in which the N additions are performed by the first addition unit and the first memory, the second memory accesses the data for adding the data already integrated N times. However, it is possible to freely read and transfer data from the second memory during the period other than that.

  Thereby, in the data collection device according to the present invention, it is possible to continue reading the data from the analog / digital converter, that is, to continue the measurement even when transferring the accumulated data to the data processing unit or the like. There is no need to provide a measurement waiting time. Further, by using the SRAM as the first memory, the idle time during the addition processing by the first addition unit is not necessary, and the measurement repetition rate can be increased. Furthermore, since the memory provided outside the integrated circuit may be an inexpensive general-purpose DDR SDRAM, the cost can be sufficiently reduced.

  In the data collection device according to the present invention, the result of integration is overwritten on the data before integration in the first memory, so that the required storage capacity of the memory does not increase even if the number of integrations is increased. On the other hand, the required storage capacity of the first memory increases as the amount of data to be integrated increases. In particular, since the increase in the storage capacity of the first memory included in the integrated circuit is a major factor in increasing the cost, it is desirable that the amount of data to be integrated is small in order to reduce the cost. Therefore, the data collection apparatus according to the present invention is suitable for an analysis apparatus in which the amount of data obtained by one measurement is relatively small and a large number of times of integration are required to obtain one measurement data. is there. In this respect, the above-described TOFMS (for example, LC-IT-TOFMS) can be said to be an analysis apparatus suitable for the present invention.

  According to the data collection device of the present invention, it is not necessary to provide an idle time between the addition process and the next addition process or a time for transferring the accumulated data, so that a waiting time for measurement is substantially provided. There is no need. In addition, although a low-speed DDR SDRAM is used for a part of integration, it is not necessary to reduce the measurement repetition rate accordingly, and repeated measurement can be performed at high speed and without waiting time for measurement. Therefore, the analysis throughput can be improved. Further, since the storage capacity of an internal memory provided in an integrated circuit such as an FPGA can be suppressed, and an inexpensive DDR SDRAM can be used instead, the cost can be sufficiently reduced.

1 is a block configuration diagram of a data collection device according to an embodiment of the present invention. The conceptual diagram of the integration process in the data collection device of a present Example. The timing diagram of the process in the data collection device of a present Example. The conceptual diagram which shows the memory area | region of DDR3-SDRAM in FIG. The figure which shows schematic structure of the data collection circuit which performs the integration process conventionally common.

Hereinafter, an embodiment of a data collection device according to the present invention will be described with reference to the accompanying drawings.
1 is a block diagram of a data collection device according to the present embodiment, FIG. 2 is a conceptual diagram of integration processing in the data collection device of the present embodiment, FIG. 3 is a timing diagram of processing in the data collection device of the present embodiment, and FIG. FIG. 2 is a conceptual diagram showing a memory area of a DDR3-SDRAM in FIG. 1;

  In the data collection device of this embodiment, an analog detection signal obtained by a detector of a liquid chromatograph-ion trap time-of-flight mass spectrometer (LC-IT-TOFMS) (not shown) is input to the ADC 43, and a digital value is obtained by the ADC 43. The data (AD value) converted into is input to the FPGA 1. A DDR3-SDRAM 2 is connected to the FPGA 1 as an external memory. The FPGA 1 has a functional block including an ADC value fetching unit 10, a 32-times accumulating unit 11, an I / F buffer unit 12 including an internal SRAM 121, a data transfer unit 122, a parallel accumulating unit 13, and a DDR controller 14. Include as.

A data collection operation accompanied by an integration process in the data collection apparatus of this embodiment will be schematically described with reference to FIGS. This is an example of the operation when N = 32 and M = 2 in the data collection device according to the present invention.
In LC-IT-TOFMS (not shown), a time-of-flight spectrum as shown in FIG. 2 is formed by one measurement (measurement of ion intensity in a predetermined time-of-flight range by TOFMS for one ion ejection from the ion trap). Data to be obtained. By repeating the measurement, time-of-flight spectrum data in a predetermined time range is obtained one after another, and such data is sequentially input to the ADC value capturing unit 10 of the FPGA 1.

  Every time one measurement is performed, the 32 times accumulating unit 11 in the FPGA 1 uses the internal SRAM 121 to perform an operation of adding the sequentially applied flight time spectrum data for each flight time, and continuously N = 32 Repeat for one measurement (for example, “1-32 # 1” in FIG. 3A). As a result, data obtained by integrating the time-of-flight spectrum data obtained by 32 measurements is obtained. Specifically, when receiving the new time-of-flight spectrum data for one measurement, the 32-times accumulating unit 11 reads out data in the middle of accumulation (data being accumulated less than 31 times) from a predetermined storage area of the internal SRAM 121, Data obtained by adding the ion intensity for each flight time is written in the predetermined storage area of the internal SRAM 121. Thereby, the data in the middle of integration is overwritten and the value is updated. By repeating this 32 times, accumulated data for 32 consecutive measurements can be obtained.

  Each time the accumulated data for 32 times is obtained, the data is written into a predetermined storage area of the external DDR3-SDRAM 2 via the DDR controller 14 (see FIG. 3C). On the other hand, in parallel with the writing of data to the DDR3-SDRAM 2, a predetermined storage area of the internal SRAM 121 is cleared. As a result, the 32-times integration unit 11 can integrate data for the next 32 consecutive measurements in cooperation with the internal SRAM 121.

  Similarly, when the time-of-flight spectrum data is integrated for the next 32 consecutive measurements (for example, “33-64 # 1” in FIG. 3B), the data is transmitted via the DDR controller 14. The data is written in a storage area different from the predetermined storage area of the DDR3-SDRAM 2. The 32-time integration unit 11 and the internal SRAM 121 continue to perform data integration for the next 32 consecutive measurements (for example, “1-32 # 2” in FIG. 3B). The parallel accumulator 13 sends two 32-times accumulated data (“1-32 # 1” continuous measurement data and “33-64 # 1” continuous measurement from the DDR3-SDRAM 2 via the DDR controller 14. Integrated data for the two measurements, and by adding the ion intensity for each flight time for these two data, the integrated data for 64 measurements is calculated. Then, the integrated data is written into yet another storage area of DDR3-SDRAM2.

  Unlike the internal SRAM 121, it takes time to read and write data in the DDR3-SDRAM 2. Therefore, as described later, the accumulated data is read from the DDR3-SDRAM 2 and then the accumulated data is written up to 10 times. It takes a time corresponding to the measurement (see FIG. 3D). Even so, the time corresponding to 10 measurements out of the period corresponding to 32 consecutive measurements may be used for data integration using the DDR3-SDRAM 2, which corresponds to the remaining 22 consecutive measurements. Is available for accessing the DDR3-SDRAM 2. Therefore, during this period, the data transfer unit 122 reads the accumulated data for the 64 measurements from the DDR3-SDRAM 2 and transfers this to the data processing unit embodied by, for example, a personal computer (see FIG. 3E). ).

  As described above, in the data collection device of the present embodiment, by performing the data integration by the 32-time integration unit 11 and the internal SRAM 121 and the data integration by the parallel integration unit 13 and the DDR3-SDRAM 2 in parallel, Integration data for 64 consecutive measurements can be obtained during a period of 64 measurements, and the integration data can be transferred to the data processing unit during a sufficiently long period.

Next, a configuration example assuming a more specific element in the data collection device of the present embodiment will be described.
In order to achieve high mass resolution in TOFMS, it is necessary to increase the sampling frequency in the ADC 43. Therefore, as the ADC 43, an element having a bit number of 10 bits and a sampling frequency of 5 GHz is used. Further, the system clock frequency of the FPGA 1 is set to 250 MHz. The DDR SDRAM 2 uses four DDR3-SDRAMs that support 800 MHz and have a storage capacity of 1 Gbits, a data bit width of 64 bits, a burst length (BL) of 128 (1024 addresses), and the time required for one measurement. It is assumed that it is 100 μsec. Further, as described above, the number of integrations N by memory access in the FPGA 1 is 32, the number of integrations M by access to the DDR SDRAM 2 is 2, and the total number of integrations is 32 × 2 = 64. Considering that the number of integrations by memory access in the FPGA 1 is 32 times, if a margin of a bit length of 5 bits per sample is secured, the memory capacity in the FPGA 1 necessary for integration, that is, the storage capacity of the internal SRAM 121 is [Sampling frequency] × [time required for measurement] × [bit length] = (5 × 10 ⁹ ) × (100 × 10 ⁻⁶ ) × (10 + 5) = 7.5 × 10 ⁶ = 7.5 [Mbits] Can be calculated.

  Since the sampling frequency of the ADC 43 is 5 GHz and the system clock frequency of the FPGA 1 is 250 MHz, a parallel memory width of 5G / 250M = 20 or more is required to capture the data converted by the ADC 43 into the internal SRAM 121 of the FPGA 1. Since the number of bits of one sample is 10 bits, a memory width of 20 × 10 = 200 [bits] or more is necessary. However, if a margin of 5 bits per sample is expected as described above, a memory width of 20 × (10 + 5) = 300 [bits] or more is required. As is well known, a power of 2 is desirable for facilitating the memory configuration. Therefore, here, each bit width is 16 bits in 32 parallels. Therefore, the internal SRAM 121 has a memory capacity of 8 Mbits. The access rate of the internal SRAM 121 is 16 × 5G = 80 [Gbps].

  When the burst length of the DDR3-SDRAM 2 is 128, the effective access efficiency is generally about 85% when an FPGA IP (Intellectual Property) core is used with default settings. Therefore, the effective access efficiency is estimated to be 80% in consideration of the maximum margin. Access to the DDR3-SDRAM 2 is a total of three times of reading the current value, reading the previous value, and writing the result of adding the previous value and the current value in one integration process. When the effective access efficiency is 80% as described above, the effective access rate of the DDR3-SDRAM 2 is a double rate and a data bit width of 64 bits, so that 800M [Hz] × 2 × 64 × 0.8 = 81.9 [Gbps].

  When integration is performed using the internal SRAM 121, since the SRAM is a dual port, the write operation and the read operation can be performed at the same time, and the processing delay (latency) is very small. The integration process can be performed almost simultaneously. On the other hand, in the case of integration using the external DDR3-SDRAM 2, the write operation and the read operation cannot be performed at the same time, and the data read operation from the address area that has been subjected to the 32nd integration process, 3 times as long as the data read operation and the data write operation to the all integration processed address areas after integration in the parallel integration unit 13 of the FPGA 1 are required. In addition, since each has a long latency, a longer processing time is actually required.

  For this reason, the time required for the integration process by accessing the DDR3-SDRAM 2 needs to be about four times the time required for the integration process by accessing the internal SRAM 121. Further, the integration by accessing the DDR3-SDRAM 2 is effective when it is desired to increase the total number of times of integration, and it is assumed that it is necessary to increase the number of times of integration especially when the ion intensity in one measurement is low. The Therefore, when trying to cope with the increase in the number of integrations, it is more controllable to read / write with 1 address 2 data (1 data is a maximum of 32 bits) rather than 1 address 4 data (1 data is a maximum of 16 bits). Easy. For this reason, it is considered that the time required for the integration process by accessing the DDR3-SDRAM 2 is about eight times the time required for the integration process by accessing the internal SRAM 121. In view of this, here, it is assumed that the time required for the integration process by accessing the DDR3-SDRAM 2 will be up to 10 times the time required for the integration process by accessing the internal SRAM 121.

  Even under such assumptions, in the data collection device of the present embodiment, as described above, 22 measurement periods out of 32 measurement periods that are vacant without being subjected to integration processing in the DDR3-SDRAM 2. The total accumulated data may be read out from the DDR3-SDRAM 2 and transferred.

  FIG. 4 is a conceptual diagram showing a memory area of DDR3-SDRAM 2 used for the integration operation as described above. FIG. 4 shows a memory area of one memory of 1 Gbits, and there are four memory areas. As described above, if the memory width is 64 bits, a 16M address area is formed in the vertical direction of one memory. Of these, the 4M address area is used as a temporary storage area for data obtained by accumulating data for 32 measurements. As described above, the address area for storing the data obtained by the 32 times accumulation using the internal SRAM 121 stores 4 data at 1 address, while storing the data obtained by further accumulating the 32 times accumulated value. The address area to be stored is one address and two data are stored, and the address area is assigned to correspond to this.

  Of course, the above-described method of using the memory is merely an example, and it is needless to say that data collection with the integration processing as described above can be realized by any other appropriate method.

  Moreover, the said Example is an example of this invention, and it is clear that even if it changes suitably, amends, and is added within the meaning of this invention, it is included by the claim of this application.

  For example, in the above embodiment, N = 32 and M = 2, but this can be any value of 2 or more. However, as is clear from the above description, the smaller the number of N, the shorter the time margin for transferring accumulated data stored in the DDR3-SDARM, and N is a certain value (the above example) If it is smaller than about 10), one data integration using DDR3-SDARM may not be completed during one cycle of data integration using the internal SRAM. In that case, since it is necessary to provide a waiting time for measurement, it is substantially meaningless to set N to a certain value or less.

1 ... FPGA
DESCRIPTION OF SYMBOLS 10 ... ADC value taking-in part 11 ... 32 times accumulation part 12 ... I / F buffer part 13 ... Parallel accumulation part 14 ... DDR controller 2 ... DDR3-SDRAM
43. Analog / digital converter

Claims (2)

In a data collection device that collects measurement data by repeatedly performing an operation of accumulating data obtained by repeated measurement of a predetermined number of times and acquiring one measurement data,
a) a first memory for temporarily storing data during integration;
b) Reading data in the middle of accumulation stored in the first memory, adding the data and newly obtained data for one measurement, and obtaining the obtained data as the first data A first addition unit that acquires data accumulated N times (N is an integer of 2 or more) by repeating the operation of writing to the memory of
c) a second memory for storing data after being multiplied N times by the first memory and the first adder;
d) The data stored in the second memory that has been integrated N times and the data that has been stored N times or the data that has been integrated N times immediately before are stored M−1 times (M is 2). By repeating the operation of reading out the integrated data) and adding the data together and writing the added data in the second memory M times (M is an integer of 2 or more), N A second adder for acquiring data accumulated × M times;
e) a data transfer unit that reads the data accumulated in N × M times stored in the second memory and transfers the data to the outside;
DDR SDRAM is used as the second memory, and the first memory, the first adder, the second adder, and the data transfer unit are included in a one-chip integrated circuit. A data collection device characterized by that. The data collection device according to claim 1,
The data collecting apparatus according to claim 1, wherein the one-chip integrated circuit is a field programmable gate array (FPGA).

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