JP2016101044A - Control method for 5-level power converter and 5-level power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a 5-level power converter capable of achieving long service life of a switching device by suppressing generation of switching loss, high efficiency of a power converter, miniaturization of an apparatus and cost reduction.SOLUTION: The 5-level power converter reduces the number of switching devices performing a switching operation when transiting to each output voltage level by forming positive-negative symmetry for a switching device making a gate-on/gate-off with an output voltage kept at a positive/negative polarity, thereby reducing the number of switching operations for suppression of switching loss.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for controlling a five-level power converter for high voltage and large capacity.

  FIG. 1 shows a circuit configuration of the three-phase five-level power conversion device disclosed in Patent Document 1, and FIG. 2 shows a circuit configuration only for the single phase. As shown in FIGS. 1 and 2, the three-phase five-level power converter includes DC voltage sources DCC1 and DCC2, flying capacitors FC1 and FC2, and first to tenth switching devices SW1 to SW10. In FIG. 1, the flying capacitors FC1 and FC2 are shared by the U phase, the V phase, and the W phase.

  In FIG. 2, the potentials of the input sections are P, FCp +, FCp−, NP, FCn +, FCn−, N, and the output terminal is O. The voltage between the terminals (P)-(NP), (NP)-(N) is 2E, and the voltage between the terminals of (FCp +)-(FCp-), (FCn +)-(FCn-) is E. The switching pattern shown in Patent Document 1 is shown in Table 1. In Table 1, 1 to S2 in the 0 / SW row indicate the first to tenth switching devices and the first and second common switches, and + 2E to -2E in the 0 / SW column denote DC voltage sources. The voltage between the common connection point NP of DCC1 and DCC2 and the output terminal is shown.

  In Table 1, 1 indicates the gate-on state of the switching device, and 0 indicates the gate-off state. The part surrounded by ○ is the switching transition part.

Japanese Patent Application No. 2013-132261 Japanese Patent Application No. 2014-100054

  Patent Document 1 shows a five-level switching pattern. However, in Patent Document 1, there are many switching devices that perform switching (conversion from 0 → 1 or 1 → 0) when transitioning to each output voltage level. In the switching pattern in which the output voltage is selected as + O, the switching devices in the gate-on state and the gate-off state are not positive and negative symmetric, so that the number of switching is particularly large when the output voltage transitions from + O to -E. An increase in the number of switching leads to an increase in switching loss. This is not preferable because the efficiency of the power conversion device is reduced and the cooling function is increased, that is, the device is increased in size and cost.

  In addition, a DC short circuit may occur due to variations in switching device characteristics and gate drive circuit characteristics. In general, in order to prevent a DC short-circuit, a dead time is provided in the gate-on signal, but Patent Document 1 does not suggest the dead time.

  In the case of Table 1, when the switching pattern + 2E transitions to + E, a DC short circuit occurs when a period in which the switching devices SW1 and SW4 are simultaneously turned on occurs without providing a dead time. Similarly, when the switching pattern -E transitions from -E to -2E, a DC short circuit occurs when a period in which the switching devices SW7 and SW8 are simultaneously turned on without a dead time is generated.

  Due to the occurrence of a DC short circuit, an overcurrent flows through the switching device, reducing the reliability of the device. Therefore, it is desirable to provide a dead time.

  As described above, in the five-level power converter, it is an object to reduce switching loss, improve the life of the switching device, improve the efficiency of the power converter, reduce the size of the device, and reduce the cost. Become.

  The present invention has been devised in view of the above-described conventional problems, and one aspect thereof is that each of the two DC voltage sources connected in series has one end connected to the negative electrode end of the upper DC voltage source. A first common switch common to each phase, a second common switch common to each phase, one end of which is connected to the positive terminal of the lower DC voltage source among the two DC voltage sources connected in series, and a first common switch A common first flying capacitor having one end connected to the other end, a second flying capacitor common to each phase having one end connected to the other end of the second common switch, and a positive terminal of the upper DC voltage source A first switching device, a second switching device, and a third switching device of each phase sequentially connected in series between the first switching device and the other end of the first common switch, and a common connection point of the first switching device and the second switching device First A fourth switching device of each phase interposed between the other end of the flying capacitor and each phase sequentially connected in series between the other end of the second common switch and the negative end of the lower DC voltage source. The fifth switching device, the sixth switching device, the seventh switching device, and the eighth of each phase interposed between the common connection point of the sixth switching device and the seventh switching device and the other end of the second flying capacitor. One end is connected to the common connection point of the switching device, the ninth switching device of each phase whose one end is connected to the common connection point of the second switching device and the third switching device, and the fifth switching device and the sixth switching device. A tenth switching device of each phase, and the other end of the ninth switching device of each phase and the first A control method for a five-level power converter using an output terminal as a common connection point to which the other end of the switching device is connected, the voltage between the common connection point of the upper DC voltage source and the lower DC voltage source and the output terminal Is controlled by the switching pattern in the rows 2E, E, 1E, and -2E in Table 2 and at least one of the switching patterns in the ± 0a and ± 0b rows in Table 3. To do.

However, 1 in the table indicates a gate-on state and 0 indicates a gate-off state. * Indicates that either is possible.

  Further, as one aspect thereof, the voltage between the common connection point of the upper DC voltage source and the lower DC voltage source and the output terminal is represented by a switching pattern in rows 2E, E, 1E, and -2E in Table 2. Control is performed by switching patterns in the rows of ± 0a and ± 0b in Table 3.

  As one aspect thereof, a dead time is provided between the gate-on signal of the first switching device and the gate-on signal of the second switching device, and a dead time is provided between the gate-on signal of the seventh switching device and the gate-on signal of the eighth switching device. It is characterized by that.

  Moreover, as one aspect thereof, a part or all of the first to tenth switching devices are set to have a series number of 2 or more.

  Another aspect is characterized in that a part or all of the first to tenth switching devices are parallel number 2 or more.

  According to the present invention, in the five-level power conversion device, it is possible to reduce the switching loss, improve the life of the switching device, improve the efficiency of the power conversion device, reduce the size of the device, and reduce the cost.

The circuit block diagram which shows the three-phase 5 level power converter device in embodiment. The figure which shows the circuit of only one phase of 5 level power converter device. The time chart which shows the gate-on signal of a switching device.

Since the present invention relates to the switching pattern of the circuit configuration disclosed in Patent Document 1, the main circuit configuration is the same as that shown in FIGS. Although the voltage state that can be output in FIG. 2 is five levels, the switching pattern is not limited to five shown in Table 1. This is because there are a plurality of switching patterns that uniquely output the output voltage = 0 (that is, the NP terminal and the O terminal have the same potential). That is, the selection of the switching pattern can be freely designed according to the idea. Here, the switching pattern design concept in the first and second embodiments is shown below.

  [Minimize the number of switching times] and [Make switching devices that are gate-on / gate-off symmetric with respect to the output voltage positive / negative].

  Embodiments 1 and 2 of a five-level power converter according to the present invention will be described in detail below with reference to FIGS.

[Embodiment 1]
First, the circuit configuration of the five-level power converter according to the first embodiment will be described with reference to FIGS.

  One end of the first common switch S1 common to each phase is connected to the negative terminal of the upper DC voltage source DCC1 among the two DC voltage sources DCC1 and DCC2 connected in series. Also, one end of the second common switch S2 common to each phase is connected to the positive terminal of the lower DC voltage source DCC2 among the two DC voltage sources DCC1 and DCC2 connected in series.

  One end of the first flying capacitor FC1 common to each phase is connected to the other end of the first common switch S1, and one end of the second flying capacitor FC2 common to each phase is connected to the other end of the second common switch S2.

  The first switching device SWu1, the second switching device SWu2, and the third switching device SWu3 (SWu3a, SWu3b) of each phase are sequentially connected in series between the positive electrode end of the upper DC voltage source DCC1 and the other end of the first common switch S1. Connected.

  A fourth switching device SWu4 of each phase is interposed between the common connection point of the first switching device SWu1 and the second switching device SWu2 and the other end of the first flying capacitor FC1.

  A fifth switching device SWu5 (SW5a, SW5b), a sixth switching device SWu6, and a seventh switching device SWu7 are sequentially connected in series between the other end of the second common switch S2 and the negative end of the lower DC voltage source DCC2. .

  An eighth switching device SWu8 of each phase is interposed between a common connection point of the sixth switching device SWu6 and the seventh switching device SWu7 and the other end of the second flying capacitor FC2.

  One end of the ninth switching device SWu9 (SW9a, SW9b) is connected to a common connection point of the second switching device SWu2 and the third switching device SWu3. One end of each phase of the tenth switching device SW10 (SW10a, SW10b) is connected to a common connection point of the fifth switching device SWu5 and the sixth switching device SWu6.

  The common connection point where the other end of the ninth switching device SWu9 (SW9b) of each phase and the other end of the tenth switching device SWu10 (SW10b) are connected is defined as an output terminal O. Although only the U phase has been described, the V phase and the W phase are similarly configured.

  Table 2 shows a list of switching patterns that can output voltage. 1 to S2 shown in the 0 / SW row and + 2E to -2E shown in the 0 / SW column are the same as those in Table 1. Compared with Table 1, “± 0” was set in the switching pattern of the output voltage = 0. In addition, since there is a switching device that does not affect the voltage output, it is indicated by * in the table. In Table 1, the switching device that turns on / off the gate depending on whether the output voltage is positive or negative is asymmetrical. However, in the switching pattern of Table 2, the switching device that turns on / off the gate depending on the positive / negative of the output voltage.

However, 1 in the table indicates a gate-on state and 0 indicates a gate-off state. * Indicates that either is possible.

  “± 0”: There are two types of switching patterns. Table 3 shows two types of switching patterns (± 0a, ± 0b). 1 to S2 shown in the 0 / SW row and + 2E to -2E shown in the 0 / SW column are the same as those in Table 1.

  ± 0a is a switching pattern in which the third and fifth switching devices SW3a, SW3b, SW5a, and SW5b are turned on in FIG. If the polarity of the output current Io of the five-level power converter is positive (in the direction of the arrow in FIG. 2), the output current flows through a route of NP → S2 → SW5a → SW5b → SW10a → SW10b → O. It has the same potential as NP. If the polarity of the output current Io is negative (in the direction opposite to the arrow in FIG. 2), the output current flows through the route of O → SW9b → SW9a → SW3a → SW3b → S1 → NP, and the terminal O has the same potential as the terminal NP. Become.

  ± 0b is a switching pattern in which the switching devices SW3a, SW3b, SW5a, and SW5b are gated off. In this case, the output current Io flows through the antiparallel diodes of the switching devices SW3a, SW3b, SW5a, SW5b. If the polarity of the output current Io of the five-level power converter is positive (in the direction of the arrow in FIG. 2), the output current flows through the route of NP → S1 → SW3b → SW3a → SW9a → SW9b → O, and terminal O is the terminal It has the same potential as NP. If the polarity of the output current Io is negative (in the direction opposite to the arrow in FIG. 2), the output current flows through the route of O → SW10b → SW10a → SW5b → SW5a → S2 → NP, and the terminal O has the same potential as the terminal NP. Become.

  As described above, the terminal O has the same potential as the terminal NP and can output a zero voltage regardless of which of the switching patterns ± 0a and ± 0b is selected.

  Next, Table 4 shows that the number of switching devices that perform switching is minimized by applying a switching pattern of ± 0b. 1 to S2 shown in the 0 / SW row and + 2E to -2E shown in the 0 / SW column are the same as those in Table 1. Further, in ± 0b in Table 4, SW4 = 1 and SW8 = 1.

  As shown in Table 4, the switching pattern in which the gate is turned on / off when the output voltage is positive / negative is symmetrical. That is, when the output voltage is + 2E, the first, second, eighth, and ninth switching devices SW1, SW2, SW8, SW9a, SW9b, and the first and second common switches S1, S2 are turned on. When the output voltage is -2E, the fourth, sixth, seventh, and tenth switching devices SW4, SW6, SW7, SW10a, SW10b, and the first and second common switches S1 and S2 are symmetrical with the switching device. The gate is on.

  On the other hand, when the output voltage is + E, the second, fourth, eighth and ninth switching devices SW2, SW4, SW8, SW9a and SW9b, and the first and second common switches S1 and S2 are turned on. When the output voltage is -E, the fourth, sixth, eighth, and tenth switching devices SW4, SW6, SW8, SW10a, SW10b, and the first and second common switches S1 and S2 are symmetric with respect to the switching device. The gate is on.

  Even when the output voltage is ± 0b, the fourth and ninth switching devices SW4, SW9a, SW9b, the first common switch S1, and the eighth and tenth switching devices SW8, SW10a, SW10b, which are symmetrical with the switching device, are provided. The second common switch S2 is turned on.

  Thus, since the switching devices that are gate-on / gate-off when the output voltage is ± 0b are positive and negative symmetric, the number of switching devices that switch when the output voltage transitions to + E and −E is reduced. can do.

  Compared to Table 1, Table 4 has fewer places surrounded by circles. By applying the switching pattern in Table 4, the number of switching devices that perform switching is reduced as compared with the conventional switching pattern in Table 1.

  As described above, according to the first embodiment, when the output voltage transitions to each level, the number of switching devices that perform switching is reduced, so that the total number of switching is reduced, and the switching loss of the switching device is reduced. Reduce. Moreover, since the switching loss of a switching device reduces, the temperature rise of a switching device is suppressed and the lifetime of a switching device is extended.

  Moreover, since the switching loss of a switching device reduces, the efficiency of a power converter device can be raised. In addition, since the switching loss of the switching device is reduced, the cooling mechanism of the power conversion device can be reduced, and the overall size of the device can be reduced.

  Furthermore, since the whole apparatus can be reduced in size, cost can be reduced.

[Embodiment 2]
FIG. 3 is a time chart showing gate-on signals of the switching devices SW1 and SW4. In the second embodiment, a method for generating a dead time to be added to a gate-on signal of a switching device will be described.

  As shown in FIG. 3, the dead time Td may be given when the gate-on signal changes from the OFF state to the ON state.

  By providing the dead time Td in the gate-on signals of the switching devices SW1 and SW4, it is possible to reliably avoid the switching devices SW1 and SW4 from being turned on at the same time, and to bring about the simultaneous on-state of the switching devices SW1 and SW4. It is possible to prevent a DC short circuit from occurring due to the SW4 → FCp + loop.

  In the second embodiment, the first and fourth switching devices SW1 and SW4 have been described. The same applies to the seventh and eighth switching devices SW7 and SW8.

As described above, according to the 5-level power conversion device of the second embodiment,
By adding the dead time Td to the gate-on signal, the occurrence of a DC short circuit can be suppressed even if the characteristics of the switching device and the gate drive circuit vary.

  Thereby, the overcurrent by the short circuit of a switching device can be suppressed, and the safe driving | operation of an apparatus is attained.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

  For example, some or all of the first to tenth switching devices SW1 to SW10 may be set to two or more in series, or may be set to two or more in parallel.

DCC1, DCC2 ... DC voltage source S1, S2 ... Common switch SW1-SW10 ... Switching device FC1, FC2 ... Flying capacitor

Claims (7)

A first common switch common to each phase, one end of which is connected to the negative end of the upper DC voltage source among the two DC voltage sources connected in series;
A second common switch common to each phase, one end of which is connected to the positive terminal of the lower DC voltage source among the two DC voltage sources connected in series;
A first flying capacitor common to each phase with one end connected to the other end of the first common switch;
A second flying capacitor common to each phase with one end connected to the other end of the second common switch;
A first switching device, a second switching device, and a third switching device of each phase sequentially connected in series between the positive end of the upper DC voltage source and the other end of the first common switch;
A fourth switching device of each phase interposed between a common connection point of the first switching device and the second switching device and the other end of the first flying capacitor;
A fifth switching device, a sixth switching device, and a seventh switching device of each phase sequentially connected in series between the other end of the second common switch and the negative electrode end of the lower DC voltage source;
An eighth switching device of each phase interposed between a common connection point of the sixth switching device and the seventh switching device and the other end of the second flying capacitor;
A ninth switching device of each phase having one end connected to a common connection point of the second switching device and the third switching device;
A tenth switching device of each phase having one end connected to a common connection point of the fifth switching device and the sixth switching device,
A control method for a five-level power converter using an output terminal as a common connection point where the other end of the ninth switching device and the other end of the tenth switching device of each phase are connected,
The voltage between the common connection point of the upper DC voltage source and the lower DC voltage source and the output terminal
Switching patterns in rows 2E, E, 1E, -2E of Table 2,
At least one of the switching patterns in the rows of ± 0a and ± 0b in Table 3,
5. A control method for a five-level power conversion device, wherein

However, 1 in the table indicates a gate-on state and 0 indicates a gate-off state. * Indicates that either is possible.

The voltage between the common connection point of the upper DC voltage source and the lower DC voltage source and the output terminal,
Switching patterns in rows 2E, E, 1E, -2E of Table 2,
Switching patterns in the ± 0a and ± 0b rows of Table 3,
The control method for a five-level power converter according to claim 1, wherein Providing a dead time between the gate-on signal of the first switching device and the gate-on signal of the second switching device;
3. The control method for a 5-level power converter according to claim 1, wherein a dead time is provided between the gate-on signal of the seventh switching device and the gate-on signal of the eighth switching device.   The control method for a five-level power converter according to any one of claims 1 to 3, wherein some or all of the first to tenth switching devices have a series number of 2 or more.   5. The method for controlling a five-level power converter according to claim 1, wherein some or all of the first to tenth switching devices have a parallel number of 2 or more.   A five-level power conversion device controlled by the control method according to claim 1.   A three-phase five-level power conversion device controlled by the control method according to any one of claims 1 to 5, comprising three first to tenth switching devices.

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