JP2016100367A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow power to be appropriately adjusted.SOLUTION: A semiconductor integrated circuit comprises a circuit block which includes a plurality of CMOS circuits to each of which power nodes are connected. Between two CMOS circuits which work in concert with each other out of the plurality of CMOS circuits included in the circuit block, voltage is adjusted in a manner such that voltage supplied to a power node of one CMOS circuit does not exceed voltage supplied to a power node of the other CMOS circuit.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor integrated circuit.

  While miniaturization of semiconductor integrated circuits progresses, the reduction of power consumption continues to be a constant problem. Even if the power per transistor is reduced due to miniaturization, the power increases as a result of the improvement of transistor integration and the improvement of device continuity by improving the device. Therefore, measures to reduce power consumption have been considered.

  As one method for reducing power consumption at the device level to cope with such a situation, a method of controlling the substrate bias voltage of a transistor is used. That is, in the case of a planar FET (Field Effect Transistor), there are four electrodes of a gate, a source, a drain, and a bias, and the operation characteristics of the device are controlled by how the substrate bias voltage is controlled with respect to the power supply voltage. Is.

  For example, in an NMOS-FET (N-channel Metal Oxide Semiconductor Field Effect Transistor, hereinafter simply referred to as NMOS), the bias electrode is usually connected to a ground voltage. Here, when a voltage slightly lower than the ground is applied to the NMOS bias electrode, a back bias state occurs, and an on-state current related to the NMOS reaction speed becomes difficult to flow, while a leakage current decreases. Conversely, when a voltage slightly higher than the ground is applied to the NMOS bias electrode, a forward bias state is entered, and an on-state current related to the NMOS reaction speed is likely to flow, while a leakage current increases.

  In a PMOS-FET (P-channel Metal Oxide Semiconductor Field Effect Transistor, hereinafter simply referred to as PMOS), the bias electrode is usually connected to the power supply voltage. Here, if a voltage slightly higher than the voltage of the power supply is applied to the bias electrode of the PMOS, it becomes a back bias state, and it becomes difficult for an on-state current related to the reaction speed of the PMOS to flow, while reducing a leakage current. Conversely, when a voltage slightly lower than the ground is applied to the PMOS bias electrode, a forward bias state is entered, and an on-state current related to the PMOS reaction speed is likely to flow, while a leakage current increases.

  Thus, the reaction speed and the leakage current can be controlled by changing the voltage applied to the bias electrodes of the NMOS and PMOS. Using this characteristic, there is a technique for reducing operating power and leakage power by controlling a voltage applied to a bias electrode of an entire CMOS (Complementary Metal Oxide Semiconductor) circuit composed of NMOS and PMOS.

  As a conventional technique for reducing power consumption for controlling a bias voltage, for example, Patent Document 1 proposes a method of switching a voltage level applied to a back gate of a MOS transistor included in an internal circuit by a selection signal corresponding to an operation mode. ing. According to this method, an example is disclosed in which a current amount is controlled by adjusting a threshold voltage of a MOS transistor according to an operation mode to achieve low power consumption. For example, Patent Document 2 proposes a method of adjusting the threshold voltage by changing the reference voltage connected to the CMOS. According to this method, an example is disclosed in which the threshold voltage is increased to reduce leakage power when the circuit is in a standby state, and the threshold voltage is decreased to increase the speed when circuit operation performance is required.

JP-A-11-1222047 JP 2006-217540 A

  However, with future miniaturization, the device will change from a planar FET (Field Effect Transistor) to a three-dimensional three-dimensional FET, particularly a fin FET. The fin type FET has a three-dimensional fin shape that protrudes into a three-dimensional fin shape, so the contact surface with the silicon substrate is small and is blocked by an insulating material. It is impossible to control. On the other hand, a fin-type semiconductor has a structure in which a fin-shaped channel is sandwiched between a front gate and a back gate, and both the front gate and the back gate act as mutual bias voltages. For this reason, since the circuit is characterized in that the state of the forward bias and the back bias is switched according to the output voltage of the preceding CMOS circuit, a direct bias control mechanism like the back gate of the conventional planar FET is provided. It cannot be used.

  This invention is made | formed in view of said subject, and it aims at providing the technique which can adjust electric power appropriately.

In order to achieve the above object, a semiconductor integrated circuit according to the present invention has the following arrangement. That is,
A semiconductor integrated circuit,
A circuit block including a plurality of CMOS circuits to which power supply nodes are connected;
The voltage supplied to one power supply node does not exceed the voltage supplied to the other power supply node between two CMOS circuits operating in cooperation among the plurality of CMOS circuits configured in the circuit block. And adjusting means for adjusting the voltage.

  According to the present invention, electric power can be adjusted appropriately.

It is a figure which shows a semiconductor integrated circuit. It is a figure which shows the example of arrangement | positioning of the internal and peripheral component of a circuit block. It is a figure which shows the structural example of a power supply adjustment part. It is a figure which shows the structural example of a power supply adjustment part. It is a figure which shows the truth table of the power supply control of a power supply adjustment part. It is a figure which shows the structural example of a power supply adjustment part. It is a figure which shows the structural example of a power supply adjustment part. It is a figure which shows the structural example of a power supply adjustment part. It is a figure which shows the electrode of 4-terminal PMOS and NMOS. It is a figure which shows the buffer comprised by MOS-FET. It is a figure which shows the electrode of fin type PMOS and NMOS. It is a figure which shows the buffer comprised by fin type FET. It is a figure which shows the buffer comprised by fin type FET.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  Conventionally, a planar FET generally has four terminals: a gate, a source, a drain, and a bias. This is shown in FIG. FIG. 9A is a schematic diagram of a PMOS of a planar FET. Gp, Sp, Dp, and Bp correspond to gate, source, drain, and bias electrodes, respectively. FIG. 9B shows a schematic diagram of an NMOS of a planar FET, and Gn, Sn, Dn, and Bn correspond to gate, source, drain, and bias electrodes, respectively. In the planar FET, the bias electrode is formed by providing a portion on the silicon substrate for applying a voltage acting as a bias to the well surrounding the source and drain. Normally, in a planar FET, the bias electrode exists independently of any of the gate, source, and drain electrodes when viewed as a single transistor, and basically the bias voltage changes independently of these other electrodes. be able to.

  FIG. 10 shows a circuit diagram in the case where a buffer is formed by a planar FET as a conventional example of a CMOS circuit configured by a planar FET, in which the bias voltage is controlled. In FIG. 10, there is a first positive power supply node 311 that provides a voltage Vdd applied to the sources of PMOSs 1003 and 1006, and a first negative power supply node 316 that provides a voltage Vss applied to the sources of NMOSs 1004 and 1007. There are a second positive power supply node 1001 for applying the bias voltage VddB of the PMOSs 1003 and 1006 and a second negative power supply node 1002 for applying the bias voltage VssB of the NMOSs 1004 and 1007, in addition to the power supply for driving these output nodes.

  In the PMOSs 1003 and 1006, the source is connected to the first positive power supply node 311, and the bias is connected to the second positive power supply node 1001. In the NMOSs 1004 and 1007, the source is connected to the first negative power supply node 316 and the bias is connected to the second negative power supply node 1002. The PMOS 1003 and the NMOS 1004 share the gate and drain nodes to form an output-side inverter 1005. The PMOS 1006 and the NMOS 1007 share the gate and drain nodes, respectively, to form an input-side inverter 1008. By connecting the output node of the inverter 1008 and the input node of the inverter 1005, a buffer is formed.

  The power supply method as shown in FIG. 10 can be similarly applied to other CMOS logic circuits such as NAND, NOR, flip-flop, etc., and drive power supply is also applied to these other CMOS logic circuits. The bias power can be divided and supplied.

  The buffer shown in FIG. 10 has a structure in which the voltages Vdd and Vss for driving the output node and the bias voltages VddB and VssB can provide different voltages, and the bias voltage is set in accordance with the required responsiveness and power. can do. When operating at high speed, it is driven in a forward bias state where the on-state current increases, and when reducing leakage power, it is set in the back bias state.

  In the future, devices will move from planar FETs to fin-type FETs for miniaturization and performance improvement. The fin-type FET has a three-dimensional structure in which a channel is formed not only on the upper surface of the fin-shaped channel but also on the side surface by a gate formed in a fin shape and a source and a drain formed so as to be orthogonal to the gate. The source, drain, and channel portions are insulated from the silicon substrate by an insulating layer, and the bias voltage is not controlled through a well like a planar FET. However, since the gate is provided so as to surround the thin channel portion formed in a fin shape, the gate for the channel on one side acts as a bias for the channel on the other side. Furthermore, the gate on one side and the gate on the other side are connected by a fin-shaped channel upper surface.

  FIG. 11 shows a schematic diagram of a fin-type FET. FIG. 11A is a schematic diagram of a PMOS of a fin-type FET, and Gp, Sp, and Dp correspond to gate, source, and drain electrodes, respectively. In the fin type FET, no bias voltage is supplied from the silicon substrate, the gate on one side acts as a bias for the gate on the other side, and the gates on both sides are short-circuited. Therefore, in FIG. 11A, a schematic diagram in which the gate Gp and the bias electrode are connected is used.

  FIG. 11B is a schematic diagram of an NMOS of a fin-type FET, and Gn, Sn, and Dn correspond to gate, source, and drain electrodes, respectively. Similarly to FIG. 11A, FIG. 11B uses a schematic diagram in which the gate Gn and the bias electrode are connected.

  FIG. 12 shows an example in which a buffer is constituted by a fin-type FET. In contrast to FIG. 10, in FIG. 12, the first positive power supply node 311 and the first negative power supply node 316 exist, and the two inverters 1203 and 1206 form a buffer in the same way. However, unlike the planar FET, the gates and biases of the fin-type FETs PMOS 1201, PMOS 1204, NMOS 1202, and NMOS 1205 are short-circuited. Therefore, the bias voltage cannot be controlled from the second positive power supply node 1001 and the second negative power supply node 1002 as shown in FIG. Also, in FIG. 10, a buffer is taken as an example. However, even in a CMOS logic circuit other than a buffer such as NAND, NOR, and flip-flop, the bias voltage cannot be directly controlled as long as a fin type FET is used. .

  For this reason, when the bias voltage is controlled in the CMOS circuit of the fin-type FET, a circuit mounting method called TCMS (Threshold Voltage Control Multiple Supply Voltages) is used.

  FIG. 13 shows a buffer configured using TCMS. FIG. 13 differs from FIG. 12 in the voltages applied to the sources of the PMOS 1204 and the NMOS 1205. The second positive power supply node 312 has a voltage VddH higher than the first positive power supply node 311 by a bias, and the second negative power supply node 317 has a voltage lower than the first negative power supply node 316 by a bias. VssH.

  By adopting such a power supply structure, the bias state of the output side inverter of the buffer can be controlled. That is, when the input Vin of FIG. 13 detects a low level input, the gate of the PMOS 1204 switches, the NMOS 1202 enters the forward bias state, and the PMOS 1201 enters the back bias state. At this time, the on-current of the NMOS 1202 increases and the leakage current of the PMOS 1201 decreases. When the input Vin in FIG. 13 detects a high level input, the gate of the NMOS 1205 is switched, the PMOS 1201 enters the forward bias state, and the NMOS 1202 enters the back bias state. At this time, the on-current of the PMOS 1201 increases and the leakage current of the NMOS 1202 decreases.

  Note that logic gates such as NAND and NOR can also be formed of TCMS circuits in the same way as buffers. Further, the TCMS circuit can be mixed with a gate composed of a normal single power source.

  An embodiment in which power consumption is adjusted by controlling the bias voltage as described above will be described below with reference to the drawings.

<Embodiment 1>
As a first embodiment, a method of controlling a bias voltage with a TCMS circuit configuration will be described.

  FIG. 1 shows the entire semiconductor integrated circuit according to the first embodiment, and shows a case where a bias voltage is controlled by a TCMS method for a semiconductor integrated circuit using fin-type FETs.

  That is, in FIG. 1, a circuit block 101 exists in the semiconductor integrated circuit 100, and a plurality of circuits including a first CMOS circuit group 102 and a second CMOS circuit group 103 exist in the circuit block 101. A first positive power supply node 105 and a first negative power supply node 106 are connected to the first CMOS circuit group 102 (more specifically, the source of the PMOS-FET). A second positive power supply node 107 and a second negative power supply node 108 are connected to the second CMOS circuit group 103 (more specifically, the source of the PMOS-FET).

  The power supply adjustment unit 109 selects the positive voltage Vdd and the voltage VddH that is higher than the positive voltage Vdd by the bias voltage, or generates a specific voltage from these, thereby generating the first positive power supply node 105 and the second voltage VddH. The voltage of the positive power supply node 107 is adjusted. The power supply adjustment unit 110 selects the negative voltage Vss and the voltage VssH that is lower than the negative voltage Vss by the bias voltage, or generates a specific voltage from the negative voltage Vss. The voltage of the negative power supply node 108 is adjusted.

  The power supply control unit 111 adjusts the voltage that the power supply adjustment unit 109 performs with respect to the first positive power supply node 105 and the second positive power supply node 107, and the power supply adjustment unit 110 uses the first negative power supply node 106 and the second positive power supply node 106. Controls the voltage adjustment to the two negative power supply nodes 108. During this adjustment, the voltage of the second positive power supply node 107 is always kept equal to or higher than that of the first positive power supply node 105. The voltage of the second negative power supply node 108 is always kept the same as or lower than that of the first negative power supply node 106.

  The first CMOS circuit group 102 is driven by an output node (output signal) 104 of the second CMOS circuit group 103. That is, the first CMOS circuit group 102 and the second CMOS circuit group 103 operate in cooperation with the output node 104. At this time, in a state where the voltage of the second positive power supply node 107 is higher than that of the first positive power supply node 105 and the voltage of the second negative power supply node 108 is lower than that of the first negative power supply node 106, A circuit composed of the CMOS circuit group 102, the second CMOS circuit group 103, and the output node 104 has a TCMS structure.

  FIG. 1 shows a state in which a buffer is configured as an example of the TCMS system. The input of the inverter 112 is connected as a logic circuit included in the first CMOS circuit group 102 and the output of the inverter 113 is connected as a logic circuit included in the second CMOS circuit group 103. Here, in a state where the voltage of the second positive power supply node 107 is higher than that of the first positive power supply node 105 and the voltage of the second negative power supply node 108 is lower than that of the first negative power supply node 106, the TCMS method is used. The buffer configuration.

  FIG. 2 shows a state in which the configuration of FIG. 1 is mounted on the semiconductor integrated circuit of the first embodiment.

  FIG. 2A shows a mounting example of a circuit block, a positive power source switching unit, and a negative power source switching unit in a semiconductor integrated circuit. That is, in FIG. 2, an example in which the circuit block 101 exists inside the semiconductor integrated circuit 100 and the power supply adjustment unit 109 that is a positive power supply switching unit and the power supply adjustment unit 110 that is a negative power supply switching unit are arranged so as to surround the circuit block 101. Is shown.

  The power supply adjustment unit 109 and the power supply adjustment unit 110 do not necessarily have to have a shape surrounding the circuit block 101. As long as the voltage applied to the CMOS circuits belonging to the first CMOS circuit group 102 and the second CMOS circuit group 103 can be adjusted, a configuration in which the circuits are discretely arranged may be used. For example, an individual CMOS circuit belonging to the first CMOS circuit group 102 or the second CMOS circuit group 103, or a mounting method in which the voltage is switched in a unit of several CMOS circuits may be employed.

  1 may be mounted on the outside of the circuit block 101, may be mounted inside, or may be mounted separately on the outside and inside. It doesn't matter. The semiconductor integrated circuit 100 may include a plurality of configurations including the circuit block 101, the power supply adjustment unit 109, the power supply adjustment unit 110, and the power supply control unit 111.

  Next, FIG. 2B shows a state in which the arrangement of a certain region 201 inside the CMOS circuit in the circuit block 101 of FIG. As shown in FIG. 2B, the first CMOS circuit group 102 and the second CMOS circuit group 103 are mixedly arranged inside the circuit block 101. FIG. 2B includes the buffer of FIG. 1 and shows a state where the inverter 112 and the inverter 113 are arranged. A circuit mounted by the TCMS method is desirably arranged close to each other with the second CMOS circuit group side as an input and the first circuit group as an output side, like the inverter 112 and the inverter 113. . Therefore, although the inverter 112 and the inverter 113 are shown as being arranged as separate cells, the circuit belonging to the first CMOS circuit group 102 and the circuit belonging to the second CMOS circuit group 103 are regarded as one cell. It may be configured and arranged.

  FIG. 3 shows a detailed configuration of the power supply adjustment unit 109 and the power supply adjustment unit 110 in FIG. 1 on the semiconductor integrated circuit of the first embodiment.

  FIG. 3A shows the internal structure of the power supply adjustment unit 109. The power supply node 301 is supplied with the voltage Vdd, and directly supplies the voltage Vdd to the first positive power supply node 105. The power supply node 302 is supplied with a voltage VddH that is higher than the voltage Vdd by a bias for the first CMOS circuit group 102. The second positive power supply node 107 can switch between the voltage Vdd and the voltage VddH by the PMOS 303, the PMOS 304, and the power switch control unit 305 based on the control signal EN_P_Bias.

  FIG. 3B shows the internal structure of the power supply adjustment unit 110. The power supply node 306 is supplied with the voltage Vss and directly supplies the voltage Vss to the first negative power supply node 106. The power supply node 307 is supplied with a voltage VssH lower than the voltage Vss by a bias for the first CMOS circuit group 102. The second negative power supply node 108 can switch between the voltage Vss and the voltage VssH by the NMOS 308, the NMOS 309, and the power switch control unit 310 based on the control signal EN_N_Bias.

  In FIGS. 3A and 3B, the control signal EN_P_Bias and the control EN_N_Bias are used as the control signals for the power switch. However, the control timing is not particularly limited and is independent even at the same timing. Different timings may be used.

  Further, the configurations shown in FIGS. 3A and 3B do not necessarily need to be used as a set, and only one of the configurations shown in FIGS. 3A and 3B may be used. I do not care.

  As described above, according to the present embodiment, the structure shown in FIG. 3A and FIG. 3B is used for the power supply adjustment unit 109 and the power supply adjustment unit 110 using the structure shown in FIG. The power consumption can be adjusted by applying the switch control unit.

  That is, a TCMS-type CMOS circuit that can operate at high speed and consumes a large amount of operating power while having a small leakage power, and a normal fin-type FET CMOS circuit that has a slightly lower operating speed but a higher leakage power, but a lower operating power. Can be switched.

  As described above, the power can be adjusted by performing bias control while utilizing the characteristics of the circuit of the fin-type FET, and a low power consumption circuit capable of adjusting the power according to the operation mode can be configured. .

<Embodiment 2>
As a second embodiment, another method for controlling the bias voltage with the configuration of the TCMS circuit will be described.

  The overall configuration of the semiconductor integrated circuit in the second embodiment is the same as that of the semiconductor integrated circuit 100 in FIG. 1 of the first embodiment, and the internal configurations of the power supply adjustment unit 109 and the power supply adjustment unit 110 are different from those in the first embodiment. .

  FIG. 4 shows a configuration example of the power supply adjustment unit 109 and the power supply adjustment unit 110 in FIG. 1 on the semiconductor integrated circuit of the second embodiment.

  FIG. 4A shows an example of the internal structure of the power supply adjustment unit 109. The voltage control of the second positive power supply node 107 is the same as that in FIG. 3A, and the control of the first positive power supply node 105 is different. That is, the first positive power supply node 105 can switch between the voltage Vdd and the voltage VddH by the power switch including the PMOS 401, the PMOS 402, and the power switch control unit 403.

  FIG. 4B shows an example of the internal structure of the power supply adjustment unit 110. The voltage control of the second negative power supply node 108 is the same as in FIG. 3B, and the control of the second negative power supply node 106 is different. That is, the first negative power supply node 106 can switch between the voltage Vdd and the voltage VddH by a power switch including the NMOS 404, the NMOS 405, and the power switch control unit 406.

  The truth table in FIG. 5 shows the relationship between the input signal and the output voltage of the power supply adjustment unit 109 and the power supply adjustment unit 110 shown in FIG.

  FIG. 5A shows the relationship between the input signal and the output voltage of the power supply adjustment unit 109 in FIG. When the control signal EN_P_Bias takes a value of 0, the second positive power supply node 107 and the first positive power supply node 105 both indicate the voltage Vdd regardless of the value of the control signal SelVddH. Only when the control signal EN_P_Bias and the control signal SelVddH each take a value of 1 and the second positive power supply node 107 takes the voltage VddH, the first positive power supply node 105 can take the voltage VddH.

  That is, the first positive power supply node 105 is controlled so as not to exceed the voltage of the second positive power supply node 107. Only when the second positive power supply node 107 takes the voltage VddH, the first positive power supply node 105 can select two voltages, a voltage Vdd that becomes a TCMS circuit and a voltage VddH that does not become a TCMS circuit. In other words, in addition to the operating state that can be taken by the semiconductor integrated circuit 100 shown in FIG. 1 of the first embodiment, it is driven by the voltage VddH and the leakage power is slightly increased as compared with the TCMS circuit, but the switching power is slightly reduced. Can be taken.

  FIG. 5B shows the relationship between the input signal and the output voltage of the power supply adjustment unit 110 in FIG. When the control signal EN_N_Bias takes a value of 0, the second negative power supply node 108 and the first negative power supply node 106 both indicate the voltage Vss regardless of the value of the control signal SelVssH. Only when the control signal EN_N_Bias and the control signal SelVssH each take a value of 1 and the second negative power supply node 108 takes the voltage VssH, the first negative power supply node 106 can take the voltage VssH.

  That is, the first negative power supply node 106 is controlled so as not to fall below the voltage of the second negative power supply node 108. Only when the second negative power supply node 108 takes the voltage VssH, the first negative power supply node 106 can select two voltages: a voltage Vss that becomes a TCMS circuit and a voltage VssH that does not become a TCMS circuit. In other words, in addition to the operating state that can be taken by the semiconductor integrated circuit 100 shown in FIG. 1 of the first embodiment, it is driven by the voltage VssH, and the leakage power is slightly increased compared to the TCMS circuit, but the switching power is slightly reduced. Can be taken.

  In the configuration shown in FIGS. 4A and 4B, the individual control signals EN_P_Bias and SelVddH and the control signals EN_N_Bias and SelVssH are used as control signals for the power switch. Each control signal is controlled according to a request for control of power consumption, and may be switched at the same timing, or may be controlled independently at different timings.

  4 (a) and 4 (b) are not necessarily used as a set, and may be used together or combined with the configurations shown in FIGS. 3 (a) and 3 (b). It doesn't matter. In the second embodiment, the configurations shown in FIGS. 4A and 4B are basically used. However, the configurations of the power supply adjustment unit 109 and the power supply adjustment unit 110 described in the following embodiments may be used in combination. .

  As described above, according to the present embodiment, the structure (power switch) shown in FIGS. 4A and 4B is used for the power supply adjustment unit 109 and the power supply adjustment unit 110 having the structure shown in FIG. By applying, power consumption can be adjusted more finely. That is, in addition to the operation states that can be taken by the semiconductor integrated circuit according to the first embodiment, the normal operation mode, the TCMS mode, and the overdrive mode can be switched according to the required power consumption.

<Embodiment 3>
As a third embodiment, another method for controlling the bias voltage with the configuration of the TCMS circuit will be described.

  The overall configuration of the semiconductor integrated circuit in the third embodiment is the same as that of the semiconductor integrated circuit in FIG. 1 of the first embodiment, and the internal configurations of the power supply adjustment unit 109 and the power supply adjustment unit 110 are different from those in the first embodiment. .

  FIG. 6 shows a configuration example of the power supply adjustment unit 109 and the power supply adjustment unit 110 in FIG. 1 on the semiconductor integrated circuit of the third embodiment.

  FIG. 6A shows an example of the internal structure of the power supply adjustment unit 109. Here, a structure in which a power cutoff switch is provided before the second positive power supply node 107 and the first positive power supply node 105 in FIG. That is, the first positive power supply node 105 can be powered off by the power cutoff mechanism composed of the PMOS 601 and the PMOS 602 controlled by the control signal P_off. FIG. 6A shows an example in which the power supply is shut off when P_off is a logical value 1.

  FIG. 6B shows an example of the internal structure of the power supply adjustment unit 110. Here, a structure in which a power cutoff switch is provided before the second negative power supply node 108 and the first negative power supply node 106 in FIG. That is, the first negative power supply node 106 can perform power shutdown by the power shutdown mechanism including the PMOS 603 and the PMOS 603 controlled by the control signal P_on. FIG. 6B shows an example in which the power is shut off when P_on is a logical value 1.

  In the configuration shown in FIGS. 6A and 6B, the individual control signals EN_P_Bias and P_off and the control signals EN_N_Bias and P_on are used as control signals for the power switch. Each control signal is controlled according to a request for control of power consumption, and may be switched at the same timing, or may be controlled independently at different timings.

  In addition, the configurations shown in FIGS. 6A and 6B do not necessarily need to be used together, and may be combined with or combined with the configurations shown in FIGS. 3A and 3B. Can also be turned off. Further, in the third embodiment, the configurations of FIG. 6A and FIG. 6B are based, but the configurations based on FIG. 4A and FIG. 4B and the following embodiments are shown. The configurations of the power supply adjustment unit 109 and the power supply adjustment unit 110 may be used in combination.

  As described above, according to the present embodiment, the structure (power cutoff mechanism) shown in FIGS. 6A and 6B is different from the power supply adjustment unit 109 and the power supply adjustment unit 110 having the structure shown in FIG. ) Can be used to use both finer voltage regulation and power shutdown mechanisms. That is, in addition to the operation state that the semiconductor integrated circuit of Embodiment 1 can take, in addition to switching between the TCMS mode and another mode according to the required power consumption, it is possible to take a power-off state.

<Embodiment 4>
As a fourth embodiment, another method for controlling the bias voltage with the configuration of the TCMS circuit will be described.

  The overall configuration of the semiconductor integrated circuit in the fourth embodiment is the same as that of the semiconductor integrated circuit of FIG. 1 in the first embodiment, and the internal configurations of the power supply adjustment unit 109 and the power supply adjustment unit 110 are different from those in the first embodiment. .

  FIG. 7 shows a configuration example of the power supply adjustment unit 109 and the power supply adjustment unit 110 in FIG. 1 on the semiconductor integrated circuit of the fourth embodiment.

  FIG. 7A shows an example of the internal structure of the power supply adjustment unit 109. Here, the voltage difference between the power supply node 302 and the power supply node 301 in FIG. That is, the voltage VddH is supplied from the voltage generation unit 701 to the power supply node 302. Further, the voltage Vdd divided by the resistors 702 and 703 becomes the voltage of the power supply node 301. The voltage VddH is set for the second positive power supply node 107 by the power supply node 302, and the voltage Vdd is set for the first positive power supply node 105 by the power supply node 301. In the power supply adjustment unit 109 having such a voltage dividing structure, even if the output voltage of the voltage generation unit 701 is changed from the voltage VddH in accordance with the control signal dVdd_cnt, the voltage of the second positive power supply node 107 is A state always higher than the voltage of power supply node 105 is maintained.

  FIG. 7B shows an example of the internal structure of the power supply adjustment unit 110. Here, a structure is adopted in which the voltage difference between the power supply node 307 and the power supply node 306 in FIG. That is, the power supply node 306 is supplied with a voltage Vss obtained by dividing the voltage supplied by the voltage generator 704 with the resistors 705 and 706. In FIG. 7B, the voltage VssH is configured to be the ground voltage at the power supply node 307. However, another configuration may be adopted as long as the voltage lower than that of the power supply node 306 can be maintained. The second negative power supply node 108 is set to the ground voltage by the power supply node 307, and the first negative power supply node 106 is set to the voltage Vss by the power supply node 306. In the power supply adjustment unit 110 having such a voltage division structure, even if the output voltage of the voltage generation unit 704 is changed in accordance with the control signal dVss_cnt, the voltage of the first negative power supply node 106 is the second negative power supply node 108. Will always stay high.

  In FIG. 7B, a configuration in which the resistor 705 is eliminated and a voltage is directly supplied from the voltage generation unit 704 to the power supply node 306 may be employed.

  Further, it is not always necessary to use both of the configurations shown in FIGS. 7A and 7B as a set. FIG. 3A, FIG. 3B, FIG. 4A, and FIG. ) And the configuration shown in FIG. 6A and FIG. 6B can be combined or combined, and the power can be shut off.

  As described above, according to the present embodiment, the structure (voltage dividing structure) shown in FIGS. 7A and 7B with respect to the power supply adjustment unit 109 and the power supply adjustment unit 110 having the structure shown in FIG. ), The bias state can be followed even when the TCMS circuit can take various power supply voltages.

<Embodiment 5>
As a fifth embodiment, another method for controlling the bias voltage with the configuration of the TCMS circuit will be described.

  The overall configuration of the semiconductor integrated circuit according to the fifth embodiment is the same as that of the semiconductor integrated circuit of FIG. 1 according to the first embodiment, which is different from that of the fourth embodiment in the partial pressure inside the power supply adjustment unit 109 and the power supply adjustment unit 110. The mechanism is different.

  FIG. 8 shows a configuration example of the power supply adjustment unit 109 and the power supply adjustment unit 110 in FIG. 1 on the semiconductor integrated circuit of the fourth embodiment.

  FIG. 8A shows an example of the internal structure of the power supply adjustment unit 109. Here, the resistor 702 in FIG. 7A is replaced with a variable resistor 801. That is, the voltage VddH is supplied from the voltage generation unit 701 to the power supply node 302. In addition, the voltage divided by the variable resistor 801 and the resistor 703 becomes the voltage of the power supply node 301. In the second positive power supply node 107, the voltage VddH is set by the power supply node 302, and in the first positive power supply node 105, a voltage divided by the variable resistor 801 and the resistor 703 is set by the power supply node 301. In power supply adjustment section 109 having such a voltage dividing structure, the voltage difference between power supply node 302 and power supply node 301 can be adjusted freely. Further, even when the output voltage of the voltage generation unit 701 is changed from the voltage VddH according to the control signal dVdd_cnt, the voltage of the second positive power supply node 107 is always kept higher than the voltage of the first positive power supply node 105. It is. Further, by using the variable resistor 801, an appropriate bias voltage can be set.

  8A, the resistor 702 in FIG. 7A is replaced with a variable resistor 801. However, the same applies to a configuration in which the resistor 703 is replaced with a variable resistor instead of the resistor 702 in FIG. 7A. The effect of can be obtained. At that time, an appropriate bias voltage can be set by appropriately selecting the resistance value of the resistor 702.

  FIG. 8B shows an example of the internal structure of the power supply adjustment unit 110. Here, the resistor 706 in FIG. 7B is replaced with a variable resistor 802. That is, a voltage obtained by dividing the voltage supplied by the voltage generation unit 704 by the resistor 705 and the variable resistor 802 is supplied to the power supply node 306. Further, in FIG. 8B, a configuration is used in which the voltage VssH becomes the ground voltage at the power supply node 307. The ground voltage is set for the second negative power supply node 108 by the power supply node 307, and the voltage divided by the resistor 705 and the variable resistor 802 is set for the first negative power supply node 106 by the power supply node 306. In power supply adjustment unit 110 having such a voltage dividing structure, the voltage difference between power supply node 307 and power supply node 306 can be freely adjusted. Further, even when the output voltage of the voltage generator 704 is changed according to the control signal dVss_cnt, the voltage of the first negative power supply node 106 is always kept higher than that of the second negative power supply node 108. Further, by using the variable resistor 802, an appropriate bias voltage can be set.

  In FIG. 8B, a configuration in which the resistor 705 is eliminated and the voltage is directly supplied from the voltage generator 704 to the power supply node 306 may be employed.

  8B, the resistor 706 in FIG. 7B is replaced with a variable resistor 802. However, the same applies to a configuration in which the resistor 705 is replaced with a variable resistor instead of the resistor 706 in FIG. 7B. The effect of can be obtained. At that time, an appropriate bias voltage can be set by appropriately selecting the resistance value of the resistor 706.

  As described above, according to the present embodiment, the structure (voltage dividing structure) shown in FIGS. 8A and 8B is different from the power supply adjustment unit 109 and the power supply adjustment unit 110 having the structure shown in FIG. ), The bias state can be followed and the bias voltage can be finely adjusted even when the TCMS circuit can take various power supply voltages.

  Note that the present invention supplies a program that realizes one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in a computer of the system or apparatus execute the program. It can also be realized by a process of reading and executing. It can also be realized by a circuit (for example, ASIC) that realizes one or more functions.

  DESCRIPTION OF SYMBOLS 100: Semiconductor integrated circuit, 101: Circuit block, 102: 1st CMOS circuit group, 103: 2nd CMOS circuit group, 104: Output node, 105: 1st positive power supply node, 106: 1st negative power supply Node 107: second positive power supply node 108: second negative power supply node 109: power supply adjustment unit 110: power supply adjustment unit 111: power supply control unit 112: inverter 113: inverter

Claims (13)

A semiconductor integrated circuit,
A circuit block including a plurality of CMOS circuits to which power supply nodes are connected;
The voltage supplied to one power supply node does not exceed the voltage supplied to the other power supply node between two CMOS circuits operating in cooperation among the plurality of CMOS circuits configured in the circuit block. A semiconductor integrated circuit, comprising: adjusting means for adjusting voltage. A semiconductor integrated circuit,
A circuit block including a first CMOS circuit group and a second CMOS circuit group, each having a positive power supply node and a negative power supply node connected to each other as a power supply node;
Between at least one of the positive power supply node and the negative power supply node connected between the first CMOS circuit group and the second CMOS circuit group, a voltage supplied to one power supply node is And adjusting means for adjusting the voltage so as not to exceed the voltage supplied to the other power supply node. The adjusting means includes selection means for selecting a first voltage supplied to the other power supply node and a second voltage higher than the first voltage when supplying a voltage to the one power supply node. ,
The selection means selects the first voltage and the second voltage only when the other power supply node selects the second voltage. The semiconductor integrated circuit according to claim 1. 4. The semiconductor integrated circuit according to claim 1, wherein the adjusting unit includes a blocking unit that blocks supply of power to the one power supply node and the other power supply node. 5. 5. The semiconductor integrated circuit according to claim 1, wherein the adjusting unit includes a setting unit that sets a voltage difference between the one power supply node and the other power supply node. 6. The semiconductor integrated circuit according to claim 1, wherein the adjusting unit includes a changing unit that changes a voltage difference between the one power supply node and the other power supply node. The adjusting means is
The first voltage is adjusted so that the voltage supplied to the first positive power supply node of the first CMOS circuit group does not exceed the voltage supplied to the second positive power supply node of the second CMOS circuit group. And the voltage supplied to the first negative power supply node of the first CMOS circuit group so as not to fall below the voltage supplied to the second negative power supply node of the second CMOS circuit group. The semiconductor integrated circuit according to claim 2, further comprising second adjusting means for adjusting. When the first adjustment means supplies a voltage to the second positive power supply node, the first adjustment means supplies a first positive voltage supplied to the first positive power supply node and a first voltage higher than the first positive voltage. First selection means for selecting a positive voltage of 2;
The second power supply adjusting means, when supplying a voltage to the second negative power supply node, is lower than the first negative voltage and the first negative voltage supplied to the first negative power supply node. The semiconductor integrated circuit according to claim 7, further comprising second selection means for selecting a second negative voltage. The first selection means is configured such that the first positive power supply node is connected to the first positive voltage and the second positive voltage node only when the second positive power supply node selects the second positive voltage. Select the positive voltage and
The second selection means is arranged such that the first negative power supply node is connected to the first negative voltage and the second negative voltage node only when the second negative power supply node selects the second negative voltage. The semiconductor integrated circuit according to claim 8, wherein the negative voltage is selected. The first adjusting means includes first cutoff means for cutting off power supply to the first positive power supply node and the second positive power supply node,
The second adjustment unit includes a second blocking unit that blocks the supply of power to the first negative power supply node and the second negative power supply node. 2. A semiconductor integrated circuit according to claim 1. The first adjusting means includes first setting means for setting a voltage difference between the first positive power supply node and the second positive power supply node,
The said 2nd adjustment means is provided with the 2nd setting means which sets the voltage difference of a said 1st negative power supply node and a said 2nd negative power supply node. The one of the Claims 7 thru | or 10 characterized by the above-mentioned. 2. The semiconductor integrated circuit according to item 1. The first adjusting means includes first changing means for changing a voltage difference between the first positive power supply node and the second positive power supply node,
The second adjusting means includes second changing means for changing a voltage difference between the first negative power supply node and the second negative power supply node. 2. The semiconductor integrated circuit according to item 1. The semiconductor integrated circuit according to claim 1, further comprising a control unit that controls an operation of the adjusting unit.

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