JP2016096495A - Clock creation apparatus and clock creation method - Google Patents

Abstract

PURPOSE: To provide a clock generation apparatus capable of selectively using a plurality of clock sources while suppressing increasing of a scale of an apparatus.CONSTITUTION: A first oscillator or a second oscillator is connected to a first terminal 31. A second terminal 32 is connected to the second oscillator or a predetermined potential. A first signal path SL1 and a second signal path SL2 are formed between the first terminal 31 and an output terminal 36. A determination part 35 determines that any one of the first signal path SL1 and the second signal path SL2 is set as a clock signal path, and control a first shutdown part 34 and a second shutdown part 35 so as to shutdown one and conduct the other. The first shutdown part 34 allows the first signal path SL1 to shutdown or conduct in accordance with that the second terminal is connected to any one of a predetermined electric potential and the second oscillator. The second shutdown part 35 allows the second signal path SL2 to shutdown or conduct in accordance with that the second terminal 32 is connected to any one of the predetermined electric potential and the second oscillator.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a clock generation device, and more particularly to a clock generation device that generates a clock signal based on an oscillation signal from an oscillator and a clock signal generation method.

  As such a clock generation device, there has been proposed a device in which two oscillators having different precisions can be connected and a clock signal is generated based on an oscillation signal from one of the oscillators (for example, Patent Documents). 1). As an oscillator connected to the clock generator, a TCXO including a passive drive type oscillator such as a crystal oscillator using a crystal oscillator as an oscillator, or a circuit for driving an oscillation source, which oscillates by voltage application from the clock generator side. An active drive type oscillator such as (temperature compensated crystal oscillator) is used.

JP 2001-251140 A

  By the way, in order to be able to use both the passive drive type and the active drive type oscillators in such a clock generation device, a processing circuit for each oscillator is required, and accordingly, a passive drive type oscillator is connected. And an external terminal for connecting an active drive type oscillator are required.

  Therefore, there is a problem that the device scale of the clock generation device increases as the number of external terminals increases.

  The present invention has been made to solve the above problem, and is a clock connected to the first oscillator or the second oscillator and generating and outputting a clock signal in accordance with an oscillation signal from the connected oscillator. A generator that is connected to the first oscillator or the second oscillator and receives an oscillation signal; a second terminal connected to the second oscillator or a predetermined potential; Connected to the first terminal through a first signal path and a second signal path, connected to an output terminal for outputting a clock signal, to the first terminal and the second terminal, A determination unit that determines which of the first signal path and the second signal path is the path of the clock signal depending on whether the second oscillator or the predetermined potential is connected. And the first signal If the path is connected between the first terminal and the output terminal, and the determination unit determines that the second signal path is the clock signal path, the first signal path is blocked. The second signal path when the first blocking part is connected between the first terminal and the output terminal in the second signal path, and the second terminal is connected to the predetermined potential. And a second blocking part for blocking the above.

  According to the clock generation method of the present invention, in the clock generation device including the first terminal, the second terminal, and the output terminal, the clock signal is generated according to the supply of the oscillation signal from the first oscillator or the second oscillator. A clock generation method for generating, the step of connecting the first terminal to the first oscillator or the second oscillator, the step of connecting the second terminal to the second oscillator or a predetermined potential, Depending on whether the second terminal is connected to the second oscillator or the predetermined potential, the first signal path and the second of the signal paths connecting the first terminal and the output terminal Determining which one of the signal paths is the signal path of the clock signal, and blocking the first signal path when it is determined that the second signal path is the path of the clock signal. And step, when the first signal path is determined to the path of the clock signal, and having the steps of: blocking the second signal path.

  According to the present invention, it is possible to provide a clock generation device that can selectively use a plurality of clock sources while suppressing an increase in device scale.

It is a figure which shows the circuit structure of the clock generation apparatus which concerns on this invention. It is a time chart which shows operation | movement of each part of the clock generation apparatus in the case of using a TCXO vibrator. It is a time chart which shows operation | movement of each part of the clock generation apparatus in the case of using an Xtal vibrator. It is a block diagram which shows the functional structure of the clock generation apparatus which concerns on this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a clock generator 10 according to the present invention.

  The XI / TCXO terminal 11 is a first external terminal for connecting, for example, a TCXO (Temperature Compensated Crystal Oscillator) as a first oscillator or a crystal oscillator as a second oscillator. The XO terminal 12 is a second external terminal for connecting a ground potential (GND) or a crystal oscillator.

  Here, the TCXO is provided with a temperature compensation circuit for correcting the frequency temperature characteristics thereof, an inverting amplifier, and the like together with the crystal resonator, and actively generates an oscillation signal without receiving a voltage supply from the clock generator 10 side. It is an active drive type oscillator. Therefore, when TCXO is used as the oscillator, the XI / TCXO terminal 11 is connected to the TCXO vibrator, and a ground potential is applied to the XO terminal 12.

  On the other hand, the crystal oscillator is a passive drive type oscillator that generates an oscillation signal by receiving a voltage supply from the clock generation device 10 via the XI / TCXO terminal 11 and the XO terminal 12. When a crystal oscillator is used as the oscillator, the crystal oscillator is connected to the XI / TCXO terminal 11 and the XO terminal 12.

  The capacitor 13 cuts the DC component of the oscillation signal input from the XI / TCXO terminal 11 and supplies it to the inverter 14.

  One end of the feedback resistor 15 is connected to the input end of the inverter 14, and the other end of the feedback resistor 15 is connected to the output end of the inverter 14. The inverter 14 and the feedback resistor 15 supply to the buffer 16 an amplitude-increasing oscillation signal that is input from the XI / TCXO terminal 11 and increases the amplitude of the oscillation signal whose DC component is cut by the capacitor 13.

  The buffer 16 generates the clock signal CK1 by binarizing the amplitude increase oscillation signal and supplies it to the counter 21 and the AND gate 23.

  One end of a feedback resistor 18 is connected to the input end of the inverter 17, and the other end of the feedback resistor 18 is connected to the output end of the inverter 17. The inverter 17 and the feedback resistor 18 use a signal obtained by binarizing the oscillation signal input from the XI / TCXO terminal 11 and increasing the amplitude as an oscillation drive signal GN, the FF 20 (D type flip flop), the counter 22, and the XO terminal 12 To supply. Here, when a crystal oscillator is connected to the XI / TCXO terminal 11 and the XO terminal 12, the inverter 17 supplies the oscillation drive signal GN to the crystal oscillator via the XO terminal 12. As a result, the crystal oscillator oscillates and supplies the oscillation signal to the buffers 16 and 19 and the inverter 17.

  The buffer 19 generates a clock signal CK 2 by binarizing the oscillation signal input from the XI / TCXO terminal 11 and supplies the clock signal CK 2 to the AND gate 24.

  An inverter 25 is connected between the output terminal of the FF 20 and the input terminal D. With this configuration, the FF 20 generates a reset signal RS that alternately repeats the signal values “0” and “1” at a frequency obtained by dividing the oscillation drive signal GN by two, that is, a frequency half that of the oscillation drive signal GN. This is supplied to the reset terminal R of the counter 21.

  The counter 21 counts up in synchronization with the rising edge of the clock signal CK1. The counter 21 counts up from 0 to 15 according to the clock signal CK1, and holds the count value when the count value reaches 15.

  The counter 21 supplies an enable signal EN 1 having a signal value “0” when the count value is 0 to 14 and a signal value “1” when the count value is 15 to the AND gate 23. The counter 21 resets the count value to 0 in response to the reset signal RS having the signal value “1”.

  The counter 22 counts up in synchronization with the rising edge of the oscillation drive signal GN. The counter 22 counts up from 0 to 15 in accordance with the oscillation drive signal GN, and holds the count value when the count value reaches 15. The counter 22 supplies the AND gate 24 with an enable signal EN2 having a signal value “0” when the count value is 0 to 14, and when the count value reaches 15, the signal value “1”.

  The AND gate 23 supplies the clock signal CK1 to the OR gate 26 when the signal value of the enable signal EN1 is “1”, while the signal value “1” when the signal value of the enable signal EN1 is “0”. 0 ”is supplied to the OR gate 26.

  The AND gate 24 supplies the clock signal CK2 to the OR gate 26 when the signal value of the enable signal EN2 is “1”, while the signal value “2” when the signal value of the enable signal EN2 is “0”. 0 ”is supplied to the OR gate 26.

  The OR gate 26 uses the clock signal CK1 supplied via the AND gate 23 or the clock signal CK2 supplied via the AND gate 24 as an output clock signal, and outputs it as an output terminal 27.

  FIG. 2 is a time chart showing the operation of each part when the TCXO is used as the oscillator in the clock generation device 10 having the circuit configuration of FIG. As described above, when the TCXO is used as the oscillator, the TCXO input terminal is connected to the XI / TCXO terminal 11 and a ground potential is applied to the XO terminal 12.

  Here, an oscillation signal is input from the TCXO through the XI / TCXO terminal 11 (FIG. 2A). The input oscillation signal has its DC component cut by the capacitor 13, the amplitude is increased by the inverter 14 and the feedback resistor 15, and is supplied to the buffer 16 as an amplitude increase oscillation signal. The buffer 16 converts the amplitude-increasing oscillation signal into a clock signal CK 1 and supplies it to the counter 21 and the AND gate 23.

  Since the XO terminal 12 is at the ground potential (FIG. 2B), the clock input terminal of the FF 20 connected to the XO terminal 12 is also at the ground potential. Therefore, the FF 20 does not perform the above-described frequency dividing operation, and generates a reset signal RS having a signal value “0” indicating non-reset (FIG. 2C).

  Since the clock input terminal of the counter 22 is connected to the XO terminal 12, it becomes a ground potential. Therefore, the counter 22 does not count up (FIG. 2 (d)). Therefore, the counter 22 outputs a signal value “0” as the enable signal EN2 (FIG. 2 (e)).

  On the other hand, the clock input terminal of the counter 21 is connected to the XI / TCXO terminal 11 via the buffer 16. Therefore, the clock signal CK1 is supplied to the counter 21. The counter 21 counts up in synchronization with the rising edge of the clock signal CK1. When the counter 21 counts up to the count value “15”, the counter 21 holds the count value (FIG. 2F), and supplies the enable signal EN 1 of the signal value “1” to the AND gate 23. That is, the counter 21 outputs an enable signal EN1 having a signal value of “0” until the count value reaches 15 and “1” after the count value reaches 15 (FIG. 2 (g)).

  The AND gate 23 supplies “0” until the count value of the counter 21 reaches 15, and supplies the clock signal CK1 to the OR gate 26 after the count value reaches 15.

  The AND gate 24 supplies the signal value “0” to the OR gate 26 because the enable signal EN2 having the signal value “0” is supplied from the counter 22 as described above.

  The OR gate 26 outputs a signal value “0” until the count value of the counter 21 reaches 15, and when the count value of the counter 21 reaches 15, the OR gate 26 outputs the clock signal CK1 as an output clock signal to the output terminal 27. (FIG. 2 (h)).

  On the other hand, FIG. 3 is a time chart showing an operation when a crystal oscillator is used as an oscillator in the clock generation apparatus 10 having the circuit configuration of FIG. As described above, when the crystal oscillator is used, the first terminal of the crystal oscillator is connected to the XI / TCXO terminal 11 and the second terminal is connected to the XO terminal 12.

  At this time, the oscillation drive signal GN output from the inverter 17 is supplied to the crystal oscillator via the XO terminal. As a result, the crystal oscillator oscillates, and the oscillation signal is supplied to the buffer 19 and the inverter 17 via the Xi / TCXO terminal 11 (FIG. 3A).

  The inverter 17 supplies the oscillation drive signal GN corresponding to the oscillation signal input via the XI / TCXO terminal 11 to the crystal oscillator via the XO terminal 12 (FIG. 3B). Further, the inverter 17 supplies the oscillation drive signal GN to the FF 20 and the counter 22.

  The FF 20 receives the oscillation drive signal GN and generates the reset signal RS in synchronization with the rising edge of the signal obtained by dividing the oscillation drive signal GN by two. That is, the FF 20 supplies a periodic reset signal RS having a period obtained by dividing the oscillation drive signal GN by 2 to the reset terminal R of the counter 21 (FIG. 3C).

  The counter 22 counts up in synchronization with the rising edge of the oscillation drive signal GN. When the counter 22 counts from the count value “0” to “15”, the counter 22 holds the count value “15” (FIG. 3D), and supplies the enable signal EN 2 of the signal value “1” to the AND gate 24. . That is, the counter 22 supplies an enable signal EN2 having “0” between the count values “0” and “14” and “1” after the count value reaches “15” to the AND gate 24 ( FIG. 3 (e)).

  During this time, a periodic reset signal RS (FIG. 3C) is supplied to the reset terminal R of the counter 21, and the count value is periodically reset. Therefore, the counter 21 repeatedly counts the count values “0” and “1” (FIG. 3F), and cannot count up to the count value “15”. Therefore, the counter 21 continues to output the enable signal EN1 having the signal value “0” to the AND gate 23 (FIG. 3 (g)).

  The OR gate 26 outputs a logical sum of the output signal of the AND gate 23 and the output signal of the AND gate 24. Therefore, at this time, the OR gate 26 is “0” until the count value of the counter 22 reaches “15”, and the clock supplied from the buffer 19 after the count value of the counter 22 reaches “15”. The signal CK2 is output as an output clock signal through the output terminal 27 (FIG. 3 (h)).

  As described above, in the clock generation device 10 shown in FIG. 1, when, for example, TCXO is connected to the first terminal (11) as the active drive type oscillator and the ground potential is applied to the second terminal (12), the clock generation device. The ten buffers 16 generate the clock signal CK1 by binarizing the oscillation signal. Here, after a period of time from when the generation of the clock signal CK1 is started until the counter 21 counts “15”, that is, after a period necessary for the clock signal to stabilize, the clock signal CK1 is ANDed. The signal is output via the gate 23, the OR gate 26 and the output terminal 27.

  On the other hand, when a passive drive type crystal oscillator, for example, is connected to the first terminal (11) and the second terminal (12), the inverter 17 as the oscillation drive unit generates the oscillation drive signal GN and passes this through the second terminal. Supply to crystal oscillator. As a result, the crystal oscillator oscillates and supplies the oscillation signal to the clock generator 10 via the first terminal. At this time, the buffer 19 of the clock generation device 10 generates the clock signal CK2 by binarizing the oscillation signal. Then, after elapse of a period of time from when the oscillation drive signal is generated until the counter 22 counts “15”, that is, a period necessary for the clock signal to stabilize, the clock signal CK2 is 24, the OR gate 26 and the output terminal 27.

  Therefore, in the clock generator 10 shown in FIG. 1, the two first terminals (11) and the second terminal (12) are shared as terminals for connecting the passive drive oscillator and the active drive oscillator. It becomes possible. Therefore, according to the clock generation device 10 shown in FIG. 1, as compared with a configuration in which a dedicated terminal for connecting a passive drive type oscillator and a dedicated terminal for connecting an active drive type oscillator are provided, It is possible to reduce the scale of the device as the number of terminals decreases.

  FIG. 4 is a block diagram functionally showing the clock generator 10 according to the present invention. The clock generation device 10 includes a first terminal 31, a second terminal 32, a determination unit 33, a first blocking unit 34, a second blocking unit 35, and an output terminal 36. The first terminal 31 and the output terminal 36 are connected by the first signal path SL1 and the second signal path SL2. The oscillation signal input from the first terminal 31 is transmitted through either the first signal path SL1 or the second signal path SL2, and is output as an output clock signal through the output terminal 36.

  The first terminal 31 is a terminal corresponding to the XI / TCXO terminal 11 in FIG. 1, and is connected to a first oscillator (for example, TCXO) or a second oscillator (for example, a crystal oscillator). The second terminal 32 is a terminal corresponding to the XO terminal 12 in FIG. 1, and is connected to a predetermined potential (for example, ground potential) or a second oscillator.

  The determination unit 33 includes a configuration corresponding to the FF 20 in FIG. 1 and is connected to the first terminal 31 and the second terminal 32. The determination unit 33 controls the first cutoff unit according to whether the second terminal 32 is connected to a predetermined potential or the second oscillator, and switches conduction / cutoff of the first signal path SL1. For example, when the second terminal 32 is connected to the second oscillator, the determination unit 33 supplies a blocking signal SS for blocking the first signal path SL1 to the first blocking unit 34. This cutoff signal SS corresponds to the reset signal RS supplied to the counter 21 by the FF 20 in FIG. On the other hand, when the second terminal 32 is connected to a predetermined potential, the determination unit 33 does not supply the cutoff signal SS to the first cutoff unit 34. This corresponds to the fact that the FF 20 does not output the reset signal RS when the ground potential is applied to the XO terminal 12 in the configuration of FIG.

  The first blocking unit 34 includes a configuration corresponding to the counter 21 and the AND gate 23 of FIG. The 1st interruption | blocking part 34 is connected between the 1st terminal 31 and the output terminal 36, and comprises 1st signal path | route SL1. When the cutoff signal SS is supplied from the determination unit 33, the first cutoff unit 34 blocks the first signal path SL1. In the configuration of FIG. 1, when the counter 21 is supplied with the reset signal RS from the FF 20, the counter 21 resets the count value and outputs the enable signal EN1 having the signal value “0” to the AND gate 23. This corresponds to the AND gate 23 supplying the signal value “0” to the OR gate 26. On the other hand, when the blocking signal SS is not supplied from the determination unit 33, the first blocking unit 34 does not block (that is, conducts) the first signal path SL1.

  The second blocking unit 35 includes a configuration corresponding to the counter 22 and the AND gate 24 of FIG. The 2nd interruption | blocking part 35 is connected between the 1st terminal 31 and the output terminal 36, and comprises 2nd signal path | route SL2. The second blocking unit 35 switches conduction / cutoff of the second signal path SL2 depending on whether the second terminal 32 is connected to a predetermined potential or a second oscillator. For example, when the second terminal 32 is connected to a predetermined potential, the second blocking unit 35 blocks the second signal path SL2. This is because the counter 22 does not count up when the ground potential is applied to the XO terminal 12 in the configuration of FIG. 1, and the counter 22 supplies the signal value “0” to the AND gate 24 as the enable signal EN2, This corresponds to the AND gate 24 supplying the signal value “0” to the OR gate 26. On the other hand, when the second terminal 32 is connected to the second oscillator, the second blocking unit 35 does not block (that is, conducts) the second signal path SL2.

  The output terminal 36 includes a configuration corresponding to the OR gate 26 and the output terminal 27 of FIG. 1, and outputs a clock signal supplied through the first signal path or the second signal path.

  As described above, the clock generator according to the present invention includes the first terminal (XI / TCXO terminal) connected to the first oscillator (TCXO) or the second oscillator (crystal oscillator), and the second oscillator. Alternatively, a second terminal (XO terminal) connected to a predetermined potential (for example, ground potential) is provided, and a clock signal is output based on supply of an oscillation signal from the first oscillator or the second oscillator. A first signal path and a second signal path are formed between the first terminal and the output terminal, and a first blocking unit (first counter and first AND gate) that blocks the first signal path; A second blocking unit (second counter and second AND gate) that blocks the second signal path, and a determination unit that determines which of the first signal path or the second signal path is the clock signal path (FF). The determination unit determines the path of the clock signal according to whether the second terminal is connected to a predetermined potential or the second oscillator, and controls the first blocking unit to block the first signal path Or conduct. The second blocking unit blocks or conducts the second signal path depending on whether the second terminal is connected to a predetermined potential or the second oscillator.

  According to this configuration, it is possible to generate a clock signal by selectively switching and connecting a plurality of oscillators while suppressing an increase in device scale due to the number of terminals.

  In the above embodiment, an example in which TCXO is used as the first oscillator has been described. However, the present invention is not limited to this, and other oscillators such as SPXO (Single Package Crystal Oscillator) may be used. Further, an example in which a crystal oscillator is used as the second oscillator has been described. However, the present invention is not limited to this, and other oscillators such as a ceramic oscillator may be used.

  Further, in the above embodiment, an example in which the second terminal (XO terminal) is connected to the ground potential when the first oscillator (TCXO) is used has been described. However, the present invention is not limited to this, and any connection is possible as long as it is connected to a predetermined fixed potential.

  In the above-described embodiment, the signal path of the clock signal is controlled using a blocking unit including a counter and an AND gate. However, the present invention is not limited to this. For example, the signal path may be controlled by turning off the power of the buffer or the inverter in accordance with the cutoff signal. According to such a configuration, it is possible to control the signal path and reduce power consumption.

DESCRIPTION OF SYMBOLS 10 Clock generator 11 XI / TCXO terminal 12 XO terminal 13 Capacitor 14 Inverter 15 Feedback resistor 16 Buffer 17 Inverter 18 Feedback resistor 19 Buffer 20 FF
21 Counter 22 Counter 23 AND Gate 24 AND Gate 25 Inverter 26 OR Gate 27 Output Terminal 31 First Terminal 32 Second Terminal 33 Determination Unit 34 First Blocking Unit 35 Second Blocking Unit 36 Output Terminal

Claims (10)

A clock generator connected to a first oscillator or a second oscillator and generating and outputting a clock signal according to an oscillation signal from the connected oscillator,
A first terminal connected to the first oscillator or the second oscillator and receiving an oscillation signal;
A second terminal connected to the second oscillator or a predetermined potential;
An output terminal connected to the first terminal via a first signal path and a second signal path and outputting a clock signal;
The first signal path or the second terminal is connected between the first terminal and the second terminal, and depending on whether the second terminal is connected to the second oscillator or the predetermined potential. A determination unit that determines which of the two signal paths is the clock signal path;
When the first signal path is connected between the first terminal and the output terminal, and the determination unit determines that the second signal path is the path of the clock signal, the first signal path A first blocking unit that blocks the signal path;
A second cutoff that is connected between the first terminal and the output terminal in the second signal path, and that cuts off the second signal path when the second terminal is connected to the predetermined potential. And
A clock generation device comprising: In the case of generating a clock signal according to the oscillation signal from the first oscillator,
The first terminal is connected to the first oscillator;
The clock generation device according to claim 1, wherein the second terminal is connected to the predetermined potential. In the case of generating a clock signal in response to the oscillation signal from the second oscillator,
The first terminal is connected to the second oscillator;
The clock generation device according to claim 1, wherein the second terminal is connected to the second oscillator. The first blocking part is
A first counter connected to the first terminal, counting according to a signal supplied from the first terminal, and outputting an enable signal according to a count value;
A first switch connected to the first terminal and the first counter and outputting a signal supplied from the first terminal in response to the supply of the enable signal from the first counter;
Including
The second blocking part is
A second counter connected to the first terminal and the second terminal, counting according to a signal supplied from the first terminal or the second terminal, and outputting an enable signal according to the count value;
A second switch connected to the first terminal and the second counter and outputting a signal supplied from the first terminal in response to the supply of the enable signal from the second counter;
4. The clock generation device according to claim 1, comprising: When the second terminal is connected to the predetermined potential,
The second counter stops supplying the enable signal to the second switch;
The clock generation device according to claim 4, wherein the second blocking unit blocks the second signal path. When the second terminal is connected to the predetermined potential,
The first counter supplies the enable signal to the first switch;
6. The clock generation device according to claim 4, wherein the first blocking unit conducts the first signal path. 7. When the first terminal is connected to the second oscillator and the second terminal is connected to the second oscillator,
The determination unit supplies a reset signal to the first counter according to a signal supplied from the first terminal,
The first counter stops the supply of the enable signal to the first switch in response to the supply of the reset signal,
The clock generation device according to claim 4, wherein the first blocking unit blocks the first signal path. A first signal supplied from the first terminal between the first terminal and the first switch in the first signal path is binarized and supplied to the first counter and the first switch. Including buffers,
A second buffer that binarizes a signal supplied from the first terminal and supplies the signal to the second switch is provided between the first terminal and the second switch in the second signal path. The clock generation device according to any one of claims 4 to 7. Between the first terminal of the first signal path and the first buffer,
A direct current component cut section for cutting the direct current component of the signal;
A first amplitude increaser for increasing the amplitude of the signal;
The clock generation device according to claim 8, comprising: In a clock generation device including a first terminal, a second terminal, and an output terminal, a clock generation method for generating a clock signal in response to supply of an oscillation signal from a first oscillator or a second oscillator,
Connecting the first terminal to the first oscillator or the second oscillator;
Connecting the second terminal to the second oscillator or a predetermined potential;
Depending on whether the second terminal is connected to the second oscillator or the predetermined potential, the first signal path and the second of the signal paths connecting the first terminal and the output terminal Determining which of the signal paths is the signal path of the clock signal;
Blocking the first signal path when it is determined that the second signal path is the path of the clock signal;
Cutting the second signal path when it is determined that the first signal path is the path of the clock signal;
A clock generation method comprising:

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