JP2016093063A - Inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To securely exert control for making the peak value of an output voltage constant by enabling the start of excitation of a transformer through turning ON a switching element at an optimum timing all the time.SOLUTION: An inverter device is designed such that an input voltage is switched by a switching element, excitation current (drain current Id) is caused to flow in the primary-side excitation winding in an ON period (Ton1) of the switching element, and an AC waveform output voltage Vout is output from the secondary-side output winding of the transformer in an OFF period of the switching element. In the inverter device, a switching control signal Sp is inverted such that after the drain current Id of the switching element flows in a negative direction reverse to a positive direction in which the excitation current flows in a period (Tout+Tx period) of time that a switching control signal Sp is turning OFF the switching element, the switching element is turned ON (Ton2) at the timing of reaching the current value OA.SELECTED DRAWING: Figure 8

Description

  The present invention relates to an inverter device.

An inverter device is used to supply a high voltage to various devices such as a discharge tube for a large plasma display and a plasma generator.
Generally, an output power value of about several watts is often used, but an inverter device having an AC output with an output voltage of several kV and a power value of several tens of watts or more is used for a plasma generator or the like. Is done.

  As such an inverter device, for example, as described in Patent Document 1, an input voltage is switched by a switching element, an exciting current is passed through an exciting winding of a transformer, and an AC high voltage is output from the output winding of the transformer. Is used.

The inverter device described in Patent Document 1 further has a ratio (duty ratio) between the ON period and the OFF period of the switching element according to the peak value of the monitor voltage of the output voltage in order to keep the peak value of the output voltage constant. Pulse width modulation (PWM) control is performed to control the above. As the monitor voltage, a voltage generated between the terminals of the switching element is used.
The PWM control is performed by variably controlling the timing when the switching element is turned on between the time when the first half wave of the monitor voltage is completed and immediately before the second harmonic appears when the switching element is OFF. Yes.

However, in such an inverter device that outputs an alternating high voltage, the transformer is a resonant transformer, and on the secondary side, the output inductance due to the output winding, the stray capacitance between the windings, the parasitic capacitance, and the load capacitance The voltage resonance occurs due to the combined capacitance.
Due to the voltage resonance, an output voltage with a reverse polarity half-wave and a high-order decay waveform following the first half-wave of the fundamental wave is generated within the switching period, so that the switching element cannot be turned on (inhibition condition time) Occurs. As a result, the period during which the PWM control can be performed is restricted, and there is a problem that the control for making the peak value of the output voltage constant cannot be performed sufficiently.

  Even in the inverter device described in Patent Document 1, a voltage having a polarity opposite to that of the first half-wave is generated during the period from the completion of the first half-wave of the monitor voltage to immediately before the appearance of the second harmonic, and the transformer is excited. A current in the direction opposite to the excitation current flows through the winding. Therefore, even if the switching element is turned on during this period, there is a problem that the excitation current is canceled while the current in the opposite direction flows, and the excitation energy cannot be stored in the transformer.

  The present invention has been made in view of such a background. In the inverter apparatus as described above, the switching element is turned on at an optimal timing so that the excitation of the transformer can be started, and the peak value of the output voltage is kept constant. It is an object of the present invention to ensure that the control for achieving the above can be performed.

  In order to achieve the above object, the present invention uses a DC voltage or a voltage in which a pulsating current is superimposed on a DC component as an input voltage, and the input voltage is switched by a switching element. In an inverter device that outputs an AC waveform output voltage from an output winding on the secondary side of the transformer during a period in which the switching element is OFF while an excitation current is supplied to the primary side excitation winding, the switching element is turned ON / OFF When the current that flows in the direction opposite to the direction in which the excitation current flows through the switching element is generated during the period when the switching element is OFF, the switching element is turned on when the current value becomes zero. An ON timing control means is provided.

  The inverter device according to the present invention can start the excitation of the transformer by turning on the switching element at an optimal timing, and can thereby reliably perform control for making the peak value of the output voltage constant.

It is a circuit diagram which shows basic embodiment of the inverter apparatus by this invention. It is a timing chart which shows the waveform of the voltage or electric current of each part in FIG. 1, and its timing relationship. It is a timing chart which shows the relationship between the switching control signal Sp, the ON period Ton of a switching element, and the drain current Id. It is a timing chart which shows the relationship between the waveform of the switching control signal Sp and the output voltage Vout. 6 is a timing chart schematically showing various timings for switching to the next ON period Ton2 when the output voltage Vout is in the positive voltage region of the first wave and the second wave. 6 is a timing chart showing simulation results of the drain-source voltage Vds and the drain current Id of the switching element when excitation of the primary side of the transformer 3 is started in the positive voltage region of the second wave in FIG. 5. 6 is a timing chart schematically showing various timings of switching to the next ON period Ton2 when the output voltage Vout is in the negative voltage region of the first wave and the second wave. It is a timing chart which shows the relationship of the waveform of the switching control signal Sp, the drain current Id, and the output voltage Vout. 1 is a circuit diagram showing a first embodiment of an inverter device according to the present invention; FIG. FIG. 10 is a circuit diagram illustrating an example of a zero cross detection circuit 16 in FIG. 9. 10 is a flowchart illustrating an operation example of the arithmetic circuit 17 in FIG. 9. 10 is a flowchart illustrating another operation example of the arithmetic circuit 17 in FIG. 9. It is a circuit diagram which shows 2nd Embodiment of the inverter apparatus by this invention. It is a diagram which shows the relationship between the peak voltage of a simulation output voltage, and the ON period to control. It is a flowchart which shows the operation example of the arithmetic circuit 17 in FIG. 14 is a flowchart illustrating another operation example of the arithmetic circuit 17 in FIG. 13. It is a circuit diagram which shows 3rd Embodiment of the inverter apparatus by this invention. FIG. 18 is a circuit diagram showing an example of a drain current detection means 19 and a current-voltage conversion circuit 20 in FIG. FIG. 19 is a timing chart showing the relationship between the drain current Id in FIG. 18 and the detection voltage Vop that is the output voltage of the operational amplifier. 18 is a timing chart for explaining the operation of the arithmetic circuit 17 shown in FIG. 18 is a flowchart illustrating an operation example of the arithmetic circuit 17 illustrated in FIG. 17. It is a circuit diagram which shows 4th Embodiment of the inverter apparatus by this invention. 23 is a timing chart for explaining the operation of the arithmetic circuit 17 shown in FIG. It is a flowchart which shows the operation example of the arithmetic circuit 17 shown in FIG. It is a circuit diagram which shows 5th Embodiment of the inverter apparatus by this invention. It is a circuit diagram which shows 6th Embodiment of the inverter apparatus by this invention.

Hereinafter, embodiments for carrying out the present invention will be specifically described with reference to the drawings.
[Description of Summary of the Invention]
First, an outline of the present invention common to each of the embodiments described later will be described using basic embodiments of the present invention.
FIG. 1 is a circuit diagram showing a basic embodiment of an inverter device according to the present invention.
In this inverter device 1, the input voltage Vin input from the input terminals I 1 and I 2 is switched by the switching element 4, and the exciting current is applied to the exciting winding Np on the primary side of the boosting transformer 3 during the period when the switching element 4 is ON. Shed. Then, during the period when the switching element 4 is OFF, an output voltage Vout having an AC waveform is output from the output winding Ns on the secondary side of the transformer 3 and supplied to the load 2 from the output terminals O1 and O2.

  The input voltage Vin is a DC voltage or a voltage in which a pulsating current is superimposed on a DC component. The switching element 4 is an n-type channel FET in this example, and the switching control signal Sp output from the control circuit 5 is applied to the gate. The switching control signal Sp is ON during the high level period, and the low level The period is OFF. Here, ON is “on” and OFF is “off”. The control circuit 5 is a switching control IC having an oscillation circuit.

The excitation winding Np of the transformer 3 and the drain and source of the switching element 4 are connected in series to a line to which the input voltage Vin is supplied from the input terminals I1 and I2. The control circuit 5 operates by applying the input voltage Vin, outputs a switching control signal Sp in the form of a rectangular wave pulse, applies it to the gate of the switching element 4, and controls its ON / OFF.
One input terminal I1 and one output terminal O1 are both connected to a frame ground (earth) GND.

FIG. 2 is a timing chart showing the voltage or current waveform of each part in FIG. 1 and its timing relationship. The following waveforms (a) to (d) in FIG. 2 are shown.
(A) is a switching control signal Sp output from the control circuit 5; a high level period is an ON period Ton in which the switching element 4 is ON; a low level period is an OFF period in which the switching element 4 is OFF. At Toff, the ON / OFF cycle is T.
(B) is a drain current Id flowing through the switching element 4, and in the figure, the positive period is an exciting current flowing through the exciting winding Np of the transformer 3.
(C) is an alternating high voltage output voltage Vout, but shows only the first half wave (positive half wave in this example) of the fundamental wave (first wave) with its crest value greatly reduced. ing.
(D) has shown the waveform of the part corresponding to the output voltage Vout shown to (c) in the output current Io which flows into the secondary side of the trans | transformer 3. FIG.

The load 2 is, for example, an opposing electrode (passive element) of the plasma generator, and has a capacitance (load capacitance) Co. In general, it is said that atmospheric pressure plasma is generated when a voltage of 6 kV or more is applied between the electrodes at normal pressure. It is also called dielectric barrier discharge or silent discharge.
The transformer 3 is a flyback type resonant transformer. On the secondary side, an inductance (output inductance) Ls of the output winding Ns, a capacitance Cs distributed or parasitic between the windings, and an electrostatic capacitance of the load 2 are provided. A voltage resonance circuit is formed by the combined capacitance of the capacitance Co. Then, voltage resonance occurs in the voltage resonance circuit during the period when the switching element 4 is OFF. The resonance constants are the above-described output inductance Ls and capacitances Cs and Co.

Since a strong magnetic field is applied to the electrical path, and the resonance constant fluctuates due to temperature, line length deviation, etc., the output voltage Vout becomes not only a fundamental wave but also a distorted output waveform, and Fourier expansion. Then, it is decomposed into a voltage that alternates with a high order and decays.
Therefore, the output voltage Vout is an alternating voltage, and its value is in the range of several kV to several tens of kV, and the average output power is in the range of several W to several tens of kW.
In the case where the output voltage is a fundamental wave with Vout of Vout (t) = √ (2Vout · sin (ωt)), the output voltage is on a function of a sine wave. Here, the output voltage Vout is an effective value.

In general, according to Faraday's law, the drain current Id for exciting the transformer is
Vin (t) = Lp · i (t) / dt
Therefore, in a very short time, the slope of Id becomes a differential coefficient, and when the exciting inductance of the transformer 3 is Lp, the drain current Id is obtained by the following equation (1).
Id = Vin · Ton / Lp (1)
(Ton: ON period of the switching element 4, Vin: input voltage)
Since the excitation inductance Lp is constant, Id∝Vin · Ton.

Here, the excitation energy ε stored in the transformer 3 by the excitation current due to the drain current Id of the switching element 4 is obtained by the following equation (2).
ε = Lp · Id ² (2)
Substituting Id according to the expression (1) into the expression (2) yields the following expression (3).
ε = (Vin · Ton) ² / Lp (3)
Therefore, if Vin · Ton is constant, the excitation energy stored in the transformer 3 is constant, and if there is no load fluctuation, the output voltage Vout is controlled to be constant.

FIG. 3 is a timing chart showing the relationship between the switching control signal Sp (corresponding to the gate-source voltage Vgs of the switching element 4), the ON period Ton of the switching element 4, and the drain current Id.
If the input voltage Vin and the excitation inductance Lp, which is the inductance of the excitation winding Np of the transformer 3, are constant, the drain current Id, which is the excitation current, is proportional to the ON period Ton of the switching element 4, and its gradient is Vin / Lp. It is. Here, the ON period Ton is a time during which the control circuit 5 turns on the switching element 4 and excites the transformer 3. That is, it is a period during which the switching control signal Sp is at a high level.

As shown in FIG. 3, the maximum value Id1 of the drain current when the ON period of the switching element 4 is Ton1 is Id1 = (Vin / Lp) · Ton1, and the maximum value Id2 of the drain current when the ON period is Ton2. Is Id2 = (Vin / Lp) · Ton2.
Here, when Ton1> Ton2, the relationship is Id1> Id2.
Since the energy ε stored on the primary side of the transformer 3 is proportional to the square of Id as can be seen from the equation (2), the energy stored on the primary side of the transformer 3 when the maximum drain current is Id1 and Id2 is expressed as ε1. , Ε2, ε1> ε2.

Assuming that the conversion efficiency of the transformer 3 is 1, and the excitation energy ε stored on the primary side of the transformer 3 is equal to the energy released on the secondary side, ε is as follows.
ε = C · Vout ²
(Vout: output voltage, C: combined capacity of Cs and Co)
Thus, Vout = √ (ε / C), and Vout is determined by the relationship between ε and C.
As shown in the equation (3) described above, ε has a relationship that depends on (Vin · Ton. Therefore, if the input voltage Vin is constant, the excitation energy ε stored on the primary side of the transformer 3 is It can be controlled linearly according to the width of the ON period Ton.

  Since the secondary side of the transformer 3 is a resonance circuit using voltage resonance, the output voltage Vout is continuously attenuated because of the resonance state. The amount of attenuation is considered to be only the amount of power consumption due to the resistance component of the output. The attenuated output transient voltage is continued during the OFF period Toff of the switching element 4, as shown in FIG.

Then, as shown in FIG. 5, after the switching control signal Sp is switched from the high level ON period Ton1 to the low level OFF period, when the output voltage Vout is in the positive voltage region indicated by hatching, It cannot be switched to the ON period Ton2.
When the output voltage Vout is in the positive voltage range, the switching control signal Sp is switched to the high level, the switching element 4 is turned on, and the primary side excitation of the transformer 3 is started. A short circuit will occur. For this reason, an excessive current flows through the transformer 3, thereby magnetically saturating the core of the transformer 3, and a large current flows through the circuit.
FIG. 5 schematically shows various timings for switching to the next ON period Ton2 when the output voltage Vout is in the positive voltage region of the first wave and the second wave.

FIG. 6 shows the voltage Vds of the switching element 4 when the switching control signal Sp is switched to the high level (ON) and the primary side excitation of the transformer 3 is started in the positive voltage region of the second wave in FIG. The simulation result of the drain current Id is shown. The voltage Vds is a voltage generated between the drain and source of the switching element 4 in synchronization with the output voltage Vout.
At this time, the voltage of the second wave is short-circuited, the core of the transformer 3 exceeds the limit value of NI (the product of the number of excitation windings Np and the maximum current value on the primary side), causes magnetic saturation, and the drain current Id is excessive. The ringing current is repeated. Therefore, the output voltage waveform cannot be output continuously.

Therefore, the switching control signal Sp is changed from the low level to the high level, and the switching timing of the switching element 4 from the OFF period to the ON period is a period in which the output voltage Vout is always in the negative voltage region as shown in FIG. It will be necessary.
FIG. 7 schematically shows various timings for switching to the next ON period Ton2 when the output voltage Vout is in the negative voltage region of the first wave and the second wave.
However, when the output voltage Vout is in the negative voltage region shown by hatching in FIG. 7, if the switching element 4 is turned ON, the drain current Id is in the negative direction when the direction in which the exciting current flows through the transformer 3 is positive. Will flow into.

Therefore, even when switching is performed to set the switching control signal SP to high level and turn on the switching element 4 at any timing when the output voltage Vout is in the negative voltage region, the period during which the drain current Id flows in the negative direction is 3 does not store excitation energy.
The reason is that a current in the direction opposite to the direction of the excitation current flowing on the primary side of the transformer 3 flows, thereby canceling the excitation current, and excitation energy is not stored in the transformer 3.

Therefore, as shown in FIG. 8, the switching element 4 is switched ON during a period in which the output voltage Vout is in the negative voltage region (shaded region) of the first wave, that is, a period in which the drain current Id is flowing in the negative direction. However, it becomes a useless period in which excitation is not possible until the current becomes 0A.
However, when the output voltage Vout is switched on in the positive voltage region of the second wave shown in FIG. 5, the drain current Id becomes excessive as described above, and the ringing current is repeated and continues. The output voltage waveform cannot be output.

  Therefore, the optimal timing is to turn on the switching element 4 at a timing when the current value becomes zero (0 A) after the drain current Id flows in the negative direction during the period when the switching element 4 is OFF. I understood that. Accordingly, the excitation of the transformer 3 can be started at an optimal timing, the excitation energy accumulated in the transformer 3 can be effectively controlled, and the peak value of the output voltage can be easily controlled to be constant. The timing at which the current value becomes zero (0 A) after the drain current Id flows in the negative direction described above naturally includes the timing within a predetermined error range.

When the drain current Id flows in the negative direction, the current value becomes zero (0 A) at the same time as the ON period Ton1 immediately after the first wave of the output voltage Vout becomes 0 V. It turns out that it is the time. This time is indicated by Tx in FIG. 8, and Tx≈Ton1.
Therefore, the control circuit 5 shown in FIG. 1 operates as follows after switching the switching control signal Sp from the high level (Ton1) to the low level (Toff).
That is, after a period (referred to as “output pulse width”) Tout in which the first wave positive voltage of the output voltage Vout is generated, at the time when the same time Tx as the immediately preceding ON period Ton1 has elapsed, the switching control signal Sp Is switched to the high level (Ton2).
Therefore, the control circuit 5 is a means for controlling the switching element ON / OFF, and after the drain current Id of the switching element 4 flows in the negative direction, the switching is performed at the timing when the current value becomes zero (0 A). It is also an ON timing control means for turning on the element 4.

Therefore, for example, after switching the switching element 4 to OFF, the zero cross points (Pz1, Pz2, Pz3, etc. shown in FIG. 8) of the output voltage Vout are detected. Then, when the same time Tx as the immediately preceding ON period Ton1 has elapsed from the time when the second zero cross point Pz2 is detected, the switching element 4 may be switched to ON.
Alternatively, the switching element 4 may be switched ON at the third zero cross point Pz3. Further, the drain current Id may be actually monitored during the period when the switching element 4 is OFF, and after that occurs, the switching element 4 may be switched ON at a timing when the current value becomes zero. Specific embodiments thereof will be described later.

In this case, the cycle when the control circuit 5 turns the switching element 4 ON / OFF, that is, the cycle T of the switching control signal Sp shown in FIG. 8 is as follows.
T = Output pulse width Tout + ON period Ton × 2
Here, when the ON period Ton changes, Ton in the above equation is the immediately preceding Ton1. When the control circuit 5 controls the ON period Ton of the switching element 4 to be constant, the excitation energy stored in the transformer 3 during each ON period Ton should always be constant. However, the output pulse width Tout varies depending on the generation state of the output voltage Vout when the switching element 4 is turned off. Therefore, the cycle T also varies according to the output pulse width Tout. This is caused by environmental changes such as temperature and humidity, load fluctuations, changes with time, and the like.

However, the cycle T for ON / OFF control of the switching element 4 is set between the output pulse width Tout in which the output voltage is generated in the period Toff in which the switching element 4 is OFF, and the period Ton in which the switching element 4 is ON. Control to be the sum of 2 times.
When the output pulse width Tout becomes longer than the reference period, the peak value of the output voltage Vout is generally higher than the reference value. At this time, the period T is longer than the reference period, but the ON period Ton is constant. Therefore, the duty ratio, which is the ratio of the ON period in one period, is reduced, and functions to lower the peak value of the output voltage Vout.

Conversely, when the output pulse generation period Tout is shorter than the reference period, the peak value of the output voltage Vout is generally lower than the reference value. At this time, although the period T is shorter than the reference period, the ON period Ton is constant, so the duty ratio, which is the ratio of the ON period in one period, increases, and functions to increase the peak value of the output voltage Vout.
Therefore, even if PWM control for detecting the peak value (peak value) of the output voltage Vout and performing feedback control on the duty ratio of the switching control signal Sp so as to make it constant is performed, control close to that is automatically performed. Will be made.

  In order to control the ON period Ton of the switching element 4 to be constant, after the control circuit 5 sets the switching control signal Sp to the high level to turn on the switching element 4, the switching circuit 4 is always switched to the low level after the predetermined ON period Ton. The element 4 may be turned off. In this case, Ton2 = Ton1 (constant) in FIG. Therefore, the cycle T (= output pulse width Tout + ON period Ton × 2) for turning ON / OFF the switching element 4 changes according to the fluctuation of the output pulse width Tout.

Or you may make it change ON period Ton of the switching element 4 according to the fluctuation | variation of the output pulse width Tout so that the control circuit 5 may keep the period T which turns ON / OFF the switching element 4 constant.
That is, when the output pulse width Tout becomes longer than the reference period, if the ON period Ton is shortened and the period is kept constant, the duty ratio, which is the ratio of the ON period in one period, becomes small, and the output voltage Vout It works to lower the peak value.

Conversely, when the output pulse generation period Tout is shorter than the reference period, if the ON period Ton is lengthened and the period T is kept constant, the duty ratio, which is the ratio of the ON period in one period, increases. It functions to increase the peak value of the voltage Vout.
Therefore, even in this case, it is always possible to detect the peak value (peak value) of the output voltage Vout and perform the feedback control of the duty ratio of the switching control signal Sp so as to make it constant. Control close to that is automatically performed.

To keep the switching element 4 ON / OFF controlled at a constant period T, the current ON is turned on when the time corresponding to the constant period T has elapsed from the time when the previous ON period Ton1 is switched to the OFF period. It is only necessary to switch from the period Ton2 to the OFF period.
In this case, the period T for turning on / off the switching element 4 is as follows.
T = output pulse width Tout + ON period Ton1 + Ton2 = constant

As described above, the inverter device according to the basic embodiment of the present invention can start the excitation of the transformer 3 by always turning on the switching element 4 at the optimum timing. Thereby, the excitation energy on the primary side of the transformer 3 can be controlled in proportion to the ON period Ton of the switching element 4 which is the transformer excitation time.
Therefore, as described above, if the control circuit 5 controls the ON period Ton of the switching element 4 to be constant, or controls the ON period so that the cycle T for ON / OFF control of the switching element 4 is constant, the output An effect of suppressing the fluctuation of the peak value of the voltage Vout is obtained.

Below, each concrete embodiment of the inverter device by this invention is described.
[First Embodiment]
FIG. 9 is a circuit diagram showing a first embodiment of an inverter device according to the present invention. 9, parts that are the same as the parts in FIG. 1 are given the same reference numerals, and descriptions thereof are omitted. The same applies to the circuit diagrams of the following embodiments. Although the configuration of the inverter device differs depending on each embodiment, the inverter device 1 is used for convenience.

  The transformer 13 of the inverter device 1 shown in FIG. 9 includes a secondary winding (also referred to as a tertiary winding) Nf in addition to the output winding Ns on the secondary side. The number of turns of the dependent winding Nf is extremely small compared to the number of turns of the output winding Ns. Therefore, a simulated output voltage (monitor voltage) Vf having a waveform that changes in synchronization with the output voltage Vout generated in the output winding Ns and whose peak value is much smaller than the output voltage Vout is generated in the dependent winding Nf. To do.

  The crest value of the simulated output voltage Vf is 1/100 or less of the crest value when the output voltage Vout is a high voltage corresponding to a high voltage or extra high voltage, and is preferably smaller than about 1/1000. Therefore, for example, when the peak value of the output voltage Vout is 10 kV, the peak value of the simulated output voltage Vf is set to a voltage of 100 V or less, preferably 10 V or less. However, the output pulse width of the simulated output voltage Vf is the same as the output pulse width of the output voltage Vout during the (output period), and its peak value varies in proportion to the peak value of the output voltage Vout. Therefore, the output voltage Vout can be monitored by the simulated output voltage Vf.

The zero-cross detection circuit 16 receives the simulated output voltage Vf generated in the dependent winding Nf of the transformer 13 and receives a zero-cross point (Pz1, Pz2, Pz3, etc. shown in FIG. 8). ) And the zero cross detection signal Zx is input to the arithmetic circuit 17.
The arithmetic circuit 17 is a circuit having a microcomputer composed of a CPU, a ROM, a RAM, etc., and manages the timing when the control circuit 15 switches the switching control signal Sp from low level to high level and switches the switching element 4 from OFF to ON. To do.

  For example, the zero-cross detection signal Zx detected by the zero-cross detection circuit 16 is counted from the time when the switching element 4 is turned off. When the second zero-cross point (Pz2 shown in FIG. 8) is counted and the same period (in this case, a fixed period) as the previous ON period of the switching element 4 has elapsed, the ON timing control signal Son Is input to the FB terminal of the control circuit 15. Thereby, the control circuit 15 inverts the switching control signal Sp from the low level to the high level, and turns on the switching element 4.

That is, at the timing when the drain current Id in the reverse direction shown in FIG. 8 becomes substantially zero (0 A), the switching element 4 is turned on, and excitation is started by supplying an excitation current to the excitation winding Np of the transformer 13.
When a certain ON period elapses, the control circuit 15 inverts the switching control signal Sp from the high level to the low level to turn off the switching element 4.

Alternatively, the arithmetic circuit 17 outputs the ON timing control signal Son and inputs it to the FB terminal of the control circuit 15 when the count value of the zero cross detection signal Zx from the zero cross detection circuit 16 becomes “3”. Also good. When this count value is “3”, the drain current Id in the reverse direction is the time when the third zero cross point (Pz3 shown in FIG. 8) is counted from the time when the switching element 4 is turned off. This is the timing when it becomes substantially zero (0A).
In the first embodiment, the dependent winding Nf, the zero cross detection circuit 16 and the arithmetic circuit 17 constitute an ON timing control means, and the control circuit 15 constitutes a means for ON / OFF control of the switching element. .

A known circuit can be used as the zero-cross detection circuit 16, and an example thereof is shown in FIG. The zero-cross detection circuit 16 uses a two-circuit photocoupler 60 having two pairs of light-emitting elements 61 and 62 such as light-emitting diodes and light-receiving elements 63 and 64 such as phototransistors. The emitters of the light receiving elements 63 and 64 are connected in common and grounded, and the point a having the collector connected in common is connected to a positive power source + V through a pull-up resistor Ra. The zero cross detection signal Zx is output from the point a.
Then, the simulated output voltage Vf generated in the dependent winding Nf of the transformer 13 shown in FIG. 9 is applied to the light emitting elements 61 and 62 of the photocoupler 60 through the variable resistor VR for sensitivity adjustment, and full-wave rectification, insulation, And logic level conversion at once.

  The light emitting element 61 emits light when a positive voltage equal to or higher than the light emitting level is applied, and the light emitting element 62 emits light when a negative voltage whose absolute value is equal to or higher than the light emitting level is applied. Therefore, when the absolute value of the simulated output voltage Vf is equal to or higher than the light emission level (a region other than the vicinity of the zero cross point), one of the light emitting elements 61 and 62 emits light. As a result, one of the light receiving elements 63 and 64 receives the light and becomes conductive, so that the point a is grounded and becomes zero level.

However, near the zero cross point where the absolute value of the simulated output voltage Vf is less than or equal to the light emission level, the light emitting elements 61 and 62 do not emit light. It becomes high level by the voltage of the power supply + V.
Therefore, a pulse-like zero cross detection signal Zx centering on the zero cross point from the point a is output. The detection sensitivity can be adjusted by the variable resistor VR.
The zero-cross detection signal Zx can be directly input to the arithmetic circuit 17 of FIG. 9 and counted. However, a steeper trigger pulse is generated at the zero-cross point through the Schmitt trigger circuit and input to the arithmetic circuit 17. Even better.

  The simulated output voltage Vf is an alternating waveform voltage that changes in synchronization with the output voltage Vout output from the output winding Ns of the transformer 3. Therefore, the zero cross point detected by the zero cross detection circuit 16 should coincide with the zero cross point of the output voltage Vout output from the output winding Ns. That is, the zero cross detection circuit 16 can detect the zero cross points (Pz1, Pz2, Pz3 shown in FIG. 8) of the output voltage Vout of the inverter device 1.

  At the zero cross point Pz1 immediately after the switching control signal Sp shown in FIG. 8 is switched from the high level to the low level, the zero cross detection signal Zx by the zero cross detection circuit 16 shown in FIG. It only changes to. However, the arithmetic circuit 17 may count the falling edge of the zero cross detection signal Zx as the first zero cross point Pz1. In this embodiment, the zero cross point is counted by the soft counter function of the arithmetic circuit 17 in FIG.

An example of the operation as the ON timing control means by the arithmetic circuit 17 will be described with reference to the flowchart of FIG. The arithmetic circuit 17 in this case has a counter function for counting the zero-cross point and a timer function for measuring a predetermined time Ton corresponding to the ON period of the switching element 4.
When the power of the inverter device 1 shown in FIG. 9 is turned on, the control circuit 15 starts to operate, outputs a switching control signal Sp at a preset period and ON period at startup, and turns on the switching element 4. Turn off and start. At the same time, the arithmetic circuit 17 starts the operation shown in FIG.

In step S1, the input of the zero cross detection signal Zx from the zero cross detection circuit 16 is waited. When the zero cross detection signal Zx is input, the counter is incremented (+1) in step S2. The counter is reset before the operation ends and is in a restart state.
Thereafter, in step S3, it is determined whether or not the count value is “2”. If it is not “2”, the process returns to step S1 to repeat the above-described operation.

When the count value becomes “2” in step S3, it can be determined that the second zero-cross point Pz2 in FIG. 8 has been detected. Therefore, the timer is started in step S4, and the predetermined time Ton corresponding to the ON time is started. To do. In step S5, a predetermined time Ton is awaited. In this case, if the predetermined time Ton is subtracted with the clock signal from the state in which the timer is set, the predetermined time Ton has elapsed when the value of the timer becomes “0”.
If it is determined in step S5 that the predetermined time Ton has elapsed, an ON timing control signal Son is output in step S6 and input to the FB terminal of the control circuit of FIG. Thereby, the control circuit 15 inverts the switching control signal Sp from the low level to the high level, and turns on the switching element 4.

Thereafter, after a slight wait time in step S7, the counter is reset and restarted, and the timer is also reset and stopped.
Then, in step S8, it is checked whether or not the power is turned off. If the power is turned off, the operation is terminated. Until the power is turned off, the process returns to step S1 and the above-described operation is repeatedly executed.

FIG. 12 is a flowchart illustrating another simpler operation example by the arithmetic circuit 17.
In FIG. 12, steps that perform the same judgment or processing as those in FIG. 11 are denoted by the same step symbols, and steps that are somewhat different are denoted by “′” in step symbols in FIG. 11. Show. In this case, the arithmetic circuit 17 does not use the timer function.

In the case of this operation example, when the arithmetic circuit 17 starts operation, the zero cross detection signal is counted in steps S1 and S2, and when the count value becomes “3” in step S3 ′, the third zero cross point Pz3 in FIG. Is detected.
In step S6, the ON timing control signal Son is output and input to the FB terminal of the control circuit 15. Thereby, the control circuit 15 inverts the switching control signal Sp from the low level to the high level, and turns on the switching element 4.
Thereafter, the counter is reset and restarted in step S7 ', and the process returns to step S1 until the power is turned off, and the above-described operation is repeatedly executed.

In this embodiment, the control circuit 15 inverts the switching control signal Sp from the low level to the high level and turns on the switching element 4. Then, the control circuit 15 sets the switching control signal Sp to the high level when a certain ON period Ton elapses. Invert from low to low. Thereby, the ON period of the switching element 4 can be controlled to be constant, and the ON / OFF cycle T of the switching element 4 can be changed in accordance with the fluctuation of the output pulse width Tout described above with reference to FIG.
Alternatively, the signal is inverted from the high level to the low level when a predetermined period T elapses from the time when the switching control signal Sp is immediately set to the low level. Thereby, the ON period of the switching element 4 can be changed according to the fluctuation of the output pulse width Tout, and the ON / OFF cycle T of the switching element 4 can be kept constant.

The inverter device 1 according to the first embodiment can start the excitation of the transformer 13 by always turning on the switching element 4 at an optimal timing, regardless of the operation described above by the arithmetic circuit 17. Thereby, the excitation energy on the primary side of the transformer 13 can be controlled completely in proportion to the ON period Ton of the switching element 4 which is the transformer excitation time.
Then, as described above, if the control circuit 15 controls the ON period Ton of the switching element 4 to be constant or controls the ON period so that the cycle T for ON / OFF control of the switching element 4 is constant, the output An effect of suppressing the fluctuation of the peak value of the voltage Vout is obtained.
In addition, since the pulse width variation of the simulated output voltage of the waveform corresponding to the output voltage is constantly monitored and feedback control is performed, it is possible to obtain a highly accurate and stable waveform output voltage against load variations. it can.

[Second Embodiment]
Next, a second embodiment of the inverter device according to the present invention will be described with reference to FIGS.
FIG. 13 is a circuit diagram of the inverter device. The difference from the first embodiment shown in FIG. 9 is that a peak voltage detection circuit 18 is provided and that the control circuit 25 has a PWM input terminal. . The arithmetic circuit 17 also has more functions related to ON period control, but the same reference numerals are used for convenience. The same applies to other embodiments described later.

The peak voltage detection circuit 18 detects the peak voltage of the simulated output voltage Vf generated in the dependent winding Nf of the transformer 13 (corresponding to the peak value voltage of the output voltage Vout), and calculates the peak voltage Vp of the low voltage. 17 to input. This peak voltage Vp is extremely low compared to the peak value of the output voltage Vout, and can be easily detected.
As this peak voltage detection circuit 18, for example, a known peak hold circuit is used. If the same hold value continues for a specified time or more, it is output as the peak voltage Vp, and the hold value is reset after a predetermined time. . The arithmetic circuit 17 may determine and reset the peak voltage Vp.

The arithmetic circuit 17 takes in the peak voltage Vp detected by the peak voltage detection circuit 18 to the A / D port together with the operation as the ON timing control means similar to the first embodiment described above. And according to the value of the peak voltage Vp, the operation | movement as an ON period control means which controls the ON period of the switching element 4 is also performed.
Therefore, the arithmetic circuit 17 converts an analog peak voltage Vp into a digital value, an A / D conversion circuit, and converts the ON time digital information determined according to the peak voltage Vp into an analog ON period control signal Sw. A D / A conversion circuit is also provided.

Here, the peak voltage Vp and the ON period are controlled to have an inversely proportional relationship as shown in FIG. 14, and the ON period is shortened when the peak voltage Vp is high, and the ON period is lengthened when the peak voltage Vp is low.
The operation of the arithmetic circuit 17 in the inverter device 1 shown in FIG. 13 will be described with reference to the flowchart of FIG. In each step of FIG. 15, the same step number is assigned to a step that performs the same determination or processing as each step in FIG. 11 described above.

When the inverter device 1 is activated, the arithmetic circuit 17 starts the process of FIG. Then, the zero cross detection signal Zx is counted in steps S1 and S2, and the peak voltage Vp is detected in step S11 until the count value becomes “2” in step S3, and the peak voltage Vp is determined in step S12. Remember.
This is because the simulated output voltage Vf corresponding to the output voltage Vout shown in FIG. 8 is generated during the period between the first cell crossing point Pz1 and the second zero crossing point Pzx2, and the peak voltage Vp during that period. Is detected.

  When the count value becomes “2” in step S3, the arithmetic circuit 17 starts a timer, and waits for a predetermined time Ton corresponding to the previous ON period of the switching element 4 to elapse in step S5. When the predetermined time Ton elapses, the ON timing control signal Son is output in step S6 and input to the FB terminal of the control circuit of FIG. Thereby, the control circuit 15 inverts the switching control signal Sp from the low level to the high level, and turns on the switching element 4.

Subsequently, in step S13, the arithmetic circuit 17 determines the ON period according to the peak voltage Vp stored in step S12. At this time, based on the relationship between the peak voltage Vp and the ON period shown in FIG. 14, the ON period can be determined by looking up a table stored in advance for the peak voltage Vp or by calculation.
However, simply, the ON period can be quickly determined by comparing the value of the peak voltage Vp with the reference value Vr corresponding to the specified peak value and determining the ON period as follows.
That is, when the value of the peak voltage Vp is larger than the reference value (Vp> Vr), the ON period is shortened by the set period (Δt) from the previous time, and when it is smaller than the reference value (Vp <Vr), the ON period is changed to the previous time. It is made longer by a set period (Δt). When the value of the peak voltage Vp is the same as the reference value Vr (Vp = Vr), the ON period is made the same as the previous time.

  In step S14, the arithmetic circuit 17 outputs an ON period control signal Sw indicating the determined ON period, and inputs it to the PWM terminal of the control circuit 25 shown in FIG. Accordingly, the control circuit 15 sets the switching control signal Sp to the high level, and then inverts the switching control signal Sp to the low level after the ON period transmitted by the ON period control signal Sw, thereby turning the switching element 4 OFF. The ON period control signal Sw is, for example, an analog voltage corresponding to the length of the ON period.

Thereafter, in step S7, the arithmetic circuit 17 resets the counter to a restart state after a slight wait time, and resets the timer to a stop state.
Then, in step S8, it is checked whether or not the power is turned off. If the power is turned off, the operation is terminated. Until the power is turned off, the process returns to step S1 and the above-described operation is repeatedly executed.

  Next, another operation example by the arithmetic circuit 17 of the second embodiment, that is, a simpler operation example combined with the operation example described with reference to FIG. 12 in the first embodiment will be described with reference to FIG. . FIG. 16 is a flowchart showing the operation of the arithmetic circuit 17 in that case, and the same step numbers are assigned to the steps for performing the determination or processing equivalent to the steps in FIGS.

The operation example shown in FIG. 16 by the arithmetic circuit 17 is different from the operation example described with reference to FIG. 15. When the count value is determined to be “2” in step S3, instead of steps S4 and S5 in FIG. In step S3 ′, the process waits for the count value to become “3”.
When the count value becomes “3” in step S3 ′, it is determined that the third zero cross point Pz3 shown in FIG. 8 has been reached, and the ON timing control signal Son is output in step S6.
The subsequent processing is almost the same as in the case of FIG. 15 described above. However, since the timer function is not used, only the counter is reset and restarted in step S7 ′ instead of step S7 in FIG. It's okay.

  The inverter device 1 according to the second embodiment can start the excitation of the transformer 13 by always turning on the switching element 4 at the optimum timing, regardless of the operation described above by the arithmetic circuit 17. Thereby, the excitation energy on the primary side of the transformer 13 can be controlled completely in proportion to the ON period Ton of the switching element 4 which is the transformer excitation time.

Further, the current primary side excitation of the transformer 13 detects the peak voltage Vp of the simulated output voltage Vf corresponding to the secondary side output voltage Vout generated during the period when the switching element 4 is OFF, and according to the value. The next ON period of the switching element 4 is controlled.
Therefore, PWM control can be reliably performed by the arithmetic circuit 17 and the control circuit 25 so as to keep the peak value of the output voltage Vout constant.
However, in this case, the cycle T for ON / OFF control of the switching element 4 is the output pulse width Tout + ON period Ton1 + Ton2, and changes depending on the fluctuation of the output pulse width and the increase / decrease of the ON period of the switching element 4.

[Third Embodiment]
Next, a third embodiment of the inverter device according to the present invention will be described with reference to FIGS.
FIG. 17 is a circuit diagram of the inverter device. As in the basic embodiment shown in FIG. 1, this inverter device 1 uses a transformer 3 that is not provided with a dependent winding Nf, and in the same way as in the second embodiment shown in FIG. Is used.

  Then, the drain current Id flowing through the switching element 4 is detected, the arithmetic circuit 17 monitors the detected value, and outputs the ON timing control signal Son. That is, during the period when the switching element 4 is OFF, after the drain current Id flows in the direction opposite to the direction in which the exciting current flows through the transformer 3, the arithmetic circuit 17 is turned on at the timing when the current value becomes zero. Is input to the control circuit 15 to the FB terminal. Thereby, the control circuit 15 inverts the switching control signal Sp from the low level to the high level, and turns on the switching element 4.

Therefore, in the inverter device 1 shown in FIG. 17, the drain current detection means 19 for detecting the drain current Id flowing through the switching element 4 and the current-voltage conversion for converting the detected current id into a voltage. A circuit 20 is provided.
FIG. 18 is a circuit diagram showing an example of the drain current detection means 19 and the current-voltage conversion circuit 20. The drain current detection means 19 uses a current transformer. Therefore, in the description of FIG.

  The current transformer 19 has the primary winding N1 interposed in series between the source of the switching element 4 and the frame ground. When the turns ratio of the primary winding N1 and the secondary winding N2 is n: 1, a current that is 1 / n of the current flowing through the primary winding N1 flows through the secondary winding N2. Therefore, when the drain current Id flows through the primary winding N1 of the current transformer 19, the current id = Id / n flows through the secondary winding N2, and the drain current Id can be detected.

The direction of the drain current indicated by an arrow in FIG. 18 is a direction in which an excitation current flows through the excitation winding Np of the transformer 3 during the ON period Ton of the switching element 4, and is the direction of the positive drain current Id shown in FIG. . However, after the switching element 4 enters the OFF period Toff, after the output pulse width Tout, the negative drain current Id shown in FIG. 19 flows in the reverse direction through the source-drain capacitance of the switching element 4. At that time, the direction of the current id flowing through the secondary winding N2 of the current transformer 19 is also opposite to the direction indicated by the arrow in FIG.
The current id flows through the resistor R1 and is converted to the voltage Vd. The voltage Vd is input to the inverting input terminal of the operational amplifier 21 and amplified. The DC bias voltage Vb from the bias voltage circuit 22 is input to the non-inverting input terminal of the operational amplifier 21. As a result, the output detection voltage Vop is biased by the bias voltage Vb as shown in FIG.

A feedback resistor R2 is connected between the output terminal and the inverting input terminal of the operational amplifier 21 shown in FIG. The operational amplifier 21, the bias voltage circuit 22, and the resistors R1 and R2 constitute a current / voltage conversion circuit 20. The current / voltage conversion circuit 20 converts the value of the current id detected by the current transformer 19 serving as a current detection means into a voltage value obtained by adding the bias voltage Vb, and detects the detected voltage Vop shown in FIG. To.
FIG. 19 is a timing chart showing the relationship between the drain current Id in FIG. 18 and the detection voltage Vop that is the output voltage of the operational amplifier 21.

The operation of the arithmetic circuit 17 shown in FIG. 17 in this embodiment will be described with reference to the timing chart of FIG. 20 and the flowchart of FIG.
The arithmetic circuit 17 in this embodiment monitors the detection voltage Vop converted into a voltage value obtained by adding the bias voltage Vb by detecting the drain current Id of the switching element 4.
Then, after the voltage value of the detection voltage Vop reaches the preset reference voltage TH0 shown in FIG. 20, the drain current value is equal to 0 from the reference voltage TH0 (in this example, the bias voltage Vb). The time point at which two different threshold voltages TH1 and TH2 are reached is monitored. Thereby, after the voltage value of the detection voltage Vop sequentially exceeds the threshold voltages TH1 and TH2, the signal for turning on the switching element 4 is generated when a predetermined delay time td has elapsed. That is, the ON timing control signal Son is inverted from the low level to the high level.

Therefore, when the inverter device 1 shown in FIG. 17 is activated, the arithmetic circuit 17 starts the operation of the flowchart shown in FIG. The arithmetic circuit 17 always captures the detection voltage Vop corresponding to the drain current Id from the current-voltage conversion circuit 20 into the A / D port.
Then, in step S21, the arithmetic circuit 17 waits for the detected voltage Vop to become equal to or lower than the reference voltage TH0. When the detection voltage Vop becomes equal to or lower than the reference voltage TH0, the process waits for the detection voltage Vop to become the threshold voltage TH1 in step S22. When the detection voltage Vop reaches the threshold voltage TH1, in step S23, it waits for the detection voltage Vop to become a threshold voltage TH2 (TH2> TH1) higher than the threshold voltage TH1.

When the detection voltage Vop reaches the threshold voltage TH2, it immediately exceeds the threshold voltage TH2, so that the arithmetic circuit 17 outputs the ON timing control signal Son in step S25 when the delay time td preset in step S24 elapses from that point. The control circuit 15 is input to the FB terminal.
Thereby, the control circuit 15 inverts the switching control signal Sp from the low level to the high level, and turns on the switching element 4.

As the delay time td, an estimated time (a very short time) until the detection voltage Vop reaches the bias voltage Vb corresponding to the value of the drain current Id from the threshold voltage TH2 is set and stored in the memory. .
The arithmetic circuit 17 then checks whether or not the power supply is OFF in step S26, and if it is OFF, the processing is terminated, but if it is not OFF, the process returns to step S21 and repeats the above-described operation.
The timing at which the control circuit 15 turns the switching element 4 from ON to OFF is the same as in the first embodiment described with reference to FIG. 9 or the like, or the ON period Ton of the switching element 4 is made constant or ON / OFF control is performed. Control may be performed so that the period T is constant.

According to the third embodiment, since the change in the detection voltage Vop of the drain current Id during the period in which the switching element 4 is OFF is monitored and the timing at which the switching element 4 is turned ON is determined, optimal switching control is performed. It can be performed with high accuracy.
That is, the switching control signal Sp can be switched at the latest timing when the drain current Id changes from the negative direction to the positive direction, and the excitation accumulated in the transformer 3 according to the width of the ON period Ton of the switching element 4. Energy can be controlled efficiently.
Thereby, the same effect as the inverter device of the first embodiment described with reference to FIG.

[Fourth Embodiment]
Next, a fourth embodiment of the inverter device according to the present invention will be described with reference to FIGS.
FIG. 22 is a circuit diagram of the inverter device. As in the second embodiment shown in FIG. 13, this inverter device 1 uses a transformer 13 provided with a dependent winding Nf, and has a zero-cross detection circuit 16 and a peak voltage detection circuit 18. The control circuit 25 has an FB terminal and a PWM terminal. Further, similarly to the third embodiment shown in FIG. 17, a drain current detection means 19 and a current-voltage conversion circuit 20 are also provided. Configuration examples and operations of these circuits are the same as those in the second and third embodiments described above.

Therefore, the inverter device 1 of the fourth embodiment shown in FIG. 22 combines the ON timing control means of the switching element 4 according to the third embodiment and the ON period control means of the switching element 4 according to the second embodiment. It has a function.
Therefore, the arithmetic circuit 17 in FIG. 22 performs the operation related to the ON timing control according to the third embodiment and the operation related to the ON period control according to the second embodiment.

The operation of the arithmetic circuit 17 will be described with reference to the timing chart shown in FIG. 23 and the flowchart shown in FIG.
FIG. 23 is a timing chart similar to FIG. 20 used in the description of the third embodiment.
In the flowchart of FIG. 24, the same step numbers are assigned to the steps for performing the same determination or processing as those of the flowcharts of FIGS.
When the inverter device 1 shown in FIG. 22 is activated, the arithmetic circuit 17 starts the operation shown in the flowchart of FIG.

When the zero-cross detection signal Zx is input from the zero-cross detection circuit 16 in step S1, the arithmetic circuit 17 increments the counter in step S2. Then, before the count value becomes “2” in step S3, the peak voltage Vp by the peak voltage detection circuit 18 is determined in step S11, and the peak voltage Vp is stored in step S12.
This is the period between the first zero cross point Pz1 and the second zero cross point Pz2 of the simulated output voltage Vf shown in FIG. 24. The peak voltage Vp of the simulated output voltage Vf (corresponding to the peak value of the output voltage Vout). Is to detect and memorize it.

When the count value becomes “2” in step S3, the simulated output voltage Vf shown in FIG. 23 has reached the second zero cross point Pz2. Therefore, from this point, the arithmetic circuit 17 monitors the detection voltage Vop by the drain current detection means 19 and the current-voltage conversion circuit 20.
Then, when the detection voltage Vop becomes the threshold voltage TH1 shown in FIG. 23 in step S22 and then becomes the threshold voltage TH2 (TH2> TH1) in step S23, the detection voltage Vop is delayed by the delay time td set in advance in step S24. When the delay time td has elapsed, the process proceeds to step S25, where the ON timing control signal Son is output and input to the FB terminal of the control circuit 15.
Thereby, the control circuit 15 inverts the switching control signal Sp from the low level to the high level, and turns on the switching element 4.

In step S13, the arithmetic circuit 17 determines the ON period Ton according to the peak voltage Vp stored in step S12. The determination method is based on any one of the methods described in the process of step S13 of FIG. 15 in the second embodiment.
In step S14, the arithmetic circuit 17 outputs an ON period control signal Sw indicating the determined ON period, and inputs it to the PWM terminal of the control circuit 25 shown in FIG. Accordingly, the control circuit 15 sets the switching control signal Sp to the high level, and then inverts the switching control signal Sp to the low level after the ON period transmitted by the ON period control signal Sw, thereby turning the switching element 4 OFF. The ON period control signal Sw is, for example, an analog voltage corresponding to the length of the ON period.

Thereafter, the arithmetic circuit 17 resets the counter to restart in step 7 ', and checks in step S8 whether the power is turned off. When the power is turned off, the operation is terminated. Until the power is turned off, the process returns to step S1, and the above-described operation is repeatedly performed.
According to the inverter device 1 of the fourth embodiment, both the effects of the second embodiment and the effects of the third embodiment described above can be achieved.

[Fifth Embodiment]
Next, a fifth embodiment of the inverter device according to the present invention will be described with reference to FIG.
FIG. 25 is a circuit diagram of the inverter device. This inverter device 1 is obtained by adding a diode D1 and a peak voltage detection circuit 28 to the inverter device 1 of the third embodiment shown in FIG.
The voltage at the connection point between the exciting winding Np of the transformer 3 and the drain side of the switching element 4, that is, the voltage Vds between the terminals of the switching element 4 (between the drain and source) is monitored by the peak voltage detection circuit 28 through the diode D1. . Then, the peak voltage Vp ′ of the positive waveform portion is detected.

The voltage Vs has a waveform that changes in synchronism with the output voltage Vout in the same manner as the simulated output voltage Vf described above, and the peak value is orders of magnitude smaller than the peak value of the output voltage Vout (for example, 1/1000 or less). ) Simulated output voltage. The peak value of the voltage Vs during the period when the switching element 4 is OFF (corresponding to the peak value of the output voltage Vout) is detected by the peak voltage detection circuit 28 and input to the A / D port of the arithmetic circuit 17.
Therefore, in this case, the transformer 3, the switching element 4, and the diode D1 constitute a simulated output voltage generating means.

The arithmetic circuit 17 in this embodiment functions as the ON timing control means of the arithmetic circuit 17 of the third embodiment shown in FIG. 17, and the ON period in the arithmetic circuit 17 of the fourth embodiment shown in FIG. It operates like a combination of functions as control means.
That is, when the inverter device 1 of this embodiment is activated and the arithmetic circuit 17 starts operation, the operation is performed according to the flowchart shown in FIG. 21 in order to control the ON timing of the switching element 4.

However, the arithmetic circuit 17 determines and stores the peak voltage Vp ′ from the peak voltage detection circuit 28 until the detection voltage Vop of the drain current Id becomes equal to or lower than the reference voltage TH0 in step S21 of FIG. Then, after the ON timing control Son is output in step S25, the ON period Ton is determined according to the stored peak voltage Vp ′, and the ON period control signal Sw indicating the ON period Ton is output.
The ON timing control Son and the ON period control signal Sw are input to the FB terminal and the PWM terminal of the control circuit 25, respectively, and the control circuit 25 controls the ON timing and the ON period of the switching element 4.
The same effect as that of the inverter device of the fourth embodiment described above can be obtained by the inverter device of the fifth embodiment.

[Sixth Embodiment]
Next, a sixth embodiment of the inverter device according to the present invention will be described with reference to FIG.
FIG. 26 is a circuit diagram of the inverter device. This inverter device 1 uses a step-up transformer 30 composed of a plurality of transformers T1 and T2 in place of the step-up transformer 13 in the inverter device 1 of the second embodiment shown in FIG. Yes.

The transformers T1 and T2 have individual magnetic paths (cores) and have the same characteristics, and the primary excitation windings Np1 and Np2 are connected in parallel to each other so that an excitation current flows simultaneously. The switching element 4 is connected in series between the input terminals I1 and I2. The secondary output windings Ns1 and Ns2 are connected in series with each other, and both ends thereof are connected to output terminals O1 and O2 that output the output voltage Vout, respectively.
Further, a slave winding Nf is provided as a simulated output voltage generating means on the secondary side of one transformer T1 in the same manner as the transformer 13 of FIG. 13 so as to generate a simulated output voltage Vf corresponding to the output voltage Vout. ing.

  The operation of the inverter device 1 of the sixth embodiment is the same as that of the inverter device 1 of the second embodiment shown in FIG. However, if the transformers T1 and T2 constituting the transformer 30 are equivalent to the transformer 13 in FIG. 13, an output voltage equivalent to the output voltage of the transformer 13 is generated in the output windings Ns1 and Ns2. The output voltage Vout is superposed so as to be stacked.

Therefore, the output voltage Vout is a high voltage (crest value and average value) that is approximately twice the output voltage Vout of the inverter device 1 of the second embodiment. Therefore, it is desirable that the time axes of the output voltage waveforms generated in the output windings Ns1, Ns2 of the transformers T1, T2 constituting the transformer 30 are synchronized.
Or when obtaining the output voltage Vout equivalent to the inverter apparatus 1 of 2nd Embodiment, each transformer T1, T2 can be reduced in size, and the whole transformer 30 can also be reduced in size.
Note that the exciting windings Np1 and Np2 of the transformers T1 and T2 constituting the transformer 30 may be connected in series so that the exciting current flows simultaneously. In this case, the voltage applied to each excitation winding Np1, Np is ½ of the input voltage, so that the withstand voltage is low.

Further, the output windings Ns1, Ns2 of the transformers T1, T2 may be connected in parallel to each other. In that case, the voltage value (crest value and average value) of the output voltage Vout is equivalent to that of a single transformer, but the output current can be doubled, so the output power is also doubled. Become.
Further, the plurality of transformers constituting the step-up transformer 30 is not limited to two, but may be three or more. The larger the number of transformers, the higher the output voltage or the higher the power. Can be output. However, it is necessary to consider the generation of electromagnetic noise from the transformer installation space and wiring.

Of course, the inverter device 1 of the sixth embodiment also provides the effect of the ON timing control and the ON period control of the switching element 4 as in the inverter device 1 of the second embodiment.
Note that the step-up transformer 13 or 3 in the first embodiment or the third to fifth embodiments may be composed of a plurality of transformers each having an individual magnetic path and having the same characteristics. .

  In each of the first, second, fourth, and sixth embodiments, the transformer 13 or the secondary side of the T1 is provided with the subordinate winding Nf having an extremely small number of turns to generate the simulated output voltage Vf. Simulated output voltage generation means. However, instead of this, the tap terminal is pulled out from the terminal side connected to the ground (earth) of the transformer output winding from several turns, and the simulated output voltage is generated between the tap terminal and the ground. Output voltage generating means may be configured.

[Application fields of the invention]
The inverter device according to the present invention has a high voltage applied to various devices such as a plasma generator, a semiconductor wafer bonding device, an image processing device, a coating device, a lighting device, an air cleaner, a discharge device, a backlight of a liquid crystal TV, and a sterilization device. Can be used as a high-voltage power supply device.
In particular, in each of the above-described embodiments, it is possible to efficiently generate atmospheric pressure plasma by connecting a plasma generator as the load 2 and applying a stable AC high voltage between the discharge electrode and the counter electrode.

And atmospheric pressure plasma is applied to various industrial products such as surface modification and removal of contaminants as one means of surface treatment. In the case of performing adhesion, printing, coating, or the like of a resin or the like, pretreatment with atmospheric pressure plasma can improve wettability.
For example, when an ultraviolet curable varnish is coated on a printed material on which resin toner is printed by an electrophotographic image forming apparatus, the varnish of the resin toner printing part is repelled by the wax component contained in the resin toner. There is.

  However, when surface modification by atmospheric pressure plasma is performed, wettability is improved, so that varnish coating is possible, and the added value of printed matter is improved. In order to generate the atmospheric pressure plasma, a high voltage is required. However, the inverter device according to the present invention can efficiently apply the high voltage. Thereby, radical species generated by the generation of atmospheric pressure plasma can be stably supplied to the surface of the printed matter, and surface modification can be reliably performed.

As mentioned above, although each embodiment of this invention has been described, the specific configuration of each part of the embodiment, the content of operation, and the like are not limited to those described therein.
Moreover, this invention is not limited to each embodiment mentioned above, It cannot be overemphasized that it is not limited at all except having the technical feature described in each claim of a claim.
Furthermore, the circuit examples, operation examples, modification examples, and the like of each embodiment described above may be changed or added as appropriate, or a part of them may be deleted, and any combination may be implemented as long as there is no contradiction with each other. Of course, it is possible.

1: Inverter device 2: Load 3, 13, 30: Transformer for boosting
4: Switching element 5, 15, 25: Control circuit
16: Zero cross detection circuit 17: Arithmetic circuit 18: Peak voltage detection circuit
19: Drain current detection means (current transformer)
20: current-voltage conversion circuit 21: operational amplifier 22: bias voltage circuit 60: photocoupler 61, 62: light emitting element 63, 64: light receiving element I1, I2: input terminal O1, O2: output terminal T1, T2: individual transformer Np, Np1, Np2: Excitation winding Ns, Ns1, Ns2: Output winding
Nf: Subordinate winding (third winding) Vin: Input voltage Vout: Output voltage
Vf: Simulated output voltage Vp, Vp ′: Peak voltage Vop: Detection voltage Id: Drain current Sp: Switching control signal Son: ON timing control signal Sw: ON period control signal

JP 2013-31338 A

Claims (10)

A DC voltage or a voltage in which a pulsating current is superimposed on the DC component is used as an input voltage, the input voltage is switched by a switching element, and an excitation current is passed through the excitation winding on the primary side of the transformer while the switching element is ON. In the inverter device that outputs the output voltage of the AC waveform from the output winding on the secondary side of the transformer during the period when the switching element is OFF,
In the means for controlling ON / OFF of the switching element, a current that flows in a direction opposite to the direction in which the excitation current flows through the switching element is generated during the OFF period of the switching element, and then the current value becomes zero. An inverter device comprising ON timing control means for turning on the switching element at a timing. The ON timing control means includes:
In synchronization with the output voltage, simulated output voltage generating means for generating a simulated output voltage having a waveform whose peak value is smaller than the output voltage;
A zero-cross detection circuit for detecting a zero-cross point of the simulated output voltage generated by the simulated output voltage generating means;
2. The inverter device according to claim 1, further comprising a circuit that generates a signal for turning on the switching element at the third zero-cross point from the time when the switching element is turned off. The ON timing control means includes:
In synchronization with the output voltage, simulated output voltage generating means for generating a simulated output voltage having a waveform whose peak value is smaller than the output voltage;
A zero-cross detection circuit for detecting a zero-cross point of the simulated output voltage generated by the simulated output voltage generating means;
A circuit for generating a signal for turning on the switching element at the time when the same period as the ON period immediately before the switching element has elapsed from the second zero-cross point from when the switching element is turned off; The inverter device according to claim 1, comprising: The ON timing control means includes:
Current detection means for detecting a current flowing in a direction opposite to a direction in which the excitation current flows in the switching element during a period in which the switching element is OFF;
A current / voltage conversion circuit for converting a current value detected by the current detection means into a voltage value obtained by adding a bias voltage;
After the voltage value converted by the current / voltage conversion circuit becomes a preset reference voltage, two different threshold voltages close to a voltage value corresponding to 0 corresponding to the current value are sequentially lower from the reference voltage. 2. The inverter device according to claim 1, further comprising a circuit that generates a signal for turning on the switching element when a predetermined delay time elapses after exceeding. The ON timing control means includes:
In synchronization with the output voltage, simulated output voltage generating means for generating a simulated output voltage having a waveform whose peak value is smaller than the output voltage;
A zero-cross detection circuit for detecting a zero-cross point of the simulated output voltage generated by the simulated output voltage generating means;
Current detection means for detecting a current flowing in a direction opposite to a direction in which the excitation current flows in the switching element during a period in which the switching element is OFF;
A current / voltage conversion circuit for converting a current value detected by the current detection means into a voltage value obtained by adding a bias voltage;
The voltage value converted by the current / voltage conversion circuit from the second zero cross point from the time when the switching element is turned off has two different threshold voltages close to the voltage value corresponding to the current value of 0. 2. The inverter device according to claim 1, further comprising a circuit that generates a signal for turning on the switching element when a predetermined delay time elapses after sequentially exceeding the lower one.   The means for controlling the ON / OFF of the switching element includes a period of ON / OFF control of the switching element, a period in which the output voltage is generated in a period in which the switching element is OFF, and a state in which the switching element is ON. 6. The inverter device according to claim 1, wherein the inverter device is controlled so as to be a sum of twice the period.   7. The inverter device according to claim 6, wherein the means for controlling the ON / OFF of the switching element keeps either the ON period of the switching element or the cycle for the ON / OFF control constant.   The means for ON / OFF control of the switching element includes a peak voltage detection circuit for detecting a peak voltage of the simulated output voltage generated by the simulated output voltage generation means, and a peak voltage value detected by the peak voltage detection circuit. 6. The inverter device according to claim 2, further comprising an ON period control unit configured to control an ON period of the switching element.   The ON period control means shortens the ON period of the switching element when the peak voltage value is larger than a predetermined value, and turns on the switching element when the peak voltage value is smaller than the predetermined value. The inverter device according to claim 8, wherein the period is longer than the previous time.   The transformer is constituted by a plurality of transformers having the same characteristics having individual magnetic paths, and the exciting windings of the transformers are connected in parallel or in series to simultaneously pass the exciting current, and the outputs of the transformers The inverter device according to any one of claims 1 to 9, wherein windings are connected in series or in parallel to output the output voltage.

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