JP2016092648A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-precision A/D converter, configured by applying probabilistic A/D conversion.SOLUTION: An A/D converter includes a charge transfer type DAC circuit 30 for outputting a DAC voltage indicating a difference between an input analog voltage and a reference voltage according to inputted digital data, an SF-ADC 23 for performing A/D conversion for the DAC voltage to digital data, a digital comparator 11 for comparing the digital data from the SF-ADC to a digital threshold value, and outputting a digital signal indicating the comparison result, and an SAR logic circuit 12 for A/D conversion of the input analog voltage to an output digital signal and outputting the signal. Threshold value generation means 42 corrects an A/D conversion error by generating a digital threshold value based on digital error data, outputted from parallel type probabilistic A/D conversion means when test digital data is inputted to the DAC circuit.SELECTED DRAWING: Figure 21

Description

  The present invention relates to an A / D converter configured by applying probabilistic A / D conversion to, for example, a successive approximation A / D converter.

  Due to the increasing demand for daily health management in recent years, a highly accurate wearable biometric sensor that can be driven by a battery for a long time is required. Accordingly, a low power consumption and high resolution A / D converter (Analog-to-Digital Converter; ADC) is required. Since power consumption is generally proportional to the square of the power supply voltage, it is important to reduce the voltage of the integrated circuit in order to reduce power consumption. However, it is difficult to secure the dynamic range due to the low voltage. Also like this. In an ADC, power consumption and resolution are in a trade-off relationship, and it is not easy to realize an ADC with low power consumption and high resolution.

FIG. 1 is a block diagram showing the configuration of a general n-bit successive approximation A / D converter according to the prior art. A typical example of a low power consumption A / D conversion system is a successive approximation type ADC (SAR-ADC) as shown in FIG. In FIG. 1, a successive approximation A / D converter includes a sample hold circuit 1, a comparator 2, a successive approximation register logic circuit (hereinafter referred to as SAR logic circuit) 3, an n-bit D / A converter 4, and the like. It is configured with. In this method, the D / A converter 4 and the comparator 2 are repeatedly used, and the determination is performed sequentially from the most significant bit D _n−1 based on the binary search algorithm.

JP 2010-045622 A

Ham Hyun-ju et al., “Parallel Stochastic A-D Converter Using Device Characteristic Mismatch”, IEEJ Transactions C, Vol. 131-C, no. 11, pp. 1848-1857, November 2011 Yusaku Hirai et al., "DAC error correction by stochastic quantizer in multi-bit delta-sigma modulator", Institute of Electrical Engineers of Japan, October 2013 H. Ham et al., "Design of a 500-MS / s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process," IEICE Electronics Express, Vol. 8, No. 6, pp. 353-359, March 2011. S. Weaver et al., "Stochastic Flash Analog-to-Digital Conversion," IEEE Transaction on Circuits Systems I, Vol. 57, No. 11, pp. 2825-2833, November 2010. J. J. Collins et al., "Stochastic resonance without tuning," NATURE, Vol. 376, No. 20, pp. 236-238, July 1995. H. Ham et al., "Application of Noise-Enhanced Detection of Subthreshold Signals for Communication Systems," IEICE Transaction on Fundamentals, Vol. E92-A, No. 4, pp. 1012-1018, April 2009. J. Um et al., "A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits," IEEE Transaction on Circuits Systems I, Vol. 60, No. 11, pp. 2845-2856, November 2013. David F. Hoeschele Jr., et al., "Analog-to-digital and digital-to-analog conversion techniques (2nd edition)," pp. 47-51, A Wiley-Interscience publication, 1994. Christopher M. Bishop, "Pattern Recognition and Machine Learning," pp. 1-177, Springer Science + Business Media, LLC, 2006. Shigeo Abe, "Support Vector Machines for Pattern Classification," pp. 93-94, Springer Science + Business Media, LLC, 2010.

  In general, the internal D / A converter of the SAR-ADC is realized by a capacitor array weighted by a power of two. In the SAR-ADC, the accuracy of the DAC greatly affects the accuracy of the entire ADC. In order to ensure the accuracy of the DAC using the capacity, it is necessary to realize a capacity with sufficient relative accuracy, but this leads to an increase in occupied area and manufacturing cost. Therefore, in order to realize a high resolution SAR-ADC, a technique for correcting these errors is required.

  An object of the present invention is an A / D converter configured to solve the above problems and apply a probabilistic A / D conversion to a successive approximation A / D converter, which is compared with the prior art. Another object of the present invention is to provide an A / D conversion device having high accuracy.

The A / D converter according to the present invention is
A sample-and-hold circuit that samples and holds an input analog voltage and a charge transfer DAC circuit having a plurality of DAC capacitors, wherein the DAC indicates a difference between the input analog voltage and a reference voltage corresponding to input digital data A charge transfer DAC circuit for outputting a voltage;
A parallel circuit that includes a plurality of comparators each having a different threshold value and an adder that adds output signals from the plurality of comparators, and A / D converts the DAC voltage from the D / A conversion means into digital data. Type probabilistic A / D conversion means;
Threshold generating means for generating a predetermined digital threshold;
A digital comparator that compares the digital data from the parallel type stochastic A / D conversion means with the generated digital threshold value and outputs a digital signal indicating a comparison result;
The input analog voltage is A / D converted into an output digital signal by controlling the digital signal from the digital comparator to repeatedly compare the digital threshold value with the digital threshold value from the most significant bit to the least significant bit. An A / D conversion device comprising a successive approximation register logic circuit for outputting
The threshold generation means generates the digital threshold based on digital error data output from the parallel stochastic A / D conversion means when predetermined test digital data is input to the DAC circuit. Thus, the A / D conversion error is corrected.

In the A / D converter, component data depending on the input code data is detected as a difference from the digital error data when predetermined input code data serving as a reference is input to the charge transfer DAC circuit. And further comprising storage means for storing,
The threshold generation means generates the digital threshold based on component data depending on the input code data.

  In the A / D converter, the parallel stochastic A / D converter performs A / D conversion by performing a time averaging process on the DAC voltage from the D / A converter. It is characterized by.

Furthermore, in the A / D converter,
An averaging filter that samples the digital data from the parallel-type stochastic A / D conversion means many times and calculates an average value to time-average the digital data and output it;
And an encoder for encoding the digital data from the averaging filter from a predetermined first bit number to a predetermined second bit number digital data.

  Furthermore, in the A / D converter, the encoder encodes binary code digital data from the averaging filter into thermometer code digital data.

In the A / D conversion apparatus, the charge transfer DAC circuit, the parallel stochastic A / D conversion means, the threshold value generation means, and the digital comparator in A / D conversion processing of a predetermined higher bit And performing the A / D conversion process using the successive approximation register logic circuit,
A / D conversion processing is performed using the charge transfer type DAC circuit, the parallel type stochastic A / D conversion means, the averaging filter, and the encoder in A / D conversion processing of a predetermined lower bit. It is characterized by.

  Further, the A / D conversion device further includes first correction means for correcting an error of the DAC capacity of the charge transfer DAC circuit using a predetermined machine learning method.

  Furthermore, the A / D conversion apparatus further includes a second correction unit that corrects the encoding characteristic of the encoder using a predetermined machine learning method.

Still further, in the A / D conversion device, the A / D conversion device is configured to be separated into a sensor and a server device and connected to be communicable via a wired communication line or a wireless communication line,
The sensor includes the charge transfer DAC circuit, the parallel type stochastic A / D conversion means, the threshold value generation means, the digital comparator, the successive approximation register logic circuit, and the first correction means.
The server device includes the second correction unit.

  Therefore, according to the A / D conversion device according to the present invention, the A / D conversion device is configured by applying the probabilistic A / D conversion to the successive approximation A / D converter, thereby comparing with the prior art. An object of the present invention is to provide an A / D converter having high accuracy.

It is a block diagram which shows the structure of the general n bit successive approximation type A / D converter based on a prior art. It is a block diagram which shows the structure of the parallel type | mold stochastic A / D converter (SF-ADC) used in the A / D converter which concerns on Embodiment 1. FIG. It is a graph which shows the input-output characteristic of SF-ADC of FIG. FIG. 3 is a block diagram illustrating a configuration of a digital control threshold variable comparator used in the first embodiment. FIG. 2 is a circuit diagram illustrating a configuration of an n-bit capacitance D / A converter including a sample and hold circuit used in the first embodiment. FIG. 2 is a block diagram illustrating a configuration of a DAC error correction circuit using SF-ADC according to the first embodiment. 6 is a table showing an example of a test input code used in the A / D conversion device according to the first embodiment. 1 is a block diagram showing a configuration of a weak signal A / D conversion circuit using SF-ADC according to Embodiment 1. FIG. It is a table | surface which shows the classification | category and characteristic of each noise component. FIG. 9 is a timing chart showing a stochastic resonance phenomenon that becomes a problem in the A / D conversion circuit of FIG. 8. FIG. 6 is a graph showing a relationship between an analog input voltage and an output code error, which is a simulation result of the A / D conversion device according to the first embodiment. 6 is a table showing simulation conditions for upper 12-bit SAR-ADC according to the first embodiment. It is a simulation result of the A / D conversion device concerning Embodiment 1, and is a graph which shows a frequency spectrum of lower 6 bits A / D conversion. 6 is a table showing simulation conditions for lower-order 12-bit SAR-ADC according to the first embodiment. 6 is a waveform diagram showing a time waveform indicating an initial error of the A / D conversion device according to the second embodiment. FIG. It is a wave form diagram which shows the time waveform which shows the residual error of the A / D converter which concerns on Embodiment 2. FIG. 10 is a flowchart showing Bayesian additional learning processing used in the A / D conversion device according to the second embodiment. It is a simulation result of the A / D conversion device concerning Embodiment 2, and is a graph which shows an example of prediction distribution using initial learning. Is a simulation result of the A / D conversion apparatus according to Embodiment 2 is a graph showing the residual error after additional learning using learning data D _T ^1. Is a simulation result of the A / D conversion apparatus according to Embodiment 2 is a graph showing the residual error after additional learning using learning data D _T ^2. It is a block diagram which shows the structure of the A / D converter which concerns on Embodiment 3. It is a block which shows the test mode (control data acquisition) process in the A / D converter of FIG. It is a flowchart which shows the production | generation process of the threshold value control data at the time of A / D conversion in the A / D converter of FIG. It is a block which shows the SAR-ADC mode (upper bit conversion) process in the A / D converter of FIG. FIG. 22 is a block diagram showing SF-ADC mode (lower bit conversion) processing in the A / D conversion device of FIG. 21. It is a block diagram which shows the structure of the A / D conversion system which concerns on Embodiment 4. It is a specific example of Embodiment 4, Comprising: It is a block diagram which shows the structure of the system for determining the encoder characteristic by machine learning. It is a table | surface which shows an example of the relationship converted from the binary code used with the A / D converter of FIG. 27 to a thermometer code.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

Embodiment 1. FIG.
1-1. Preface In this embodiment, on the premise of an environment mounted on a microcomputer (microcomputer) or on the same board as the microcomputer, a low-voltage high-resolution A / D systematically using functions of the microcomputer (nonvolatile storage area, etc.) The purpose is to realize a converter. In the proposed method, a comparator capable of digitally controlling the threshold value is realized by using a parallel type stochastic A / D converter (for example, see Non-Patent Documents 3 and 4) described later. This is used as a comparator of the SAR-ADC, and is acquired by a test signal input in advance, and the threshold value of the comparator is dynamically controlled using the control data stored in the nonvolatile storage area of the microcomputer, so that the SAR-ADC The DAC error is corrected. Further, by applying a probabilistic A / D conversion method using noise to A / D conversion of lower bits where noise is dominant, A / D conversion of a signal buried in noise is enabled.

1-2. Probabilistic A / D Conversion FIG. 2 is a block diagram showing a configuration of a parallel type stochastic A / D converter (SF-ADC) used in the A / D conversion apparatus according to the first embodiment. A flash ADC according to the prior art includes a reference voltage generator (resistor ladder, etc.), (2 ^L −1) comparators (L is the number of bits), and an encoder that encodes a thermometer code into a binary code ( (Thermo to to Binary Encoder). On the other hand, as shown in FIG. 2, the SF-ADC includes a comparator array 5 including N comparators 5-1 to 5 -N and an adder 6.

The adder 6 has a function of outputting the total number of comparators that output 1 to N comparators 5-1 to 5-N in binary code. SF-ADC is an A / D conversion method based on a stochastic resonance phenomenon (see, for example, Non-Patent Document 5) in which a signal is amplified by noise, and uses an input conversion offset voltage of a comparator as a threshold value. Yes. In the SF-ADC, the offset voltage Δoff _{, i} generated in each of the comparators 5-1 to 5-N cannot be predicted individually, but the statistical properties as a group, that is, the standard deviation and the average value are predicted. can do. According to the central limit value theorem, it can be assumed that the offset voltage distribution of a large number of comparator groups follows a Gaussian distribution. When the input voltage V _in and the standard deviation σ _off of the offset voltage are assumed, the probability P (V) that the comparator outputs 1 (high level). _in ) is given by the following equation (see Non-Patent Document 3, for example).

  However, the average value of the offset voltage is assumed to be zero. In addition, erf (y) is an error function (Error Function), and is represented by the following equation (for example, see Non-Patent Documents 3 and 6).

N _H is the number of comparators that output 1 (high level) and corresponds to the output digital signal of the adder 6 in FIG. In SF-ADC, an output digital signal is determined according to the number of comparators that output 1.

  FIG. 3 is a graph showing the input / output characteristics of the SF-ADC 23 of FIG. Since it can be assumed that the offset distribution follows a Gaussian distribution, the input / output characteristics of the SF-ADC 23 are equal to the product of the cumulative distribution of the Gaussian distribution and the total number of comparators N as shown in FIG.

FIG. 4 is a block diagram showing the configuration of the digital control threshold variable comparator 10 used in the first embodiment. As shown in FIG. 4, consider a digital comparator 10 that compares an input digital signal (threshold data D _th ) with an output from an adder 6 and quantizes it to 1 bit. The digital control threshold variable comparator 10 includes a comparator array 5, an adder 6, and a digital comparator 11.

Using the configuration shown in FIG. 4, by quantizing one bit using digital threshold D _th output signals from the SF-ADC 23 consisting comparator array 5 and the adder 6, the effective threshold voltage A comparator 10 in which V _{th and eff} can be digitally controlled can be realized. In the present embodiment, a method is proposed in which the SF-ADC 23 and the digital comparator 11 are combined as described above to be used as the threshold variable comparator 10 and applied to the SAR-ADC 23 to correct the DAC error. .

1-3. DAC error correction by SF-ADC.
FIG. 5 is a circuit diagram showing a configuration of an n-bit capacitor D / A converter including a sample and hold circuit used in the first embodiment. In many cases, the internal DAC circuit 30 (FIG. 6) of the A / D converter includes capacitors (DAC capacitances) C _{0 to} C _n−1 and switches SW0 to SW (n−1), as shown in FIG. This is realized by an array of SW (Sample). The switch SW (Sample) is turned on or off by a control signal. The DAC circuit 30 in FIG. 5 is a charge transfer DAC circuit including a sample-and-hold circuit, and operates as follows (for example, see Non-Patent Document 7).

In the initial state, the switches switch SW0~SW (n-1), for discharging the charges accumulated in the respective DAC capacitor _C 0 _{~C n-1} by connecting SW to (Sample) to the ground. Then, the switch SW to (Sample) is turned on, and connect other switches SW0~SW the (n-1) to the input analog voltage _{V in} each respective DAC capacitor _C 0 _{~C n-1} with respect to the input analog voltage to transfer the charge of V _in. Further, the switch SW (Sample) is turned off, and the corresponding switches SW0 to SW (n−1) are connected to the reference voltage V _ref according to the values of the input codes (digital signals) D _{0 to} D _n−1 . Alternatively, an output signal is obtained by connecting to the ground. That, DAC circuit 30 according to the input analog voltage _{V in} samples incorporates a function of the sample-and-hold circuit for holding in an input analog voltage _{V in,} input code (digital _{signal) D} 0 _{~D n-1} The difference from the reference voltage is output as an output signal voltage (DAC voltage) V _dac . The capacitance values C _{0 to} C _n−1 are normally weighted by a power of 2, and the i-th (i = 0,..., N) capacitance C _i is expressed by the following equation (for example, see Non-Patent Document 7). ).

Here, _Cu is a unit capacity. Ε _i represents a relative error (mismatch) of the capacitance C _i due to manufacturing variations. The capacity C _c connected in series are split capacitor scaling the capacitance values, m of formula (3) represents the bits to insert the split capacitor.

  In the present embodiment, the internal D / A converter of the SAR-A / D converter that uses the circuit shown in FIG. 5 in a differential configuration is used. Here, capacitance mismatch and parasitic capacitance are considered as error factors of the D / A converter. The effects of transient noise and countermeasures will be described later.

When the output voltage of the D / A converter is V _dac and the ideal output voltage of the D / A converter is V _{dac, ideal} , the error ΔV _dac of the D / A converter is defined by the following equation.

Since the influence of the error component varies depending on the selection status of the capacitor C _i , ΔV _dac has an input code dependency. Than this, ΔV _{dac (D in)} can be divided into input code-independent component _{E off} the input code _{D i} in dependent component _{E i (i = 0, ...} , n-1) as follows.

However, D _in = (D _n−1 ,..., D ₁ , D ₀ ) ₂ .

FIG. 6 is a block diagram illustrating a configuration of a DAC error correction circuit using an SF-A / D converter (SF-ADC) according to the first embodiment. Detection of the optimum threshold control data D _th for canceling the above error can be performed using a configuration as shown in FIG. In FIG. 6, the DAC error correction circuit includes a multiplexer 21, a charge transfer DAC circuit (hereinafter referred to as a DAC circuit) 30 having a sample and hold circuit, an SF-A / D converter (SF-ADC) 23, A digital comparator 11 and a SAR logic circuit 12 are provided. Here, the SAR logic circuit 12 has the same configuration as that of the SAR logic circuit 3, and the input digital value input to the digital comparator 11 is synchronized with the input clock from the digital threshold value Dth and the most significant bit. By repeating successive comparison up to the least significant bit, it is converted into an output digital signal and output.

In FIG. 6, the input to the DAC circuit 30 is switched by the multiplexer 21, and a test digital signal (hereinafter referred to as test data) D _{in, test} is input from the outside during _{the test} . When the output voltage V _{dac, ideal} of the ideal D / A converter corresponding to the test data D _{in, test} is an input analog signal (V _in = V _{dac, ideal} (D _{in, test} )), the output voltage of the DAC circuit 30 V _dac has only an error ΔV _dac . The error of the DAC circuit 30 is canceled by setting the output data D _test of the SF-A / D converter 23 for the error ΔV _{dac as} the threshold data D _th of the digital comparator 11. By dynamically canceling the error of the DAC circuit 30 using the control data _Dth detected in this way, the SAR-A / D converter can be highly accurate. However, when performing such correction, it is necessary to set an appropriate threshold value for the error ΔV _dac of the D / A converter in all cases. However, as can be seen from the equation (5), the error ΔV _dac takes 2 ⁿ values depending on the input code D _in .

In the environment assumed in the present embodiment, the control data of the digital control threshold variable comparator 10 described above is acquired by a test signal input after manufacture and stored in a nonvolatile storage area of the microcomputer. Then, it is read and referred to the register table (41 in FIG. 21) in the A / D converter at the time of activation. For example, in the case of n = 12, the test and control data _Dth must be stored for 2 ¹² = 4096 cases, which is not realistic. Therefore, a method for dynamically generating an optimum _Dth from a realistic number of data according to input data is required.

From equation (5), it can be seen that DAC error ΔV _dac (D _in ) can be obtained if E _i (D _i ) can be known for i = 0,..., N−1. However, it is impossible to directly detect E _i (D _i ). Therefore, a method is proposed _in which input codes D _{in and std serving} as a reference are determined, and E _i (D _i ) is detected and stored as a difference from the DAC error at that time.

The reference input code D _{in, std} can be arbitrarily selected, but for simplification of the control circuit, D _i = 0, (i = 0,..., N−1) for D _{in, std} , that is, all bits are Assume that it is zero. At this time, the following equation is obtained from equation (5).

すなわちＤ_ｊのみ１となるような入力Ｄ_ｉｎ，ｊを入力した場合のΔＶ_ｄａｃ（Ｄ_ｉｎ，ｊ）は次式となる。 Next, the input expressed by

That is, ΔV _dac (D _{in, j} ) when an input D _{in, j in} which only D _j is 1 is given by the following equation.

By taking these differences, the following equation is obtained as error information due to D _j = 1.

In this manner, error information when the j-th bit is 1 can be obtained and stored as a difference from a reference D _{in, std} .

When an error is obtained for an arbitrary input code D _in , an operation opposite to that described above may be performed. Specifically, by adding the _{E j (1) -E j (} 0) to ΔV _{dac (D in, std)} at the time of _D j = _1, it can be realized by doing nothing when the _D j = 0. These operations can be realized by a digital circuit. By using the above method, error correction is performed on 2 ⁿ patterns with only one reference ΔV _dac (D _{in, std} ) and n difference E _i (1) −E _i (0) data. This makes it possible to reduce the test time and storage area. As an example, FIG. 7 shows test input data in the case of n = 12. That is, FIG. 7 is a table showing an example of the test input code used in the A / D conversion device according to the first embodiment.

1-4. Weak signal detection by SF-A / D converter When realizing a highly accurate A / D converter with a low power supply voltage, noise components (thermal noise, flicker noise, etc.) that change with time in A / D conversion of the lower bits ) Is dominant, and it is necessary to give resolution to signals buried in these. A signal having a noise level or less can be detected by using the statistical property of noise using an SF-A / D converter.

  FIG. 8 is a block diagram showing a configuration of a weak signal A / D conversion circuit based on SF-ADC according to the first embodiment. That is, FIG. 8 shows an outline of a circuit that performs A / D conversion on a weak signal buried in noise. Noise (including DC components) generated in this circuit is DAC noise, comparator noise, and comparator offset. In FIG. 8, A0 to AN are virtual adders for adding DAC noise. 7 is an averaging filter, and 8 is an encoder.

  FIG. 9 is a table showing the classification and characteristics of each noise component. Comparator noise is generated by the individual comparators 5-1 to 5-N and is uncorrelated with each other. The proposed method enables detection of a signal buried in noise by utilizing a phenomenon called stochastic resonance (for example, see Non-Patent Document 5) in which uncorrelated random noise amplifies the signal. The SF-A / D converter is a system that treats a DC offset as noise and performs A / D conversion using this stochastic resonance.

FIG. 10 is a timing chart showing the stochastic resonance phenomenon which is a problem in the A / D conversion circuit of FIG. FIG. 10 shows an outline of signal detection using the stochastic resonance phenomenon. Usually, only the weak signal s (t) cannot exceed the threshold value of the comparator. However, by superimposing noise on a weak signal, it can be observed as a periodic pulse exceeding the threshold value with a certain probability. Here, since the noise n (t) can be assumed to follow a Gaussian distribution, the probability density function p (x) of the signal x (t) = s (t) + n (t) buried in the noise represents the standard deviation of the noise as σ. _n is expressed by the following formula.

When such a signal x (t) is input to a comparator having a threshold value V _{th, comp} , the probability P (x> V _{th, comp} ) that 1 is output is expressed by the following equation (for example, non- (See Patent Document 6).

Here, erf (y) is an error function represented by Expression (2). By superimposing noise on the signal, it becomes possible to exceed the threshold value with a certain probability P (x> V _{th, comp} ) and restore the signal level from that probability.

  In order to use such a stochastic resonance phenomenon, it is necessary to observe a probability that a signal on which output noise is superimposed exceeds a threshold value. Therefore, it is necessary to parallelize a large number of comparators and take a set average, or perform sampling a number of times to obtain a time average. However, even if a large number of comparators are arranged in parallel, there is actually an offset voltage larger than noise, so the number of comparators having a threshold in the signal range below the noise level is significantly limited. Therefore, in the proposed method, as shown in FIG. 8, the same input signal is sampled a number of times and an average value is calculated by calculating an average value, thereby providing an averaging filter 7 for sampling the same signal a number of times. The resolution is ensured by taking the time average.

  The output code of the averaging filter 7 represents a probability corresponding to the magnitude of the signal, but does not correspond to the signal level as an absolute value. Therefore, this output code cannot be output as it is as a lower-bit A / D conversion result. This is due to the fact that the probability of exceeding the threshold depends on the magnitude of noise, as can be seen from equation (11). For this reason, it is necessary to encode and output the output of the averaging filter by the encoder 8 of FIG. A specific example in which the encoding characteristic by the encoder 8 of FIG. 8 is determined by machine learning will be described later in detail in the fourth embodiment.

  As described above, the proposed method makes it possible to perform A / D conversion of a signal buried in noise by using uncorrelated noise generated in each comparator. However, noise generated by the D / A converter is input to all the comparators 5-1 to 5-N in common and becomes a factor that limits the resolution. For this reason, it is necessary to suppress the noise generated from the D / A converter sufficiently low or reduce it sufficiently by a low-pass filter.

1-5. Simulation Verification System level verification using MATLAB was performed for the method proposed in this embodiment. Here, in order to realize a full-scale voltage of 0.5 V and 18-bit resolution, the upper 12 bits are SAR-A / D converters using the proposed method, and the lower 6 bits are SF-A / D conversion using noise. Assume that A / D conversion is performed by a device.

  FIG. 11 is a graph showing a simulation result of the A / D conversion device according to the first embodiment and showing a relationship between an analog input voltage and an output code error. That is, FIG. 11 shows a verification result regarding DAC error correction of SAR-ADC using A / D conversion of upper 12 bits, that is, a threshold variable comparator by SF-ADC. FIG. 11 shows the relationship between the differential input voltage and the output code error (the difference between the ideal output code and the actual output code).

  FIG. 12 is a table showing simulation conditions for the upper 12-bit SAR-ADC according to the first embodiment. Here, only the mismatch is considered without including the influence of the parasitic capacitance. The capacity mismatch was set larger and the standard deviation value was 3.0%. From FIG. 11, it can be confirmed that the error due to the capacity mismatch of the D / A converter is corrected and the error of the output code can be reduced by the proposed method.

  FIG. 13 is a graph showing a simulation result of the A / D conversion device according to the first embodiment and showing a frequency spectrum of the lower 6-bit A / D conversion. That is, FIG. 13 shows a simulation result related to A / D conversion of lower 6 bits, that is, A / D conversion of a weak signal by SF-ADC using noise. FIG. 14 is a table showing simulation conditions for the lower 12-bit SAR-ADC according to the first embodiment. At this time, the signal-to-noise and distribution ratio (SNDR) is 35.2 dB, and the effective number of bits (ENOB) is calculated by the following equation.

  From this, it was confirmed that a desired resolution can be obtained even for a signal buried in noise by the above-described stochastic A / D conversion method using noise.

1-6. Summary In the first embodiment described above, the low-voltage high-resolution A / D conversion method for the wearable biological measurement sensor has been described. This system is a DAC error correction technique for a SAR-A / D converter using a digitally controlled threshold variable comparator using an SF-A / D converter, and a weak signal detection technique using an SF-A / D converter using noise. Consists of.

  By combining an SF-A / D converter using an offset voltage and a digital comparator, a comparator capable of digitally controlling the threshold value can be realized. In this method, a digital code for threshold control is detected in advance by test signal input, and the threshold value is dynamically controlled using these values during conversion, so that a DAC error having input code dependency can be obtained. Correct. Threshold control digital code detection is performed only for the minimum required number of patterns, and the optimum values are dynamically generated during actual conversion, reducing the load on the test process and storage space. ing. System level verification confirmed that the effect of DAC error can be greatly reduced by this method.

  In the A / D conversion of the lower bits where the resolution cannot be ensured due to the influence of noise in the SAR-A / D converter, the weak signal A / D conversion method by the SF-A / D converter using the statistical property of noise is exceeded. Sampling achieves the desired resolution.

  As described above, the proposed method makes it possible to realize a low-voltage, high-resolution A / D converter required for a wearable living body measurement sensor. Specifically, by dynamically controlling the threshold value of the comparator 10 using the SF-A / D converter 23 and the variable level digital comparator 10, the error factor dependent on the code selection in the capacitor DAC can be greatly reduced. .

  In the proposed method according to the present embodiment, an operation for obtaining the probability that (signal + noise) exceeds the threshold value by sampling the same input with respect to the same signal many times (Ns) and taking an average. Is going. In the example of this embodiment, this operation is performed, data of 500 kSps is output, and averaged with Ns = 8. Oversampling is performed on the 500 kSps data obtained in this way in the form of band limitation at 500 Hz as shown in FIG. 14 to reduce the influence of common noise. The value of SNDR in the present embodiment is also calculated after oversampling. This is an auxiliary operation that is performed to obtain a desired resolution as an embodiment. The former is called “time averaging”, and the latter can be distinguished from “oversampling”. That is, in the SF-A / D converter 23, the “time averaging” process is always necessary, but the “oversampling” process is not necessarily executed.

  As described above, according to the present embodiment, the SF-A / D converter 23 (including time averaging) is applied to the SAR-A / D converter, so that the resolution is higher than the resolution of the capacitive DAC. Accuracy can be achieved. Further, the residual error in the SAR-A / D converter is also A / D converted with high resolution in the SF-A / D converter 23, so that the total accuracy can be improved. In the A / D conversion device according to the first embodiment, the machine learning from the second embodiment onward may be integrated and applied.

Embodiment 2. FIG.
2-1. Preface Due to recent advances in computing resources, an environment has been established in which the output of an A / D converter can be easily corrected by software. The present embodiment relates to an output correction algorithm of a high-precision successive approximation ADC. In particular, the present embodiment is a correction method based on machine learning that takes into account the characteristics of the target A / D converter, and a framework for performing additional learning as appropriate in accordance with changes in the characteristics of the A / D converter due to deterioration over time. Including.

2-2. SAR-A / D Converter As a low power consumption A / D conversion method, a successive approximation ADC (SAR-ADC) shown in FIG. 1 is representative (see, for example, Non-Patent Document 8). ). In this method, a D / A converter and a comparator are repeatedly used, and determination is performed in order from the most significant bit D _n based on a binary search algorithm. The D / A converter is often realized by an array of capacitors and switches as shown in FIG. The value of the capacity is usually weighted by a power of 2, and the i-th capacity C _i is expressed by the following equation.

Here, _Cu is a unit capacity. Also, ε _i represents an error from the power of 2 due to manufacturing variations.

In the SAR-A / D converter, the error from the power of 2 is one of the factors that limit the resolution. Also, when realizing a high resolution SAR-A / D converter, the value of the capacitance becomes enormous, performs the scaling of the capacitance value by inserting a capacitor in series as in C _c usually Figure 5, error of the capacitance C _c also becomes a factor limiting the resolution. Since the influence of these errors on the D / A converter output depends on the selection of the capacitance by the switch, the influence of the errors depends on the determination result of the upper bits.

  The relative error of the capacity can be reduced by increasing the unit capacity. However, since the occupied area on the integrated circuit increases and the manufacturing cost increases, these errors are necessary to realize a high-resolution SAR-A / D converter. Need to be corrected. Therefore, the correction method at the software level is described below.

に対応したアナログ電圧を高精度Ｄ／Ａ変換器を用いて生成し、その電圧に対するＳＡＲ−Ａ／Ｄ変換器の出力

を出力測定値とする。また、教師信号ｔ^ｋと出力測定値ｍ^ｋを十進数表記したものを、それぞれ

と表す。さらに、考えられる２^ｎ通りの学習データに対応する添字集合をＴと表し、添字集合Ｔに対応する学習データの集合を次式とする。 2-3. Output error correction model In the following, the selection of the correction model and its learning method will be examined. For the output error correction of the high-precision SAR-A / D converter with n-bit resolution, a pair (learning data) of p actual output measurement values and ideal output values (teacher signals) is used. In order to obtain the learning data k = 1,.

An analog voltage corresponding to is generated using a high-precision D / A converter, and the output of the SAR-A / D converter for that voltage

Is the output measurement value. Also, the decimal representation of the teacher signal t ^k and the output measurement value m ^k

It expresses. Furthermore, a subscript set corresponding to 2 ⁿ possible learning data is represented by T, and a set of learning data corresponding to the subscript set T is represented by the following equation.

2-3-1. Error Function Considering Circuit Model Considering the characteristics of SAR-ADC shown in FIG. 5, an arbitrary measurement value m = (m ₀ ,..., M _n−1 ) is a correction function h (m) that approximates a teacher signal. The following equation is used.

は、補正関数の調整パラメータであり、便宜上ｗ＝（ｅ，ｆ，g，δ）と表す。式（１４）の第２項は測定値の２のべき乗からの誤差を、第３項はスイッチによる容量の選択状況による誤差を補正するためのものである。また、第４項はＡ／Ｄ変換器の変換結果の大域的な傾向を補正する。 here,

Is an adjustment parameter of the correction function and is expressed as w = (e, f, g, δ) for convenience. The second term of the equation (14) is for correcting an error from a power of 2 of the measured value, and the third term is for correcting an error due to a capacitance selection state by the switch. The fourth term corrects the global tendency of the conversion result of the A / D converter.

FIG. 15 is a waveform diagram showing a time waveform indicating the initial error m _D −t _D of the A / D conversion device according to the second embodiment. FIG. 16 is a waveform diagram showing a time waveform indicating the residual error h (m _D ) −t _D of the A / D converter according to the second embodiment.

と定め、その二乗和を最小化する調整パラメータｗを求めるため、次式の最小化問題を解く。 2-3-2. Output error correction by least square method In the following, it is considered to apply the least square method in order to appropriately obtain the adjustment parameter of the correction function. The error for the kth teacher signal and output measurement pair

In order to obtain the adjustment parameter w that minimizes the sum of squares, the minimization problem of the following equation is solved.

Here, c ₁ and c ₂ are weights of normalization terms. By adding a normalization term for each variable, the values of the parameters e, f, and g are prevented from becoming too large. The adjustment parameter w ^* = (e ^* , f ^* , g ^* , δ ^* ) of the correction function is obtained analytically as follows.

Here, Φ, d, and I _c are given as follows.

の平均誤差を、以下の式を用いて評価した。 2-3-3. Numerical experiments Numerical experiments were conducted to evaluate the proposed correction model and to confirm the effectiveness of learning by the least squares method. In the experiment, all learning data _DT obtained by simulating the operation of the 15-bit SAR-A / D converter was used. Further, c ₁ = 0.1 and c ₂ = 0.01. Here, the measured output value after correction using the adjustment parameter w ^*

Was evaluated using the following equation.

が０．８６ＬＳＢであり、１．０ＬＳＢ以下に抑えられていることが確認できた。 The error e ₀ before correction was evaluated by the adjustment parameter and w = 0. The results of the experiment, with respect to the average output error _{e 0} before correction of a 5.08LSB, the average output error after correction

Was 0.86LSB, and it was confirmed that it was suppressed to 1.0LSB or less.

Furthermore, in order to examine the generalization of the correction function obtained by this method, 10-fold cross validation (for example, see Non-Patent Document 10) was performed on all learning data _DT . As a result, it was confirmed that stable output error correction was performed.

2-4. Additional learning using a Bayesian model In the following, a learning method that assumes the actual manufacturing status and usage status of a SAR-A / D converter is proposed. When manufacturing a product incorporating a SAR-A / D converter, correction is performed on each product. It is also necessary to correct for changes over time that occur as the product is used. In the present embodiment, a correction function learning method corresponding to these two cases is considered, but in this embodiment, the focus is on correction at the time of product manufacture.

  The output measurement value necessary for learning of the SAR-A / D converter needs to be measured using the target SAR-ADC, but in order to suppress the influence of thermal noise or the like, it is necessary to average the measurement results over time. is there. Therefore, it is not realistic to measure output measurement values for all teacher signals, and it is necessary to perform learning with limited learning data. Therefore, a method for performing additional learning while appropriately selecting learning data used for learning is proposed.

  In addition, as the resolution of the SAR-A / D converter to be corrected increases, the reliability of the output of the high-accuracy DAC is lowered due to the influence of thermal noise and the like, and it is considered that the teacher signal also includes an error. Therefore, additional data is selected using the predicted distribution obtained by Bayesian linear regression described in the next section.

2-5. Bayesian linear regression Let us consider performing linear regression using Bayesian estimation using Equation (15) similar to Section 2-3 as the correction function. First, it is assumed that the teacher signal follows the normal distribution N (t | h (m), β ⁻¹ ) because the low-order bits have low reliability. Further, it is assumed that the prior distribution of the adjustment parameter of h (m) is a normal distribution of the following equation.

At this time, the following equation is obtained by maximizing the posterior distribution p (w | D _T ) of w corresponding to the set D _{T of} learning data with respect to w.

からなる行列を表し、ｄ_Ｔは、その要素が

である縦ベクトルを表す。さらに、このときのｔの予測分布は次式で表される。 Where Φ _T is the line

D _T is the element of which

Represents a vertical vector. Further, the predicted distribution of t at this time is expressed by the following equation.

とし、ｌ＝０として、まず、ｎ_０個のデータ

を用いて初期学習を行い、その後ｌ_ｍａｘ回追加学習を行う。 2-4-2. Additional learning Additional learning can also be realized by using the Bayesian linear regression approach described in section 2-4-1. In this section, we consider selecting the learning data to be learned next using the prediction distribution for the learning data learned so far. The learning data set used for the 1st additional learning

And l = 0, first, n ₀ data

Is used for initial learning and then additional learning is performed l _max times.

  FIG. 17 is a flowchart showing Bayesian additional learning processing used in the A / D conversion device according to the second embodiment. The additional learning process includes steps S1 to S5 as shown in FIG.

とし、ｌ反復後の次式の予測分布を用いて以下のように行う。 Here, a method using a predicted distribution is proposed as a method for selecting additional data. The number of additional data in each additional learning is the same

And using the prediction distribution of the following equation after l iterations, the following is performed.

に分割する。それぞれの区間からｎ_ｖ個の追加学習データを選択する。その際、まず、その候補として、各区間からｎ_ｖのｓ_ｎ倍のデータを一様ランダムに選択し、その中でｔの分散σ^２が大きい上位ｎ_ｖ個を追加学習データとする。また、対応する集合Ｔ_ｌ＋１と表す。この方法をベイズ選択法（Ｂａｙｅｓ）と呼ぶ。また、比較のため、未選択の学習データ中から一様ランダムに選択する方法も考え、この方法をランダム選択法（Ｒａｎｄｏｍ）と呼ぶ。 T is ν intervals

Divide into To select a n _v number of additional learning data from each section. In that case, first, as the candidate, data of s _n times n _v is uniformly selected from each section, and among them, the upper n _v items having a large variance σ ² of t are set as additional learning data. Also, the corresponding set T _{l + 1} is represented. This method is called a Bayesian selection method (Bayes). For comparison, a method of uniformly selecting randomly from unselected learning data is also considered, and this method is called a random selection method (Random).

2-4-3. Numerical experiments Numerical experiments were performed to compare the effectiveness of the proposed additional learning method. As in section 2-3-3, the model obtained by simulating a 15-bit SAR-A / D converter is used for the experiment, and the initial learning data set T ₀ is uniform from the entire learning data set T. Randomly select n ₀ = 200. Also, n _v = 100, ν = 4, s _n = 10, c ₁ = 0.1, c ₂ = 0.01, and l _max = 8.

FIG. 18 is a graph showing an example of a prediction distribution using initial learning, which is a simulation result of the A / D conversion device according to the second embodiment. That is, FIG. 18 shows an example of the prediction distribution for each m in the prediction distribution obtained using the learning data of 200 points uniformly selected at random. The points in the figure indicate the decimal representation m _D of each output measurement value used for learning, and the band indicates the variance of the predicted distribution.

  Next, 10 trials of each of the 2 proposed methods were performed on 3 learning data sets obtained assuming different 15-bit SAR-A / D converters.

FIG. 19 is a graph showing a simulation result of the A / D conversion device according to the second embodiment and showing a residual error after additional learning using the learning data D _T ¹ . FIG. 20 is a graph showing a simulation result of the A / D conversion device according to the second embodiment and showing a residual error after additional learning using the learning data D _T ² . This shows the 10 trial average output error and its standard deviation for all learning data sets after each additional learning for the proposed methods (Bayes) and (Random).

As a result, it reduces the output error for each of the additional learning iteration 4 is about iteration (Random), the error _{e w} in both methods of (Bayes) is below 1LSB, a level close to the accuracy when using the entire training data It can be seen that the correction at is performed. In addition, for any of the three types of learning data sets used in the experiment, (Bayes) has a higher output error reduction capability than (Random), and the superiority of using information on the predicted distribution was confirmed.

2-5. Summary In the present embodiment, in order to improve the conversion accuracy of a low power consumption, high resolution SAR-A / D converter, a correction function taking into account the characteristics of the A / D converter is derived, and a parameter setting method for the function is provided. explained. In addition, from the viewpoint of the actual usage situation of the A / D converter, an additional learning method using Bayesian linear regression was also shown. By performing data selection based on the predicted distribution during the additional learning, the average error can be suppressed to 1 LSB or less even in learning with limited learning data.

Embodiment 3. FIG.
FIG. 21 is a block diagram illustrating a configuration of an A / D conversion device according to the third embodiment. The A / D conversion device according to the third embodiment includes the A / D conversion device according to the first embodiment and the A / D conversion device according to the second embodiment. In FIG. 21, the A / D conversion device according to the third embodiment is configured to include the following components. In addition, the same code | symbol is attached | subjected about the component similar to 1st and 2nd embodiment.
(1) a charge transfer type DAC circuit 30 incorporating a sample hold circuit;
(2) SF-A / D converter 23 comprising comparator array 5 and adder 6;
(3) averaging filter 7;
(4) Encoder 8;
(5) SAR-A / D converter correction digital comparator 11;
(6) SAR logic circuit 12;
(7) an output register 13 for temporarily storing the output digital signal and outputting it to an external circuit;
(8) When the test enable signal indicates the test mode, the test input data D _in input to the terminal A is input and output to the D / A converter 30, while the test enable signal indicates the non-test mode. A multiplexer 21 for inputting the output data _Dout input to the terminal B and outputting it to the D / A converter 30;
(9) A reference voltage generator 31 that generates a predetermined reference voltage necessary for the D / A converter 30 and outputs the reference voltage to the D / A converter 30;
(10) Multiplexer 32 that outputs input data to any of terminals A, B, and C based on a mode control signal; where, in test mode, output to terminal C, and in SAR-ADC mode Is output to terminal A, and is output to terminal B in the SF-ADC mode;
(11) A register table 33 for temporarily storing threshold data for the encoder 8 input from an external circuit and outputting the data to the encoder 8;
(12) a register table 41 that temporarily stores digital threshold data (error data) input from an external circuit and outputs the digital threshold data to the digital threshold generator 42;
(13) a digital threshold value generator 42 for generating a digital threshold value based on data from the register table 41 and outputting it to the digital comparator 11;
(14) A clock generator 51 that generates a clock CLK for an internal circuit based on a reference clock from an external circuit and outputs the clock CLK to the comparator array 5, the SAR logic circuit 12, and the control logic circuit 52;
(15) A control logic circuit 52 that generates a mode control signal based on the clock CLK and outputs the mode control signal to the multiplexer 32 and the digital threshold generator 42.

In the A / D conversion device according to the present embodiment, A / D conversion processing is performed according to the following procedure.
(1) In test mode processing that is pre-processing, control data is acquired (FIG. 22).
(2) Sample and hold the input analog voltage to be input. Here, _{D th,} the _std used as a threshold _{D th.}
(3) SAR-ADC mode (upper bit conversion) processing is performed (FIG. 24).
(4) The output data from the DAC circuit 30 is held, and the output data from the SAR logic circuit 12 is held.
(5) The A / D conversion data of the upper bit is output to the output register 13 and held.
(6) Perform SF-ADC mode (lower bit conversion) processing (FIG. 25).
(7) The output data from the encoder 8 is held and output to the output register 13.
(8) The output register 13 outputs an output digital signal composed of upper bit conversion data and lower bit conversion data.

FIG. 22 is a block diagram showing a test mode (control data acquisition) process in the A / D converter of FIG. In FIG. 22, in the test mode, the multiplexer 21, the DAC circuit 30, the SF-A / D converter 23, and the multiplexer 32 operate. The multiplexer 21 selects the terminal A based on the test enable signal, and the multiplexer 32 selects the terminal C based on the mode control signal. The differential input analog voltage _{V in} is input to the DAC circuit 30. On the other hand, the test input data D _{in, test} from the external circuit is input to the DAC circuit 30 via the terminal A of the multiplexer 21, and the analog input voltage V _in and the reference voltage corresponding to the test input data D _{in, test} After being D / A converted, the difference is input to the SF-A / D converter 23. The SF-A / D converter 23 performs probabilistic A / D conversion using the input analog voltage V _in as test input data D _{in, test} as threshold data, and then uses the multiplexer 32 as test output data D _test. Is output.

In the test mode process of FIG. 22, _assuming that V _in = V _{dac, ideal} (D _in ) with respect to the test input data D _{in ,} the output DAC voltage V _dac of the DAC circuit 30 has an error ΔV _dac (D _in ). The output data D _test of the SF-A / D converter 23 at this time corresponds to the error. Here, if D _th = D _test , the error of the D / A converter in the DAC circuit 30 is canceled. Actually, the threshold value _Dth for canceling the DAC error is dynamically generated as shown below.

  FIG. 23 is a flowchart showing threshold value control data generation processing during A / D conversion in the A / D conversion apparatus of FIG. 23, i = n−1, n−2,..., 0, and the processing of FIG. 23 shows processing for generating a threshold value when i = j. The process includes the processes of steps S11 to S14. In the initial state, it is expressed by the following equation.

D _th (n−1) = D _{th, std} + D _{th, n−1}

In this process, the threshold control data D _{th, j} is generated by dynamically executing a process opposite to the process in the test mode for the following expression at the time of A / D conversion. The following equation corresponds to E _j (1) −E _j (0) described above.

D _{th, j}
= D _test (ΔV _dac (D _{in, j} ) −D _test (ΔV _dac (D _{in, std} ))

Specifically, the threshold control data D _{th, j} is repeatedly calculated from i = n−1 (MSB) to i = 0 (LSB) for each determination step. Note that in S11 of FIG. 23, two of D _th1 (j) and D _th0 (j) are calculated, and the latency accompanying this calculation corresponds to each determination step in the SAR-ADC mode (corresponding to S12 of FIG. 23). This is because the dynamic generation of the threshold value Dth (j) used in (1) is quickly performed.

FIG. 24 is a block diagram showing SAR-ADC mode (upper bit conversion) processing in the A / D conversion apparatus of FIG. In FIG. 24, the multiplexer 21 selects the terminal B based on the test enable signal, and the multiplexer 32 selects the terminal A based on the mode control signal. The threshold control data D _{th, j} generated as described above is supplied to the digital threshold generator 42 as error data, and the digital threshold generator 42 generates a digital threshold based on the error data. And output to the digital comparator 11. Here, in the “SF-A / D converter in which the digital threshold value is controlled” composed of the DAC circuit 30, the SF-ADC, the multiplexer 32, the digital comparator 11, the SAR logic circuit 12 and the multiplexer 21, the input analog voltage a / D conversion of high-order bits with respect to V _in is performed, the output digital signal from the SAR logic circuit 12 is output via the output register 13.

  FIG. 25 is a block diagram showing SF-ADC mode (lower bit conversion) processing in the A / D conversion apparatus of FIG. In FIG. 25, the multiplexer 32 selects the terminal B based on the mode control signal. The input analog voltage Vin is input to the DAC circuit 30 and D / A converted, then A / D converted by the SF-A / D converter 23, averaged by the averaging filter 7, and encoded by the encoder 8. And output through the output register 13.

  As described above, according to the present embodiment, after threshold control data is acquired in the test mode, A / D conversion is performed on the upper bits in the SAR-ADC mode, and SF-ADC is performed on the lower bits. By performing A / D conversion in the mode, it is possible to perform A / D conversion with higher accuracy than in the prior art.

Embodiment 4 FIG.
FIG. 26 is a block diagram illustrating a configuration of an A / D conversion system according to the fourth embodiment. In FIG. 26, the A / D conversion system according to the fourth embodiment includes a sensor 70 and a server device 80, and the sensor 70 and the server device 80 are connected to each other via a wired communication line or a wireless communication line. The In the fourth embodiment, when the error of the capacitive DAC (due to manufacturing variations, parasitic elements, etc.) is digitally corrected based on the machine learning result, the A / D conversion correction of the error of the capacitive DAC is performed in the sensor 70. An object is to reduce the size and power consumption of the A / D converter by making corrections possible not only inside the A / D converter but also by the external server device 80.

  26, the sensor 70 includes an A / D converter 71, a correction parameter storage unit 72, a simple correction processing unit 73, a transmission / reception unit 74, and a test data generation unit 75. The server device 80 includes a transmission / reception unit 81, an altitude correction processing unit 82, and a correction parameter estimation processing unit 83. The A / D conversion system according to this embodiment is characterized in that the sensor device 70 performs simple correction processing while the server device 80 performs altitude correction processing.

  Here, the simple correction process is specifically a DAC error correction by the SF-ADC according to the first embodiment, and the altitude correction process is a least square method or a Bayesian model according to the second embodiment. Is a correction process. However, these are examples assumed in the demonstration experiment, and depending on the calculation capability on the sensor side in consideration of power consumption, a part of the altitude correction processing (for example, simple addition / subtraction) can be implemented on the sensor side. .

In the embodiment of FIG. 26, during machine learning, as indicated by a broken line, the test data generation unit 75 of the sensor 70 generates test data based on an instruction signal from the server device 80 to generate an A / D converter 71. And the output data is transmitted to the correction parameter estimation processing unit 83 of the server device 80. Based on this, the correction parameter estimation processing unit 83 estimates the correction parameter, stores it in the correction parameter storage unit 72 of the sensor 70, and uses it in the simple correction processing unit 73 as a correction parameter during actual use. The correction parameter is, for example, a characteristic of the encoder 8 described later. Then, in actual use, after the A / D converter 71 converts the input analog voltage V _in the A / D, and the correction and outputs the result to the simple correction processing unit 73, the altitude correction processing unit of the server 80 82, and after altitude correction processing is performed, it is output as an output digital signal.

  As described above, according to the present embodiment, it is possible to correct the error of the capacitive DAC, for example, not only inside the A / D converter of the sensor 70 but also, for example, the server device 80 that is an external circuit. For example, the A / D converter body such as the sensor 70 can be reduced in size and power consumption.

  FIG. 27 is a specific example of the fourth embodiment, and is a block diagram illustrating a configuration of a system for determining encoder characteristics by machine learning. 27, the sensor 70 includes an SF-A / D converter 23, an averaging filter 7, an encoder 8 having a register table 33, and a transmission / reception unit 74 having an antenna 74a, for example. In addition, the server device 80 includes, for example, a transmission / reception unit 81 having an antenna 81a and a server processing unit 84. Here, the server processing unit 84 includes, for example, the altitude correction unit 82 and the correction parameter estimation correction unit 83 of FIG.

The system of FIG. 27 operates as follows.
(1) A test signal is input to the SF-A / D converter 23 of the sensor 70, and the A / D conversion value is processed using the averaging filter 7 and the encoder 8.
(2) The output code after A / D conversion is transmitted from the transmission / reception unit 74 to the server processing unit 84 via the transmission / reception unit 81 of the server device 80.
(3) The server processing unit 84 evaluates the error of the output code after A / D conversion, and estimates the optimum threshold value in the encoder 8.
(4) The transmission / reception unit 81 transmits the estimated optimum threshold value to the register table 33 of the sensor 70, stores it, and applies it to the encoding by the encoder 8.
(5) In the system, the process of the above steps (1) to (4) is repeated to minimize the A / D conversion error.

  FIG. 28 is a table showing an example of a relationship for converting from binary code to thermometer code used in the A / D conversion device of FIG. In the present embodiment, the A / D conversion value (ideal value) Value_ideal, the A / D conversion value (actual value) Value_means, and the error Error can be modeled as the following equation.

Here _{, Di, ideal} is the ideal output binary code of the A / D converter _{, Di, meas} are the actual output binary code of the A / D converter _{, and Ti, ideal} are _{the values} of _{Di, ideal} . Lower k bits are converted into thermometer codes, _{and Ti, meas} are actual output lower k bits converted into thermometer codes. E _{i, i} is the binary code weight in the actual measurement, and E _{i, j} indicates the determined bit dependency. Further, E _{T, i} is an error (error from an ideal value) in the case of an actual thermometer code, Δ _ideal is a quantization error of the ideal output binary code, and Δ _nonideal is a quantum of the actual output binary code. Error. Here, p is a trial number and P is the total number of trials.

を用いても良い。 Here, the accuracy of A / D conversion can be improved by minimizing the error of the equation (24) by machine learning. Instead of the formula (24), the following formula similar to the formula (15) of the second embodiment is used.

May be used.

  In each embodiment, for the upper n bits of A / D conversion (n is an integer of 2 or more), A / D conversion is performed by binary search using a SAR-A / D converter. Considering the error (the error for the first term of Equation (22) and the first term of Equation (23)), the machine learning method is error-corrected by the method according to the second embodiment. Further, the upper k bits of A / D conversion (k is an integer of 2 or more) is performed by parallel comparison encoding, and the output of the SF-A / D converter (lower k bits) is binary by the external server device 80. The error is evaluated by converting the code into a thermometer code.

  According to the above embodiment, the error (capacitance variation, due to parasitic elements) of the capacitance DAC is digitally corrected based on the machine learning result (possible even by processing outside the ADC). Thus, A / D conversion can be performed with high accuracy.

  As described above in detail, according to the A / D converter according to the present invention, the A / D converter is configured by applying probabilistic A / D conversion to the successive approximation A / D converter. It is possible to provide an A / D conversion device having higher accuracy than the conventional technology.

1 ... Sample and hold circuit,
2 ... Comparator,
3 ... SAR logic circuit,
4 ... D / A converter (DAC),
5-1 to 5-N: Comparator,
6 ... adder,
7 ... Averaging filter,
8 ... Encoder,
10: Digitally controlled threshold variable comparator,
11: Digital comparator 12: SAR logic circuit,
13: Output register,
21 ... Multiplexer,
23 ... SF-A / D converter (SF-ADC),
30 ... DAC circuit,
31 ... Reference voltage generator,
32. Multiplexer,
33 ... register table,
41 ... register table,
51. Clock generator,
52. Control logic circuit,
70: Sensor,
71 ... A / D converter,
72 ... correction parameter storage unit,
73 ... a simple correction processing unit,
74: Transmitter / receiver,
74a ... antenna,
75... Correction signal generator,
80 ... Server device,
81 ... transmission / reception unit,
81a ... antenna,
82 ... Altitude correction processing unit,
83 ... correction parameter estimation processing unit,
84 ... Server processing unit,
C _{0 to} C _n-1 ... capacitance of the capacitor,
SW0 to SW (n-1), SW (Sample) ... switch.

Claims (9)

A sample-and-hold circuit that samples and holds an input analog voltage and a charge transfer DAC circuit having a plurality of DAC capacitors, wherein the DAC indicates a difference between the input analog voltage and a reference voltage corresponding to input digital data A charge transfer DAC circuit for outputting a voltage;
A parallel circuit that includes a plurality of comparators each having a different threshold value and an adder that adds output signals from the plurality of comparators, and A / D converts the DAC voltage from the D / A conversion means into digital data. Type probabilistic A / D conversion means;
Threshold generating means for generating a predetermined digital threshold;
A digital comparator that compares the digital data from the parallel type stochastic A / D conversion means with the generated digital threshold value and outputs a digital signal indicating a comparison result;
The input analog voltage is A / D converted into an output digital signal by controlling the digital signal from the digital comparator to repeatedly compare the digital threshold value with the digital threshold value from the most significant bit to the least significant bit. An A / D conversion device comprising a successive approximation register logic circuit for outputting
The threshold generation means generates the digital threshold based on digital error data output from the parallel stochastic A / D conversion means when predetermined test digital data is input to the DAC circuit. Thus, the A / D conversion apparatus corrects the A / D conversion error. A storage means for detecting and storing component data depending on the input code data as a difference from the digital error data when a predetermined input code data serving as a reference is input to the charge transfer DAC circuit;
2. The A / D converter according to claim 1, wherein the threshold value generating means generates the digital threshold value based on component data depending on the input code data.   3. The parallel type probabilistic A / D conversion means performs A / D conversion by executing a time averaging process on the DAC voltage from the D / A conversion means. A / D converter. An averaging filter that samples the digital data from the parallel-type stochastic A / D conversion means many times and calculates an average value to time-average the digital data and output it;
4. The encoder according to claim 1, further comprising an encoder that encodes the digital data from the averaging filter into digital data having a predetermined second number of bits from a predetermined first number of bits. The A / D conversion device according to any one of the above.   5. The A / D converter according to claim 4, wherein the encoder encodes binary code digital data from the averaging filter into thermometer code digital data. In the A / D conversion processing of a predetermined upper bit, the charge transfer type DAC circuit, the parallel type probabilistic A / D conversion unit, the threshold generation unit, the digital comparator, and the successive approximation register logic circuit are used. While performing A / D conversion processing,
A / D conversion processing is performed using the charge transfer type DAC circuit, the parallel type stochastic A / D conversion means, the averaging filter, and the encoder in A / D conversion processing of a predetermined lower bit. The A / D conversion device according to claim 4, wherein:   7. The apparatus according to claim 1, further comprising: a first correction unit that corrects an error in the DAC capacity of the charge transfer DAC circuit using a predetermined machine learning method. The A / D conversion device described.   8. The A / D conversion apparatus according to claim 7, further comprising second correction means for correcting the encoding characteristic of the encoder using a predetermined machine learning method. The A / D conversion device is configured to be separated into a sensor and a server device and connected to be communicable via a wired communication line or a wireless communication line,
The sensor includes the charge transfer DAC circuit, the parallel type stochastic A / D conversion means, the threshold value generation means, the digital comparator, the successive approximation register logic circuit, and the first correction means.
9. The A / D conversion apparatus according to claim 8, wherein the server apparatus includes the second correction unit.

Images