JP2016092076A - Evaluation device for semiconductor device, and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evaluate plasma (process) included damage (PID) based on Vth shift to a device under test (DUT) in the substantial same area as an existent MISFET by applying a structure and a measurement technique to which well-known charge based capacitance measurement (CBCM) capable of performing minute capacitance measurement is applied.SOLUTION: When evaluating the PID including a pseudo inverter and a CBCM circuit including a gate capacitance DUT, a counter electrode is provided for an antenna that becomes a PID source and by supplying a clock signal of the same phase as a DUT gate, floating capacitance of the antenna is cancelled. The present technology may be applicable to CMOS.SELECTED DRAWING: Figure 6

Description

  The present technology relates to a semiconductor device evaluation device and a semiconductor device, and in particular, by applying a known CBCM (Charge Based Capacitance Measurement) circuit capable of measuring a minute capacitance, a DUT (Device Under) having almost the same area as an existing MISFET. The present invention relates to a semiconductor device evaluation apparatus that enables evaluation of PID (Plasma (Process) Induced Damage) due to a Vth shift with respect to Test), and a semiconductor device.

  Many thin-film devices such as etching, ashing, ion implantation, and plasma CVD (Chemical Vapor Deposition) are used to manufacture thin film devices for semiconductor integrated circuits such as MISFETs (Metal Insulator Semiconductor Field-Effect Transistors).

  Conventionally, in such a plasma process, electric charge flows into the gate electrode of the MISFET and a strong electric field is applied to the gate insulating film at that time, causing a large current to flow, and a semiconductor interface such as in the gate insulating film or Si (silicon) layer. Are known to generate defects and carrier trap levels. In addition, as the gate insulating film becomes thinner with miniaturization, the effect of this phenomenon has become serious in recent years.

  Damage caused by the generation of defects and carrier trap levels at the semiconductor interface is called PID (Plasma (Process) Induced Damage). This PID affects MISFET characteristic deterioration, and in particular, there are a gate leak and a Vth shift as indices indicating the degree of PID.

  This PID evaluation is referred to as an antenna (Antenna), where the metal area or the number of Vias in the wiring process PID source Metal or Via is a small reference, with a larger antenna (Antenna) or a larger antenna (Antenna) based on the increase in gate leakage and Vth shift in case of having a protection diode (the protection diode has the effect of releasing charge during the plasma process and making it difficult to damage the gate oxide film) Made.

  The gate leak is obtained based on a current monitored by the gate electrode or the well electrode when a voltage is applied between the gate electrode, the well electrode, and the source-drain electrode.

  Vth shift is generally calculated from Vg (gate electrode applied voltage) -Id (drain current) characteristics of MISFET, but from Cg (gate insulating film capacitance) -Vg measurement (hereinafter also referred to as CV measurement). It is also possible to calculate.

  Conventionally, CV measurement (impedance measurement) is generally performed by an LCR meter or an impedance analyzer.

  In recent years, a Charge Based Capacitance Measurement circuit (hereinafter also referred to as a CBCM circuit) is also mainly used for measuring a minute capacitance between wirings (see Non-Patent Document 1) as a minute capacitance measurement method. An applied example has also been reported (see Non-Patent Document 2).

  In evaluating the influence of PID on MISFET, the carrier trap interface state, which is thought to be derived from PID at the semiconductor interface such as gate insulating film and Si, is also an important index.

  There are several methods for evaluating the interface state, and one of them is a charge pumping method (see Non-Patent Document 3).

  In evaluating the influence of PID on MISFET, it is also important to manufacture a sample that can appropriately evaluate the influence of only a specific antenna (Antenna) against various antennas (Antenna) such as Metal and Via. For example, an example relating to a manufacturing method of a semiconductor device capable of suppressing plasma damage from being applied to a gate insulating film of a TEG (Test Element Group) has been reported after a specific process (see Patent Document 1).

JC Chen, BW McGaughy, D. Sylvester, and C. Hu, “An on-chip attofarad interconnect charge-based capacitance measurement (CBCM) technique,” in IEDM Tech. Dig., 1996, pp. 3.4.1-3.4. 4. / Yao-Wen Chang, Hsing-Wen Chang, Chung-Hsuan Hsieh, Han-Chao Lai, Tao-Cheng Lu, Wenchi Ting, Joseph Ku, and Chih-Yuan Lu, "A Novel Simple CBCM Method Free From Charge Injection -Induced Errors "in IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 5, MAY 2004 pp.262-264 Bernhard Sell, Alejandro Avellan, and Wolfgang H. Krautschneider, "Charge-Based Capacitance Measurements (CBCM) on MOS Devices" in IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 2, NO. 1, MARCH 2002 pp.9-12 G. Groeseneken, HEMeas, N. Beltran, and RTDeKeersmaecher, “A Reliable Approach to Charge-Pumping Measurements in MOS Transistors,” IEEE Trans. Electron. Dev., Vol.ED-31, pp.42-53, 1984 .

JP 2007-123691 A

  By the way, as an influence on the MISFET characteristics of PID, a change in gate leak and / or a Vth shift are observed. Of these, when only the Vth shift is observed, it is possible to observe the Vth shift by CV measurement and the interface state density change due to damage. It was difficult to realize the interface state density evaluation simultaneously for the following reasons.

  That is, in general CV measurement, a capacitance of several pF or more is required, and both the gate capacitance and the antenna are large and difficult to mount. Moreover, the junction of the output part of the pseudo-inverter serves as a protection diode only by the method using the conventional Charge Based Capacitance Measurement (CBCM) circuit capable of measuring a minute capacity, and the influence of PID cannot be evaluated appropriately. It was.

  In addition, the charge pumping method is often used as an interface state evaluation method for gate insulating films. When considering gate insulating film interface evaluation by PID, a CV is used in a device under test (DUT) that implements the charge pumping method. A capacitance of at least several pF is required to perform the measurement, and a large area gate capacitance DUT is required.In addition, in order to induce PID in a large area gate capacitance DUT of several pF or more, Metal Antenna's The area became large and could not be evaluated without a large DUT.

  This technology has been made in view of such a situation, and in particular, by applying a known CBCM circuit capable of measuring minute capacitance, PID evaluation by Vth shift for a DUT having almost the same area as an existing MISFET Is possible.

  An evaluation apparatus according to one aspect of the present technology includes a CBCM (Charge Based Capacitance Measurement) circuit having a pseudo inverter and a MISFET (Metal Insulator Semiconductor Field-Effect Transistor) serving as a DUT (Device Under Test). An evaluation apparatus for evaluating PID (Plasma (Process) Induced Damage), wherein a gate of the DUT and an antenna are connected in parallel.

  The antenna and the output of the pseudo-inverter can be connected by an upper layer wiring than the antenna.

  After the DUT and the gate of the pseudo inverter are formed, the antenna connected to the DUT is formed, and thereafter, the antenna is connected in an upper layer than the antenna.

  A counter electrode of the antenna may be further included.

  The capacity of the DUT can be about several fF to several tens of fF.

  The pseudo inverter is configured by a PMISFET (P-type Metal Insulator Semiconductor Field Effect Transistor: hereinafter also referred to as PMIS) and an NMISFET (N-type Metal Insulator Semiconductor Field Effect Transistor: hereinafter also referred to as NMIS). Can do.

  The pseudo inverter can be configured by a transfer gate (CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) Switch).

  The antenna may be a through hole in a laminated chip structure composed of laminated chips.

  The antenna may have a laminated chip structure including laminated chips, and the pseudo inverter and the DUT may be arranged on each chip of the laminated chip.

  An antenna counter electrode arranged to face the antenna may be further included, and a clock signal having the same phase as the gate of the DUT may be input to the antenna counter electrode. it can.

  The clock signal input to the antenna counter electrode and the two systems of clock signals input to the CBCM circuit may further include a circuit that generates a branch from one clock signal.

  The Source / Drain terminal and Well terminal of the DUT may be separated.

  The voltage of the Well terminal is higher than the voltage of the gate of the DUT, and a negative voltage can be effectively applied to the MISFET.

  A current measuring unit that measures the charge pumping current may be further included.

  A semiconductor device according to one aspect of the present technology includes a CBCM (Charge Based Capacitance Measurement) circuit having a pseudo inverter and a MISFET (Metal Insulator Semiconductor Field-Effect Transistor) serving as a DUT (Device Under Test). A semiconductor device including an evaluation device for evaluating PID (Plasma (Process) Induced Damage), wherein a gate and an antenna of the DUT are connected in parallel, and after detecting a Vth shift as the PID, a chip having a large Vth shift Only includes a correction unit that boosts the internal power supply voltage by trimming with a fuse.

  The correction unit may boost the internal power supply voltage only for chips in which the Vth shift is greater than a predetermined value.

  In the correction unit, the circuit with strong PID resistance is mounted in advance, and for the chip with the Vth shift larger than a predetermined value, the circuit with low PID resistance is cut with a fuse and switched to a circuit with high resistance. Can be.

  The correction unit may be configured to switch from the circuit with weak PID tolerance to the circuit with strong tolerance for a chip having the Vth shift larger than the predetermined value.

  A semiconductor device according to one aspect of the present technology includes a CBCM (Charge Based Capacitance Measurement) circuit having a pseudo inverter and a MISFET (Metal Insulator Semiconductor Field-Effect Transistor) serving as a DUT (Device Under Test). An evaluation apparatus for evaluating PID (Plasma (Process) Induced Damage), wherein the gate of the DUT and the antenna are connected in parallel, and are manufactured under the plasma process conditions determined based on the evaluation result.

  In one aspect of the present technology, a CBCM (Charge Based Capacitance Measurement) circuit having a pseudo inverter is connected to a MISFET (Metal Insulator Semiconductor Field-Effect Transistor) serving as a DUT (Device Under Test), and the PID ( Plasma (Process) Induced Damage) is evaluated, and the gate of the DUT and the antenna are connected in parallel.

  The evaluation device according to one aspect of the present technology may be an independent device or a block that functions as an evaluation device.

  According to one aspect of the present technology, it is possible to evaluate a PID (Plasma (Process) Induced Damage) due to a Vth shift with respect to a DUT (Device Under Test) having almost the same area as an existing MISFET.

It is a figure explaining the generation principle of PID. It is a figure explaining the principle of the evaluation method of PID. It is a figure explaining the CV measuring method for evaluating PID. It is a figure explaining the structural example of a CBCM circuit. It is a figure explaining the evaluation method of PID by the charge pump method. It is a figure explaining the structural example of 1st Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the operation | movement method of the CBCM circuit of FIG. It is a figure explaining the structural example of 2nd Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the effect in the evaluation method by the evaluation apparatus of FIG. It is a figure explaining the effect in the evaluation method by the evaluation apparatus of FIG. It is a figure explaining the structural example of 3rd Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the structural example of 4th Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the structural example of 5th Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the structural example of 6th Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the structural example of 7th Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the structural example of 8th Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the structural example of 9th Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the structural example of 10th Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the structural example of 11th Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the structural example of 12th Embodiment of the evaluation apparatus of PID of this technique. It is a figure explaining the structural example of 13th Embodiment of the evaluation apparatus of PID of this technique. FIG. 22 is a flowchart for describing a first correction process for improving the yield of a semiconductor device by a semiconductor device incorporating the evaluation device of FIG. 21 and a measurement unit; It is a figure explaining the effect by the 1st correction process of FIG. It is a figure explaining the structural example of 14th Embodiment of the evaluation apparatus of PID of this technique. FIG. 25 is a flowchart for describing a second correction process for improving the yield of a semiconductor device by a semiconductor device incorporating the evaluation device of FIG. 24 and a measurement unit. It is a figure explaining the structural example of 15th Embodiment of the evaluation apparatus of PID of this technique, Comprising: It is a figure explaining the structural example which converts 1 clock into 3 systems of clocks.

<Outline of evaluation device>
Many plasma processes such as etching, ashing, ion implantation, and plasma CVD (Chemical Vapor Deposition) are used for manufacturing a thin film device of a semiconductor integrated circuit.

  The electric charge in this plasma process flows into the gate electrode of MISFET (Metal Insulator Semiconductor Field Effect Transistor), and at that time, a strong electric field is applied to the gate insulating film, causing a large current to flow. It has been found that defects and carrier trap levels are generated at the semiconductor interface such as silicon.

  More specifically, one of the factors that cause charge inflow is the spatial non-uniformity of the plasma. If the plasma (plasma potential, electron density, electron temperature, etc.) is non-uniform within the surface of the wafer to be processed, as shown by state A in FIG. 1, the equilibrium state between the electron current flowing from the plasma into the wafer and the ion current Collapses locally. As a result, charges are accumulated in the upper electrode (corresponding to the gate electrode of the transistor).

  Another factor is the “electronic shading effect”. As shown in the state B of FIG. 1, a fine pattern with a high aspect ratio covering an insulating film (for example, a photoresist / oxide film) exists on the wafer in the middle of the process. At this time, due to the difference in the spatial momentum between electrons and ions, the electrons adhere to the top of the fine pattern and the electron current is blocked. As a result, the balance between the electron current and the ionic current is lost, and charge accumulation is induced. Charge accumulation due to the electron shading effect is a phenomenon that can occur even when the plasma is spatially uniform.

  When such charge accumulation occurs, a high electric field is applied to the gate oxide film of the transistor and a tunnel current flows, so that the gate oxide film is destroyed or deteriorated. Damage based on the destruction and deterioration of the gate oxide film is PID (Plasma (Process) Induced Damage). This PID is directly connected to a defective transistor and a decrease in manufacturing yield.

  Therefore, it is considered to evaluate a product by measuring MISFET characteristic deterioration due to this PID (Plasma (Process) Induced Damage).

  More specifically, when evaluating PID, there are gate leak and Vth shift as indicators.

<Conventional PID evaluation structure>
FIG. 2 shows a schematic diagram of a conventional PID evaluation structure. Metal and Via, which are PID sources in the wiring process, are called antennas. For the evaluation of the PID, the case where the metal area or the number of Vias of the antenna 12 is small as shown in the left part of FIG. When the antenna 12 as shown in the middle part of FIG. 2 is large, or the antenna 12 as shown in the right part of FIG. 2 is large and has a protective diode 13 (the protective diode is a plasma process). It is based on the observation results of gate leak and Vth shift, with the effect of releasing the charge inside and making it difficult to damage the gate oxide film).

  The gate leak is obtained by applying a voltage between the gate electrode, the well electrode, and the source-drain electrode and monitoring the current with the gate electrode or the well electrode.

  In FIG. 2, the source and drain are grounded, a voltage V is applied from the power source to the gate via the antenna 12, and the gate leak of the gate capacitance DUT (Device Under Test) 11 is monitored by the ammeter A. Here, the area of the antenna 12 is small in the left part of FIG. 2, but the antenna 12 'is connected to the middle part of FIG. 2 so as to have a larger area. Further, a protection diode 13 is provided on the right side of FIG.

  The Vth shift is generally calculated from the Vg (gate electrode applied voltage) -Id (drain current) characteristics of the MISFET, but from Cg (gate insulating film capacitance) -Vg measurement (hereinafter referred to as CV measurement). It is also possible to calculate.

<Outline of CV measurement>
Here, with reference to FIG. 3, an outline of CV measurement (impedance measurement) using an LCR meter or an impedance analyzer, which has been generally used conventionally, will be described.

  As shown in FIG. 3, in the CV measurement, an oscillator OC, a power supply V, a DUT, and an ammeter A are connected in series, and Vth is calculated by monitoring and calculating them.

  In recent years, Charge Based Capacitance Measurement (hereinafter referred to as CBCM method) has also been used mainly for inter-wiring microcapacitance measurement as a microcapacitance measurement method. (See Non-Patent Document 2).

  Here, the configuration of a conventional CBCM circuit will be described with reference to FIG. The CBCM circuit 30 includes a pseudo inverter 31 and a gate capacitor DUT 32.

  The pseudo inverter 31 includes a transistor Tr11 composed of PMISFET (P-type Metal Insulator Semiconductor Field Effect Transistor: hereinafter also referred to as PMIS) and a transistor composed of NMISFET (N-type Metal Insulator Semiconductor Field Effect Transistor: hereinafter also referred to as NMIS). It consists of Tr12. The outputs of the transistors Tr11 to Tr12 are connected to the gate capacitor DUT32.

  It does not overlap with the gate electrodes (PMIS gate electrode: CLK1 / NMIS gate electrode: CLK2) of the transistors Tr11 and Tr12 composed of PMIS and NMIS (when PMIS is On, NMIS is Off, and when NMIS is On, PMIS is By applying a pulse voltage (hereinafter referred to as CLK) that is off and PMIS and NMIS do not turn on at the same time, the current is monitored by the Vds electrode or Vgnd electrode using the fact that the DUT repeatedly charges and discharges. Then, the charge / discharge charge is calculated by integrating the obtained current. Here, the Tr11 made of PMIS and the Tr12 made of NMIS may be replaced with Tranfer Gates (CMIS (Complementary Metal Insulator Semiconductor Field Effect Transistor) Switches), respectively.

<Charge pumping method>
In evaluating the influence of MISFET in PID, the carrier trap interface state which is thought to be derived from PID at the semiconductor interface such as gate insulating film and Si is also an important index. There are several methods for evaluating the interface state, and one of them is the charge pumping method shown in FIG. 5 (see Non-Patent Document 3).

Basically, a pulse generator for repeatedly switching the transistor from the accumulation state to the inversion state is connected to the gate electrode G of the MISFET. While the pulse is applied to the gate electrode G, the recombination of majority carriers and minority carriers occurs at the rising and falling timing of the pulse, and as a result, a current in the direction opposite to the current between the normal drain D and source S is generated. Occur. This current is called charge pumping current I _CP and can be measured by connecting a highly sensitive ammeter to the bulk or substrate electrode of the MISFET. By measuring the charge pumping current I _CP in the ammeter A, the carrier trap charge density _Nit is obtained as shown in the following equation (1). By using this, the carrier trap interface state is determined. Can be evaluated.

・・・（１）

... (1)

<Influence of Vth shift>
By the way, in recent years, at the MISFET production site, the influence of the Vth shift has become large as a characteristic change of the MISFET due to the PID during the wiring process. For example, the Vth shift due to the PID narrows the operation margin of the circuit and causes the worst malfunction. There is a risk of it happening.

  There is an urgent need to reduce the effects of the Vth shift due to PID, but it is necessary to quantitatively monitor the Vth shift due to PID before that. In other words, if there is a method for accurately monitoring the Vth shift, it is considered that there is a possibility that an effective measure by the process, device, structure, circuit, etc. can be taken.

  When no gate leak is observed and only a Vth shift is observed (hereinafter referred to as Vth shift mode PID), in addition to the method of calculating the Vth shift from the Vg-Id static characteristics of the MISFET, as represented by FIG. A technique for calculating the Vth shift by simple CV measurement is also common.

  However, in CV measurement using this LCR meter or impedance analyzer, a capacitance of at least several pF is required so that the capacitance of the DUT (Device Under Test) to be measured is not affected by external noise of the measurement system. It is.

  In order to measure the Vth shift mode PID by the measurement method described with reference to FIG. 3, the gate area of the MISFET serving as the DUT also becomes a considerably large area. In addition, in order to effectively evaluate the influence of the PID, the PID The antenna (Antenna) for inducing this also has a large area accordingly.

  In other words, it is not only an unrealistic area for mounting on a scribe line or product chip (Chip), but also has to be evaluated with a large area structure that deviates from the MISFET constituting the product chip. Become.

  As a means for preventing the DUT area from becoming too large in order to secure a capacitance of several pF or more, there is a technique using the CBCM circuit described with reference to FIG.

  In this measurement method, as described above, the DUT is connected to the PMIS and NMIS outputs called the pseudo inverter 31 and overlaps with the PMIS and NMIS gate electrodes (PMIS gate electrode: CLK1 / NMIS gate electrode: CLK2). (When PMIS is On, NMIS is Off, and when NMIS is On, PMIS is Off and PMIS and NMIS are not on simultaneously) By applying a pulse voltage (hereinafter referred to as CLK signal), Utilizing the fact that the DUT is repeatedly charged / discharged, the current is monitored by the Vds electrode or the Vgnd electrode, and the charge / discharge charge can be calculated by integrating the obtained current.

  More specifically, the monitor current flowing through the Vds electrode or the Vgnd electrode is I [A], the CLK period input to the gate electrode of the pseudo inverter is f [Hz], and the voltage applied to the gate insulating film of the DUT is V [V ] (Vds-Vsdb), where C [F] is the desired capacity, the capacity C can be calculated by the following equation (2).

・・・（２）

... (2)

  As can be seen from equation (2), in the CBCM circuit, the measurement current can be increased by increasing the period of the CLK signal input to the pseudo inverter, and even a small capacitance of several fF to several tens fF can be measured. It is a big feature.

  However, the output junction of the pseudo inverter (the part surrounded by the dotted line in the transistors Tr11 and Tr12 in FIG. 4) is connected to the DUT gate, and this junction acts as a protective diode and induces sufficient charge during the plasma process on the DUT gate. Because it is not possible, the structure of the CBCM circuit cannot be used for PID evaluation.

  In addition, Metal or Via serving as an antenna is observed as a parasitic capacitance when measuring the gate capacitance DUT. Currently, in the structure that has been measured and evaluated, a parasitic capacitance of about 1 pF is observed for a DUT gate capacitance of several tens of fF.

  As an index for evaluating PID, in addition to the above-described gate leak and Vth shift, there is an interface state density at the gate insulating film-semiconductor (Si, etc.) interface.

  There is a charge pumping method as an evaluation method for extracting the interface state density. If the Vth shift is extracted using the above-mentioned CBCM circuit and the interface state density by the charge pumping method can be extracted by the same DUT (Device Under Test), the analysis for PID will be improved and the discussion will be deepened.

  However, the charge pumping method cannot be directly applied to the MISFET using the CBCM circuit.

  That is, as described with reference to FIG. 5, the charge pumping method uses the carrier trap level (this is the vicinity of the gate insulating film-semiconductor interface) in the process of the channel transitioning from the accumulation state to the inversion state (or vice versa). This is based on the fact that carriers are captured and released at the interface state) and the trapped emission current at that time is observed as an injection current into the semiconductor substrate.

  Therefore, in the charge pumping method, it is necessary to control the pulse voltage input to the gate electrode so that the channel portion of the MISFET changes from the accumulation state to the inversion state. That is, it is necessary to apply this pulse voltage by changing it from negative to positive or from positive to negative.

  However, if this voltage is applied to the CBCM circuit as it is, it is necessary to apply a negative voltage to Vds or Vgnd. In this case, the n + diffusion layer of the pseudo inverter 31 and the Pwell become forward biased, and the DUT A desired voltage cannot be applied to the gate. Even when a positive voltage is applied, the p + diffusion layer and Nwell may become forward biased depending on the voltage condition (Vds or Vgnd> power supply voltage).

  The summary is as follows.

  <1> A method for constantly and quantitatively monitoring the Vth shift due to PID has not been established, and effective measures have not been taken.

  <2> The conventional CV measurement (LCR meter) shown in FIG. 3 requires a capacitance of pF or more, and the DUT and the antenna are both large, so it cannot be said that it reflects the MISFET structure of the product chip.

  <3> In the conventional CBCM structure, the DUT gate is connected to the pseudo-inverter junction and acts as a protective diode, so that the desired PID cannot be induced to the DUT gate.

  <4> The capacitance of Metal or Via serving as an antenna is excessively observed as parasitic capacitance.

  <5> When considering applying the charge pumping measurement method to the conventional CBCM circuit, applying a negative voltage to the DUT gate causes the junction of the pseudo inverter to become a forward bias and apply a negative voltage to the DUT gate. Can not do it.

<First configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
This technology proposes an effective CBCM circuit and monitoring method for evaluating Vth shift mode PID.

  First, an equivalent circuit and a cross-sectional structure of an evaluation apparatus effective for evaluating a Vth shift mode PID to which the present technology is applied will be described with reference to FIG. The evaluation apparatus of FIG. 6 includes the first feature and the second feature of the present technology. In addition, the left part of FIG. 6 has shown the equivalent circuit of the evaluation apparatus of this technique, and the right part of FIG. 6 has shown the cross-section of the evaluation apparatus. In FIG. 6 and subsequent figures, components having the same functions as those described with reference to any of FIGS. 1 to 5 are denoted by the same reference numerals and names, and the description thereof is as follows. Shall be omitted.

  As shown in the cross-sectional structure on the right side of FIG. 6, the first feature of the present technology is that the metal process that is the metal or via that is the antenna 50 in the CBCM circuit is connected to the pseudo inverter 31. It is that you are.

  That is, in the right part of FIG. 6, the antenna 50 is configured by terminals Vds, CLK1, CLK2, Vgnd, inverting circuits In11, In12, transistors Tr11 to Tr14, and wirings 52 to 54 via wiring 52 in the upper layer part. Connected in parallel to the pseudo inverter 31.

  In the right part of FIG. 6, the antenna 50 is further sandwiched between the counter electrodes 51-1 and 51-2 (CLKm in the left part of FIG. 6 is input to the counter electrodes 51-1 and 51-2. The upper surface is connected to the wiring 52 and the lower surface is connected to the wiring 54. The wiring 54 is the gate of the DUT, and the source and drain terminals of the DUT are grounded. In the left part of FIG. 6, the capacitance of the antenna 50 is indicated by Cm, and the parasitic capacitance of the circuit is indicated by Cp.

  As a result, the PID charge from the antenna flows into the terminal 54 which is the DUT gate, and the PID charge after the antenna 50 is formed allows the junction of the pseudo inverter 31 to function as a protective diode and escape. Therefore, the Vth shift mode PID for only the antenna 50 can be evaluated by performing the CV measurement with this structure.

  FIG. 7 schematically shows the relationship between the counter electrode input CLKm and the pseudo inverter inputs CLK1 and CLK2.

  This is Charge Injection-induced-Error-Free CBCM (CIEF-CBCM) (Yao-Wen Chang, Hsing-Wen Chang, Chung-Hsuan Hsieh, Han-Chao Lai, Tao-Cheng Lu, Wenchi Ting, Joseph Ku, and Chih. -Yuan Lu, "A Novel Simple CBCM Method Free From Charge Injection-Induced Errors" in IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 5, MAY 2004 pp.262-264) .

  As shown in FIGS. 6 and 7, the second feature is that, in this structure, the counter electrodes 51-1 and 51-2 are installed on the metal or via of the antenna 50, and the antenna (Antenna). This is a monitoring method in which the parasitic capacitance of the antenna 50 is not observed by always inputting the counter electrode input CLKm having the same phase as the DUT gate to the counter electrodes 51-1 and 51-2.

  That is, the counter electrode input CLKm is changed from the voltage Vgnd to the voltage Vds before the pseudo inverter input CLK1 is turned ON, and the counter electrode input CLKm is changed from the voltage Vds to the voltage Vgnd before the pseudo inverter input CLK2 is turned ON. To be input to the counter electrodes 51-1 and 51-2. As a result, the potential of the counter electrode input CLKm is always the same potential (same phase) as that of the DUT gate 54, no potential difference is generated in the antenna 50, and no parasitic capacitance Cm is observed.

  In the above, in the pseudo inverter 31, an example configured by a transfer gate (CMIS Switch) is shown, but other configurations may be used as long as they function similarly, for example, The transistor Tr11 made of PMIS and the transistor Tr12 made of NMIS shown in FIG. 4 may be used.

<Second configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
Next, with reference to FIG. 8, an evaluation apparatus using a monitoring method based on a charge pumping method using a CBCM circuit will be described. The evaluation apparatus in FIG. 8 includes the third feature of the present technology.

  That is, the third feature of the present technology is that, as shown in FIG. 8, the well terminal (Vwell) and the source-drain terminal (VSD) of the DUT are separated and a negative voltage is applied to the DUT gate insulating film. In this method, a negative voltage is effectively applied to the gate insulating film by adjusting the well terminal potential Vwell so that the well terminal potential Vwell> the gate potential Vds. The charge pumping current can be measured even with the CBCM circuit by using this DUT gate well terminal and source-drain terminal as separate terminals and this monitoring method.

<About effects>
Next, CV measurement results and charge pumping measurement results according to the configuration examples of FIGS. 6 and 8 will be described with reference to FIGS. 9 and 10.

  The left part of FIG. 9 shows the CV measurement result before canceling the parasitic capacitance of the antenna 50, and the right part of FIG. 9 shows the parasitic capacitance of the antenna 50 by applying the technique of the present technology. It is a CV measurement result after cancelling. In both cases, the left part of the vertical axis is the total capacity C_all obtained by adding the capacity Cm of the antenna 50 and the parasitic capacity Cp of the circuit to the capacity Cg of the gate capacity DUT 32, and the right part is described with reference to FIGS. Cm is canceled by the monitoring method and there is another method (for example, a method of extracting only Cp in a structure in which the gate capacitance DUT described in Non-Patent Document 1 is not connected. For example, Charge Injection-induced-Error-Free CBCM (CIEF-CBCM ) (Yao-Wen Chang, Hsing-Wen Chang, Chung-Hsuan Hsieh, Han-Chao Lai, Tao-Cheng Lu, Wenchi Ting, Joseph Ku, and Chih-Yuan Lu, "A Novel Simple CBCM Method Free From Charge Injection- Induced Errors "in IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 5, MAY 2004 pp.262-264)), the gate capacitance calculated after canceling Cp. This is the gate capacitance Cg of DUT32, and the horizontal axis shows the output of the pseudo inverter. This is the gate potential Vds of the gate capacitance DUT32 applied via the gate capacitance DUT32.

  That is, the parasitic capacitance of about 1 pF is dominant in the left part of FIG. 9 and it is difficult to observe the gate capacitance, whereas the right part of FIG. 9 to which the present technique is applied has several fF to several tens of fF. It has been shown that the gate capacitance can be extracted sufficiently.

  FIG. 10 shows a result of measurement for each antenna ratio (AR) by the monitoring method described with reference to the configuration example of FIG. Under constant CLK amplitude, the horizontal axis is the base voltage, and the vertical axis is the charge pumping current Icp. In FIG. 10, it can be seen that Icp increases as the antenna ratio increases, that is, the interface state density increases. That is, it is shown that the interface state density can be extracted according to the antenna ratio by applying this technique.

<Third configuration example of an evaluation device including a CBCM circuit to which the present technology is applied>
The antenna 50 may be an antenna 50A made of metal, for example, as shown in FIG.

<Fourth configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
The antenna 50 may be, for example, an antenna 50B made of Via as shown in FIG.

<Fifth configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
For example, as shown in FIG. 13, the antenna 50 may be an antenna 50C made of a through hole such as TSV (Through Silicon Via), or a chip stack structure, in which the DUT and the pseudo inverter are respectively It may be provided in different layers L1 and L2.

<Sixth configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
For example, as shown in FIG. 14, the antenna 50 may be an antenna 50D formed of a through hole such as TSV (Through Silicon Via), or has a chip laminated structure, and the antenna 50D is provided in the layer L1. The DUT and the pseudo inverter may be provided in the same layer L2.

<Seventh configuration example of an evaluation device including a CBCM circuit to which the present technology is applied>
For example, as shown in FIG. 15, the antenna 50 may be an antenna 50E formed of a through hole such as TSV (Through Silicon Via) 2 penetrating the bonding surface F of the layer L1, or a chip. The antenna 50E may be provided in the layer L1, and the DUT and the pseudo inverter may be provided in the same different layer. For the configuration of TSV1 and TSV2 in this example, refer to Japanese Patent Application Laid-Open No. 2014-082514.

<Eighth configuration example of evaluation device including CBCM circuit to which this technology is applied>
For example, as shown in FIG. 16, the antenna 50 may be an antenna 50F formed of a through hole such as TSV (Through Silicon Via) 1 that does not penetrate the bonding surface F of the layer L1, or a chip. In the stacked structure, the antenna 50F and the DUT may be provided in the layer L1, and the pseudo inverter may be provided in different layers. For the configuration of TSV1 and TSV2 in this example, refer to Japanese Patent Application Laid-Open No. 2014-082514.

<Ninth configuration example of evaluation device including CBCM circuit to which this technology is applied>
For example, as shown in FIG. 17, the antenna 50 may be a multi-layer structure of layers L1 to L3 and may be an antenna 50G made of metal, or may be a chip stack structure, and the antenna 50G and the DUT are arranged. The pseudo inverter may be provided in a different layer L3 provided in the layer L1.

<Tenth configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
When performing only capacitance measurement by the normal CBCM method, the Source / Drain / Well terminals of the MISFET may be shared as shown in FIG. This configuration is the same as the configuration shown in FIG.

<Eleventh configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
Further, when both capacitance measurement and charge pumping measurement are performed by the normal CBCM method, the source / drain and well terminals of the MISFET are separated as shown in FIG.

<Twelfth configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
Further, when measuring the current-voltage characteristics, as shown in FIG. 20, all the Source, Drain, and Well terminals of the MISFET are separated.

<13th configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
An evaluation device including a CBCM circuit to which the present technology is applied may be built in a chip which is a semiconductor device.

  FIG. 21 shows a configuration example of a chip that is a semiconductor device as an evaluation device including a CBCM circuit to which the present technology is applied, and an external measurement unit that executes correction processing according to the evaluation result.

  A plurality of chips 101 are formed on the wafer 141 (FIG. 23) and finally manufactured by dicing. The CBCM circuit 30, the body circuit 111, the internal reference voltage control unit 112, And an internal reference voltage generator 113.

  The external measurement unit 102 adjusts the internal reference voltage for each chip 101 provided on the wafer 141 (FIG. 23), and includes a Vth monitor unit 131, a Vth determination unit 132, and an internal reference voltage increase command. Part 133 is provided.

  The main circuit 111 is a circuit that realizes various functions. The CBCM circuit 30 is one of the series of circuit configurations described above. The internal reference voltage control unit 112 performs trimming by cutting the fuses F1 to Fn (fuse groups composed of a plurality of fuses) connecting the internal reference voltage generation unit 113 based on a command from the external measurement unit 102. The internal reference voltage is adjusted, and an appropriate reference voltage is supplied to the main circuit 111.

  The Vth monitor 131 of the external measurement unit 102 performs CV measurement on the CBCM circuit 30 based on the output signal, obtains a Vth shift, and supplies the Vth determination unit 132 with it.

  The Vth determination unit 132 determines whether or not the Vth shift is larger than a predetermined value, and supplies the determination result to the internal reference voltage increase command unit 133.

  When the Vth shift is larger than a predetermined value based on the determination result supplied from the Vth determination unit 132, the internal reference voltage increase command unit 133 is internally connected to the internal reference voltage control unit 122 of the target chip 101. Outputs a signal that is a command to raise the reference voltage. Based on this command, the internal reference voltage control unit 122 performs trimming by cutting the plurality of fuses F1 to Fn so as to have appropriate voltages.

<First correction processing>
Next, a first correction process for improving the yield of the chip will be described with reference to the flowchart of FIG. 22 using the measurement technique of the present technology by the chip 101 and the external measurement unit 102 of FIG.

  In step S <b> 11, a signal necessary for monitoring the Vth shift by the CBCM circuit 30, which is the evaluation device described above, is measured by CV measurement and output to the Vth monitor unit 131.

  In step S <b> 12, the Vth monitor unit 131 detects the Vth shift by the above-described method based on the detection result, and outputs it to the Vth determination unit 132.

  In step S13, the Vth determination unit 132 determines whether or not the Vth shift is larger than a predetermined value, and outputs the determination result to the internal reference voltage increase command unit 132. The internal reference voltage increase command unit 132 instructs the internal reference voltage control unit 112 of the chip 101 to increase the internal reference voltage when it is determined that the chip 101 has a Vth shift larger than a predetermined value. send. Based on this command, the internal reference voltage control unit 112 performs trimming, for example, by blowing the fuse Fn so as to increase the internal reference voltage. As a result, the internal reference voltage generation unit 113 raises the internal reference voltage and supplies it to the main circuit 111.

  That is, as shown in FIG. 23, among the chips 101-1 to 101-x arranged in an array on the plane of the wafer 141 (x is the number of chips arranged on the wafer 141), the Vth shift is For the chips 101-1 to 101-4 in a range larger than the predetermined value, for example, surrounded by a dotted line, a command is sent to increase the internal reference voltage. Based on this, the internal reference voltage control units 112 of the chips 101-1 to 101-4 perform trimming based on this command, for example, by blowing the fuse Fn so as to increase the internal reference voltage. As a result, the internal reference voltage generation unit 113 raises the internal reference voltage and supplies it to the main circuit 111.

  As a result, a product chip that is regarded as a defective product due to a Vth shift due to PID can be remedied as a non-defective product.

<Fourteenth configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
In the above description, the internal reference voltage is increased for a chip having a Vth shift larger than a predetermined value. However, it may be replaced with a functional block having high (strong) PID resistance.

  FIG. 24 shows a configuration example of a chip that is a semiconductor device as an evaluation device including a CBCM circuit, and an external measurement unit that performs correction processing according to the evaluation result and replaces it with a functional block having high PID resistance. Yes. 24, components having the same functions as those in FIG. 21 are denoted by the same names and the same reference numerals, and the description thereof will be omitted.

  That is, FIG. 24 is different from FIG. 21 in that, in the chip 101, instead of the internal voltage control unit 112 and the internal reference voltage generation unit 113, the PID tolerance function switching control unit 151 and (PID tolerance is weak = general The functional block 152 and the functional block 153 (higher PID resistance = higher than general PID resistance) are provided. The external measurement unit 102 is provided with a PID tolerance function block switching command unit 161 instead of the internal reference voltage increase command unit 133.

  That is, based on the determination result of the Vth determination unit 132, the PID tolerance function block switching instruction unit 161 instructs the chip 101 to switch to a higher tolerance PID tolerance function block when the Vth shift is larger than a predetermined value. This is supplied to the PID resistant function block switching control unit 151.

  Based on the instruction from the PID tolerance functional block switching instruction section 161, the PID tolerance function block switching control section 151 is configured such that each of the function block 152 (low PID tolerance) and the function block 153 (strong PID tolerance) is a main circuit. Switching is performed by cutting (for example, fusing) one of the fuses F101 and F102 connected to 111.

  More specifically, when there is no command from the PID resistant function block switching instruction unit 161, the PID resistant function block switching control unit 151 determines that the PID resistant need not be high, and the functional block 153 with high PID resistant is connected. The fuse F102 is cut, and the functional block 152 with low PID resistance and the main circuit 111 are connected via the fuse F101. That is, in this case, a general PID-resistant functional block 152 is connected to the main body circuit 111.

  On the other hand, when there is an instruction from the PID resistant functional block switching instruction unit 161, the PID resistant functional block switching control unit 151 determines that the PID resistant needs to be increased, and the functional block 152 having a low PID resistant is connected. The fuse F101 is disconnected, and the functional block 153 having high PID resistance and the main body circuit 111 are connected via the fuse F102. That is, in this case, the functional block 153 having higher tolerance than general PID tolerance is connected to the main circuit 111. As a result, it becomes possible to selectively connect an appropriate PID-resistant functional block, and it is possible to relieve a product chip that is considered to be defective due to a Vth shift due to PID as a good product.

<Second correction process>
Next, referring to the flowchart of FIG. 25, a chip with a Vth shift or interface state density larger than a predetermined value by the chip 101 and the external measurement unit 102 of FIG. 24 has high (strong) PID resistance. The second correction process that replaces the functional block will be described.

  That is, when the Vth shift or the interface state density is measured by the processes of steps S31 and S32 as in the processes of steps S11 and S12 in FIG. 22 described above, the Vth shift or interface state density is determined in step S33. In the case of the chip 101 larger than the predetermined value, the PID resistant function block switching command unit 161 sends an instruction to the PID resistant function block switching control unit 151 so as to switch to a functional block having high PID resistance. As a result, the PID resistant function block switching instruction unit 161 cuts the fuse F101 based on the instruction from the PID resistant function block switching instruction unit 161 to connect the functional block 153 having high PID resistance and the main circuit 111 to the fuse F102. Is connected to the function block 153 having high PID resistance.

  On the other hand, in step S33, in the case of the chip 101 whose Vth shift or interface state density is not larger than a predetermined value, the PID resistant function block switching instruction unit 161 sends a function block having weak PID resistance to the PID resistant function block switching control unit 151. Do not send a command to switch to. As a result, the PID tolerance functional block switching instruction unit 161 cuts the fuse F102 and keeps the functional block 152 with weak PID tolerance connected to the main circuit 111 via the fuse F101.

  As a result, even in the above processing, a product chip that is regarded as a malfunctioning product due to a Pth Vth shift can be relieved as a non-defective product.

  In the above, the example in which each step of FIG. 22 or FIG. 25 is executed in cooperation with the external measurement unit 102 and the chip 101 which is a semiconductor device has been described, but the same function is mounted in the product chip 101. Thus, it may be executed alone in the chip 101. Further, the trimming of the internal reference voltage or the switching to the functional block having a strong PID resistance is executed by cutting the fuse, but it may be replaced with another functional block having a switching function. Furthermore, in the above description, two cases, the case where the Vth shift is higher than the predetermined value and the case where the Vth shift is lower, have been described. By implementing trimming or switching to a functional block with strong PID tolerance, a product chip that becomes a defective product may be more appropriately relieved as a non-defective product.

<Fifteenth configuration example of an evaluation apparatus including a CBCM circuit to which the present technology is applied>
In the above, an example in which the input of the clock signal is three systems has been described. However, an input of only one clock may be separated into three systems and operated.

  FIG. 26 shows a configuration example of an evaluation apparatus in which an input of only one system clock is separated into three systems. In addition, about the structure provided with the same function as the structure of FIG. 6, the same name and the same code | symbol are attached | subjected, and the description shall be abbreviate | omitted suitably.

  That is, the circuit configuration of the evaluation apparatus of FIG. 26 is different from the configuration of FIG. 6 in only one system of the pseudo-inverter input CLK terminal, which is provided with a CLK_ENABLE terminal and an Antenna_Cap_Cancelling_ENABLE terminal. Further, instead of the terminals Vds and Vgnd, terminals Vds1, Vgnd1, Vds2 and Vgnd2 are provided. 183 and transistors Tr31 to Tr34.

  As a result, it is possible to realize processing of three clock signals with one clock signal, and to drive the CBCM circuit described above.

  Based on the above, by applying the structure and measurement method of this technology to a well-known CBCM circuit capable of measuring minute capacitance, Vth shift mode PID monitoring is possible for DUTs with almost the same area as MISFETs used in product chips It becomes.

  Further, since the interface state density can be monitored with the same DUT, the correlation between the Vth shift and the interface state density with the same DUT can be obtained. As a result, we can expect the effect of investigating PID mechanism, presenting guidelines for process improvement, and obtaining correlation with product characteristics.

  In addition, because the mounting area is small and can be mounted on product chips, not only can you manage the time-series trend of Vth shift mode PID, but it can also be used as an index to improve product yield, such as boosting the internal voltage only for chips with a large Vth shift. We can expect utilization.

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

  In addition, each step described in the above flowchart can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.

  Further, when a plurality of processes are included in one step, the plurality of processes included in the one step can be executed by being shared by a plurality of apparatuses in addition to being executed by one apparatus.

In addition, this technique can also take the following structures.
(1) A CBCM (Charge Based Capacitance Measurement) circuit having a pseudo inverter is connected to a MISFET (Metal Insulator Semiconductor Field-Effect Transistor) serving as a DUT (Device Under Test), and the MISFET PID (Plasma (Process) Induced In an evaluation device for evaluating (Damage),
An evaluation apparatus in which a gate of the DUT and an antenna are connected in parallel.
(2) The evaluation device according to (1), wherein the antenna and the output of the pseudo inverter are connected by a wiring higher than the antenna.
(3) The evaluation apparatus according to (2), wherein after the gates of the DUT and the pseudo inverter are formed, the antenna connected to the DUT is formed and then connected in an upper layer than the antenna.
(4) The evaluation apparatus according to any one of (1) to (3), further including a counter electrode of the antenna.
(5) The evaluation device according to any one of (1) to (4), wherein the capacity of the DUT is approximately several fF to several tens fF.
(6) The evaluation apparatus according to any one of (1) to (5), wherein the pseudo inverter includes a PMISFET and an NMISFET.
(7) The evaluation apparatus according to any one of (1) to (6), wherein the pseudo inverter includes a transfer gate (CMISFET Switch).
(8) The evaluation device according to any one of (1) to (7), wherein the antenna is a through hole in a multilayer chip structure including a multilayer chip.
(9) The antenna has a multilayer chip structure composed of multilayer chips,
The evaluation apparatus according to any one of (1) to (8), wherein the pseudo inverter and the DUT are arranged on each chip of the multilayer chip.
(10) It further includes an antenna counter electrode disposed to face the antenna,
The evaluation device according to any one of (1) to (9), wherein a clock signal in phase with the gate of the DUT is input to the antenna counter electrode.
(11) The circuit further includes a circuit for branching and generating a clock signal input to the antenna counter electrode and two clock signals input to the CBCM circuit from one clock signal (1) to (10) The evaluation apparatus of crab.
(12) The evaluation apparatus according to any one of (1) to (11), wherein a source / drain terminal and a well terminal of the DUT are separated.
(13) The evaluation device according to any one of (1) to (12), wherein a voltage of the Well terminal is higher than a voltage of the gate of the DUT, and a negative voltage is effectively applied to the MISFET.
(14) The evaluation device according to any one of (1) to (13), further including a current measurement unit that measures the charge pumping current.
(15) A CBCM (Charge Based Capacitance Measurement) circuit having a pseudo inverter and a MISFET (Metal Insulator Semiconductor Field-Effect Transistor) serving as a DUT (Device Under Test) are connected, and the PID (Plasma (Process) Induced of the MISFET A semiconductor device including an evaluation device for evaluating (Damage),
The gate of the DUT and the antenna are connected in parallel,
A semiconductor device comprising: a correction unit that boosts an internal power supply voltage by trimming only a chip having a large Vth shift after detecting a Vth shift as the PID.
(16) The semiconductor device according to (15), wherein the correction unit boosts an internal power supply voltage only for a chip in which the Vth shift is larger than a predetermined value.
(17) The correction unit mounts a circuit with strong PID tolerance in advance, and cuts a circuit with low PID resistance with a fuse for a chip with the Vth shift larger than a predetermined value, to make a circuit with high resistance. Switch The semiconductor device according to (15).
(18) The semiconductor device according to (15), wherein a circuit with a weaker PID resistance is switched from a circuit with a weaker PID tolerance to a chip with a larger Vth shift than the predetermined value.
(19) A CBCM (Charge Based Capacitance Measurement) circuit having a pseudo inverter and a MISFET (Metal Insulator Semiconductor Field-Effect Transistor) serving as a DUT (Device Under Test) are connected, and the PID (Plasma (Process) Induced of the MISFET In a semiconductor device to evaluate damage)
A semiconductor device manufactured under a plasma process condition determined based on an evaluation result of an evaluation device in which a gate and an antenna of the DUT are connected in parallel.

  11 Gate Capacitance DUT (Device Under Test), 12, 12 'Antenna, 13 Protection Diode, 30 CBCM (Charge Based Capacitance Measurement) Circuit, 31 Pseudo Inverter, 32 Gate Capacitance DUT (Device Under Test), 50, 50A Through 50G antenna, 51, 51-1, 51-2 counter electrode, 52 through 54 electrode, 101 chip, 102 external measurement unit, 111 body circuit, 112 internal reference voltage control unit, 113 internal reference voltage Generation unit, 131 Vth monitor unit, 132 Vth determination unit, 133 internal reference voltage increase command unit, 141 wafer, 151 PID tolerance function block switching control unit, 152 (weak PID tolerance) function block, 153 (strong PID tolerance) Functional block, 161 PID tolerance functional block switching command part

Claims (19)

A CBCM (Charge Based Capacitance Measurement) circuit with a pseudo-inverter and a MISFET (Metal Insulator Semiconductor Field-Effect Transistor) that is a DUT (Device Under Test) are connected, and the PID (Plasma (Process) Induced Damage) of the MISFET In the evaluation device to evaluate,
An evaluation apparatus in which a gate of the DUT and an antenna are connected in parallel. The evaluation apparatus according to claim 1, wherein the antenna and the output of the pseudo inverter are connected to each other by wiring above the antenna. The evaluation apparatus according to claim 2, wherein after the gates of the DUT and the pseudo inverter are formed, the antenna connected to the DUT is formed and then connected in an upper layer than the antenna. The evaluation apparatus according to claim 1, further comprising a counter electrode of the antenna. The evaluation apparatus according to claim 1, wherein a capacity of the DUT is approximately several fF to several tens fF. The evaluation apparatus according to claim 1, wherein the pseudo inverter includes a PMISFET and an NMISFET. The evaluation apparatus according to claim 1, wherein the pseudo inverter includes a transfer gate (CMISFET Switch). The evaluation apparatus according to claim 1, wherein the antenna is a through hole in a multilayer chip structure including a multilayer chip. The antenna has a multilayer chip structure composed of multilayer chips,
The evaluation apparatus according to claim 1, wherein the pseudo inverter and the DUT are arranged on each chip of the multilayer chip. An antenna counter electrode disposed opposite to the antenna;
The evaluation apparatus according to claim 1, wherein a clock signal having the same phase as that of the gate of the DUT is input to the antenna counter electrode. The evaluation apparatus according to claim 1, further comprising: a circuit that branches and generates a clock signal input to the antenna counter electrode and two clock signals input to the CBCM circuit from one clock signal. The evaluation apparatus according to claim 1, wherein a source / drain terminal and a well terminal of the DUT are separated. The evaluation apparatus according to claim 1, wherein a voltage of the Well terminal is higher than a voltage of a gate of the DUT, and a negative voltage is effectively applied to the MISFET. The evaluation apparatus according to claim 1, further comprising a current measurement unit that measures the charge pumping current. A CBCM (Charge Based Capacitance Measurement) circuit with a pseudo-inverter and a MISFET (Metal Insulator Semiconductor Field-Effect Transistor) that is a DUT (Device Under Test) are connected, and the PID (Plasma (Process) Induced Damage) of the MISFET A semiconductor device including an evaluation device for evaluation,
The gate of the DUT and the antenna are connected in parallel,
A semiconductor device comprising: a correction unit that boosts an internal power supply voltage by trimming only a chip having a large Vth shift after detecting a Vth shift as the PID. The semiconductor device according to claim 15, wherein the correction unit boosts an internal power supply voltage only for a chip in which the Vth shift is larger than a predetermined value. The correction unit is mounted in advance with a circuit with strong PID tolerance, and for a chip with the Vth shift larger than a predetermined value, a circuit with weak PID resistance is cut with a fuse and switched to a circuit with high resistance. 15. The semiconductor device according to 15. The semiconductor device according to claim 15, wherein a circuit with a weaker PID tolerance is switched from a circuit with a weaker PID tolerance to a chip with a larger Vth shift than the predetermined value. A CBCM (Charge Based Capacitance Measurement) circuit with a pseudo-inverter and a MISFET (Metal Insulator Semiconductor Field-Effect Transistor) that is a DUT (Device Under Test) are connected, and the PID (Plasma (Process) Induced Damage) of the MISFET In the semiconductor device to be evaluated,
The gate of the DUT and the antenna are connected in parallel,
A semiconductor device manufactured under the plasma process conditions determined based on the evaluation result of the evaluation device.

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