JP2016091534A - Memory system and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve efficiency of control over a nonvolatile memory.SOLUTION: A memory system includes a nonvolatile memory, a configuration unit, an address translation unit, a write unit and a control unit. The configuration unit assigns a plurality of write management areas included in the nonvolatile memory to a plurality of spaces and an input space. The write management area is a unit of an area which manages the number of write. The address translation unit associates a logical address of write data with a physical address which indicates a position of the write data in the nonvolatile memory. The write unit writes the write data to the input space and then writes the write data in the input space to a space corresponding to the write data amongst the plurality of spaces. The control unit controls the plurality of spaces individually with respect to the nonvolatile memory.SELECTED DRAWING: Figure 1

Description

  Embodiments relate to a memory system and a program.

  A solid state drive (SSD) includes a nonvolatile semiconductor memory and has an interface similar to that of a hard disk drive (HDD). For example, the SSD receives a write command, a write destination LBA (Logical Block Addressing), and write data from the information processing apparatus at the time of data writing, and converts the LBA to PBA (Physical Block Addressing) based on the LUT (Look Up Table). Convert and write the write data at the position indicated by PBA.

JP 2013-191174 A

  Embodiments provide a memory system and a program that improve the efficiency of control over a nonvolatile memory.

  According to the embodiment, the memory system includes a nonvolatile memory, a setting unit, an address conversion unit, a writing unit, and a control unit. The setting unit allocates a plurality of write management areas included in the nonvolatile memory to a plurality of spaces and input spaces. The write management area is an area for managing the number of writes. The address conversion unit associates the logical address of the write data with the physical address indicating the position of the write data in the nonvolatile memory. The writing unit writes the write data in the input space, and then writes the write data in the input space into a space corresponding to the write data among the plurality of spaces. The control unit controls the nonvolatile memory for each of a plurality of spaces.

1 is a block diagram showing an example of the configuration of an information processing system according to a first embodiment. The block diagram which shows an example of the relationship between LBA space, a name space, an address conversion table, a garbage collection part, and management data. The flowchart which shows an example of the process of the reception part and setting part which concern on 1st Embodiment. 5 is a flowchart illustrating an example of processing of a garbage collection unit and an address conversion unit according to the first embodiment. The block diagram which shows an example of a structure of the information processing system which concerns on 2nd Embodiment. The data structure figure showing an example of the conversion table concerning a 2nd embodiment. 9 is a flowchart showing an example of first write processing of the memory system according to the second embodiment. 9 is a flowchart showing an example of second write processing of the memory system according to the second embodiment. 10 is a flowchart illustrating an example of a read process of the memory system according to the second embodiment. The block diagram which shows an example of a structure of the information processing system which concerns on 3rd Embodiment. The perspective view which shows the storage system which concerns on 3rd Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, about the same function and component, the same code | symbol is attached | subjected and duplication description is performed only when necessary. In the following embodiments, access means both data reading and data writing.

[First Embodiment]
FIG. 1 is a block diagram illustrating an example of the configuration of the information processing system according to the present embodiment.

  The information processing system 1 includes an information processing device 2 and a memory system 3. The information processing system 1 may include a plurality of information processing devices 2. A case where the information processing system 1 includes a plurality of information processing apparatuses will be described in a second embodiment described later.

  The memory system 3 is, for example, an SSD, and includes a controller 4 and a nonvolatile memory 5. The memory system 3 may be built in the information processing apparatus 2, and the information processing apparatus 2 and the memory system 3 may be connected to each other so as to be able to transmit and receive data via a network or the like.

  In the present embodiment, for example, at least one NAND flash memory is used as the nonvolatile memory 5. However, the present embodiment is, for example, a NOR flash memory, an MRAM (Magnetoresistive Random Access Memory), a PRAM (Phase change Random Access Memory), a ReRAM (Resistive Random Access Memory), or an FeRAM (Ferroelectric Random Access Memory). Such various kinds of nonvolatile memories can be applied when including a plurality of write management areas. Here, the write management area is a unit area for managing the number of times of writing. The nonvolatile memory 5 may include a three-dimensional memory.

  For example, the nonvolatile memory 5 includes a plurality of blocks (physical blocks). The plurality of blocks include a plurality of memory cells arranged at intersections of word lines and bit lines. In the non-volatile memory 5, data is erased collectively in block units. That is, the block is an area of a data erasing unit. Data writing and data reading are performed in units of pages (word lines) in each block. That is, a page is an area of a data writing unit or a data reading unit.

  In this embodiment, it is assumed that the write count is managed in units of blocks.

  The information processing device 2 is a host device of the memory system 3. The information processing apparatus 2 sends to the memory system 3 a setting command C1 for associating the block of the nonvolatile memory 5 with a space including at least one block.

  In the following description, a space is described as a name space.

  Further, the information processing apparatus 2 sends the namespace identification data (NSID) 6, the LBA 7 indicating the write destination, the data size 8 of the write data, and the write data 9 together with the write command C 2 to the memory system 3.

In the present embodiment, each of the plurality of namespaces NS _{0 to} NS _M (M is an integer of 1 or more) includes a plurality of blocks B _{0 to} B _N (N is an integer of M or more) included in the nonvolatile memory 5. It is a space obtained by partitioning. In the present embodiment, the name space NS ₀ includes blocks B _{0 to} B ₂ , and the name space NS _M includes blocks B _{N−2 to} B _N. It is assumed that the other namespaces NS _{1 to} NS _M-1 are the same as the namespaces NS ₀ and NS _M.

Further, in the present embodiment, the namespaces NS _{0 to} NS _M are divided into a plurality of input groups IG _{0 to} IG _P (P is an integer of 1 or more). The namespaces NS _{0 to} NS _M may be handled as one input group without being divided.

Input group IG ₀ contains the name space NS _0, NS _1, input group IG _P includes the name space NS _M-1 ~NS _M. The other input groups IG ₁ ~IG _P-1 is also similar to the input group IG _0, IG _P.

In addition, input group IG ₀ ~IG _P, respectively, including the input name space INS ₀ ~INS _P.

Each of the input name spaces INS _{0 to} INS _P includes three blocks B. However, the number of blocks B included in the input name space INS ₀ may be one or more.

Hereinafter, the input namespace INS ₀ will be described using the input group IG ₀ including the namespaces NS ₀ and NS ₁ .

The input namespace INS ₀ stores write data 9 for the namespaces NS ₀ and NS ₁ . In the present embodiment, it is assumed that the input namespace INS ₀ does not store data from the namespaces NS ₀ and NS ₁ . The input name space INS ₀ may move data between blocks in the input name space INS ₀ .

Data stored in the input namespace INS ₀ is namespace NS ₀ or namespace when separate garbage collection against NS ₁ is executed, the namespace is executed garbage collection NS ₀ or namespace NS Stored in ₁ .

In the present embodiment, the allocation relationship between the namespaces NS _{0 to} NS _M and the blocks B _{0 to} B _N , the allocation relationship between the input namespaces INS _{0 to} INS _P and the block B, and the namespace NS ₀ to The assignment relationship between NS _M and the input namespaces INS _{0 to} INS _P is an example, and the number of blocks assigned to one name space, the number of blocks assigned to one input namespace, and one input group are assigned. The number of namespaces can be changed as appropriate. For example, the input namespaces INS _{0 to} INS _P assigned to the namespaces NS _{0 to} NS _M may be selectable. The number of blocks may be different between the plurality of namespaces NS _{0 to} NS _M , and the number of blocks may be different between the plurality of input namespaces INS _{0 to} INS _P.

The controller 4 includes a storage unit 10, buffer memories F _{0 to} F _M , and a processor 11.

The storage unit 10 stores address conversion tables (address conversion data) T _{0 to} T _M corresponding to the namespaces NS _{0 to} NS _M. For example, the storage unit 10 may be used as a working memory. The storage unit 10 may be a volatile memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), or may be a nonvolatile memory. The storage unit 10 may be a combination of a nonvolatile memory and a volatile memory.

The address conversion tables T _{0 to} T _M are data in which LBAs and PBAs are related in writing data to the namespaces NS _{0 to} NS _M , for example, LUTs. Part or all of the address conversion tables T _{0 to} T _M may be stored in another memory such as the memory 12.

Buffer memory F ₀ to F _M, respectively, in writing data in the namespace NS ₀ ~NS _M, stores to a data amount suitable to write data to the write. In the present embodiment, the buffer memory F ₀ to F _M are respectively provided for each namespace NS ₀ ~NS _M. However, a buffer memory may be provided for each of the input namespaces INS _{0 to} INS _P. In this case, the number of buffer memories can be reduced.

The processor 11 includes a memory 12, receiving unit 13, setting unit 14, the address conversion section 15, write section 16, the garbage collection unit G ₀ ~G _Y.

  The memory 12 stores a program 17 and management data 18. In the present embodiment, the memory 12 is included in the processor 11, but may be provided outside the processor 11. The memory 12 is a nonvolatile memory, for example. Part or all of the program 17 and the management data 18 may be stored in another memory such as the storage unit 10.

The program 17 is firmware, for example. The processor 11 executes a program 17, reception unit 13, setting unit 14, the address conversion section 15, write section 16, which functions as a garbage collection unit G ₀ ~G _Y.

The management data 18 includes the relationship between the namespaces NS _{0 to} NS _M and the blocks B _{0 to} B _N , the relationship between the input namespaces INS _{0 to} INS _P and the block B, the namespaces NS _{0 to} NS _M and the input namespace INS. _{0 to} INS _P is data indicating the relationship (input groups IG _{0 to} IG _P ). By referring to the management data 18, it can be determined which block belongs to which namespace or input namespace, and which input namespace is assigned to which namespace.

Further, in the present embodiment, the management data 18 includes the relationship between the data stored in the input namespaces INS _{0 to} INS _P and the namespaces NS _{0 to} NS _M corresponding to the data, the input namespaces INS _{0 to} INS. amount of data for each namespace NS ₀ ~NS _M stored in _P, the write data amount of each namespace NS ₀ ~NS _M, the maximum amount of data that can be written per namespace NS ₀ ~NS _M, Various data such as the write time data of block B included in the input namespace INS _{0 to} INS _P (the time when the write was executed), the amount of valid data for each block B included in the input namespace INS _{0 to} INS _P Contains information.

  In the present embodiment, the data amount may be represented by, for example, a data size or a block size. For example, when the data size of each data is the same, the data amount may be represented by the number of data or the number of blocks.

  The receiving unit 13 receives a setting command C <b> 1 for associating each block of the nonvolatile memory 5 with each name space from the information processing device 2. The accepting unit 13 accepts a write command C 2, NSID 6, LBA 7, data size 8, and data 9 from the information processing apparatus 2.

In the following description, for simplification of the description, the write command C2, it will be described a case where NSID6 showing a namespace NS ₀ is attached. However, it is also possible to attach NSIDs indicating other namespaces NS _{1 to} NS _M to the write command C2.

When the receiving unit 13 receives the namespace setting command C1, the setting unit 14 assigns blocks B _{0 to} B _N to the namespaces NS _{0 to} NS _M based on the setting command C1, and inputs the input namespace INS. _{0 ~INS P} to allocate the block B, assigned the namespace NS ₀ ~NS _M to the input namespace INS _{0 ~INS P,} to set the input group IG ₀ ~IG _P.

Allocation between the namespace NS ₀ ~NS _M and the block B ₀ .about.B _N is setting unit 14 monitors the data storage state of namespace NS ₀ ~NS _M, each namespace NS ₀ ~NS _M, The data capacity, the access frequency, the write frequency, the access count, the write count, or the data storage rate may be performed at the same level, or may be performed in accordance with an instruction from the information processing device 2, and the memory This may be performed in accordance with an instruction from an administrator of the system 3.

  Here, the data capacity is the writable data size, the access frequency or the write frequency is the number of accesses or the number of writes per unit time, and the data storage rate is the size of the area where data has been stored for a certain area size A value indicating the ratio of.

The setting unit 14, the namespace NS ₀ ~NS _M on the information assigned to the block B ₀ .about.B _N, Input namespace INS ₀ ~INS _P on information allocates a block B, Input namespace INS ₀ ~INS _P Information in which the namespaces NS _{0 to} NS _M are allocated, information indicating the relationship between the data stored in the input namespaces INS _{0 to} INS _P and the namespaces NS _{0 to} NS _M corresponding to the data, the input namespace INS ₀ ~INS amount of data corresponding to the stored respective namespace NS ₀ and ～NS _M to _P, the write data amount of each namespace NS ₀ ~NS _M, writing for each namespace NS ₀ ~NS _M maximum amount of data that can be, Bro contained in input namespace INS ₀ ~INS _P It generates management data 18 including click write time data, the data amount such as various kinds of information of the valid data of each block B Input namespace INS ₀ ~INS _P, storing management data 18 in the memory 12.

For example, the setting unit 14, each time the data in the input namespace INS ₀ ~INS _P is written, the data amount of data for each namespace NS ₀ ~NS _M stored in the input namespace INS ₀ ~INS _P Ask. The setting unit 14, a predetermined corresponding to the namespace NS ₀ ~NS _M from the data amount, the data for each namespace NS ₀ stored in the input namespace INS ₀ ~INS _P obtained ～NS _M A number of blocks corresponding to a value obtained by subtracting the data amount is allocated to the namespaces NS _{0 to} NS _M.

For example, the setting unit 14, and namespace NS ₀ ~NS _M, information indicating the relationship between the amount of data for each namespace NS ₀ ~NS _M stored in the input namespace INS ₀ ~INS _P, Managed by management data 18.

For example, the setting unit 14 selects a data movement target block from among the blocks B included in the input name spaces INS _{0 to} INS _P. Setting unit 14, if the valid data corresponding to the namespace NS ₀ ~NS _M is stored in the block data migration target has been moved to a block of namespace NS ₀ ~NS _M corresponding to the valid data, The amount of valid data moved to the name spaces NS _{0 to} NS _M is subtracted from the amount of data for the name spaces NS _{0 to} NS _M stored in the input name spaces INS _{0 to} INS _P. Then, the setting unit 14 updates the management data 18 with the subtracted value.

Here, as a method for selecting a block to which valid data is moved, the setting unit 14 selects a block with the oldest write time data among the blocks B included in the input name spaces INS _{0 to} INS _P as a block to be moved. You may choose as

As a method for selecting a block to which valid data is to be moved, the setting unit 14 selects a block having the smallest amount of valid data from among the blocks B included in the input name spaces INS _{0 to} INS _P as a data movement target block. You may choose. Further, in the present embodiment, for example, among the blocks included in the input name spaces INS _{0 to} INS _P , a block whose effective data amount is less than the first threshold value is selected as a data movement target block. You may choose as

The setting unit 14 inputs the input namespaces INS _{0 to} INS _P when the amount of valid data stored in the data movement target block selected to move valid data is smaller than the second threshold value. The number of blocks allocated to may be reduced. On the contrary, the setting unit 14 assigns the number of blocks to be assigned to the input namespaces INS _{0 to} INS _P when the amount of valid data stored in the data movement target block is larger than the third threshold value. You may increase.

For example, when the number of blocks included in the input namespace INS _{0 to} INS _P is larger than the fourth threshold value, the setting unit 14 selects a block to be moved from the input namespace INS _{0 to} INS _P. May be. In this case, the writing unit 16 moves the valid data stored in the data movement target block to the namespaces NS _{0 to} NS _M corresponding to the valid data. Then, the setting unit 14 reduces the number of blocks included in the input namespaces INS _{0 to} INS _P and increases the number of blocks included in the namespaces NS _{0 to} NS _M.

In addition, based on the result of the garbage collection performed for each of the namespaces NS _{0 to} NS _M , the setting unit 14 converts empty blocks that do not store data from the namespace that belongs to the garbage collection to another namespace. And the management data 18 is updated. As a result, wear leveling can be performed between the namespaces NS _{0 to} NS _M. The allocation change between the namespaces NS _{0 to} NS _M and the blocks B _{0 to} B _N is performed when the setting unit 14 monitors the data storage state of the namespaces NS _{0 to} NS _M and generates the management data 18 described above. Similarly, it may be performed according to the monitoring result, may be performed according to an instruction from the information processing apparatus 2, or may be performed according to an instruction from an administrator of the memory system 3. For example, the name space NS _{0 to} NS _M is changed by changing an empty block of a name space with a small data capacity, a low access frequency, a low access frequency, or a low data storage rate to a high data capacity or an access frequency. The name space is converted into a name space with a high access frequency or a high data storage rate.

Further, for over provisioning, the setting unit 14 normally stores in the nonvolatile memory 5 for each of the namespaces NS _{0 to} NS _M and the input namespaces INS _{0 to} INS _P based on the setting command C 1. Spare areas P _{0 to} P _Y that are not used are set. The setting of the spare areas P _{0 to} P _Y may be performed by the setting unit 14 according to the data capacity of the name spaces NS _{0 to} NS _M and the input name spaces INS _{0 to} INS _P. It may be performed according to an instruction, or may be performed according to an instruction from an administrator of the memory system 3.

In the present embodiment, the spare areas P _{0 to} P _Y are secured in the nonvolatile memory 5, but may be secured in another memory in the memory system 3 that is not the nonvolatile memory 5. For example, the spare areas P _{0 to} P _Y may be secured in a memory such as DRAM or SRAM.

The address conversion unit 15, when a write command C2 is received by the receiving unit 13, the address conversion table T ₀ corresponding to the namespace NS ₀ indicated by NSID6 had been subjected to the write command C2, the write command C2 The association for converting the LBA 7 attached to the PBA into the PBA is performed.

For example, the address conversion unit 15, at the time of writing, the LBA7, in association with the PBA Input namespace INS _0, updates the address conversion table T _0. Further, the address converting unit 15, when the relationship between LBA7 and PBA is changed by moving the data from the input namespace INS ₀ to namespace NS _0, in association with the PBA of LBA7 and namespace NS _0, It updates the address conversion table T _0.

  In the present embodiment, the address conversion unit 15 is realized by the processor 11. However, the address conversion unit 15 may have a configuration different from that of the processor 11.

The address conversion unit 15 performs address conversion based on the address conversion tables T _{0 to} T _M , but may perform address conversion by key value type search instead. For example, by using LBA as a key and PBA as a value, address conversion by key-value search can be realized.

The write unit 16 writes the write data 9 to the position indicated by the PBA in the Input namespace INS ₀ ~INS _P obtained by the address converting unit 15, then, obtained by the address converter 15 from the input namespace INS ₀ ~INS _P Write data 9 is written at a position indicated by PBA in the designated name spaces NS _{0 to} NS _M.

In the present embodiment, the writing unit 16 stores the write data 9 in the buffer memory F ₀ corresponding to the name space NS ₀ indicated by the NSID 6 attached to the write command C2. Next, the write unit 16, when the buffer memory F ₀ becomes data amount suitable for the input namespace INS ₀ or namespace NS _0, the input namespace INS _0, writes the data in the buffer memory F _0. The write unit 16, for example, based on the execution of the garbage collection for the namespace NS _0, the valid data corresponding to the namespace NS ₀ is stored in the block of the selected data migration target by setting unit 14, Move to a block in namespace NS ₀ associated with the valid data. For example, the writing unit 16, the valid data corresponding to the namespace NS ₀ is stored in the input namespace INS ₀ together when the garbage collection performed for the namespace NS _0, writes the namespace NS _0. The data movement from the input namespace INS ₀ to the namespace NS ₀ by the writing unit 16 may be executed at an arbitrary timing.

Garbage collection unit G ₀ ~G _Y corresponds to the namespace NS ₀ ~NS _M and input namespace INS ₀ ~INS _P, for each namespace NS ₀ ~NS _M and input namespace INS ₀ ~INS _P Garbage collection can be performed independently. Garbage collection is a process of releasing a memory area that is no longer needed, or a process of collecting data written in a memory area with a gap and securing a continuous usable memory area. The garbage collection units G _{0 to} G _Y may execute garbage collection in parallel, or may sequentially execute the garbage collection units G _{0 to} G _Y.

It will be specifically described with reference to garbage collection unit G ₀ of the garbage collection unit G ₀ ~G _Y. The garbage collection unit G ₀ first selects blocks B _{0 to} B ₂ corresponding to the name space NS ₀ based on the management data 18. Next, the garbage collection unit G ₀ performs garbage collection on the selected blocks B _{0 to} B ₂ . Then, based on the garbage collection result by the garbage collection unit G ₀ , the address conversion unit 15 updates the address conversion table T ₀ .

In the present embodiment, LBA and PBA are associated with each other in the address conversion tables T _{0 to} T _M , and a block that can be identified with PBA and NSID are associated with each other in the management data 18. Therefore, if the management data 18 is generated with a unique address that does not overlap the LBA, the processor 11 can identify the write destination namespace NS ₀ from the LBA 7 attached to the write command C2. Therefore, after the LBA 7 is not duplicated and the management data 18 is generated, the NSID 6 is not added to the write command C 2, and the processor is based on the LBA 7, the address conversion tables T _{0 to} T _M, and the management data 18. NSID 6 may be obtained on the 11th side.

FIG. 2 is a block diagram illustrating an example of the relationship among the LBA space, the namespaces NS _{0 to} NS _M , the address conversion tables T _{0 to} T _M , the garbage collection units G _{0 to} G _M, and the management data 18. is there.

LBA space A ₀ to A _M of the information processing apparatus 2 are respectively assigned to the namespace NS ₀ ~NS _M.

LBA space A ₀ includes logical addresses ₀ to E ₀ . LBA space A ₁ includes logical addresses 0 to E ₁ . The LBA space A _M includes logical addresses 0 to E _M. The other LBA spaces A _{2 to} A _M-1 similarly include a plurality of logical addresses.

In the following description, to simplify the description, it will be described as a representative and namespace NS ₀ being allocated to LBA space A ₀ Toko of LBA space A _0. However, the same applies to the other LBA spaces A _{1 to} A _M and the name spaces NS _{1 to} NS _M.

The information processing apparatus 2, LBA data space A ₀ when writing to a non-volatile memory 5, the write command C2, LBA NSID6 shows a namespace NS ₀ corresponding to the spatial A _0, LBA space A ₀ in LBA7, data Write data 9 corresponding to size 8 and LBA 7 is sent to the memory system 3.

The management data 18 is associated with the name space NS ₀ and the blocks B _{0 to} B ₂ .

Garbage collection unit G _0, based on the management data 18, the block B ₀ .about.B ₂ contained in the namespace NS ₀ corresponding to garbage collection unit G _0, performs garbage collection.

As a result of the garbage collection, the arrangement of data changes in the blocks B _{0 to} B ₂ . For this reason, the garbage collection unit G ₀ instructs the address conversion unit 15 omitted in FIG. 2 to update the address conversion table T ₀ , so that the address conversion unit 15 matches the data arrangement after the garbage collection. , to update the address conversion table T ₀ corresponding to the name space NS _0.

  FIG. 3 is a flowchart illustrating an example of processing of the reception unit 13 and the setting unit 14 according to the present embodiment.

In step S301, the reception unit 13 receives a setting command C1 for the namespaces NS _{0 to} NS _M.

In step S302, the setting unit 14, information on a namespace NS ₀ ~NS _M was assigned a block B ₀ .about.B _N, Input namespace INS ₀ ~INS _{information P} to the allocated block B, Input namespace INS ₀ ~ information assigned a namespace NS ₀ ~NS _M in INS _P, information indicating the relationship between the namespace NS ₀ ~NS _M corresponding to the data and the data stored in the input namespace INS ₀ ~INS _P, other The management data 18 including the various types of information is generated.

  In step S <b> 303, the setting unit 14 stores the management data 18 in the memory 12.

In step S304, the setting unit 14 determines whether to update the management data 18 or not. For example, the setting unit 14 determines to update the management data 18 when data is moved from the input namespace INS _{0 to} INS _P to the namespace NS ₀ to NS _M based on execution of garbage collection.

  If the management data 18 is not updated, the process moves to step S307.

  When updating the management data 18, the setting unit 14 updates the management data 18 in step S305.

  In step S <b> 306, the setting unit 14 stores the updated management data 18 in the memory 12.

  In step S307, the setting unit 14 determines whether or not to continue the process.

  When the process is continued, the process moves to step S304.

  If the process is not continued, the process ends.

Figure 4 is a flowchart illustrating an example of a process of garbage collection unit G ₀ and the address converting unit 15 according to the present embodiment. Incidentally, the same processing even other garbage collection unit G ₁ ~G _M is performed. The process of FIG. 4 may be performed according to an instruction from the information processing apparatus 2, for example, or may be performed according to an instruction from an administrator of the memory system 3. Further, the garbage collection unit G ₀ spontaneously executes the process of FIG. 4 such as monitoring the data storage state of the namespace NS ₀ subject to garbage collection and determining the start of garbage collection. Also good. To be more specific, for example, garbage collection unit G ₀ is less than a predetermined number of free blocks in the namespace NS _0, or the proportion of free blocks for all block in the namespace NS ₀ is less than the predetermined value, the In this case, garbage collection is executed for the namespace NS ₀ .

In step S401, garbage collection unit G _0, based on the management data 18, selects a block B ₀ .about.B ₂ corresponding to the namespace NS ₀ subject to garbage collection.

In step S402, garbage collection unit G ₀ performs garbage collection for the block B ₀ .about.B ₂ in the namespace NS ₀ selected. Based on the execution of the garbage collection, the writing unit 16 may move data from the input namespace INS ₀ to the namespace NS ₀ .

In step S403, the address converter 15, the address conversion table T ₀ corresponding to the namespace NS ₀ subject to garbage collection, after the garbage collection of the block B ₀ .about.B ₂ state and block B Input namespace INS ₀ Update according to the state.

Above in the present embodiment described, each namespace NS ₀ ~NS _M, can be assigned a block amount set by the predetermined or the information processing apparatus 2, corresponding to the namespace NS ₀ ~NS _M data can be written into that namespace NS ₀ ~NS blocks B allocated to the _{M 0} .about.B _N, it is possible to set a different data amount for each namespace NS ₀ ~NS _M.

In the present embodiment, data stored in the input namespaces INS _{0 to} INS _P can be moved to the namespaces NS _{0 to} NS _M at an arbitrary timing such as execution of garbage collection.

In the present embodiment, based on the management data 18, it is possible to recognize which name space NS _{0 to} NS _M each data stored in the input name spaces INS _{0 to} INS _P relates to.

In the present embodiment, when data is written into the input namespace INS ₀ ~INS _P, data of the corresponding data to the input namespace INS ₀ ~INS _P to the stored namespace NS ₀ and ～NS _M Calculate Then, the number of blocks B _{0 to} B _N allocated to the namespaces NS _{0 to} NS _M is subtracted by the determined data amount.

As a result, the number of blocks allocated to the corresponding name spaces NS _{0 to} NS _M can be reduced by the amount of data stored in the input name spaces INS _{0 to} INS _P , and the name spaces NS ₀ to NS NS _M can be assigned.

In the present embodiment, a data movement target block is selected from the blocks B included in the input name spaces INS _{0 to} INS _P , and the valid data stored in the data movement target block is selected as the valid data. You can move to the namespace block corresponding to. In this case, the amount of data corresponding to the input namespace INS ₀ ~INS _P-stored in and namespace NS ₀ ~NS _M, namespaces are stored in blocks of data migration target NS ₀ ~NS _M The amount of valid data corresponding to is subtracted.

Thus, even when data is moved from the input namespace INS _{0 to} INS _P to the namespace NS ₀ to NS _M , the data is stored in the input namespace INS _{0 to} INS _P and is stored in the namespace NS _{0 to} NS P. _The amount of data corresponding to _M can be recognized.

In the present embodiment, old data can be moved from the input namespaces INS _{0 to} INS _P to the namespaces NS ₀ to NS _M.

In the present embodiment, for example, a block with less valid data can be selected from the input namespaces INS _{0 to} INS _P, and valid data can be moved from the selected block to the namespaces NS ₀ to NS _M. Further, in the present embodiment, for example, among the blocks included in the input name spaces INS _{0 to} INS _P , a block whose effective data amount is less than the first threshold value is selected as a data movement target block. Can be selected.

As a result, the amount of data moved from the input namespaces INS _{0 to} INS _P to the namespaces NS ₀ to NS _M can be reduced, and the performance degradation of the memory system 3 can be prevented.

In the present embodiment, the number of blocks allocated to the input namespaces INS _{0 to} INS _P is reduced when the amount of valid data in a block selected for moving valid data is smaller than the second threshold value. be able to. Further, in the present embodiment, when the amount of valid data in a block selected for moving valid data is larger than the third threshold, the number of blocks to be allocated to the input namespaces INS _{0 to} INS _P is set as follows. Can do a lot.

Thereby, the number of blocks allocated to the input name spaces INS _{0 to} INS _P can be optimized.

In the present embodiment, when the number of blocks included in the input namespace INS _{0 to} INS _P is larger than the fourth threshold value, the setting unit 14 selects a block from the input namespace INS _{0 to} INS _P , The writing unit 16 moves the valid data stored in the selected block to the namespaces NS ₀ to NS _M corresponding to the valid data. In the present embodiment, the setting unit 14 reduces the number of blocks included in the input namespaces INS _{0 to} INS _P and increases the number of blocks included in the namespaces NS _{0 to} NS _M.

As a result, it is possible to prevent the name spaces NS _{0 to} NS _{M from} becoming insufficient due to an increase in the size of the input namespaces INS _{0 to} INS _P.

In the present embodiment, it is possible to specify at which position of the name spaces NS _{0 to} NS _M the data is written.

In the present embodiment, garbage collection can be performed efficiently and independently for each of the namespaces NS _{0 to} NS _M and the input namespaces INS _{0 to} INS _P.

In the present embodiment, as a result of garbage collection, an empty block that does not store data can be changed from a namespace before garbage collection to another namespace, and an empty block is secured in another namespace. be able to. As a result, the namespace assigned to the block can be changed, wear leveling can be executed between the namespaces NS _{0 to} NS _M , and the non-volatile memory 5 can be extended in life.

In the present embodiment, it is possible to set a reserve area P ₀ to P _M different data amount for each namespace NS ₀ ~NS _M, can be achieved over provisioning for each namespace NS ₀ ~NS _M. As a result, the writing speed can be increased and the performance can be maintained, and the reliability can be improved.

In the present embodiment, the address conversion table T for each namespace NS ₀ ~NS _{M 0} ~T _M is managed for each namespace NS ₀ ~NS _M, changing the relationship between the address translation and LBA and PBA Can be performed efficiently.

  In the present embodiment, when address conversion is performed by key-value type search, even if the data capacity of the nonvolatile memory 5 is large, the address conversion can be performed efficiently.

In the present embodiment, advanced memory management can be realized for each of the namespaces NS _{0 to} NS _M , the lifetime of the nonvolatile memory 5 can be extended, the cost can be reduced, and the namespace NS Writing to and reading from the non-volatile memory 5 divided by _{0 to} NS _M can be speeded up.

In the present embodiment, instead of the garbage collection unit G ₀ ~G _Y, or, together with the garbage collection unit G ₀ ~G _Y, namespace NS ₀ ~NS _M and compaction unit of each input namespace INS ₀ ~INS _P May be provided. The compaction unit corresponding to each namespace NS ₀ ~NS _M and input namespace INS ₀ ~INS _P, based on the management data 18, each namespace NS ₀ ~NS _M and input namespace INS ₀ ~INS _P Perform compaction on.

In the present embodiment, for example, the communication of the setting command C1 between the information processing device 2 and the memory system 3 may be omitted. For example, the address conversion unit 15 may have a part or all of the functions of the setting unit 14. For example, the address conversion unit 15 associates the NSID 6 and the LBA 7 attached to the write command C2 with the PBA corresponding to the LBA 7, so that the address conversion table T for each of the management data 18 and the namespaces NS _{0 to} NS _{M is obtained. 0 to} T _M may be generated. The management data 18 and the address conversion tables T _{0 to} T _M can be appropriately combined or divided. A configuration in which communication of the setting command C1 is omitted and a part or all of the functions of the setting unit 14 are provided in the address conversion unit 15 will be described in a second embodiment to be described later.

[Second Embodiment]
In the present embodiment, an information processing system will be described in which a memory system writes write data from a plurality of information processing apparatuses, and a memory system sends read data to the plurality of information processing apparatuses.

  FIG. 5 is a block diagram illustrating an example of the configuration of the information processing system according to the present embodiment.

The information processing system 1A includes a plurality of information processing devices D _{0 to} D _M and a memory system 3A. Each of the plurality of information processing devices D _{0 to} D _M has the same function as the information processing device 2 described above. The memory system 3A mainly includes a conversion table (conversion data) 20 in place of the address conversion tables T _{0 to} T _M and the management data 18, and data between the plurality of information processing devices D _{0 to} D _M. The memory system 3 is different from the memory system 3 in that information, signals, commands, and the like are transmitted and received, and the function of the setting unit 14 is provided in the address conversion unit 15. In the present embodiment, differences from the first embodiment will be described, and the description of the same or substantially the same part will be omitted or briefly described.

The memory system 3A is provided in a cloud computing system, for example. The memory system 3A will be described as an example in which the memory system 3A is shared by a plurality of information processing devices D _{0 to} D _M , but may be shared by a plurality of users, for example. At least one of the plurality of information processing apparatuses D _{0 to} D _M may be a virtual machine.

  In the present embodiment, the NSID attached to the command is used as a name space access key.

In the present embodiment, it is assumed that the plurality of information processing apparatuses D _{0 to} D _M have access authority to the namespaces NS _{0 to} NS _M corresponding to the information processing apparatuses D _{0 to} D _M. However, one information processing apparatus may have access authority to one or more name spaces, and a plurality of information processing apparatuses may have access authority to a common name space.

Each of the information processing devices D _{0 to} D _M sends, for example, the NSID 6W indicating the write destination space corresponding to itself, the LBA 7W indicating the write destination, the data size 8 and the write data 9W to the memory system 3A together with the write command C2. send.

Each of the information processing devices D _{0 to} D _M sends, together with the read command C3, for example, NSID 6R indicating the read destination space corresponding to itself and LBA 7R indicating the read destination to the memory system 3A.

Each of the information processing devices D _{0 to} D _M receives, from the memory system 3A, read data 9R corresponding to the read command C3 or information indicating that reading is impossible.

  The memory system 3A includes a controller 4A and a nonvolatile memory 5.

The controller 4 </ b> A includes an interface unit 19, a storage unit 10, buffer memories F _{0 to} F _M , and a processor 11. In the present embodiment, the number of processors provided in the controller 4A is one or more and can be freely changed.

The interface unit 19 transmits and receives data, information, signals, commands, and the like with an external device such as the information processing devices D _{0 to} D _M.

  The storage unit 10 stores a conversion table 20. A part or all of the conversion table 20 may be stored in another memory such as the memory 12.

  The conversion table 20 is data in which LBA, PBA, NSID, data size, and information indicating whether data is stored in the input namespace (hereinafter referred to as an input flag) are associated with each other. The conversion table 20 will be described later with reference to FIG.

Buffer memory F ₀ to F _M, respectively, it is used for the namespace NS ₀ ~NS _M as a write buffer memory and the read buffer memory.

The processor 11 includes a memory 12 which stores a program 17, reception unit 13, the address conversion section 15, write section 16, read section 21, the garbage collection unit G ₀ ~G _Y. The processor 11 functions as the reception unit 13, the address conversion unit 15, the writing unit 16, the reading unit 21, and the garbage collection units G _{0 to} G _Y by executing the program 17.

Reception unit 13 receives at the time of data writing, the information processing apparatus D ₀ written from to D _M via the interface unit 19 commands C2, NSID6W, LBA7W, data size 8, the write data 9W.

Receiving unit 13, when reading data, receives the read command C3, NSID6R, the LBA7R from the information processing apparatus D ₀ to D _M via the interface unit 19.

  When the write command C2 is received by the receiving unit 13, the address converting unit 15 determines the write destination in the input namespace corresponding to the name space indicated by the NSID 6W based on the LBA 7W and the NSID 6W attached to the write command C2. The PBA is determined, and the conversion table 20 is updated in association with the LBA 7W, NSID 6W, the determined input namespace PBA, the data size, and the input flag Y indicating that data is stored in the input namespace.

  When data is moved from the input namespace to the namespace, the address conversion unit 15 determines the PBA of the write destination in the namespace, LBA7W, NSID6W, the determined namespace PBA, data size, input namespace The conversion table 20 is updated with the input flag N indicating that no data is stored.

  When the read command C3 is received by the receiving unit 13, the address conversion unit 15 uses the namespace indicated by the NSID 6R or the NSID 6R based on the LBA 7R, the NSID 6R, and the conversion table 20 attached to the read command C3. The PBA to be read in the input namespace corresponding to the indicated namespace is determined.

  The writing unit 16 writes the write data 9W to the position indicated by the PBA in the input namespace corresponding to the name space indicated by the NSID 6W via the buffer memory corresponding to the name space indicated by the NSID 6W. Thereafter, the writing unit 16 writes the write data 9W to the position indicated by PBA in the name space indicated by the NSID 6W obtained by the address conversion unit 15 from the input name space.

  The reading unit 21 reads the read data 9R from the name space indicated by the NSID 6R or the position indicated by the PBA in the input name space corresponding to the name space via the buffer memory corresponding to the name space indicated by the NSID 6R. Then, the reading unit 21 sends the read data 9R to the information processing apparatus that has issued the read command C3 via the interface unit 19.

In the present embodiment, the garbage collection units G _{0 to} G _Y execute garbage collection for each of the namespaces NS _{0 to} NS _M and the input namespaces INS _{0 to} INS _P based on the conversion table 20.

  FIG. 6 is a data structure diagram illustrating an example of the conversion table 20 according to the present embodiment.

The conversion table 20 manages LBA, PBA, NSID, data size, and input flag in association with each other. For example, the conversion table 20 associates an LBA 200, PBA 300, NS ₀ , data size Z, and an input flag N indicating that data is not stored in the input namespace. For example, the conversion table 20 relates an LBA 201, PBA 301, NS ₀ , data size Z, and an input flag Y indicating that data is stored in the input name space. For example, the conversion table 20 associates an LBA 200, PBA 399, NS _M , data size Z, and an input flag N indicating that no data is stored in the input namespace.

In the present embodiment, the data size is managed by the conversion table 20. However, if the data size is constant, the data size may be deleted from the conversion table 20. When the data size is constant, instead of the data size, based on the number of valid data in each block B of the input namespace INS _{0 to} INS _P and each block B _{0 to} B _N of the namespace NS _{0 to} NS _M Thus, the amount of valid data in each of the blocks B and B _{0 to} B _N may be recognized.

In the present embodiment, the input flag is managed by the conversion table 20. However, since the data can be recognized in the input namespace INS _{0 to} INS _P or the namespace NS _{0 to} NS _M based on the PBA, even if the input flag is omitted from the conversion table 20. Good.

For example, the address conversion unit 15 determines the PBA so that the PBA 300 related to the LSID 200 indicating the LBA 200 and the NSID indicating the namespace NS ₀ and the PBA 399 related to the NSID indicating the LBA 200 and the namespace NS _M are different from each other. .

Accordingly, the address conversion unit 15 can select the PBA 300 when the NSID received together with the LBA 200 indicates the namespace NS ₀ , and the PBA 399 when the NSID received together with the LBA 200 indicates the namespace NS _M. Can be selected.

Therefore, even when the same logical address is used among the plurality of information processing apparatuses D _{0 to} D _M , the memory system 3A can be shared by the plurality of information processing apparatuses D _{0 to} D _M.

  FIG. 7 is a flowchart showing an example of the first write process of the memory system 3A according to the present embodiment.

In the description of FIG. 7, the write command C2 from the information processing apparatus D ₀ of the plurality of information processing apparatuses D ₀ to D _M is issued, NSID6W showing a namespace NS ₀ are assigned to the write command C2 A case will be described as an example. However, the same applies when the write command C2 is issued from the information processing devices D _{1 to} D _M. The same applies to the case where the write command C2 has an NSID 6W indicating any of the other namespaces NS _{1 to} NS _M.

In step S701, the reception unit 13 writes the information processing apparatus D ₀ via the interface unit 19 commands C2, NSID6W, LBA7W, data size 8, accept the write data 9W.

In step S702, when the write command C2 is received by the receiving unit 13, the address conversion unit 15 inputs based on the LBA 7W and NSID 6W attached to the write command C2 and corresponding to the namespace NS ₀ indicated by the NSID 6W. The write destination PBA in the name space INS ₀ is determined.

  In step S703, the address conversion unit 15 updates the conversion table 20 with the LBA 7W, NSID 6W, the determined PBA, the data size Z, and the input flag Y indicating that data is stored in the input namespace. To do.

In step S704, the writing unit 16 via the buffer memory F ₀ corresponding to the namespace NS ₀ indicated by NSID6W, the position indicated by the PBA in the Input namespace INS ₀ corresponding to the namespace NS ₀ indicated by NSID6W, Write the write data 9W.

  FIG. 8 is a flowchart showing an example of the second write process of the memory system 3A according to the present embodiment.

In the description of FIG. 8, a case where valid data is moved from the input namespace INS ₀ to the namespace NS ₀ will be described as an example. However, the same applies when valid data is moved from the input namespaces INS _{1 to} INS _P to the namespaces NS ₀ to NS _M.

In step S801, the writing unit 16 by, for instance, it is determined whether garbage collection is performed to determine whether to move the valid data from the input namespace INS ₀ to namespace NS _0.

  If it is not determined to move the valid data, the process proceeds to step S805.

If it is determined that the moving valid data, in step S802, the address converter 15 selects a block of data moved from among the blocks B that are included in the input namespace INS _0.

In step S803, the writing unit 16 moves the valid data stored in blocks of data movement target block namespace NS ₀ corresponding to the valid data.

In step S804, the address converter 15, an input indicating that no stored PBA, NSID showing a namespace NS _0, data size Z, the data is the input namespace in LBA, namespace NS ₀ corresponding to the effective data The conversion table 20 is updated so as to relate the flag N.

  In step S805, it is determined whether the second writing process is continued.

  When the second writing process is continued, the second writing process moves to step S801.

  If the second write process is not continued, the second write process ends.

  FIG. 9 is a flowchart showing an example of a read process of the memory system 3A according to the present embodiment.

In the description of FIG. 9, a read command C3 is issued from the information processing device D _M out of the plurality of information processing devices D _{0 to} D _M , and the read command C3 is assigned NSID 6R indicating the namespace NS _M. A case will be described as an example. However, the same applies when a read command C3 is issued from the information processing devices D _{0 to} D _M−1 . The same applies to the case where NSID 6R indicating any of the other name spaces NS _{0 to} NS _M-1 is attached to the read command C3.

In step S901, the reception section 13 receives the read command C3, NSID6R, the LBA7R from the information processing apparatus D _M via the interface unit 19.

In step S902, when the read command C3 is received by the receiving unit 13, the address converting unit 15 inputs the input namespace INS _P , based on the LBA 7R, NSID 6R, and the conversion table 20 attached to the read command C3. Alternatively, the PBA of the reading destination in the name space NS _M is determined.

In step S903, the read unit 21, via the buffer memory F _M corresponding to the namespace NS _M indicated by NSID6R, namespace NS _M indicated NSID6R, or input namespace INS _P corresponding to the namespace NS _M from the position indicated by the PBA in, it reads the read data 9R, via the interface unit 19, the information processing apparatus D _M that issued the read command C3, and sends the read data 9R.

In the present embodiment described above, the nonvolatile memory 5 is divided into a plurality of input namespaces INS _{0 to} INS _P and namespaces NS _{0 to} NS _M. The information processing devices D _{0 to} D _M can access a name space to which the information processing devices D _{0 to} D _M have access authority among the plurality of input namespaces INS _{0 to} INS _P and the namespaces NS _{0 to} NS _M. Thereby, data security can be improved.

The controller 4A of the memory system 3A performs independent control for each of the input namespaces INS _{0 to} INS _P and the namespaces NS _{0 to} NS _M. As a result, the use conditions can be switched for each of the input namespaces INS _{0 to} INS _P and the namespaces NS _{0 to} NS _M.

  Since the memory system 3A associates the LBA, the PBA, and the NSID, for example, even when the same LBA is received from a plurality of independent information processing apparatuses, the data can be distinguished by the NSID.

  In each of the above embodiments, the data in the table format may be implemented in another data structure such as a list format.

[Third Embodiment]
In the present embodiment, the detailed configuration of the information processing systems 1 and 1A described in the first and second embodiments will be described.

  FIG. 10 is a block diagram illustrating an example of a detailed configuration of the information processing system according to the present embodiment.

In FIG. 10, an information processing system 1B includes an information processing device 2B and a memory system 3B. The information processing system 1B may include a plurality of information processing apparatuses as in the second embodiment. That is, any one of the information processing devices 2 and D _{0 to} D _M of the first and second embodiments corresponds to the information processing device 2B.

  The memory systems 3 and 3A of the first and second embodiments correspond to the memory system 3B.

  The processor 11 of the first and second embodiments corresponds to the CPUs 43F and 43B.

The address conversion tables T _{0 to} T _{M of} the first embodiment and the conversion table 20 of the second embodiment correspond to the LUT 45.

  The storage unit 10 of the first and second embodiments corresponds to the DRAM 47.

  The interface unit 19 in the second embodiment corresponds to the host interface 41 and the host interface controller 42.

The buffer memories F _{0 to} F _M of the first and second embodiments correspond to the write buffer WB and the read buffer RB.

  The information processing device 2B functions as a host device.

  The controller 4 includes a front end 4F and a back end 4B.

  The front end (host communication unit) 4F includes a host interface 41, a host interface controller 42, an encryption / decryption unit 44, and a CPU 43F.

  The host interface 41 communicates requests (such as a write command, a read command, and an erase command), LBA, data, and the like with the information processing apparatus 2B.

  The host interface controller (control unit) 42 controls communication of the host interface 41 based on the control of the CPU 43F.

  An encryption / decryption unit (Advanced Encryption Standard (AES)) 44 encrypts write data (plain text) transmitted from the host interface controller 42 in the data write operation. The encryption / decryption unit 44 decrypts the encrypted read data transmitted from the read buffer RB of the back end 4B in the data read operation. Note that it is possible to transmit the write data and the read data without going through the encryption / decryption unit 44 as necessary.

  The CPU 43F controls each of the components 41, 42, 44 of the front end 4F, and controls the entire operation of the front end 4F.

  The back end (memory communication unit) 4B includes a write buffer WB, a read buffer RB, an LUT 45, a DDRC 46, a DRAM 47, a DMAC 48, an ECC 49, a randomizer RZ, a NANDC 50, and a CPU 43B.

  The write buffer (write data transfer unit) WB temporarily stores the write data transmitted from the information processing apparatus 2B. Specifically, the write buffer WB temporarily stores data until the write data has a predetermined data size suitable for the nonvolatile memory 5.

  The read buffer (read data transfer unit) RB temporarily stores read data read from the nonvolatile memory 5. Specifically, in the read buffer RB, the read data is rearranged so as to be in an order suitable for the information processing apparatus 2B (order of logical addresses LBA designated by the information processing apparatus 2B).

  The LUT 45 is data for converting the logical address LBA into a predetermined physical address PBA.

  The DDRC 46 controls DDR (Double Data Rate) in the DRAM 47.

  The DRAM 47 is, for example, a volatile memory that stores the LUT 45.

  A DMAC (Direct Memory Access Controller) 48 transfers write data, read data, and the like via the internal bus IB. Although one DMAC 48 is illustrated in FIG. 10, the controller 4 may include two or more DMACs 48. The DMAC 48 is set at various positions in the controller 4 as required.

  The ECC (error correction unit) 49 adds ECC (Error Correcting Code) to the write data transmitted from the write buffer WB. When the ECC 49 is transmitted to the read buffer RB, the read data read from the nonvolatile memory 5 is corrected as necessary using the added ECC.

  The randomizer RZ (or scrambler) distributes the write data so that the write data is not biased to a specific page or word line direction of the nonvolatile memory 5 during the data write operation. Thus, by distributing the write data, the number of times of writing can be leveled, and the cell life of the memory cells of the nonvolatile memory 5 can be extended. Therefore, the reliability of the nonvolatile memory 5 can be improved. Further, read data read from the nonvolatile memory 5 during the data read operation passes through the randomizer RZ.

  A NANDC (NAND Controller) 50 accesses the nonvolatile memory 5 in parallel using a plurality of channels (here, four channels CH0 to CH3) in order to satisfy a predetermined speed requirement.

  The CPU 43B controls each configuration (45 to 50, RZ) of the back end 4B, and controls the overall operation of the back end 4B.

  Note that the configuration of the controller 4 shown in FIG. 10 is an example, and the present invention is not limited to this configuration.

  FIG. 11 is a perspective view showing the storage system according to this embodiment.

  The storage system 100 includes a memory system 3B as an SSD.

  The memory system 3B is, for example, a relatively small module, and an example of an external dimension thereof is about 20 mm × 30 mm. Note that the size and dimensions of the memory system 3B are not limited to this, and can be appropriately changed to various sizes.

  Further, the memory system 3B can be used by being mounted on an information processing apparatus 2B such as a server in a data center or a cloud computing system operated in a company (enterprise), for example. Therefore, the memory system 3B may be an enterprise SSD (eSSD).

  The memory system 3B includes, for example, a plurality of connectors (for example, slots) 30 opened upward. Each connector 30 is, for example, a SAS (Serial Attached SCSI) connector. According to this SAS connector, the information processing apparatus 2B and each memory system 3B can perform high-speed communication with each other by 6 Gbps Dual Port. However, the present invention is not limited to this, and each connector 30 may be, for example, PCIe (PCI Express) or NVMe (NVM Express).

  The plurality of memory systems 3B are respectively attached to the connectors 30 of the information processing apparatus 2B, and are supported side by side in an upright posture in the vertical direction. According to such a configuration, a plurality of memory systems 3B can be packaged in a compact manner, and the memory system 3B can be downsized. Furthermore, each shape of the memory system 3B according to the present embodiment is a 2.5-inch SFF (Small Form Factor). With such a shape, the memory system 3B can achieve a compatible shape (compatible shape) with the enterprise HDD (eHDD), and can realize easy system compatibility with the eHDD.

  The memory system 3B is not limited to enterprise use. For example, the memory system 3B can also be applied as a storage medium for consumer electronic devices such as notebook portable computers or tablet terminals.

  As described above, in the information processing system 1B and the storage system 100 having the configuration described in this embodiment, the same effects as those in the first and second embodiments can be obtained for large-capacity storage. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1, 1A, 1B ... information processing _{system, 2,2A, 2B, D 0 ~D} M ... information processing apparatus, 3, 3A, 3B ... memory system, 4 ... controller, 5 ... non-volatile memory, 6,6W, 6R ... NSID, 20 ... Replacement management unit, 7, 7W, 7R ... LBA, 8 ... Data size, 9, 9W ... Write data, 9R ... Read data, 10 ... Storage unit, 11 ... Processor, 12 ... Memory, 13 ... Reception , 14 ... setting section, 15 ... address conversion section, 16 ... writing section, 17 ... program, 18, 19 ... interface section, 20 ... conversion table ... management data, NS _{0 to} NS _M ... name space, IG _{0 to} IG _P ... input _group, NS _{0 ~INS P} ... input name space, C1 ... setting command, C2 ... write command, P ₀ ~P _Y ... spare area, F ₀ ~F _M ... buffer Memory, G _{0 to} G _{Y ...} garbage collection unit, A _{0 to} A _M ... LBA space, T _{0 to} T _M ... address conversion table, 41 ... host interface, 42 ... host interface controller, 43B, 43F ... CPU, WB ... Write buffer, RB ... Read buffer, 4F ... Front end, 4B ... Back end, 44 ... Encryption / decryption unit, 45 ... LUT, 46 ... DDRC, 47 ... DRAM, 48 ... DMAC, 49 ... ECC, RZ ... Randomizer 50, NANDC, IB, internal bus.

Claims (13)

Non-volatile memory;
A plurality of write management areas included in the non-volatile memory are allocated to a plurality of spaces and input spaces, and the write management area is a unit area for managing the number of writes, and a setting unit.
An address conversion unit that associates a logical address of write data with a physical address indicating a position of the write data in the nonvolatile memory;
A writing unit for writing the write data in the input space to a space corresponding to the write data in the plurality of spaces after writing the write data in the input space;
A control unit that controls the nonvolatile memory for each of the plurality of spaces;
A memory system comprising: The control unit performs garbage collection for each of the plurality of spaces.
The memory system according to claim 1. The writing unit stores first data corresponding to the first space stored in the input space based on execution of the first garbage collection for the first space among the plurality of spaces. Writing in the first space;
The memory system according to claim 2. The setting unit generates management data including a relationship between data stored in the input space and a space corresponding to the data;
The memory system according to claim 1 or 2. The setting unit obtains a data amount of data stored in the input space and corresponding to a first space among the plurality of spaces, and is obtained from a predetermined data amount corresponding to the first space. Assigning at least one write management area to the first space based on a value obtained by subtracting the amount of data obtained;
The memory system according to claim 1, claim 2, or claim 4. The management data further includes a relationship between the first space and the determined amount of data,
The setting unit is determined when the valid data stored in the write management area of the input space in the input space and corresponding to the first space is moved to the first space. Updating the management data based on a value obtained by subtracting the data amount of the valid data moved to the first space from the data amount
The memory system according to claim 5. The setting unit selects, from the input space, a write management area with the oldest write time as a write management area for data movement,
The writing unit writes the valid data stored in the write management area to be moved to the space corresponding to the valid data;
The memory system according to any one of claims 1 to 5. The setting unit selects, from the input space, a write management area with the least amount of valid data as a write management area for data movement,
The writing unit writes the valid data stored in the write management area to be moved to a space corresponding to the valid data;
The memory system according to any one of claims 1 to 5. The setting unit selects, from the input space, a write management area in which the amount of valid data is less than a threshold as a write management area for data movement,
The writing unit writes the valid data stored in the write management area to be moved to a space corresponding to the valid data;
The memory system according to any one of claims 1 to 5. The setting unit includes the write management area included in the input space when the amount of valid data stored in the write management area targeted for data movement in the input space is smaller than a threshold value. Reduce the number of
The memory system according to any one of claims 1 to 5. The setting unit includes the write management area included in the input space when the amount of valid data stored in the write management area targeted for data movement in the input space is greater than a threshold value. Increase the number of
The memory system according to any one of claims 1 to 5. The setting unit assigns the plurality of spaces to a plurality of input spaces,
The writing unit writes the write data in the first input space corresponding to the write data in the plurality of input spaces, and then writes the write data in the first input space to the plurality of spaces. Write to the space corresponding to the write data of
The memory system according to any one of claims 1 to 11. Computer
A plurality of write management areas included in the nonvolatile memory are allocated to a plurality of spaces and input spaces, and the write management area is a unit area for managing the number of times of writing, and a setting unit;
An address conversion unit that associates a logical address of write data with a physical address indicating a position of the write data in the nonvolatile memory;
A writing unit for writing the write data in the input space to a space corresponding to the write data in the plurality of spaces after writing the write data in the input space;
A control unit that controls the nonvolatile memory for each of the plurality of spaces;
Program to make it function.

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