JP2016082297A - Communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable correct reception of a communication signal from an opposite communication party without affected by a noise, in a communication device in which a multi-drop communication bus is adopted.SOLUTION: An ECU 5 as the communication device includes: a resistor 11 which pulls up a communication bus 3 to a power voltage VB; a driver 13 which, when switched on, outputs a dominant to the communication bus 3 by making the communication bus 3 conducting to a ground potential, and when switched off, outputs a recessive to the communication bus 3; a comparator 15 which compares the magnitude of the voltage of the communication bus 3 with a threshold Vth to binarize to a high or low signal; a noise filter 17 to which an output signal Scp of the comparator 15 is input; and a microcomputer 19 which processes the output signal Sout of the noise filter 17 as a reception signal. The noise filter 17 is configured to have a filter time for the low input which represents the dominant, whereas to immediately react with an output to the high input which represents the recessive.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a communication device that employs a multi-drop communication bus.

  A communication device that communicates with other devices via a communication bus is provided with a noise filter for removing noise from an input communication signal. As a noise filter, there is one that changes the level (high or low) of an output signal to the same level as the level of the input signal if the level (high or low) of the input signal is the same for a certain period of time. (For example, refer to Patent Document 1).

  In addition, as a communication bus, for example, there is a multi-drop type communication bus employed in LIN (Local Interconnect Network) or the like. In the multi-drop communication bus, the voltage of the communication bus is stabilized to a voltage that represents recessive by a resistor. Then, when the driver that turns the voltage of the communication bus to a voltage representing a dominant is turned on, the dominant is output as a signal to the communication bus. Further, when the driver is turned off, recessive is output as a signal to the communication bus. Recessive is a recessive signal and dominant is a dominant signal.

JP-A-11-55235

  In a multi-drop communication bus, the impedance of the communication bus differs depending on whether the driver is off or on. That is, the impedance is smaller when the driver is on than when the driver is off. Therefore, among the communication bus levels, a recessive level (hereinafter also simply referred to as recessive) when the driver is off, and a dominant level (hereinafter also simply referred to as dominant) when the driver is on. Then, how to ride noise is different. Specifically, the dominant is harder to get the noise than the recessive. That is, when noise is on the communication bus, recessive is likely to become dominant, and dominant is difficult to become recessive.

Therefore, if the noise filter of the above-mentioned document 1 is used for a communication device that employs a multidrop communication bus, the following problems occur.
It is assumed that when the communication partner changes the communication signal to the communication bus from dominant to recessive, noise is riding on the communication bus and the recessive intermittently becomes dominant. In this case, since the input signal of the noise filter does not become the same level (a level representing recessive) for a certain period of time, the output signal of the noise filter does not change according to the communication signal. As a result, the communication signal from the communication partner cannot be received correctly.

  Accordingly, an object of the present invention is to enable a communication apparatus employing a multi-drop communication bus to correctly receive a communication signal from a communication partner without being affected by noise.

  The communication device of the first invention is a communication device that communicates with other devices in a communication system using a multi-drop communication bus. In the multi-drop communication bus, the voltage of the communication bus is stabilized to a voltage representing a recessive signal which is a recessive signal by a resistor. Then, when a driver that turns the voltage of the communication bus to a voltage representing a dominant signal representing dominant is turned on, the dominant is output to the communication bus, and when the driver is turned off, recessive is output to the communication bus. The

  A communication device according to a first aspect of the present invention receives the resistor and the driver, a binarization circuit that binarizes the voltage of the communication bus into a high level or low level signal, and an output signal of the binarization circuit as inputs. A noise filter; and a processing unit that processes an output signal of the noise filter as a reception signal.

  The noise filter processes the output signal to the processing unit between the high level and the low level when the output signal of the binarization circuit becomes a level representing the recessive of the high level and the low level. Set to the first level that the part judges to be recessive. In addition, the noise filter outputs the output signal to the processing unit to the high level when the output signal of the binarization circuit is the level representing the dominant of the high level and the low level for a predetermined time. And the low level, the second level which is determined by the processing unit as a dominant is set. The predetermined time is shorter than a time corresponding to one bit in communication performed via the communication bus.

  In other words, even if the input signal (the output signal of the binarization circuit) reaches a level that represents a dominant level, the noise filter does not continue for a predetermined time. However, when the input signal becomes the level representing the recessive level, the output signal is immediately changed to the first level corresponding to the recessive level. In other words, the noise filter has a predetermined filter time for the dominant input, but immediately reacts the output to the recessive input.

  For this reason, when another device which is a communication partner outputs recessive to the communication bus, the output signal of the noise filter becomes the first level corresponding to recessive. And even if the noise gets on the communication bus and the recessive becomes dominant due to the noise, the output signal of the noise filter is the first level as long as the duration of the dominant due to the noise does not exceed the predetermined time (filter time). Will remain. Therefore, recessiveness can be correctly transmitted to the processing unit. Incidentally, the fact that recessive becomes dominant due to noise means that the voltage of the communication bus changes due to noise, and the output signal of the binarization circuit changes from the level representing recessive to the level representing dominant. It means that.

  Further, when another device outputs a dominant to the communication bus, the impedance of the communication bus becomes small, so that the dominant is difficult to become recessive due to noise. That is, it is unlikely that the voltage of the communication bus changes due to noise, and the output signal of the binarization circuit changes from the level representing dominant to the level representing recessive. For this reason, if a dominant signal is output to the communication bus, the output signal of the binarization circuit will be at the level representing the dominant for a predetermined time or longer even if noise is applied to the communication bus. The output signal of the filter becomes the second level corresponding to the dominant. Therefore, the dominant can be correctly transmitted to the processing unit.

  Then, when another device changes the output signal (communication signal) to the communication bus from dominant to recessive, it is assumed that noise is riding on the communication bus and the recessive becomes intermittently dominant. In that case, if the output signal of the binarization circuit reaches a level that represents recessive even once, the output signal of the noise filter changes from the second level to the first level. This is because there is no filter time for recessive. Therefore, the change from dominant to recessive can be correctly transmitted to the processing unit.

From the above, according to the communication device of the first invention, the communication signal from the communication partner can be correctly transmitted to the processing unit without being affected by noise, and as a result, correct reception is possible.
In addition, the code | symbol in the parenthesis described in the claim shows the correspondence with the specific means as described in embodiment mentioned later as one aspect, Comprising: The technical scope of this invention is limited is not.

It is a block diagram showing the structure of the communication apparatus of embodiment. It is explanatory drawing explaining the effect | action of a noise filter. It is a block diagram showing the noise filter of a comparative example. It is explanatory drawing explaining the effect | action of the noise filter of a comparative example. It is a block diagram showing the structure of the communication apparatus of other embodiment (modification 3).

A communication system according to an embodiment to which the present invention is applied will be described below.
A communication system 1 according to the embodiment shown in FIG. 1 is a communication system mounted on, for example, a vehicle (automobile).

  In the communication system 1, a plurality of electronic control devices (two shown in FIG. 1, hereinafter referred to as ECUs) 5 and 6 are connected to the communication bus 3. The communication bus 3 is a multi-drop communication bus. Moreover, the communication bus 3 consists of one communication line in this embodiment. For this reason, hereinafter, the communication bus 3 is referred to as a communication line 3. The ECUs 5 and 6 correspond to communication devices that communicate via the communication line 3. Each of the ECUs 5 and 6 transmits information to other ECUs or receives information from other ECUs. Each of the ECUs 5 and 6 uses information acquired from other ECUs by communication, for example, for controlling its own control target. In addition, since the structure regarding communication of each ECU5 and 6 is the same, below, ECU5 is mainly demonstrated below.

  As shown in FIG. 1, the ECU 5 includes a resistor (termination resistor) 11 that pulls up the communication line 3 to the power supply voltage VB. For this reason, the voltage of the communication line 3 is stabilized to the power supply voltage VB by the resistor 11. Further, the ECU 5 includes a driver 13 that causes the communication line 3 to conduct (connect) to a predetermined potential lower than the power supply voltage VB. In this example, the power supply voltage VB is a vehicle battery voltage (for example, typically 12 V), and corresponds to a voltage representing recessive. The predetermined potential is a ground potential (0 V) and corresponds to a voltage representing a dominant.

  The driver 13 is a switch that, when turned on, causes the communication line 3 to conduct to the predetermined potential (hereinafter referred to as a ground potential), and is configured by, for example, an NPN transistor with a common emitter. When the driver 13 is turned on, the voltage of the communication line 3 becomes the ground potential from the power supply voltage VB stabilized by the resistor 11. Therefore, a dominant signal that is a dominant signal is output to the communication line 3 when the driver 13 is turned on, and a recessive signal that is a recessive signal is output when the driver 13 is turned off. As the level of the communication line 3, the dominant level is the ground potential, and the recessive level is the power supply voltage VB.

  The ECU 5 further includes a binarization circuit 15 that binarizes the voltage of the communication line 3 into a high-level or low-level signal, a noise filter 17 that receives the output signal Scp of the binarization circuit 15, and noise. And a microcomputer 19 as a processing unit that processes the output signal Sout of the filter 17 as a received signal.

  In the present embodiment, the binarization circuit 15 is a comparator. Therefore, hereinafter, the binarization circuit 15 is referred to as a comparator 15. The driver 13, the comparator 15, and the noise filter 17 are integrated into an IC, and are configured in one transceiver IC 21.

  The comparator 15 receives a threshold voltage Vth between the power supply voltage VB and the ground potential. Then, the comparator 15 compares the voltage of the communication line 3 with the threshold voltage Vth, thereby binarizing the voltage of the communication line 3 into a high level or low level signal. For example, the high level is the same potential as the operating voltage (for example, 5 V) of the microcomputer 19, and the low level is the ground potential.

  Specifically, the comparator 15 outputs a high level if the voltage of the communication line 3 is larger than the threshold voltage Vth, and outputs a low level if the voltage of the communication line 3 is smaller than the threshold voltage Vth. For this reason, in the present embodiment, as the output signal Scp of the comparator 15, the high level is the level representing the recessive level, and the low level is the level representing the dominant level.

  The microcomputer 19 includes a communication circuit 23 based on, for example, a UART (Universal Asynchronous Receiver / Transmitter) communication method. Then, a transmission signal is output from the transmission signal terminal (TX) of the communication circuit 23 to the driver 13, and the driver 13 is turned on / off according to the transmission signal. Further, the output signal Sout of the noise filter 17 is input to the reception signal terminal (RX) of the communication circuit 23 as a reception signal. The communication circuit 23 converts the received signal into data having a logical value “1” or a logical value “0”, and stores the data in, for example, a received data register in the microcomputer 19.

  In the present embodiment, the output signal Sout of the noise filter 17 has a high level at the first level and a low level at the second level. That is, for the output signal Sout of the noise filter 17, the microcomputer 19 determines that the high level is recessive and the low level is dominant as in the meaning of the output signal Scp of the comparator 15. For example, assuming that data with a logical value “1” is processed as recessive data and data with a logical value “0” is processed as dominant data, the communication circuit 23 has the level of the output signal Sout of the noise filter 17. Of these, the high level is data having a logical value “1”, and the low level is data having a logical value “0”.

  The noise filter 17 includes a clock source 29, a plurality of (two in this example) D-type flip-flops 31 and 32 having a set function, and an OR circuit 33 as an output circuit.

The period of the clock output from the clock source 29 is sufficiently shorter than the time for one bit in communication performed via the communication line 3.
In the noise filter 17, the clock from the clock source 29 is input to the clock terminals (CK terminals) of the D flip-flops 31 and 32, and the D flip-flops 31 and 32 are connected in the form of a shift register. Yes. That is, the Q output terminal (Q terminal) of the preceding D flip-flop (31 in this example) is connected to the data input terminal (D terminal) of the succeeding D flip-flop (32 in this example).

  Furthermore, of the D-type flip-flops 31 and 32, the data input terminal of the D-type flip-flop 31 arranged in the first stage in the form of the shift register, and the set terminals (SET terminals) of all the D-type flip-flops 31 and 32 In addition, the output signal Scp of the comparator 15 is inputted. The set terminals of the D-type flip-flops 31 and 32 are high-active input terminals.

  The OR circuit 33 includes a Q output (hereinafter referred to as Q1) which is an output from the Q output terminal of the D-type flip-flop 31, and a Q output (hereinafter referred to as Q2) of the D-type flip-flop 32. Is entered. Then, the OR circuit 33 outputs a logical sum signal of Q1 and Q2 to the microcomputer 19 as the output signal Sout of the noise filter 17.

  In such a noise filter 17, when the output signal Scp of the comparator 15 becomes high level even for a moment, all the D-type flip-flops 31, 32 are set, and all their Q outputs (Q1, Q2) are set. The output signal Sout from the OR circuit 33 becomes high level. In the noise filter 17, if the output signal Scp of the comparator 15 continues to be low level and the rising edge of the clock occurs twice while the output signal Scp is low level, all D The Q outputs (Q1, Q2) of the type flip-flops 31, 32 become low level. At that time, the output signal Sout from the OR circuit 33 becomes low level.

  That is, the noise filter 17 immediately sets the output signal Sout to the high level when the output signal Scp of the comparator 15 becomes the high level representing the recessive. On the other hand, the noise filter 17 sets the output signal Sout to the low level when the output signal Scp of the comparator 15 is at the low level indicating the dominant and continues for a predetermined time. The predetermined time is a filter time for a low-level input. In this example, the predetermined time is a maximum of two clock cycles and a minimum of one clock cycle. Further, the predetermined time (hereinafter also referred to as filter time) is shorter than the time for one bit in communication.

  Therefore, even if the input signal (the output signal Scp of the comparator 15) becomes low level, the noise filter 17 does not change the output signal Sout to low level unless the low level continues for a predetermined time, but the input signal is high. When the level is reached, the output signal Sout is immediately changed to a high level.

  Next, the operation of the noise filter 17 in the ECU 5 will be described with reference to FIG. In FIG. 2, the stage (first stage) of the “no-noise bus waveform” represents the voltage waveform (communication signal on the communication line 3) of the communication line 3 when no noise is present. The stage (second stage) of the “bus waveform with noise” represents the voltage waveform of the communication line 3 when high-frequency noise is present. Although not shown, the horizontal axis in FIG. 2 is time. The same applies to FIG. 4 described later.

  As shown before time t1 in FIG. 2, when another ECU (for example, ECU 6) as a communication partner outputs a recessive to the communication line 3, the recessive has become dominant due to noise on the communication line 3. To do. In this example, the recessive may become dominant due to noise, as shown in the second and third stages of FIG. 2, “The voltage of the communication line 3 falls below the threshold voltage Vth due to noise and the output of the comparator 15. The signal Scp changes from a high level representing recessive to a low level representing dominant.

  In that case, if the output signal Scp of the comparator 15 becomes high level even for a moment, the output signal Sout of the noise filter 17 becomes high level. The output signal Sout of the noise filter 17 remains at a high level unless the duration of dominant due to noise exceeds the predetermined time (filter time). Therefore, recessive can be correctly transmitted to the microcomputer 19.

  Further, as shown in the period from time t1 to time t2 in FIG. 2, when another ECU outputs a dominant to the communication line 3, the impedance of the communication line 3 becomes small. For this reason, even if noise gets on the communication line 3, the dominant is difficult to become recessive. That is, in this example, it is unlikely that “the voltage of the communication line 3 exceeds the threshold voltage Vth due to noise and the output signal Scp of the comparator 15 changes from low level to high level”.

  For this reason, as shown in the period from time t1 to time t2 in FIG. 2, when a dominant is output to the communication line 3, the output signal Scp of the comparator 15 is the above-mentioned even if noise is applied to the communication line 3. It will be the low level that represents the dominant for a predetermined period of time. As a result, the output signal Sout of the noise filter 17 becomes low level. Therefore, the dominant can be correctly transmitted to the microcomputer 19. Note that “Tf” in FIG. 2 is the time from when a dominant is output to the communication line 3 until the rising of the clock occurs twice. In the example of FIG. 2, Tf is the filter time.

  Further, as shown after time t2 in FIG. 2, when another ECU changes the output signal (communication signal) to the communication line 3 from dominant to recessive, the recession is caused by noise on the communication line 3. Suppose you become a dominant.

  In this case, the recessive pattern may become intermittently dominant, but if the output signal Scp of the comparator 15 becomes high level even once, the output signal Sout of the noise filter 17 changes from low level to high level. This is because there is no filter time for recessive. Therefore, the change from dominant to recessive can be correctly transmitted to the microcomputer 19.

  According to the ECU 5 of the present embodiment, since the noise filter 17 is provided, a communication signal from a communication partner can be correctly transmitted to the microcomputer 19 without being affected by noise. Therefore, correct reception is possible.

Here, FIG. 3 shows a noise filter 37 of a comparative example.
The noise filter 37 of FIG. 3 changes the output signal Sout only when the input signal (in this example, the output signal Scp of the comparator 15) continues at the same level for a predetermined time.

  Specifically, the noise filter 37 includes a clock source 39 similar to the clock source 29 described above, two D-type flip-flops 41 and 42 connected in the form of a shift register, and an AND circuit 43. , A NOR circuit 44 and a set / reset type flip-flop (SR latch) 45.

  The clock from the clock source 39 is input to the clock terminals (CK terminals) of the D flip-flops 41 and 42. The output signal Scp of the comparator 15 is input to the data input terminal (D terminal) of the D-type flip-flop 41 arranged in the first stage.

  The AND circuit 43 outputs a logical product signal of Qa that is the Q output of the D-type flip-flop 41 and Qb that is the Q output of the D-type flip-flop 42. The NOR circuit 44 outputs a negative logical sum signal of Qa and Qb.

  The output signal Ss of the AND circuit 43 is input as a set signal to the set terminal (SET terminal) of the flip-flop 45, and the output signal Sr of the NOR circuit 44 is input as a reset signal to the reset terminal (RES terminal) of the flip-flop 45. . The Q output of the flip-flop 45 is the output signal Sout of the noise filter 37.

  The noise filter 37 has a filter time for both a low level input and a high level input, and if the input signal does not become the same level continuously for at least one clock cycle, The output signal Sout does not change.

  Therefore, assuming that the noise filter 37 is mounted on the ECU 5, as shown in FIG. 4, when the communication partner ECU changes the communication signal to the communication line 3 from dominant to recessive, the recession is intermittent due to noise. If it becomes dominant, the output signal Sout of the noise filter 37 does not change from low level to high level. This is because if the recessive becomes dominant due to noise, the opportunity to make both Qa and Qb high level is lost.

On the other hand, if the noise filter 17 of FIG. 1 is used, the problem as shown in FIG. 4 can be avoided.
Further, since the noise filter 17 is composed of a digital circuit, it can be easily integrated into an IC. In the ECU 5, the noise filter 17 is configured in one transceiver IC 21 together with the driver 13 and the comparator 15, so that the ECU 5 is reduced in size. The resistor 11 may also be provided in the transceiver IC 21.

  The noise filter 17 is composed of a clock source 29, D-type flip-flops 31 and 32, and an OR circuit 33. This can be said to be a configuration with a minimum number of elements. For this reason, it is advantageous for size reduction and cost reduction.

  The number of D-type flip-flops constituting the noise filter 17 may be three or more. If the number of D-type flip-flops is N (where N is an integer equal to or greater than 2), the filter time for a low-level input is a maximum of N clock cycles, and the minimum is “N−1” cycles of the clock. It will be minutes. The number of D-type flip-flops and the frequency of the clock may be determined as appropriate so that the filter time is shorter than the time of 1 bit in communication and longer than the pulse width of the noise to be removed.

[Other Embodiments (Modifications)]
<Modification 1>
In the noise filter 17, contrary to the above embodiment, the comparator 15 outputs a low level if the voltage of the communication line 3 is larger than the threshold voltage Vth, and if the voltage of the communication line 3 is smaller than the threshold voltage Vth. The high level may be output. In this case, as the output signal Scp of the comparator 15, the low level is the level representing the recessive level, and the high level is the level representing the dominant level.

  In that case, the noise filter 17 may be configured to have a filter time only for a high level input of a low level input and a high level input. For example, the noise filter 17 in FIG. 1 may be modified as shown in <1> and <2> below.

  <1> The output signal Scp of the comparator 15 is input to the reset terminals (RES terminals) of the D-type flip-flops 31 and 32. In this case, the reset terminals of the D-type flip-flops 31 and 32 are low-active input terminals. When the output signal Scp of the comparator 15 becomes low, the D-type flip-flops 31 and 32 are reset and Q1 and Q2 become low. Try to be level. In this case, the D-type flip-flops 31 and 32 may not have a set function (no set terminal).

<2> Instead of the OR circuit 33, a NAND circuit is used as the output circuit.
<Modification 2>
The output signal Sout of the noise filter 17 may be a low level at the first level and a high level at the second level. That is, for the output signal Sout of the noise filter 17, the microcomputer 19 may determine that the low level is recessive and the high level is dominant, contrary to the above-described content.

  In this case, in the embodiment of FIG. 1, for example, a signal obtained by inverting the output of the OR circuit 33 by an inverting circuit (inverter) is used as the output signal Sout of the noise filter 17, or A (NOR) circuit may be replaced. Similarly, in the first modification, the signal obtained by inverting the output of the NAND circuit of <2> by the inverting circuit is used as the output signal Sout of the noise filter 17, or the NAND circuit is ANDed (AND ) Replace with a circuit.

<Modification 3>
The present invention can be similarly applied to a communication apparatus in which the communication bus is a communication bus that employs a two-wire differential voltage (communication bus for a two-wire differential signal).

An example is shown in FIG. In FIG. 5, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG.
In the communication system 51 shown in FIG. 5, a plurality of ECUs (two are shown in FIG. 5) 55 and 56 are connected to the communication bus 53 as communication devices. The communication bus 53 is a multi-drop type communication bus. In this example, the communication bus 53 includes two communication lines 53a and 53b. In addition, since the structure regarding communication of each ECU55 and 56 is the same, below, ECU55 is demonstrated. Differences from the ECU 5 in FIG. 1 will be described.

  The ECU 55 includes two resistors R1 and R2 that divide a predetermined power supply voltage VD into, for example, a half voltage, and two resistors R3 and R4 similar to the resistors R1 and R2. The power supply voltage VD is, for example, 5V.

  A connection point between the resistors R1 and R2 is connected to one communication line 53a forming the communication bus 53. The connection point between the resistors R3 and R4 is connected to the other communication line 53b that forms the communication bus 53. For this reason, the voltage of each of the communication lines 53a and 53b is stabilized to a voltage half of the power supply voltage VD (in this example, 2.5 V) by the resistors R1 to R4.

  The ECU 55 includes two drivers 61 a and 61 b as drivers for outputting signals to the communication bus 53. The driver 61a is a so-called high-side driver, and the driver 61b is a so-called low-side driver.

  The driver 61a is a switch that, when turned on, causes the communication line 53a to conduct to the power supply voltage VD via the resistor R5, and is configured by a transistor. The driver 61b is a switch that, when turned on, causes the communication line 53b to conduct to the ground potential (0 V), and includes a transistor. Even if the communication line 53a is short-circuited to the ground potential when the driver 61a is on, the resistor R5 prevents the driver 61a from being damaged due to overcurrent. However, the resistance value of the resistor R5 is It is sufficiently smaller than the resistance values of R1 and R2. Moreover, the structure without resistance R5 may be sufficient.

  The driver 61a and the driver 61b are turned on / off at the same time in accordance with a transmission signal from the microcomputer 19. When the driver 61a is turned on, the voltage of the communication line 53a is changed from 2.5V to 5V (= VD) by the resistors R1 and R2, and when the driver 61b is turned on, the voltage of the communication line 53b is changed to the resistors R3 and R3. It becomes 0V from 2.5V by R4.

  In this example, the voltage of the communication line 53a and the voltage of the communication line 53b are both 2.5V, and the voltage difference between the communication line 53a and the communication line 53b is 0V. Corresponds to a voltage representing recessive. Further, when the voltage of the communication line 53a is 5V and the voltage of the communication line 53b is 0V, and the voltage difference between the communication line 53a and the communication line 53b is 5V, the voltage of the communication bus 53 is dominant. This corresponds to the voltage to be expressed. In other words, the recessive side voltage for each of the communication lines 53a and 53b is 2.5V, but for the communication line 53a, 5V is the dominant side voltage, and for the communication line 53b, 0V is the dominant side voltage. is there.

The binarization circuit 63 provided in the ECU 55 includes a differential amplifier circuit 65 and a comparator 67.
The differential amplifier circuit 65 outputs a voltage proportional to the voltage difference between the communication line 53a and the communication line 53b (in this example, “voltage of the communication line 53a” − “voltage of the communication line 53b”). The output voltage of the differential amplifier circuit 65 increases as the voltage difference between the communication line 53a and the communication line 53b increases.

The comparator 67 binarizes the voltage of the communication bus 53 into a high level or low level signal by comparing the output voltage of the differential amplifier circuit 65 with a predetermined threshold voltage Vt.
Specifically, the comparator 67 outputs a high level if the output voltage of the differential amplifier circuit 65 is larger than the threshold voltage Vt, and outputs a low level if the output voltage of the differential amplifier circuit 65 is smaller than the threshold voltage Vt. Output level. The output signal of the comparator 67 becomes the output signal of the binarization circuit 63.

  Therefore, in this example, as the output signal of the binarization circuit 63, the low level is the level representing the recessive level, and the high level is the level representing the dominant level. For this reason, the noise filter 17 that receives the output signal of the binarization circuit 63 has the configuration described in the first modification. If the output signal of the binarization circuit 63 is inverted and input to the noise filter 17, the noise filter 17 may have the configuration shown in FIG.

And also by such a modification 3, the effect similar to embodiment of FIG. 1 is acquired.
As mentioned above, although embodiment of this invention was described, this invention can take a various form, without being limited to the said embodiment. The above-mentioned numerical values are also examples, and other values may be used.

For example, the communication systems 1 and 51 may be other than those used for vehicles. The noise filter 17 may be configured using an analog element such as a capacitor or a resistor.
In addition, the functions of one component in the above embodiment may be distributed as a plurality of components, or the functions of a plurality of components may be integrated into one component. In addition, at least a part of the configuration of the above embodiment may be replaced with a known configuration having a similar function. Moreover, you may abbreviate | omit a part of structure of the said embodiment. In addition, all the aspects included in the technical idea specified by the wording described in the claims are embodiments of the present invention. In addition to the ECU described above, the present invention can be implemented in various forms such as a communication system including the ECU as a constituent element and a noise filter for a communication device.

  DESCRIPTION OF SYMBOLS 1,51 ... Communication system 3,53 ... Communication bus 5, 6, 55, 56 ... Electronic control unit (ECU) 11, R1-R4 ... Resistance, 13, 61a, 61b ... Driver, 15, 63 ... Two Value circuit, 17 ... noise filter, 19 ... microcomputer

Claims (4)

As a communication bus, the voltage of the communication bus (3, 53) is stabilized by a resistor (11, R1-R4) to a voltage representing a recessive signal, which is a recessive signal, and the voltage of the communication bus is a dominant signal. When the driver (13, 61a, 61b) that represents the voltage is turned on, the dominant is output to the communication bus, and when the driver is turned off, the recessive is output to the communication bus. In a communication system (1, 51) using a communication bus,
A communication device (5, 55) communicating with another device (6, 56) via the communication bus,
The resistor and the driver;
A binarization circuit (15, 63) for binarizing the voltage of the communication bus into a high level or low level signal;
A noise filter (17) having the output signal of the binarization circuit as an input;
A processing unit (19) for processing the output signal of the noise filter as a received signal,
The noise filter is
When the output signal of the binarization circuit is at a level representing the recessive of high level and low level, the output signal to the processing unit is processed at the processing level between high level and low level. If the output signal of the binarization circuit is the level representing the dominant of the high level and the low level, and the level is determined to be the recessive level, the predetermined level continues for a predetermined time, The output signal to the processing unit is configured to be a second level of the high level and the low level, which is determined by the processing unit as the dominant,
The predetermined time is shorter than a time corresponding to one bit in communication performed via the communication bus;
A communication device characterized by the above. The communication device according to claim 1,
In the output signal of the binarization circuit, a high level is a level representing the recessive, and a low level is a level representing the dominant,
The noise filter is
A clock source (29) for outputting a clock having a shorter cycle than the time of 1 bit;
A plurality of D-type flip-flops (31, 32) with a set function,
The clock is input to clock terminals of the plurality of D-type flip-flops, and the plurality of D-type flip-flops are connected in the form of a shift register,
Among the plurality of D-type flip-flops, the output of the binarization circuit is connected to the data input terminal of the D-type flip-flop arranged in the first stage in the form of the shift register and the set terminals of all the D-type flip-flops. The signal is input,
Furthermore, the noise filter is
When at least one of the Q outputs of the plurality of D-type flip-flops is at a high level, the output signal to the processing unit is set to the first level, and the Q outputs of the plurality of D-type flip-flops are all low. An output circuit (33) for setting the output signal to the processing unit to the second level when the level is
A communication device characterized by the above. The communication device according to claim 2,
The first level is a high level and the second level is a low level;
The output circuit is an OR circuit (33) having Q outputs of the plurality of D-type flip-flops as inputs;
A communication device characterized by the above. The communication device according to any one of claims 1 to 3,
The noise filter is configured in one IC (21) together with the driver and the binarization circuit,
A communication device characterized by the above.

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